ar71xx: use backported QCA955x patches
[openwrt/svn-archive/archive.git] / target / linux / ar71xx / patches-3.8 / 031-MIPS-ath79-add-IRQ-handling-code-for-the-QCA955X-SoC.patch
1 From f1c0239d61d6d43469133d144e458f485b6cbda6 Mon Sep 17 00:00:00 2001
2 From: Gabor Juhos <juhosg@openwrt.org>
3 Date: Fri, 15 Feb 2013 18:53:47 +0000
4 Subject: [PATCH] MIPS: ath79: add IRQ handling code for the QCA955X SoCs
5
6 commit 53330332f176eaa9567481c69bbad8b2176b4eb5 upstream.
7
8 The IRQ routing in the QCA955x SoCs is slightly
9 different from the routing implemented in the
10 already supported SoCs.
11
12 Cc: Rodriguez, Luis <rodrigue@qca.qualcomm.com>
13 Cc: Giori, Kathy <kgiori@qca.qualcomm.com>
14 Cc: QCA Linux Team <qca-linux-team@qca.qualcomm.com>
15 Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
16 Patchwork: http://patchwork.linux-mips.org/patch/4955/
17 Signed-off-by: John Crispin <blogic@openwrt.org>
18 ---
19 arch/mips/ath79/irq.c | 110 ++++++++++++++++++++++--
20 arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 32 +++++++
21 arch/mips/include/asm/mach-ath79/irq.h | 6 +-
22 3 files changed, 140 insertions(+), 8 deletions(-)
23
24 --- a/arch/mips/ath79/irq.c
25 +++ b/arch/mips/ath79/irq.c
26 @@ -103,7 +103,10 @@ static void __init ath79_misc_irq_init(v
27
28 if (soc_is_ar71xx() || soc_is_ar913x())
29 ath79_misc_irq_chip.irq_mask_ack = ar71xx_misc_irq_mask;
30 - else if (soc_is_ar724x() || soc_is_ar933x() || soc_is_ar934x())
31 + else if (soc_is_ar724x() ||
32 + soc_is_ar933x() ||
33 + soc_is_ar934x() ||
34 + soc_is_qca955x())
35 ath79_misc_irq_chip.irq_ack = ar724x_misc_irq_ack;
36 else
37 BUG();
38 @@ -150,6 +153,88 @@ static void ar934x_ip2_irq_init(void)
39 irq_set_chained_handler(ATH79_CPU_IRQ(2), ar934x_ip2_irq_dispatch);
40 }
41
42 +static void qca955x_ip2_irq_dispatch(unsigned int irq, struct irq_desc *desc)
43 +{
44 + u32 status;
45 +
46 + disable_irq_nosync(irq);
47 +
48 + status = ath79_reset_rr(QCA955X_RESET_REG_EXT_INT_STATUS);
49 + status &= QCA955X_EXT_INT_PCIE_RC1_ALL | QCA955X_EXT_INT_WMAC_ALL;
50 +
51 + if (status == 0) {
52 + spurious_interrupt();
53 + goto enable;
54 + }
55 +
56 + if (status & QCA955X_EXT_INT_PCIE_RC1_ALL) {
57 + /* TODO: flush DDR? */
58 + generic_handle_irq(ATH79_IP2_IRQ(0));
59 + }
60 +
61 + if (status & QCA955X_EXT_INT_WMAC_ALL) {
62 + /* TODO: flush DDR? */
63 + generic_handle_irq(ATH79_IP2_IRQ(1));
64 + }
65 +
66 +enable:
67 + enable_irq(irq);
68 +}
69 +
70 +static void qca955x_ip3_irq_dispatch(unsigned int irq, struct irq_desc *desc)
71 +{
72 + u32 status;
73 +
74 + disable_irq_nosync(irq);
75 +
76 + status = ath79_reset_rr(QCA955X_RESET_REG_EXT_INT_STATUS);
77 + status &= QCA955X_EXT_INT_PCIE_RC2_ALL |
78 + QCA955X_EXT_INT_USB1 |
79 + QCA955X_EXT_INT_USB2;
80 +
81 + if (status == 0) {
82 + spurious_interrupt();
83 + goto enable;
84 + }
85 +
86 + if (status & QCA955X_EXT_INT_USB1) {
87 + /* TODO: flush DDR? */
88 + generic_handle_irq(ATH79_IP3_IRQ(0));
89 + }
90 +
91 + if (status & QCA955X_EXT_INT_USB2) {
92 + /* TODO: flush DDR? */
93 + generic_handle_irq(ATH79_IP3_IRQ(1));
94 + }
95 +
96 + if (status & QCA955X_EXT_INT_PCIE_RC2_ALL) {
97 + /* TODO: flush DDR? */
98 + generic_handle_irq(ATH79_IP3_IRQ(2));
99 + }
100 +
101 +enable:
102 + enable_irq(irq);
103 +}
104 +
105 +static void qca955x_irq_init(void)
106 +{
107 + int i;
108 +
109 + for (i = ATH79_IP2_IRQ_BASE;
110 + i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
111 + irq_set_chip_and_handler(i, &dummy_irq_chip,
112 + handle_level_irq);
113 +
114 + irq_set_chained_handler(ATH79_CPU_IRQ(2), qca955x_ip2_irq_dispatch);
115 +
116 + for (i = ATH79_IP3_IRQ_BASE;
117 + i < ATH79_IP3_IRQ_BASE + ATH79_IP3_IRQ_COUNT; i++)
118 + irq_set_chip_and_handler(i, &dummy_irq_chip,
119 + handle_level_irq);
120 +
121 + irq_set_chained_handler(ATH79_CPU_IRQ(3), qca955x_ip3_irq_dispatch);
122 +}
123 +
124 asmlinkage void plat_irq_dispatch(void)
125 {
126 unsigned long pending;
127 @@ -185,6 +270,17 @@ asmlinkage void plat_irq_dispatch(void)
128 * Issue a flush in the handlers to ensure that the driver sees
129 * the update.
130 */
131 +
132 +static void ath79_default_ip2_handler(void)
133 +{
134 + do_IRQ(ATH79_CPU_IRQ(2));
135 +}
136 +
137 +static void ath79_default_ip3_handler(void)
138 +{
139 + do_IRQ(ATH79_CPU_IRQ(3));
140 +}
141 +
142 static void ar71xx_ip2_handler(void)
143 {
144 ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_PCI);
145 @@ -209,11 +305,6 @@ static void ar933x_ip2_handler(void)
146 do_IRQ(ATH79_CPU_IRQ(2));
147 }
148
149 -static void ar934x_ip2_handler(void)
150 -{
151 - do_IRQ(ATH79_CPU_IRQ(2));
152 -}
153 -
154 static void ar71xx_ip3_handler(void)
155 {
156 ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_USB);
157 @@ -259,8 +350,11 @@ void __init arch_init_irq(void)
158 ath79_ip2_handler = ar933x_ip2_handler;
159 ath79_ip3_handler = ar933x_ip3_handler;
160 } else if (soc_is_ar934x()) {
161 - ath79_ip2_handler = ar934x_ip2_handler;
162 + ath79_ip2_handler = ath79_default_ip2_handler;
163 ath79_ip3_handler = ar934x_ip3_handler;
164 + } else if (soc_is_qca955x()) {
165 + ath79_ip2_handler = ath79_default_ip2_handler;
166 + ath79_ip3_handler = ath79_default_ip3_handler;
167 } else {
168 BUG();
169 }
170 @@ -271,4 +365,6 @@ void __init arch_init_irq(void)
171
172 if (soc_is_ar934x())
173 ar934x_ip2_irq_init();
174 + else if (soc_is_qca955x())
175 + qca955x_irq_init();
176 }
177 --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
178 +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
179 @@ -300,6 +300,7 @@
180 #define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac
181
182 #define QCA955X_RESET_REG_BOOTSTRAP 0xb0
183 +#define QCA955X_RESET_REG_EXT_INT_STATUS 0xac
184
185 #define MISC_INT_ETHSW BIT(12)
186 #define MISC_INT_TIMER4 BIT(10)
187 @@ -398,6 +399,37 @@
188 AR934X_PCIE_WMAC_INT_PCIE_RC1 | AR934X_PCIE_WMAC_INT_PCIE_RC2 | \
189 AR934X_PCIE_WMAC_INT_PCIE_RC3)
190
191 +#define QCA955X_EXT_INT_WMAC_MISC BIT(0)
192 +#define QCA955X_EXT_INT_WMAC_TX BIT(1)
193 +#define QCA955X_EXT_INT_WMAC_RXLP BIT(2)
194 +#define QCA955X_EXT_INT_WMAC_RXHP BIT(3)
195 +#define QCA955X_EXT_INT_PCIE_RC1 BIT(4)
196 +#define QCA955X_EXT_INT_PCIE_RC1_INT0 BIT(5)
197 +#define QCA955X_EXT_INT_PCIE_RC1_INT1 BIT(6)
198 +#define QCA955X_EXT_INT_PCIE_RC1_INT2 BIT(7)
199 +#define QCA955X_EXT_INT_PCIE_RC1_INT3 BIT(8)
200 +#define QCA955X_EXT_INT_PCIE_RC2 BIT(12)
201 +#define QCA955X_EXT_INT_PCIE_RC2_INT0 BIT(13)
202 +#define QCA955X_EXT_INT_PCIE_RC2_INT1 BIT(14)
203 +#define QCA955X_EXT_INT_PCIE_RC2_INT2 BIT(15)
204 +#define QCA955X_EXT_INT_PCIE_RC2_INT3 BIT(16)
205 +#define QCA955X_EXT_INT_USB1 BIT(24)
206 +#define QCA955X_EXT_INT_USB2 BIT(28)
207 +
208 +#define QCA955X_EXT_INT_WMAC_ALL \
209 + (QCA955X_EXT_INT_WMAC_MISC | QCA955X_EXT_INT_WMAC_TX | \
210 + QCA955X_EXT_INT_WMAC_RXLP | QCA955X_EXT_INT_WMAC_RXHP)
211 +
212 +#define QCA955X_EXT_INT_PCIE_RC1_ALL \
213 + (QCA955X_EXT_INT_PCIE_RC1 | QCA955X_EXT_INT_PCIE_RC1_INT0 | \
214 + QCA955X_EXT_INT_PCIE_RC1_INT1 | QCA955X_EXT_INT_PCIE_RC1_INT2 | \
215 + QCA955X_EXT_INT_PCIE_RC1_INT3)
216 +
217 +#define QCA955X_EXT_INT_PCIE_RC2_ALL \
218 + (QCA955X_EXT_INT_PCIE_RC2 | QCA955X_EXT_INT_PCIE_RC2_INT0 | \
219 + QCA955X_EXT_INT_PCIE_RC2_INT1 | QCA955X_EXT_INT_PCIE_RC2_INT2 | \
220 + QCA955X_EXT_INT_PCIE_RC2_INT3)
221 +
222 #define REV_ID_MAJOR_MASK 0xfff0
223 #define REV_ID_MAJOR_AR71XX 0x00a0
224 #define REV_ID_MAJOR_AR913X 0x00b0
225 --- a/arch/mips/include/asm/mach-ath79/irq.h
226 +++ b/arch/mips/include/asm/mach-ath79/irq.h
227 @@ -10,7 +10,7 @@
228 #define __ASM_MACH_ATH79_IRQ_H
229
230 #define MIPS_CPU_IRQ_BASE 0
231 -#define NR_IRQS 48
232 +#define NR_IRQS 51
233
234 #define ATH79_CPU_IRQ(_x) (MIPS_CPU_IRQ_BASE + (_x))
235
236 @@ -26,6 +26,10 @@
237 #define ATH79_IP2_IRQ_COUNT 2
238 #define ATH79_IP2_IRQ(_x) (ATH79_IP2_IRQ_BASE + (_x))
239
240 +#define ATH79_IP3_IRQ_BASE (ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT)
241 +#define ATH79_IP3_IRQ_COUNT 3
242 +#define ATH79_IP3_IRQ(_x) (ATH79_IP3_IRQ_BASE + (_x))
243 +
244 #include_next <irq.h>
245
246 #endif /* __ASM_MACH_ATH79_IRQ_H */