ar71xx: use backported QCA955x patches
[openwrt/svn-archive/archive.git] / target / linux / ar71xx / patches-3.8 / 036-MIPS-ath79-add-PCI-controller-registration-code-for-.patch
1 From bc14333054c5ecee4bc7e8760d0ffbb730f32c54 Mon Sep 17 00:00:00 2001
2 From: Gabor Juhos <juhosg@openwrt.org>
3 Date: Fri, 15 Feb 2013 13:38:23 +0000
4 Subject: [PATCH] MIPS: ath79: add PCI controller registration code for the
5 QCA955X SoCs
6
7 commit 0a5f3b1c9f20eb44142e3b37662de15c944f759d upstream.
8
9 Add SoC specific PCI IRQ map, and register platform
10 devices for the two built-in PCIe RCs.
11
12 Cc: Rodriguez, Luis <rodrigue@qca.qualcomm.com>
13 Cc: Giori, Kathy <kgiori@qca.qualcomm.com>
14 Cc: QCA Linux Team <qca-linux-team@qca.qualcomm.com>
15 Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
16 Patchwork: http://patchwork.linux-mips.org/patch/4951/
17 Signed-off-by: John Crispin <blogic@openwrt.org>
18 ---
19 arch/mips/ath79/Kconfig | 2 ++
20 arch/mips/ath79/pci.c | 36 ++++++++++++++++++++++++
21 arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 13 +++++++++
22 3 files changed, 51 insertions(+)
23
24 --- a/arch/mips/ath79/Kconfig
25 +++ b/arch/mips/ath79/Kconfig
26 @@ -90,6 +90,8 @@ config SOC_AR934X
27
28 config SOC_QCA955X
29 select USB_ARCH_HAS_EHCI
30 + select HW_HAS_PCI
31 + select PCI_AR724X if PCI
32 def_bool n
33
34 config PCI_AR724X
35 --- a/arch/mips/ath79/pci.c
36 +++ b/arch/mips/ath79/pci.c
37 @@ -49,6 +49,21 @@ static const struct ath79_pci_irq ar724x
38 }
39 };
40
41 +static const struct ath79_pci_irq qca955x_pci_irq_map[] __initconst = {
42 + {
43 + .bus = 0,
44 + .slot = 0,
45 + .pin = 1,
46 + .irq = ATH79_PCI_IRQ(0),
47 + },
48 + {
49 + .bus = 1,
50 + .slot = 0,
51 + .pin = 1,
52 + .irq = ATH79_PCI_IRQ(1),
53 + },
54 +};
55 +
56 int __init pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, uint8_t pin)
57 {
58 int irq = -1;
59 @@ -64,6 +79,9 @@ int __init pcibios_map_irq(const struct
60 soc_is_ar9344()) {
61 ath79_pci_irq_map = ar724x_pci_irq_map;
62 ath79_pci_nr_irqs = ARRAY_SIZE(ar724x_pci_irq_map);
63 + } else if (soc_is_qca955x()) {
64 + ath79_pci_irq_map = qca955x_pci_irq_map;
65 + ath79_pci_nr_irqs = ARRAY_SIZE(qca955x_pci_irq_map);
66 } else {
67 pr_crit("pci %s: invalid irq map\n",
68 pci_name((struct pci_dev *) dev));
69 @@ -225,6 +243,24 @@ int __init ath79_register_pci(void)
70 AR724X_PCI_MEM_SIZE,
71 0,
72 ATH79_IP2_IRQ(0));
73 + } else if (soc_is_qca9558()) {
74 + pdev = ath79_register_pci_ar724x(0,
75 + QCA955X_PCI_CFG_BASE0,
76 + QCA955X_PCI_CTRL_BASE0,
77 + QCA955X_PCI_CRP_BASE0,
78 + QCA955X_PCI_MEM_BASE0,
79 + QCA955X_PCI_MEM_SIZE,
80 + 0,
81 + ATH79_IP2_IRQ(0));
82 +
83 + pdev = ath79_register_pci_ar724x(1,
84 + QCA955X_PCI_CFG_BASE1,
85 + QCA955X_PCI_CTRL_BASE1,
86 + QCA955X_PCI_CRP_BASE1,
87 + QCA955X_PCI_MEM_BASE1,
88 + QCA955X_PCI_MEM_SIZE,
89 + 1,
90 + ATH79_IP3_IRQ(2));
91 } else {
92 /* No PCI support */
93 return -ENODEV;
94 --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
95 +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
96 @@ -94,6 +94,19 @@
97 #define AR934X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000)
98 #define AR934X_SRIF_SIZE 0x1000
99
100 +#define QCA955X_PCI_MEM_BASE0 0x10000000
101 +#define QCA955X_PCI_MEM_BASE1 0x12000000
102 +#define QCA955X_PCI_MEM_SIZE 0x02000000
103 +#define QCA955X_PCI_CFG_BASE0 0x14000000
104 +#define QCA955X_PCI_CFG_BASE1 0x16000000
105 +#define QCA955X_PCI_CFG_SIZE 0x1000
106 +#define QCA955X_PCI_CRP_BASE0 (AR71XX_APB_BASE + 0x000c0000)
107 +#define QCA955X_PCI_CRP_BASE1 (AR71XX_APB_BASE + 0x00250000)
108 +#define QCA955X_PCI_CRP_SIZE 0x1000
109 +#define QCA955X_PCI_CTRL_BASE0 (AR71XX_APB_BASE + 0x000f0000)
110 +#define QCA955X_PCI_CTRL_BASE1 (AR71XX_APB_BASE + 0x00280000)
111 +#define QCA955X_PCI_CTRL_SIZE 0x100
112 +
113 #define QCA955X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
114 #define QCA955X_WMAC_SIZE 0x20000
115