rpcd: iwinfo plugin fixes
[openwrt/svn-archive/archive.git] / target / linux / ar71xx / patches-4.4 / 630-MIPS-ath79-fix-chained-irq-disable.patch
1 --- a/arch/mips/ath79/irq.c
2 +++ b/arch/mips/ath79/irq.c
3 @@ -26,6 +26,9 @@
4 #include "common.h"
5 #include "machtypes.h"
6
7 +static struct irq_chip ip2_chip;
8 +static struct irq_chip ip3_chip;
9 +
10 static void ath79_misc_irq_handler(struct irq_desc *desc)
11 {
12 void __iomem *base = ath79_reset_base;
13 @@ -145,8 +148,7 @@ static void ar934x_ip2_irq_init(void)
14
15 for (i = ATH79_IP2_IRQ_BASE;
16 i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
17 - irq_set_chip_and_handler(i, &dummy_irq_chip,
18 - handle_level_irq);
19 + irq_set_chip_and_handler(i, &ip2_chip, handle_level_irq);
20
21 irq_set_chained_handler(ATH79_CPU_IRQ(2), ar934x_ip2_irq_dispatch);
22 }
23 @@ -174,7 +176,7 @@ static void qca953x_irq_init(void)
24
25 for (i = ATH79_IP2_IRQ_BASE;
26 i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
27 - irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq);
28 + irq_set_chip_and_handler(i, &ip2_chip, handle_level_irq);
29
30 irq_set_chained_handler(ATH79_CPU_IRQ(2), qca953x_ip2_irq_dispatch);
31 }
32 @@ -238,15 +240,13 @@ static void qca955x_irq_init(void)
33
34 for (i = ATH79_IP2_IRQ_BASE;
35 i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
36 - irq_set_chip_and_handler(i, &dummy_irq_chip,
37 - handle_level_irq);
38 + irq_set_chip_and_handler(i, &ip2_chip, handle_level_irq);
39
40 irq_set_chained_handler(ATH79_CPU_IRQ(2), qca955x_ip2_irq_dispatch);
41
42 for (i = ATH79_IP3_IRQ_BASE;
43 i < ATH79_IP3_IRQ_BASE + ATH79_IP3_IRQ_COUNT; i++)
44 - irq_set_chip_and_handler(i, &dummy_irq_chip,
45 - handle_level_irq);
46 + irq_set_chip_and_handler(i, &ip3_chip, handle_level_irq);
47
48 irq_set_chained_handler(ATH79_CPU_IRQ(3), qca955x_ip3_irq_dispatch);
49 }
50 @@ -331,13 +331,13 @@ static void qca956x_irq_init(void)
51
52 for (i = ATH79_IP2_IRQ_BASE;
53 i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
54 - irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq);
55 + irq_set_chip_and_handler(i, &ip2_chip, handle_level_irq);
56
57 irq_set_chained_handler(ATH79_CPU_IRQ(2), qca956x_ip2_irq_dispatch);
58
59 for (i = ATH79_IP3_IRQ_BASE;
60 i < ATH79_IP3_IRQ_BASE + ATH79_IP3_IRQ_COUNT; i++)
61 - irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq);
62 + irq_set_chip_and_handler(i, &ip3_chip, handle_level_irq);
63
64 irq_set_chained_handler(ATH79_CPU_IRQ(3), qca956x_ip3_irq_dispatch);
65
66 @@ -463,8 +463,36 @@ IRQCHIP_DECLARE(ar79_cpu_intc, "qca,ar71
67
68 #endif
69
70 +static void ath79_ip2_disable(struct irq_data *data)
71 +{
72 + disable_irq(ATH79_CPU_IRQ(2));
73 +}
74 +
75 +static void ath79_ip2_enable(struct irq_data *data)
76 +{
77 + enable_irq(ATH79_CPU_IRQ(2));
78 +}
79 +
80 +static void ath79_ip3_disable(struct irq_data *data)
81 +{
82 + disable_irq(ATH79_CPU_IRQ(3));
83 +}
84 +
85 +static void ath79_ip3_enable(struct irq_data *data)
86 +{
87 + enable_irq(ATH79_CPU_IRQ(3));
88 +}
89 +
90 void __init arch_init_irq(void)
91 {
92 + ip2_chip = dummy_irq_chip;
93 + ip2_chip.irq_disable = ath79_ip2_disable;
94 + ip2_chip.irq_enable = ath79_ip2_enable;
95 +
96 + ip3_chip = dummy_irq_chip;
97 + ip3_chip.irq_disable = ath79_ip3_disable;
98 + ip3_chip.irq_enable = ath79_ip3_enable;
99 +
100 if (mips_machtype == ATH79_MACH_GENERIC_OF) {
101 irqchip_init();
102 return;