target/linux/aruba-2.6/files/arch/mips/pci/pci-aruba.c

   1 /**************************************************************************
   2  *
   3  *  BRIEF MODULE DESCRIPTION
   4  *     PCI initialization for IDT EB434 board
   5  *
   6  *  Copyright 2004 IDT Inc. (rischelp@idt.com)
   7  *
   8  *  This program is free software; you can redistribute  it and/or modify it
   9  *  under  the terms of  the GNU General  Public License as published by the
  10  *  Free Software Foundation;  either version 2 of the  License, or (at your
  11  *  option) any later version.
  12  *
  13  *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
  14  *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
  15  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  16  *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
  17  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  18  *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
  19  *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  20  *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
  21  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  22  *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  23  *
  24  *  You should have received a copy of the  GNU General Public License along
  25  *  with this program; if not, write  to the Free Software Foundation, Inc.,
  26  *  675 Mass Ave, Cambridge, MA 02139, USA.
  27  *
  28  *
  29  **************************************************************************
  30  * May 2004 rkt, neb
  31  *
  32  * Initial Release
  33  *
  34  *
  35  *
  36  **************************************************************************
  37  */
  38
  39 #include <linux/autoconf.h>
  40 #include <linux/types.h>
  41 #include <linux/pci.h>
  42 #include <linux/kernel.h>
  43 #include <linux/init.h>
  44 #include <asm/idt-boards/rc32434/rc32434.h>
  45 #include <asm/idt-boards/rc32434/rc32434_pci.h>
  46
  47 #define PCI_ACCESS_READ  0
  48 #define PCI_ACCESS_WRITE 1
  49
  50 #undef DEBUG
  51 #ifdef DEBUG
  52 #define DBG(x...) printk(x)
  53 #else
  54 #define DBG(x...)
  55 #endif
  56 /* define an unsigned array for the PCI registers */
  57 unsigned int korinaCnfgRegs[25] = {
  58         KORINA_CNFG1,    KORINA_CNFG2,  KORINA_CNFG3,  KORINA_CNFG4,
  59         KORINA_CNFG5,    KORINA_CNFG6,  KORINA_CNFG7,  KORINA_CNFG8,
  60         KORINA_CNFG9,    KORINA_CNFG10, KORINA_CNFG11, KORINA_CNFG12,
  61         KORINA_CNFG13, KORINA_CNFG14, KORINA_CNFG15, KORINA_CNFG16,
  62         KORINA_CNFG17, KORINA_CNFG18, KORINA_CNFG19, KORINA_CNFG20,
  63         KORINA_CNFG21, KORINA_CNFG22, KORINA_CNFG23, KORINA_CNFG24
  64 };
  65
  66 static struct resource rc32434_res_pci_mem2;
  67
  68 static struct resource rc32434_res_pci_mem1 = {
  69         .name = "PCI MEM1",
  70         .start = 0x50000000,
  71         .end = 0x5FFFFFFF,
  72         .flags = IORESOURCE_MEM,
  73         .child = &rc32434_res_pci_mem2,
  74 };
  75 static struct resource rc32434_res_pci_mem2 = {
  76         .name = "PCI MEM2",
  77         .start = 0x60000000,
  78         .end = 0x6FFFFFFF,
  79         .flags = IORESOURCE_MEM,
  80         .parent = &rc32434_res_pci_mem1,
  81 };
  82 static struct resource rc32434_res_pci_io1 = {
  83         .name = "PCI I/O1",
  84         .start = 0x18800000,
  85         .end = 0x188FFFFF,
  86         .flags = IORESOURCE_IO,
  87 };
  88
  89 extern struct pci_ops rc32434_pci_ops;
  90
  91 struct pci_controller rc32434_controller = {
  92         .pci_ops = &rc32434_pci_ops,
  93         .mem_resource = &rc32434_res_pci_mem1,
  94         .io_resource = &rc32434_res_pci_io1,
  95         .mem_offset     = 0x00000000UL,
  96         .io_offset      = 0x00000000UL,
  97 };
  98
  99 extern unsigned int arch_has_pci;
 100
 101 static int __init rc32434_pcibridge_init(void)
 102 {
 103
 104         unsigned int pciConfigAddr = 0;/*used for writing pci config values */
 105         int          loopCount=0    ;/*used for the loop */
 106
 107         unsigned int pcicValue, pcicData=0;
 108         unsigned int dummyRead, pciCntlVal = 0;
 109
 110         if (!arch_has_pci) return 0;
 111
 112         printk("PCI: Initializing PCI\n");
 113
 114         /* Disable the IP bus error for PCI scaning */
 115         pciCntlVal=rc32434_pci->pcic;
 116         pciCntlVal &= 0xFFFFFF7;
 117         rc32434_pci->pcic = pciCntlVal;
 118
 119         ioport_resource.start = rc32434_res_pci_io1.start;
 120         ioport_resource.end = rc32434_res_pci_io1.end;
 121 /*
 122         iomem_resource.start = rc32434_res_pci_mem1.start;
 123         iomem_resource.end = rc32434_res_pci_mem1.end;
 124 */
 125
 126         pcicValue = rc32434_pci->pcic;
 127         pcicValue = (pcicValue >> PCIM_SHFT) & PCIM_BIT_LEN;
 128         if (!((pcicValue == PCIM_H_EA) ||
 129               (pcicValue == PCIM_H_IA_FIX) ||
 130               (pcicValue == PCIM_H_IA_RR))) {
 131                 /* Not in Host Mode, return ERROR */
 132                 return -1;
 133         }
 134
 135         /* Enables the Idle Grant mode, Arbiter Parking */
 136         pcicData |=(PCIC_igm_m|PCIC_eap_m|PCIC_en_m);
 137         rc32434_pci->pcic = pcicData; /* Enable the PCI bus Interface */
 138         /* Zero out the PCI status & PCI Status Mask */
 139         for(;;) {
 140                 pcicData = rc32434_pci->pcis;
 141                 if (!(pcicData & PCIS_rip_m))
 142                         break;
 143         }
 144
 145         rc32434_pci->pcis = 0;
 146         rc32434_pci->pcism = 0xFFFFFFFF;
 147         /* Zero out the PCI decoupled registers */
 148         rc32434_pci->pcidac=0; /* disable PCI decoupled accesses at initialization */
 149         rc32434_pci->pcidas=0; /* clear the status */
 150         rc32434_pci->pcidasm=0x0000007F; /* Mask all the interrupts */
 151         /* Mask PCI Messaging Interrupts */
 152         rc32434_pci_msg->pciiic = 0;
 153         rc32434_pci_msg->pciiim = 0xFFFFFFFF;
 154         rc32434_pci_msg->pciioic = 0;
 155         rc32434_pci_msg->pciioim = 0;
 156
 157         /* Setup PCILB0 as Memory Window */
 158         rc32434_pci->pcilba[0].a = (unsigned int) (PCI_ADDR_START);
 159
 160         /* setup the PCI map address as same as the local address */
 161
 162         rc32434_pci->pcilba[0].m = (unsigned int) (PCI_ADDR_START);
 163
 164         /* Setup PCILBA1 as MEM */
 165 #ifdef __MIPSEB__
 166         rc32434_pci->pcilba[0].c = ( ((SIZE_16MB & 0x1f) << PCILBAC_size_b) | PCILBAC_sb_m);
 167 #else
 168         rc32434_pci->pcilba[0].c = ( ((SIZE_16MB & 0x1f) << PCILBAC_size_b));
 169 #endif
 170         dummyRead = rc32434_pci->pcilba[0].c; /* flush the CPU write Buffers */
 171
 172         rc32434_pci->pcilba[1].a = 0x60000000;
 173
 174         rc32434_pci->pcilba[1].m = 0x60000000;
 175         /* setup PCILBA2 as IO Window*/
 176 #ifdef __MIPSEB__
 177         rc32434_pci->pcilba[1].c = ( ((SIZE_256MB & 0x1f) << PCILBAC_size_b) |  PCILBAC_sb_m);
 178 #else
 179         rc32434_pci->pcilba[1].c = ((SIZE_256MB & 0x1f) << PCILBAC_size_b);
 180 #endif
 181         dummyRead = rc32434_pci->pcilba[1].c; /* flush the CPU write Buffers */
 182         rc32434_pci->pcilba[2].a = 0x18C00000;
 183
 184         rc32434_pci->pcilba[2].m = 0x18FFFFFF;
 185         /* setup PCILBA2 as IO Window*/
 186 #ifdef __MIPSEB__
 187         rc32434_pci->pcilba[2].c = ( ((SIZE_4MB & 0x1f) << PCILBAC_size_b)  |  PCILBAC_sb_m);
 188 #else
 189         rc32434_pci->pcilba[2].c = ((SIZE_4MB & 0x1f) << PCILBAC_size_b);
 190 #endif
 191
 192         dummyRead = rc32434_pci->pcilba[2].c; /* flush the CPU write Buffers */
 193
 194
 195         rc32434_pci->pcilba[3].a = 0x18800000;
 196
 197         rc32434_pci->pcilba[3].m = 0x18800000;
 198         /* Setup PCILBA3 as IO Window */
 199
 200 #ifdef __MIPSEB__
 201         rc32434_pci->pcilba[3].c = ( (((SIZE_1MB & 0x1ff) << PCILBAC_size_b) | PCILBAC_msi_m)   |  PCILBAC_sb_m);
 202 #else
 203         rc32434_pci->pcilba[3].c = (((SIZE_1MB & 0x1ff) << PCILBAC_size_b) | PCILBAC_msi_m);
 204 #endif
 205         dummyRead = rc32434_pci->pcilba[2].c; /* flush the CPU write Buffers */
 206
 207         pciConfigAddr = (unsigned int)(0x80000004);
 208         for(loopCount = 0; loopCount < 24; loopCount++){
 209                 rc32434_pci->pcicfga = pciConfigAddr;
 210                 dummyRead = rc32434_pci->pcicfga;
 211                 rc32434_pci->pcicfgd = korinaCnfgRegs[loopCount];
 212                 dummyRead=rc32434_pci->pcicfgd;
 213                 pciConfigAddr += 4;
 214         }
 215         rc32434_pci->pcitc=(unsigned int)((PCITC_RTIMER_VAL&0xff) << PCITC_rtimer_b) |
 216                 ((PCITC_DTIMER_VAL&0xff)<<PCITC_dtimer_b);
 217
 218         pciCntlVal = rc32434_pci->pcic;
 219         pciCntlVal &= ~(PCIC_tnr_m);
 220         rc32434_pci->pcic = pciCntlVal;
 221         pciCntlVal = rc32434_pci->pcic;
 222
 223         register_pci_controller(&rc32434_controller);
 224
 225         rc32434_sync();
 226         return 0;
 227 }
 228
 229 arch_initcall(rc32434_pcibridge_init);
 230
 231 /* Do platform specific device initialization at pci_enable_device() time */
 232 int pcibios_plat_dev_init(struct pci_dev *dev)
 233 {
 234         return 0;
 235 }