Fixed bug in mmc driver (can now write to SD-Card within Linux). Changed
[openwrt/svn-archive/archive.git] / target / linux / at91-2.6 / patches / 012-at91-mmcfix.patch
1 --- linux-2.6.21.1.old/drivers/mmc/at91_mci.c 2007-06-05 09:08:57.000000000 +0200
2 +++ linux-2.6.21.1/drivers/mmc/at91_mci.c 2007-06-05 10:59:11.000000000 +0200
3 @@ -79,7 +79,8 @@
4
5 #define DRIVER_NAME "at91_mci"
6
7 -#undef SUPPORT_4WIRE
8 +//#undef SUPPORT_4WIRE
9 +#define SUPPORT_4WIRE
10
11 #define FL_SENT_COMMAND (1 << 0)
12 #define FL_SENT_STOP (1 << 1)
13 @@ -132,7 +133,7 @@
14 /*
15 * Copy from sg to a dma block - used for transfers
16 */
17 -static inline void at91mci_sg_to_dma(struct at91mci_host *host, struct mmc_data *data)
18 +static inline void at91_mci_sg_to_dma(struct at91mci_host *host, struct mmc_data *data)
19 {
20 unsigned int len, i, size;
21 unsigned *dmabuf = host->buffer;
22 @@ -181,7 +182,7 @@
23 /*
24 * Prepare a dma read
25 */
26 -static void at91mci_pre_dma_read(struct at91mci_host *host)
27 +static void at91_mci_pre_dma_read(struct at91mci_host *host)
28 {
29 int i;
30 struct scatterlist *sg;
31 @@ -249,23 +250,24 @@
32 /*
33 * Handle after a dma read
34 */
35 -static void at91mci_post_dma_read(struct at91mci_host *host)
36 +static int at91_mci_post_dma_read(struct at91mci_host *host)
37 {
38 struct mmc_command *cmd;
39 struct mmc_data *data;
40 + int completed = 0;
41
42 pr_debug("post dma read\n");
43
44 cmd = host->cmd;
45 if (!cmd) {
46 pr_debug("no command\n");
47 - return;
48 + return 1;
49 }
50
51 data = cmd->data;
52 if (!data) {
53 pr_debug("no data\n");
54 - return;
55 + return 1;
56 }
57
58 while (host->in_use_index < host->transfer_index) {
59 @@ -300,39 +302,14 @@
60
61 /* Is there another transfer to trigger? */
62 if (host->transfer_index < data->sg_len)
63 - at91mci_pre_dma_read(host);
64 + at91_mci_pre_dma_read(host);
65 else {
66 + at91_mci_write(host, AT91_MCI_IDR, AT91_MCI_ENDRX);
67 at91_mci_write(host, AT91_MCI_IER, AT91_MCI_RXBUFF);
68 - at91_mci_write(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS);
69 }
70
71 pr_debug("post dma read done\n");
72 -}
73 -
74 -/*
75 - * Handle transmitted data
76 - */
77 -static void at91_mci_handle_transmitted(struct at91mci_host *host)
78 -{
79 - struct mmc_command *cmd;
80 - struct mmc_data *data;
81 -
82 - pr_debug("Handling the transmit\n");
83 -
84 - /* Disable the transfer */
85 - at91_mci_write(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS);
86 -
87 - /* Now wait for cmd ready */
88 - at91_mci_write(host, AT91_MCI_IDR, AT91_MCI_TXBUFE);
89 - at91_mci_write(host, AT91_MCI_IER, AT91_MCI_NOTBUSY);
90 -
91 - cmd = host->cmd;
92 - if (!cmd) return;
93 -
94 - data = cmd->data;
95 - if (!data) return;
96 -
97 - data->bytes_xfered = host->total_length;
98 + return completed;
99 }
100
101 /*
102 @@ -340,10 +317,17 @@
103 */
104 static void at91_mci_enable(struct at91mci_host *host)
105 {
106 + unsigned int mr;
107 +
108 at91_mci_write(host, AT91_MCI_CR, AT91_MCI_MCIEN);
109 at91_mci_write(host, AT91_MCI_IDR, 0xffffffff);
110 at91_mci_write(host, AT91_MCI_DTOR, AT91_MCI_DTOMUL_1M | AT91_MCI_DTOCYC);
111 - at91_mci_write(host, AT91_MCI_MR, AT91_MCI_PDCMODE | 0x34a);
112 + mr = AT91_MCI_PDCMODE | 0x34a;
113 +
114 + if (cpu_is_at91sam9260() || cpu_is_at91sam9263())
115 + mr |= AT91_MCI_RDPROOF | AT91_MCI_WRPROOF;
116 +
117 + at91_mci_write(host, AT91_MCI_MR, mr);
118
119 /* use Slot A or B (only one at same time) */
120 at91_mci_write(host, AT91_MCI_SDCR, host->board->slot_b);
121 @@ -359,9 +343,8 @@
122
123 /*
124 * Send a command
125 - * return the interrupts to enable
126 */
127 -static unsigned int at91_mci_send_command(struct at91mci_host *host, struct mmc_command *cmd)
128 +static void at91_mci_send_command(struct at91mci_host *host, struct mmc_command *cmd)
129 {
130 unsigned int cmdr, mr;
131 unsigned int block_length;
132 @@ -372,8 +355,7 @@
133
134 host->cmd = cmd;
135
136 - /* Not sure if this is needed */
137 -#if 0
138 + /* Needed for leaving busy state before CMD1 */
139 if ((at91_mci_read(host, AT91_MCI_SR) & AT91_MCI_RTOE) && (cmd->opcode == 1)) {
140 pr_debug("Clearing timeout\n");
141 at91_mci_write(host, AT91_MCI_ARGR, 0);
142 @@ -383,7 +365,7 @@
143 pr_debug("Clearing: SR = %08X\n", at91_mci_read(host, AT91_MCI_SR));
144 }
145 }
146 -#endif
147 +
148 cmdr = cmd->opcode;
149
150 if (mmc_resp_type(cmd) == MMC_RSP_NONE)
151 @@ -440,50 +422,48 @@
152 at91_mci_write(host, ATMEL_PDC_TCR, 0);
153 at91_mci_write(host, ATMEL_PDC_TNPR, 0);
154 at91_mci_write(host, ATMEL_PDC_TNCR, 0);
155 + ier = AT91_MCI_CMDRDY;
156 + } else {
157 + /* zero block length in PDC mode */
158 + mr = at91_mci_read(host, AT91_MCI_MR) & 0x7fff;
159 + at91_mci_write(host, AT91_MCI_MR, mr | (block_length << 16) | AT91_MCI_PDCMODE);
160 +
161 + /*
162 + * Disable the PDC controller
163 + */
164 + at91_mci_write(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS);
165
166 - at91_mci_write(host, AT91_MCI_ARGR, cmd->arg);
167 - at91_mci_write(host, AT91_MCI_CMDR, cmdr);
168 - return AT91_MCI_CMDRDY;
169 - }
170 -
171 - mr = at91_mci_read(host, AT91_MCI_MR) & 0x7fff; /* zero block length and PDC mode */
172 - at91_mci_write(host, AT91_MCI_MR, mr | (block_length << 16) | AT91_MCI_PDCMODE);
173 -
174 - /*
175 - * Disable the PDC controller
176 - */
177 - at91_mci_write(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS);
178 -
179 - if (cmdr & AT91_MCI_TRCMD_START) {
180 - data->bytes_xfered = 0;
181 - host->transfer_index = 0;
182 - host->in_use_index = 0;
183 - if (cmdr & AT91_MCI_TRDIR) {
184 - /*
185 - * Handle a read
186 - */
187 - host->buffer = NULL;
188 - host->total_length = 0;
189 + if (cmdr & AT91_MCI_TRCMD_START) {
190 + data->bytes_xfered = 0;
191 + host->transfer_index = 0;
192 + host->in_use_index = 0;
193 + if (cmdr & AT91_MCI_TRDIR) {
194 + /*
195 + * Handle a read
196 + */
197 + host->buffer = NULL;
198 + host->total_length = 0;
199
200 - at91mci_pre_dma_read(host);
201 - ier = AT91_MCI_ENDRX /* | AT91_MCI_RXBUFF */;
202 - }
203 - else {
204 - /*
205 - * Handle a write
206 - */
207 - host->total_length = block_length * blocks;
208 - host->buffer = dma_alloc_coherent(NULL,
209 - host->total_length,
210 - &host->physical_address, GFP_KERNEL);
211 -
212 - at91mci_sg_to_dma(host, data);
213 -
214 - pr_debug("Transmitting %d bytes\n", host->total_length);
215 -
216 - at91_mci_write(host, ATMEL_PDC_TPR, host->physical_address);
217 - at91_mci_write(host, ATMEL_PDC_TCR, host->total_length / 4);
218 - ier = AT91_MCI_TXBUFE;
219 + at91_mci_pre_dma_read(host);
220 + ier = AT91_MCI_ENDRX /* | AT91_MCI_RXBUFF */;
221 + }
222 + else {
223 + /*
224 + * Handle a write
225 + */
226 + host->total_length = block_length * blocks;
227 + host->buffer = dma_alloc_coherent(NULL,
228 + host->total_length,
229 + &host->physical_address, GFP_KERNEL);
230 +
231 + at91_mci_sg_to_dma(host, data);
232 +
233 + pr_debug("Transmitting %d bytes\n", host->total_length);
234 +
235 + at91_mci_write(host, ATMEL_PDC_TPR, host->physical_address);
236 + at91_mci_write(host, ATMEL_PDC_TCR, host->total_length / 4);
237 + ier = AT91_MCI_CMDRDY;
238 + }
239 }
240 }
241
242 @@ -498,39 +478,24 @@
243 if (cmdr & AT91_MCI_TRCMD_START) {
244 if (cmdr & AT91_MCI_TRDIR)
245 at91_mci_write(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
246 - else
247 - at91_mci_write(host, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
248 }
249 - return ier;
250 -}
251
252 -/*
253 - * Wait for a command to complete
254 - */
255 -static void at91mci_process_command(struct at91mci_host *host, struct mmc_command *cmd)
256 -{
257 - unsigned int ier;
258 -
259 - ier = at91_mci_send_command(host, cmd);
260 -
261 - pr_debug("setting ier to %08X\n", ier);
262 -
263 - /* Stop on errors or the required value */
264 + /* Enable selected interrupts */
265 at91_mci_write(host, AT91_MCI_IER, AT91_MCI_ERRORS | ier);
266 }
267
268 /*
269 * Process the next step in the request
270 */
271 -static void at91mci_process_next(struct at91mci_host *host)
272 +static void at91_mci_process_next(struct at91mci_host *host)
273 {
274 if (!(host->flags & FL_SENT_COMMAND)) {
275 host->flags |= FL_SENT_COMMAND;
276 - at91mci_process_command(host, host->request->cmd);
277 + at91_mci_send_command(host, host->request->cmd);
278 }
279 else if ((!(host->flags & FL_SENT_STOP)) && host->request->stop) {
280 host->flags |= FL_SENT_STOP;
281 - at91mci_process_command(host, host->request->stop);
282 + at91_mci_send_command(host, host->request->stop);
283 }
284 else
285 mmc_request_done(host->mmc, host->request);
286 @@ -539,7 +504,7 @@
287 /*
288 * Handle a command that has been completed
289 */
290 -static void at91mci_completed_command(struct at91mci_host *host)
291 +static void at91_mci_completed_command(struct at91mci_host *host)
292 {
293 struct mmc_command *cmd = host->cmd;
294 unsigned int status;
295 @@ -583,7 +548,7 @@
296 else
297 cmd->error = MMC_ERR_NONE;
298
299 - at91mci_process_next(host);
300 + at91_mci_process_next(host);
301 }
302
303 /*
304 @@ -595,7 +560,60 @@
305 host->request = mrq;
306 host->flags = 0;
307
308 - at91mci_process_next(host);
309 + at91_mci_process_next(host);
310 +}
311 +
312 +/*
313 + * Handle transmitted data
314 + */
315 +static void at91_mci_handle_transmitted(struct at91mci_host *host)
316 +{
317 + struct mmc_command *cmd;
318 + struct mmc_data *data;
319 +
320 + pr_debug("Handling the transmit\n");
321 +
322 + /* Disable the transfer */
323 + at91_mci_write(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS);
324 +
325 + /* Now wait for cmd ready */
326 + at91_mci_write(host, AT91_MCI_IDR, AT91_MCI_TXBUFE);
327 +
328 + cmd = host->cmd;
329 + if (!cmd) return;
330 +
331 + data = cmd->data;
332 + if (!data) return;
333 +
334 + if (cmd->opcode == MMC_WRITE_MULTIPLE_BLOCK) {
335 + pr_debug("multiple write : wait for BLKE...\n");
336 + at91_mci_write(host, AT91_MCI_IER, AT91_MCI_BLKE);
337 + } else
338 + at91_mci_write(host, AT91_MCI_IER, AT91_MCI_NOTBUSY);
339 +
340 + data->bytes_xfered = host->total_length;
341 +}
342 +
343 +
344 +/*Handle after command sent ready*/
345 +static int at91_mci_handle_cmdrdy(struct at91mci_host *host)
346 +{
347 + if (!host->cmd)
348 + return 1;
349 + else if (!host->cmd->data) {
350 + if (host->flags & FL_SENT_STOP) {
351 + /*After multi block write, we mus wait for NOTBUSY*/
352 + at91_mci_write(host, AT91_MCI_IER, AT91_MCI_NOTBUSY);
353 + } else return 1;
354 + } else if (host->cmd->data->flags & MMC_DATA_WRITE) {
355 + /*After sending multi-block-write command, start DMA transfer*/
356 + at91_mci_write(host, AT91_MCI_IER, AT91_MCI_TXBUFE);
357 + at91_mci_write(host, AT91_MCI_IER, AT91_MCI_BLKE);
358 + at91_mci_write(host, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
359 + }
360 +
361 + /* command not completed, have to wait */
362 + return 0;
363 }
364
365 /*
366 @@ -698,29 +716,33 @@
367 at91_mci_handle_transmitted(host);
368 }
369
370 + if (int_status & AT91_MCI_ENDRX) {
371 + pr_debug("ENDRX\n");
372 + at91_mci_post_dma_read(host);
373 + }
374 +
375 if (int_status & AT91_MCI_RXBUFF) {
376 pr_debug("RX buffer full\n");
377 - at91_mci_write(host, AT91_MCI_IER, AT91_MCI_CMDRDY);
378 + at91_mci_write(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS);
379 + at91_mci_write(host, AT91_MCI_IDR, AT91_MCI_RXBUFF | AT91_MCI_ENDRX);
380 + completed = 1;
381 }
382
383 if (int_status & AT91_MCI_ENDTX)
384 pr_debug("Transmit has ended\n");
385
386 - if (int_status & AT91_MCI_ENDRX) {
387 - pr_debug("Receive has ended\n");
388 - at91mci_post_dma_read(host);
389 - }
390 -
391 if (int_status & AT91_MCI_NOTBUSY) {
392 pr_debug("Card is ready\n");
393 - at91_mci_write(host, AT91_MCI_IER, AT91_MCI_CMDRDY);
394 + completed = 1;
395 }
396
397 if (int_status & AT91_MCI_DTIP)
398 pr_debug("Data transfer in progress\n");
399
400 - if (int_status & AT91_MCI_BLKE)
401 + if (int_status & AT91_MCI_BLKE) {
402 pr_debug("Block transfer has ended\n");
403 + completed = 1;
404 + }
405
406 if (int_status & AT91_MCI_TXRDY)
407 pr_debug("Ready to transmit\n");
408 @@ -730,14 +752,14 @@
409
410 if (int_status & AT91_MCI_CMDRDY) {
411 pr_debug("Command ready\n");
412 - completed = 1;
413 + completed = at91_mci_handle_cmdrdy(host);
414 }
415 }
416
417 if (completed) {
418 pr_debug("Completed command\n");
419 at91_mci_write(host, AT91_MCI_IDR, 0xffffffff);
420 - at91mci_completed_command(host);
421 + at91_mci_completed_command(host);
422 } else
423 at91_mci_write(host, AT91_MCI_IDR, int_status);
424