target/linux/atheros/files-2.6.28/arch/mips/atheros/ar5315/board.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 2003 Atheros Communications, Inc.,  All Rights Reserved.
   7  * Copyright (C) 2006 FON Technology, SL.
   8  * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
   9  * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
  10  */
  11
  12 /*
  13  * Platform devices for Atheros SoCs
  14  */
  15
  16 #include <linux/autoconf.h>
  17 #include <linux/init.h>
  18 #include <linux/module.h>
  19 #include <linux/types.h>
  20 #include <linux/string.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/kernel.h>
  23 #include <linux/reboot.h>
  24 #include <linux/delay.h>
  25 #include <asm/bootinfo.h>
  26 #include <asm/reboot.h>
  27 #include <asm/time.h>
  28 #include <asm/irq.h>
  29 #include <asm/io.h>
  30 #include <ar531x.h>
  31 #include <linux/leds.h>
  32 #include <asm/gpio.h>
  33
  34 static int is_5315 = 0;
  35
  36 static struct resource ar5315_eth_res[] = {
  37         {
  38                 .name = "eth0_membase",
  39                 .flags = IORESOURCE_MEM,
  40                 .start = AR5315_ENET0,
  41                 .end = AR5315_ENET0 + 0x2000,
  42         },
  43         {
  44                 .name = "eth0_irq",
  45                 .flags = IORESOURCE_IRQ,
  46                 .start = AR5315_IRQ_ENET0_INTRS,
  47                 .end = AR5315_IRQ_ENET0_INTRS,
  48         },
  49 };
  50
  51 static struct ar531x_eth ar5315_eth_data = {
  52         .phy = 1,
  53         .mac = 0,
  54         .reset_base = AR5315_RESET,
  55         .reset_mac = AR5315_RESET_ENET0,
  56         .reset_phy = AR5315_RESET_EPHY0,
  57         .phy_base = AR5315_ENET0
  58 };
  59
  60 static struct platform_device ar5315_eth = {
  61         .id = 0,
  62         .name = "ar531x-eth",
  63         .dev.platform_data = &ar5315_eth_data,
  64         .resource = ar5315_eth_res,
  65         .num_resources = ARRAY_SIZE(ar5315_eth_res)
  66 };
  67
  68 static struct platform_device ar5315_wmac = {
  69         .id = 0,
  70         .name = "ar531x-wmac",
  71         /* FIXME: add resources */
  72 };
  73
  74 static struct resource ar5315_spiflash_res[] = {
  75         {
  76                 .name = "flash_base",
  77                 .flags = IORESOURCE_MEM,
  78                 .start = KSEG1ADDR(AR5315_SPI_READ),
  79                 .end = KSEG1ADDR(AR5315_SPI_READ) + 0x800000,
  80         },
  81         {
  82                 .name = "flash_regs",
  83                 .flags = IORESOURCE_MEM,
  84                 .start = 0x11300000,
  85                 .end = 0x11300012,
  86         },
  87 };
  88
  89 static struct platform_device ar5315_spiflash = {
  90         .id = 0,
  91         .name = "spiflash",
  92         .resource = ar5315_spiflash_res,
  93         .num_resources = ARRAY_SIZE(ar5315_spiflash_res)
  94 };
  95
  96 #ifdef CONFIG_LEDS_GPIO
  97 static struct gpio_led ar5315_leds[8];
  98
  99 static struct gpio_led_platform_data ar5315_led_data = {
 100         .num_leds = ARRAY_SIZE(ar5315_leds),
 101         .leds = (void *) ar5315_leds,
 102 };
 103
 104 static struct platform_device ar5315_gpio_leds = {
 105         .name = "leds-gpio",
 106         .id = -1,
 107         .dev = {
 108                 .platform_data = (void *) &ar5315_led_data,
 109         }
 110 };
 111 #endif
 112
 113 static struct platform_device ar5315_wdt =
 114 {
 115         .id = 0,
 116         .name = "ar2315_wdt",
 117 };
 118
 119 static __initdata struct platform_device *ar5315_devs[6];
 120
 121 static void *flash_regs;
 122
 123 static inline __u32 spiflash_regread32(int reg)
 124 {
 125         volatile __u32 *data = (__u32 *)(flash_regs + reg);
 126
 127         return (*data);
 128 }
 129
 130 static inline void spiflash_regwrite32(int reg, __u32 data)
 131 {
 132         volatile __u32 *addr = (__u32 *)(flash_regs + reg);
 133
 134         *addr = data;
 135 }
 136
 137 #define SPI_FLASH_CTL      0x00
 138 #define SPI_FLASH_OPCODE   0x04
 139 #define SPI_FLASH_DATA     0x08
 140
 141 static __u8 spiflash_probe(void)
 142 {
 143          __u32 reg;
 144
 145         do {
 146                 reg = spiflash_regread32(SPI_FLASH_CTL);
 147         } while (reg & SPI_CTL_BUSY);
 148
 149         spiflash_regwrite32(SPI_FLASH_OPCODE, 0xab);
 150
 151         reg = (reg & ~SPI_CTL_TX_RX_CNT_MASK) | 4 |
 152                 (1 << 4) | SPI_CTL_START;
 153
 154         spiflash_regwrite32(SPI_FLASH_CTL, reg);
 155
 156         do {
 157                 reg = spiflash_regread32(SPI_FLASH_CTL);
 158         } while (reg & SPI_CTL_BUSY);
 159
 160         reg = (__u32) spiflash_regread32(SPI_FLASH_DATA);
 161         reg &= 0xff;
 162
 163         return (u8) reg;
 164 }
 165
 166
 167 #define STM_8MBIT_SIGNATURE     0x13
 168 #define STM_16MBIT_SIGNATURE    0x14
 169 #define STM_32MBIT_SIGNATURE    0x15
 170 #define STM_64MBIT_SIGNATURE    0x16
 171 #define STM_128MBIT_SIGNATURE   0x17
 172
 173
 174 static char __init *ar5315_flash_limit(void)
 175 {
 176         u8 sig;
 177         u32 flash_size = 0;
 178
 179         /* probe the flash chip size */
 180         flash_regs = ioremap_nocache(ar5315_spiflash_res[1].start, ar5315_spiflash_res[1].end - ar5315_spiflash_res[1].start);
 181         sig = spiflash_probe();
 182         iounmap(flash_regs);
 183
 184         switch(sig) {
 185                 case STM_8MBIT_SIGNATURE:
 186                         flash_size = 0x00100000;
 187                         break;
 188                 case STM_16MBIT_SIGNATURE:
 189                         flash_size = 0x00200000;
 190                         break;
 191                 case STM_32MBIT_SIGNATURE:
 192                         flash_size = 0x00400000;
 193                         break;
 194                 case STM_64MBIT_SIGNATURE:
 195                         flash_size = 0x00800000;
 196                         break;
 197                 case STM_128MBIT_SIGNATURE:
 198                         flash_size = 0x01000000;
 199                         break;
 200         }
 201
 202         ar5315_spiflash_res[0].end = ar5315_spiflash_res[0].start + flash_size;
 203         return (char *) ar5315_spiflash_res[0].end;
 204 }
 205
 206 int __init ar5315_init_devices(void)
 207 {
 208         struct ar531x_config *config;
 209         struct ar531x_boarddata *bcfg;
 210         int dev = 0;
 211 #ifdef CONFIG_LEDS_GPIO
 212         int i;
 213         char *tmp;
 214 #endif
 215
 216         if (!is_5315)
 217                 return 0;
 218
 219         /* Find board configuration */
 220         ar531x_find_config(ar5315_flash_limit());
 221         bcfg = (struct ar531x_boarddata *) board_config;
 222
 223         config = (struct ar531x_config *) kzalloc(sizeof(struct ar531x_config), GFP_KERNEL);
 224         config->board = board_config;
 225         config->radio = radio_config;
 226         config->unit = 0;
 227         config->tag = (u_int16_t) (sysRegRead(AR5315_SREV) & AR5315_REV_CHIP);
 228
 229         ar5315_eth_data.board_config = board_config;
 230         ar5315_eth_data.macaddr = bcfg->enet0Mac;
 231         ar5315_wmac.dev.platform_data = config;
 232
 233         ar5315_devs[dev++] = &ar5315_eth;
 234         ar5315_devs[dev++] = &ar5315_wmac;
 235         ar5315_devs[dev++] = &ar5315_spiflash;
 236         ar5315_devs[dev++] = &ar5315_wdt;
 237
 238 #ifdef CONFIG_LEDS_GPIO
 239         ar5315_led_data.num_leds = 0;
 240         for(i = 1; i < 8; i++)
 241         {
 242                 if((i != AR5315_RESET_GPIO) && (i != bcfg->resetConfigGpio))
 243                 {
 244                         if(i == bcfg->sysLedGpio)
 245                         {
 246                                 tmp = kstrdup("wlan", GFP_KERNEL);
 247                         } else {
 248                                 tmp = kmalloc(6, GFP_KERNEL);
 249                                 if(tmp)
 250                                         sprintf((char*)tmp, "gpio%d", i);
 251                         }
 252                         if(tmp)
 253                         {
 254                                 ar5315_leds[ar5315_led_data.num_leds].name = tmp;
 255                                 ar5315_leds[ar5315_led_data.num_leds].gpio = i;
 256                                 ar5315_leds[ar5315_led_data.num_leds].active_low = 0;
 257                                 ar5315_led_data.num_leds++;
 258                         } else {
 259                                 printk("failed to alloc led string\n");
 260                                 continue;
 261                         }
 262                 }
 263         }
 264         ar5315_devs[dev++] = &ar5315_gpio_leds;
 265 #endif
 266
 267         return platform_add_devices(ar5315_devs, dev);
 268 }
 269
 270 static void ar5315_halt(void)
 271 {
 272          while (1);
 273 }
 274
 275 static void ar5315_power_off(void)
 276 {
 277          ar5315_halt();
 278 }
 279
 280
 281 static void ar5315_restart(char *command)
 282 {
 283         void (*mips_reset_vec)(void) = (void *) 0xbfc00000;
 284
 285         /* reset the system */
 286         sysRegWrite(AR5315_COLD_RESET,AR5317_RESET_SYSTEM);
 287
 288         /* Cold reset does not work on the AR2315/6, use the GPIO reset bits a workaround.
 289          * give it some time to attempt a gpio based hardware reset
 290          * (atheros reference design workaround) */
 291         gpio_direction_output(AR5315_RESET_GPIO, 0);
 292         mdelay(100);
 293
 294         /* Some boards (e.g. Senao EOC-2610) don't implement the reset logic
 295          * workaround. Attempt to jump to the mips reset location -
 296          * the boot loader itself might be able to recover the system */
 297         mips_reset_vec();
 298 }
 299
 300
 301 /*
 302  * This table is indexed by bits 5..4 of the CLOCKCTL1 register
 303  * to determine the predevisor value.
 304  */
 305 static int __initdata CLOCKCTL1_PREDIVIDE_TABLE[4] = {
 306     1,
 307     2,
 308     4,
 309     5
 310 };
 311
 312 static int __initdata PLLC_DIVIDE_TABLE[5] = {
 313     2,
 314     3,
 315     4,
 316     6,
 317     3
 318 };
 319
 320 static unsigned int __init
 321 ar5315_sys_clk(unsigned int clockCtl)
 322 {
 323     unsigned int pllcCtrl,cpuDiv;
 324     unsigned int pllcOut,refdiv,fdiv,divby2;
 325         unsigned int clkDiv;
 326
 327     pllcCtrl = sysRegRead(AR5315_PLLC_CTL);
 328     refdiv = (pllcCtrl & PLLC_REF_DIV_M) >> PLLC_REF_DIV_S;
 329     refdiv = CLOCKCTL1_PREDIVIDE_TABLE[refdiv];
 330     fdiv = (pllcCtrl & PLLC_FDBACK_DIV_M) >> PLLC_FDBACK_DIV_S;
 331     divby2 = (pllcCtrl & PLLC_ADD_FDBACK_DIV_M) >> PLLC_ADD_FDBACK_DIV_S;
 332     divby2 += 1;
 333     pllcOut = (40000000/refdiv)*(2*divby2)*fdiv;
 334
 335
 336     /* clkm input selected */
 337         switch(clockCtl & CPUCLK_CLK_SEL_M) {
 338                 case 0:
 339                 case 1:
 340                         clkDiv = PLLC_DIVIDE_TABLE[(pllcCtrl & PLLC_CLKM_DIV_M) >> PLLC_CLKM_DIV_S];
 341                         break;
 342                 case 2:
 343                         clkDiv = PLLC_DIVIDE_TABLE[(pllcCtrl & PLLC_CLKC_DIV_M) >> PLLC_CLKC_DIV_S];
 344                         break;
 345                 default:
 346                         pllcOut = 40000000;
 347                         clkDiv = 1;
 348                         break;
 349         }
 350         cpuDiv = (clockCtl & CPUCLK_CLK_DIV_M) >> CPUCLK_CLK_DIV_S;
 351         cpuDiv = cpuDiv * 2 ?: 1;
 352         return (pllcOut/(clkDiv * cpuDiv));
 353 }
 354
 355 static inline unsigned int ar5315_cpu_frequency(void)
 356 {
 357     return ar5315_sys_clk(sysRegRead(AR5315_CPUCLK));
 358 }
 359
 360 static inline unsigned int ar5315_apb_frequency(void)
 361 {
 362     return ar5315_sys_clk(sysRegRead(AR5315_AMBACLK));
 363 }
 364
 365 static void __init ar5315_time_init(void)
 366 {
 367         mips_hpt_frequency = ar5315_cpu_frequency() / 2;
 368 }
 369
 370 void __init ar5315_prom_init(void)
 371 {
 372         u32 memsize, memcfg, devid;
 373
 374         is_5315 = 1;
 375         memcfg = sysRegRead(AR5315_MEM_CFG);
 376         memsize   = 1 + ((memcfg & SDRAM_DATA_WIDTH_M) >> SDRAM_DATA_WIDTH_S);
 377         memsize <<= 1 + ((memcfg & SDRAM_COL_WIDTH_M) >> SDRAM_COL_WIDTH_S);
 378         memsize <<= 1 + ((memcfg & SDRAM_ROW_WIDTH_M) >> SDRAM_ROW_WIDTH_S);
 379         memsize <<= 3;
 380         add_memory_region(0, memsize, BOOT_MEM_RAM);
 381
 382         /* Detect the hardware based on the device ID */
 383         devid = sysRegRead(AR5315_SREV) & AR5315_REV_CHIP;
 384         switch(devid) {
 385                 case 0x90:
 386                 case 0x91:
 387                         mips_machtype = MACH_ATHEROS_AR2317;
 388                         break;
 389                 default:
 390                         mips_machtype = MACH_ATHEROS_AR2315;
 391                         break;
 392         }
 393 }
 394
 395 void __init ar5315_plat_setup(void)
 396 {
 397         unsigned int config = read_c0_config();
 398
 399         /* Clear any lingering AHB errors */
 400         write_c0_config(config & ~0x3);
 401         sysRegWrite(AR5315_AHB_ERR0,AHB_ERROR_DET);
 402         sysRegRead(AR5315_AHB_ERR1);
 403         sysRegWrite(AR5315_WDC, WDC_IGNORE_EXPIRATION);
 404
 405         board_time_init = ar5315_time_init;
 406
 407         _machine_restart = ar5315_restart;
 408         _machine_halt = ar5315_halt;
 409         pm_power_off = ar5315_power_off;
 410
 411         serial_setup(KSEG1ADDR(AR5315_UART0), ar5315_apb_frequency());
 412 }
 413
 414 arch_initcall(ar5315_init_devices);