[atheros]: Add initial kernel 2.6.28 support for atheros target.
[openwrt/svn-archive/archive.git] / target / linux / atheros / files-2.6.28 / drivers / net / ar2313 / dma.h
1 #ifndef __ARUBA_DMA_H__
2 #define __ARUBA_DMA_H__
3
4 /*******************************************************************************
5 *
6 * Copyright 2002 Integrated Device Technology, Inc.
7 * All rights reserved.
8 *
9 * DMA register definition.
10 *
11 * File : $Id: dma.h,v 1.3 2002/06/06 18:34:03 astichte Exp $
12 *
13 * Author : ryan.holmQVist@idt.com
14 * Date : 20011005
15 * Update :
16 * $Log: dma.h,v $
17 * Revision 1.3 2002/06/06 18:34:03 astichte
18 * Added XXX_PhysicalAddress and XXX_VirtualAddress
19 *
20 * Revision 1.2 2002/06/05 18:30:46 astichte
21 * Removed IDTField
22 *
23 * Revision 1.1 2002/05/29 17:33:21 sysarch
24 * jba File moved from vcode/include/idt/acacia
25 *
26 *
27 ******************************************************************************/
28
29 #define AR_BIT(x) (1 << (x))
30 #define DMA_RX_ERR_CRC AR_BIT(1)
31 #define DMA_RX_ERR_DRIB AR_BIT(2)
32 #define DMA_RX_ERR_MII AR_BIT(3)
33 #define DMA_RX_EV2 AR_BIT(5)
34 #define DMA_RX_ERR_COL AR_BIT(6)
35 #define DMA_RX_LONG AR_BIT(7)
36 #define DMA_RX_LS AR_BIT(8) /* last descriptor */
37 #define DMA_RX_FS AR_BIT(9) /* first descriptor */
38 #define DMA_RX_MF AR_BIT(10) /* multicast frame */
39 #define DMA_RX_ERR_RUNT AR_BIT(11) /* runt frame */
40 #define DMA_RX_ERR_LENGTH AR_BIT(12) /* length error */
41 #define DMA_RX_ERR_DESC AR_BIT(14) /* descriptor error */
42 #define DMA_RX_ERROR AR_BIT(15) /* error summary */
43 #define DMA_RX_LEN_MASK 0x3fff0000
44 #define DMA_RX_LEN_SHIFT 16
45 #define DMA_RX_FILT AR_BIT(30)
46 #define DMA_RX_OWN AR_BIT(31) /* desc owned by DMA controller */
47
48 #define DMA_RX1_BSIZE_MASK 0x000007ff
49 #define DMA_RX1_BSIZE_SHIFT 0
50 #define DMA_RX1_CHAINED AR_BIT(24)
51 #define DMA_RX1_RER AR_BIT(25)
52
53 #define DMA_TX_ERR_UNDER AR_BIT(1) /* underflow error */
54 #define DMA_TX_ERR_DEFER AR_BIT(2) /* excessive deferral */
55 #define DMA_TX_COL_MASK 0x78
56 #define DMA_TX_COL_SHIFT 3
57 #define DMA_TX_ERR_HB AR_BIT(7) /* hearbeat failure */
58 #define DMA_TX_ERR_COL AR_BIT(8) /* excessive collisions */
59 #define DMA_TX_ERR_LATE AR_BIT(9) /* late collision */
60 #define DMA_TX_ERR_LINK AR_BIT(10) /* no carrier */
61 #define DMA_TX_ERR_LOSS AR_BIT(11) /* loss of carrier */
62 #define DMA_TX_ERR_JABBER AR_BIT(14) /* transmit jabber timeout */
63 #define DMA_TX_ERROR AR_BIT(15) /* frame aborted */
64 #define DMA_TX_OWN AR_BIT(31) /* descr owned by DMA controller */
65
66 #define DMA_TX1_BSIZE_MASK 0x000007ff
67 #define DMA_TX1_BSIZE_SHIFT 0
68 #define DMA_TX1_CHAINED AR_BIT(24) /* chained descriptors */
69 #define DMA_TX1_TER AR_BIT(25) /* transmit end of ring */
70 #define DMA_TX1_FS AR_BIT(29) /* first segment */
71 #define DMA_TX1_LS AR_BIT(30) /* last segment */
72 #define DMA_TX1_IC AR_BIT(31) /* interrupt on completion */
73
74 #define RCVPKT_LENGTH(X) (X >> 16) /* Received pkt Length */
75
76 #define MAC_CONTROL_RE AR_BIT(2) /* receive enable */
77 #define MAC_CONTROL_TE AR_BIT(3) /* transmit enable */
78 #define MAC_CONTROL_DC AR_BIT(5) /* Deferral check */
79 #define MAC_CONTROL_ASTP AR_BIT(8) /* Auto pad strip */
80 #define MAC_CONTROL_DRTY AR_BIT(10) /* Disable retry */
81 #define MAC_CONTROL_DBF AR_BIT(11) /* Disable bcast frames */
82 #define MAC_CONTROL_LCC AR_BIT(12) /* late collision ctrl */
83 #define MAC_CONTROL_HP AR_BIT(13) /* Hash Perfect filtering */
84 #define MAC_CONTROL_HASH AR_BIT(14) /* Unicast hash filtering */
85 #define MAC_CONTROL_HO AR_BIT(15) /* Hash only filtering */
86 #define MAC_CONTROL_PB AR_BIT(16) /* Pass Bad frames */
87 #define MAC_CONTROL_IF AR_BIT(17) /* Inverse filtering */
88 #define MAC_CONTROL_PR AR_BIT(18) /* promiscuous mode (valid frames
89 only) */
90 #define MAC_CONTROL_PM AR_BIT(19) /* pass multicast */
91 #define MAC_CONTROL_F AR_BIT(20) /* full-duplex */
92 #define MAC_CONTROL_DRO AR_BIT(23) /* Disable Receive Own */
93 #define MAC_CONTROL_HBD AR_BIT(28) /* heart-beat disabled (MUST BE
94 SET) */
95 #define MAC_CONTROL_BLE AR_BIT(30) /* big endian mode */
96 #define MAC_CONTROL_RA AR_BIT(31) /* receive all (valid and invalid
97 frames) */
98
99 #define MII_ADDR_BUSY AR_BIT(0)
100 #define MII_ADDR_WRITE AR_BIT(1)
101 #define MII_ADDR_REG_SHIFT 6
102 #define MII_ADDR_PHY_SHIFT 11
103 #define MII_DATA_SHIFT 0
104
105 #define FLOW_CONTROL_FCE AR_BIT(1)
106
107 #define DMA_BUS_MODE_SWR AR_BIT(0) /* software reset */
108 #define DMA_BUS_MODE_BLE AR_BIT(7) /* big endian mode */
109 #define DMA_BUS_MODE_PBL_SHIFT 8 /* programmable burst length 32 */
110 #define DMA_BUS_MODE_DBO AR_BIT(20) /* big-endian descriptors */
111
112 #define DMA_STATUS_TI AR_BIT(0) /* transmit interrupt */
113 #define DMA_STATUS_TPS AR_BIT(1) /* transmit process stopped */
114 #define DMA_STATUS_TU AR_BIT(2) /* transmit buffer unavailable */
115 #define DMA_STATUS_TJT AR_BIT(3) /* transmit buffer timeout */
116 #define DMA_STATUS_UNF AR_BIT(5) /* transmit underflow */
117 #define DMA_STATUS_RI AR_BIT(6) /* receive interrupt */
118 #define DMA_STATUS_RU AR_BIT(7) /* receive buffer unavailable */
119 #define DMA_STATUS_RPS AR_BIT(8) /* receive process stopped */
120 #define DMA_STATUS_ETI AR_BIT(10) /* early transmit interrupt */
121 #define DMA_STATUS_FBE AR_BIT(13) /* fatal bus interrupt */
122 #define DMA_STATUS_ERI AR_BIT(14) /* early receive interrupt */
123 #define DMA_STATUS_AIS AR_BIT(15) /* abnormal interrupt summary */
124 #define DMA_STATUS_NIS AR_BIT(16) /* normal interrupt summary */
125 #define DMA_STATUS_RS_SHIFT 17 /* receive process state */
126 #define DMA_STATUS_TS_SHIFT 20 /* transmit process state */
127 #define DMA_STATUS_EB_SHIFT 23 /* error bits */
128
129 #define DMA_CONTROL_SR AR_BIT(1) /* start receive */
130 #define DMA_CONTROL_ST AR_BIT(13) /* start transmit */
131 #define DMA_CONTROL_SF AR_BIT(21) /* store and forward */
132
133
134 typedef struct {
135 volatile unsigned int status; // OWN, Device control and status.
136 volatile unsigned int devcs; // pkt Control bits + Length
137 volatile unsigned int addr; // Current Address.
138 volatile unsigned int descr; // Next descriptor in chain.
139 } ar2313_descr_t;
140
141
142 #endif // __ARUBA_DMA_H__