f7c45bae2ee2908f1b5994238dad9d947f3265a8
[openwrt/svn-archive/archive.git] / target / linux / atheros / files / arch / mips / atheros / ar5315 / board.c
1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
7 * Copyright (C) 2006 FON Technology, SL.
8 * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
9 * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
10 */
11
12 /*
13 * Platform devices for Atheros SoCs
14 */
15
16 #include <linux/autoconf.h>
17 #include <linux/init.h>
18 #include <linux/module.h>
19 #include <linux/types.h>
20 #include <linux/string.h>
21 #include <linux/platform_device.h>
22 #include <linux/kernel.h>
23 #include <linux/reboot.h>
24 #include <asm/bootinfo.h>
25 #include <asm/reboot.h>
26 #include <asm/time.h>
27 #include <asm/irq.h>
28 #include <asm/io.h>
29 #include <ar531x.h>
30 #include <linux/leds.h>
31 #include <asm/gpio.h>
32
33 static int is_5315 = 0;
34
35 static struct resource ar5315_eth_res[] = {
36 {
37 .name = "eth0_membase",
38 .flags = IORESOURCE_MEM,
39 .start = AR5315_ENET0,
40 .end = AR5315_ENET0 + 0x2000,
41 },
42 {
43 .name = "eth0_irq",
44 .flags = IORESOURCE_IRQ,
45 .start = AR5315_IRQ_ENET0_INTRS,
46 .end = AR5315_IRQ_ENET0_INTRS,
47 },
48 };
49
50 static struct ar531x_eth ar5315_eth_data = {
51 .phy = 1,
52 .mac = 0,
53 .reset_base = AR5315_RESET,
54 .reset_mac = AR5315_RESET_ENET0,
55 .reset_phy = AR5315_RESET_EPHY0,
56 .phy_base = AR5315_ENET0
57 };
58
59 static struct platform_device ar5315_eth = {
60 .id = 0,
61 .name = "ar531x-eth",
62 .dev.platform_data = &ar5315_eth_data,
63 .resource = ar5315_eth_res,
64 .num_resources = ARRAY_SIZE(ar5315_eth_res)
65 };
66
67 static struct platform_device ar5315_wmac = {
68 .id = 0,
69 .name = "ar531x-wmac",
70 /* FIXME: add resources */
71 };
72
73 static struct resource ar5315_spiflash_res[] = {
74 {
75 .name = "flash_base",
76 .flags = IORESOURCE_MEM,
77 .start = KSEG1ADDR(AR5315_SPI_READ),
78 .end = KSEG1ADDR(AR5315_SPI_READ) + 0x800000,
79 },
80 {
81 .name = "flash_regs",
82 .flags = IORESOURCE_MEM,
83 .start = 0x11300000,
84 .end = 0x11300012,
85 },
86 };
87
88 static struct platform_device ar5315_spiflash = {
89 .id = 0,
90 .name = "spiflash",
91 .resource = ar5315_spiflash_res,
92 .num_resources = ARRAY_SIZE(ar5315_spiflash_res)
93 };
94
95 #ifdef CONFIG_LEDS_GPIO
96 static struct gpio_led ar5315_leds[8];
97
98 static struct gpio_led_platform_data ar5315_led_data = {
99 .num_leds = ARRAY_SIZE(ar5315_leds),
100 .leds = (void *) ar5315_leds,
101 };
102
103 static struct platform_device ar5315_gpio_leds = {
104 .name = "leds-gpio",
105 .id = -1,
106 .dev = {
107 .platform_data = (void *) &ar5315_led_data,
108 }
109 };
110 #endif
111
112 static struct platform_device ar5315_wdt =
113 {
114 .id = 0,
115 .name = "ar2315_wdt",
116 };
117
118 static __initdata struct platform_device *ar5315_devs[6];
119
120 static void *flash_regs;
121
122 static inline __u32 spiflash_regread32(int reg)
123 {
124 volatile __u32 *data = (__u32 *)(flash_regs + reg);
125
126 return (*data);
127 }
128
129 static inline void spiflash_regwrite32(int reg, __u32 data)
130 {
131 volatile __u32 *addr = (__u32 *)(flash_regs + reg);
132
133 *addr = data;
134 }
135
136 #define SPI_FLASH_CTL 0x00
137 #define SPI_FLASH_OPCODE 0x04
138 #define SPI_FLASH_DATA 0x08
139
140 static __u8 spiflash_probe(void)
141 {
142 __u32 reg;
143
144 do {
145 reg = spiflash_regread32(SPI_FLASH_CTL);
146 } while (reg & SPI_CTL_BUSY);
147
148 spiflash_regwrite32(SPI_FLASH_OPCODE, 0xab);
149
150 reg = (reg & ~SPI_CTL_TX_RX_CNT_MASK) | 4 |
151 (1 << 4) | SPI_CTL_START;
152
153 spiflash_regwrite32(SPI_FLASH_CTL, reg);
154
155 do {
156 reg = spiflash_regread32(SPI_FLASH_CTL);
157 } while (reg & SPI_CTL_BUSY);
158
159 reg = (__u32) spiflash_regread32(SPI_FLASH_DATA);
160 reg &= 0xff;
161
162 return (u8) reg;
163 }
164
165
166 #define STM_8MBIT_SIGNATURE 0x13
167 #define STM_16MBIT_SIGNATURE 0x14
168 #define STM_32MBIT_SIGNATURE 0x15
169 #define STM_64MBIT_SIGNATURE 0x16
170 #define STM_128MBIT_SIGNATURE 0x17
171
172
173 static char __init *ar5315_flash_limit(void)
174 {
175 u8 sig;
176 u32 flash_size = 0;
177
178 /* probe the flash chip size */
179 flash_regs = ioremap_nocache(ar5315_spiflash_res[1].start, ar5315_spiflash_res[1].end - ar5315_spiflash_res[1].start);
180 sig = spiflash_probe();
181 iounmap(flash_regs);
182
183 switch(sig) {
184 case STM_8MBIT_SIGNATURE:
185 flash_size = 0x00100000;
186 break;
187 case STM_16MBIT_SIGNATURE:
188 flash_size = 0x00200000;
189 break;
190 case STM_32MBIT_SIGNATURE:
191 flash_size = 0x00400000;
192 break;
193 case STM_64MBIT_SIGNATURE:
194 flash_size = 0x00800000;
195 break;
196 case STM_128MBIT_SIGNATURE:
197 flash_size = 0x01000000;
198 break;
199 }
200
201 ar5315_spiflash_res[0].end = ar5315_spiflash_res[0].start + flash_size;
202 return (char *) ar5315_spiflash_res[0].end;
203 }
204
205 int __init ar5315_init_devices(void)
206 {
207 struct ar531x_config *config;
208 struct ar531x_boarddata *bcfg;
209 int dev = 0;
210 #ifdef CONFIG_LEDS_GPIO
211 int i;
212 char *tmp;
213 #endif
214
215 if (!is_5315)
216 return 0;
217
218 /* Find board configuration */
219 ar531x_find_config(ar5315_flash_limit());
220 bcfg = (struct ar531x_boarddata *) board_config;
221
222 #if 0
223 {
224 /* Detect the hardware based on the device ID */
225 u32 devid = sysRegRead(AR5315_SREV) & AR5315_REV_MAJ >> AR5315_REV_MAJ_S;
226 switch(devid) {
227 case 0x9:
228 mips_machtype = MACH_ATHEROS_AR2317;
229 break;
230 /* FIXME: how can we detect AR2316? */
231 case 0x8:
232 default:
233 mips_machtype = MACH_ATHEROS_AR2315;
234 break;
235 }
236 }
237 #endif
238
239 config = (struct ar531x_config *) kzalloc(sizeof(struct ar531x_config), GFP_KERNEL);
240 config->board = board_config;
241 config->radio = radio_config;
242 config->unit = 0;
243 config->tag = (u_int16_t) (sysRegRead(AR5315_SREV) & AR5315_REV_CHIP);
244
245 ar5315_eth_data.board_config = board_config;
246 ar5315_eth_data.macaddr = bcfg->enet0Mac;
247 ar5315_wmac.dev.platform_data = config;
248
249 ar5315_devs[dev++] = &ar5315_eth;
250 ar5315_devs[dev++] = &ar5315_wmac;
251 ar5315_devs[dev++] = &ar5315_spiflash;
252 ar5315_devs[dev++] = &ar5315_wdt;
253
254 #ifdef CONFIG_LEDS_GPIO
255 ar5315_led_data.num_leds = 0;
256 for(i = 0; i < 8; i++)
257 {
258 if((i != AR5315_RESET_GPIO) && (i != bcfg->resetConfigGpio))
259 {
260 if(i == bcfg->sysLedGpio)
261 {
262 tmp = kstrdup("wlan", GFP_KERNEL);
263 } else {
264 tmp = kmalloc(6, GFP_KERNEL);
265 if(tmp)
266 sprintf((char*)tmp, "gpio%d", i);
267 }
268 if(tmp)
269 {
270 ar5315_leds[ar5315_led_data.num_leds].name = tmp;
271 ar5315_leds[ar5315_led_data.num_leds].gpio = i;
272 ar5315_leds[ar5315_led_data.num_leds].active_low = 0;
273 ar5315_led_data.num_leds++;
274 } else {
275 printk("failed to alloc led string\n");
276 continue;
277 }
278 }
279 }
280 ar5315_devs[dev++] = &ar5315_gpio_leds;
281 #endif
282
283 return platform_add_devices(ar5315_devs, dev);
284 }
285
286 static void ar5315_halt(void)
287 {
288 while (1);
289 }
290
291 static void ar5315_power_off(void)
292 {
293 ar5315_halt();
294 }
295
296
297 static void ar5315_restart(char *command)
298 {
299 unsigned int reg;
300 for(;;) {
301 /* reset the system */
302 sysRegWrite(AR5315_COLD_RESET,AR5317_RESET_SYSTEM);
303
304 /*
305 * Cold reset does not work on the AR2315/6, use the GPIO reset bits a workaround.
306 */
307 gpio_direction_output(AR5315_RESET_GPIO, 0);
308 }
309 }
310
311
312 /*
313 * This table is indexed by bits 5..4 of the CLOCKCTL1 register
314 * to determine the predevisor value.
315 */
316 static int __initdata CLOCKCTL1_PREDIVIDE_TABLE[4] = {
317 1,
318 2,
319 4,
320 5
321 };
322
323 static int __initdata PLLC_DIVIDE_TABLE[5] = {
324 2,
325 3,
326 4,
327 6,
328 3
329 };
330
331 static unsigned int __init
332 ar5315_sys_clk(unsigned int clockCtl)
333 {
334 unsigned int pllcCtrl,cpuDiv;
335 unsigned int pllcOut,refdiv,fdiv,divby2;
336 unsigned int clkDiv;
337
338 pllcCtrl = sysRegRead(AR5315_PLLC_CTL);
339 refdiv = (pllcCtrl & PLLC_REF_DIV_M) >> PLLC_REF_DIV_S;
340 refdiv = CLOCKCTL1_PREDIVIDE_TABLE[refdiv];
341 fdiv = (pllcCtrl & PLLC_FDBACK_DIV_M) >> PLLC_FDBACK_DIV_S;
342 divby2 = (pllcCtrl & PLLC_ADD_FDBACK_DIV_M) >> PLLC_ADD_FDBACK_DIV_S;
343 divby2 += 1;
344 pllcOut = (40000000/refdiv)*(2*divby2)*fdiv;
345
346
347 /* clkm input selected */
348 switch(clockCtl & CPUCLK_CLK_SEL_M) {
349 case 0:
350 case 1:
351 clkDiv = PLLC_DIVIDE_TABLE[(pllcCtrl & PLLC_CLKM_DIV_M) >> PLLC_CLKM_DIV_S];
352 break;
353 case 2:
354 clkDiv = PLLC_DIVIDE_TABLE[(pllcCtrl & PLLC_CLKC_DIV_M) >> PLLC_CLKC_DIV_S];
355 break;
356 default:
357 pllcOut = 40000000;
358 clkDiv = 1;
359 break;
360 }
361 cpuDiv = (clockCtl & CPUCLK_CLK_DIV_M) >> CPUCLK_CLK_DIV_S;
362 cpuDiv = cpuDiv * 2 ?: 1;
363 return (pllcOut/(clkDiv * cpuDiv));
364 }
365
366 static inline unsigned int ar5315_cpu_frequency(void)
367 {
368 return ar5315_sys_clk(sysRegRead(AR5315_CPUCLK));
369 }
370
371 static inline unsigned int ar5315_apb_frequency(void)
372 {
373 return ar5315_sys_clk(sysRegRead(AR5315_AMBACLK));
374 }
375
376 static void __init ar5315_time_init(void)
377 {
378 mips_hpt_frequency = ar5315_cpu_frequency() / 2;
379 }
380
381 void __init ar5315_prom_init(void)
382 {
383 u32 memsize, memcfg;
384
385 is_5315 = 1;
386 memcfg = sysRegRead(AR5315_MEM_CFG);
387 memsize = 1 + ((memcfg & SDRAM_DATA_WIDTH_M) >> SDRAM_DATA_WIDTH_S);
388 memsize <<= 1 + ((memcfg & SDRAM_COL_WIDTH_M) >> SDRAM_COL_WIDTH_S);
389 memsize <<= 1 + ((memcfg & SDRAM_ROW_WIDTH_M) >> SDRAM_ROW_WIDTH_S);
390 memsize <<= 3;
391 add_memory_region(0, memsize, BOOT_MEM_RAM);
392
393 /* Initialize it to AR2315 for now. Real detection will be done
394 * in ar5315_init_devices() */
395 mips_machtype = MACH_ATHEROS_AR2315;
396 }
397
398 void __init ar5315_plat_setup(void)
399 {
400 unsigned int config = read_c0_config();
401
402 /* Clear any lingering AHB errors */
403 write_c0_config(config & ~0x3);
404 sysRegWrite(AR5315_AHB_ERR0,AHB_ERROR_DET);
405 sysRegRead(AR5315_AHB_ERR1);
406 sysRegWrite(AR5315_WDC, WDC_IGNORE_EXPIRATION);
407
408 board_time_init = ar5315_time_init;
409
410 _machine_restart = ar5315_restart;
411 _machine_halt = ar5315_halt;
412 pm_power_off = ar5315_power_off;
413
414 serial_setup(KSEG1ADDR(AR5315_UART0), ar5315_apb_frequency());
415 }
416
417 arch_initcall(ar5315_init_devices);