target/linux/atheros/files/arch/mips/atheros/ar5315/pci.c

   1 /*
   2  * This program is free software; you can redistribute it and/or
   3  * modify it under the terms of the GNU General Public License
   4  * as published by the Free Software Foundation; either version 2
   5  * of the License, or (at your option) any later version.
   6  *
   7  * This program is distributed in the hope that it will be useful,
   8  * but WITHOUT ANY WARRANTY; without even the implied warranty of
   9  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  10  * GNU General Public License for more details.
  11  *
  12  * You should have received a copy of the GNU General Public License
  13  * along with this program; if not, write to the Free Software
  14  * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  15  */
  16
  17 #include <linux/types.h>
  18 #include <linux/pci.h>
  19 #include <linux/kernel.h>
  20 #include <linux/init.h>
  21 #include <linux/mm.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/delay.h>
  24 #include <linux/irq.h>
  25 #include <asm/paccess.h>
  26 #include <asm/irq_cpu.h>
  27 #include <asm/io.h>
  28 #include "ar531x.h"
  29
  30 #define AR531X_MEM_BASE    0x80800000UL
  31 #define AR531X_MEM_SIZE    0x00ffffffUL
  32 #define AR531X_IO_SIZE     0x00007fffUL
  33
  34 #define IDSEL_SHIFT     13
  35
  36 static spinlock_t ar531x_pci_lock = SPIN_LOCK_UNLOCKED;
  37 static u32 cfgaddr;
  38
  39 static int config_access(int busno, int dev, int func, int where, int size, u32 ptr, int write)
  40 {
  41         u32 address;      /* Address to read from */
  42         u32 reg;
  43         unsigned long flags;
  44         int ret = -1;
  45
  46         if ((busno != 0) || (dev > 3) || (func > 2))
  47                 return ret;
  48
  49         spin_lock_irqsave(&ar531x_pci_lock, flags);
  50
  51         /* Select Configuration access */
  52         reg = sysRegRead(AR5315_PCI_MISC_CONFIG);
  53         reg |= AR5315_PCIMISC_CFG_SEL;
  54         sysRegWrite(AR5315_PCI_MISC_CONFIG, reg);
  55         (void)sysRegRead(AR5315_PCI_MISC_CONFIG);
  56
  57         address = (u32)cfgaddr + (1 << (IDSEL_SHIFT + dev)) + (func << 8) + where;
  58
  59         if (size == 1)
  60                 address ^= 0x3;
  61         else if (size == 2)
  62                 address ^= 0x2;
  63
  64         if (write) {
  65                 if (size == 1)
  66                         ret = put_dbe(ptr, (u8 *) address);
  67                 else if (size == 2)
  68                         ret = put_dbe(ptr, (u16 *) address);
  69                 else if (size == 4)
  70                         ret = put_dbe(ptr, (u32 *) address);
  71         } else {
  72                 if (size == 1)
  73                         ret = get_dbe(*((u32 *)ptr), (u8 *) address);
  74                 else if (size == 2)
  75                         ret = get_dbe(*((u32 *)ptr), (u16 *) address);
  76                 else if (size == 4)
  77                         ret = get_dbe(*((u32 *)ptr), (u32 *) address);
  78         }
  79
  80         /* Select Memory access */
  81         reg = sysRegRead(AR5315_PCI_MISC_CONFIG);
  82         reg &= ~AR5315_PCIMISC_CFG_SEL;
  83         sysRegWrite(AR5315_PCI_MISC_CONFIG, reg);
  84         (void)sysRegRead(AR5315_PCI_MISC_CONFIG);
  85
  86         spin_unlock_irqrestore(&ar531x_pci_lock, flags);
  87
  88         if (ret) {
  89                 *((u32 *)ptr) = 0xffffffff;
  90                 return PCIBIOS_DEVICE_NOT_FOUND;
  91         }
  92
  93         return PCIBIOS_SUCCESSFUL;
  94 }
  95
  96 static int ar531x_pci_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 * value)
  97 {
  98         return config_access(bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), where, size, (u32) value, 0);
  99 }
 100
 101 static int ar531x_pci_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 value)
 102 {
 103         return config_access(bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), where, size, value, 1);
 104 }
 105
 106 struct pci_ops ar531x_pci_ops = {
 107         .read   = ar531x_pci_read,
 108         .write  = ar531x_pci_write,
 109 };
 110
 111 static struct resource ar531x_mem_resource = {
 112         .name   = "AR531x PCI MEM",
 113         .start  = AR531X_MEM_BASE,
 114         .end    = AR531X_MEM_BASE + AR531X_MEM_SIZE - AR531X_IO_SIZE - 1,
 115         .flags  = IORESOURCE_MEM,
 116 };
 117
 118 static struct resource ar531x_io_resource = {
 119         .name   = "AR531x PCI I/O",
 120         .start  = 0,
 121         .end    = AR531X_IO_SIZE,
 122         .flags  = IORESOURCE_IO,
 123 };
 124
 125 struct pci_controller ar531x_pci_controller = {
 126         .pci_ops        = &ar531x_pci_ops,
 127         .mem_resource   = &ar531x_mem_resource,
 128         .io_resource    = &ar531x_io_resource,
 129 };
 130
 131 int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 132 {
 133         return AR5315_IRQ_LCBUS_PCI;
 134 }
 135
 136 int pcibios_plat_dev_init(struct pci_dev *dev)
 137 {
 138         u32 reg;
 139
 140         pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 5);
 141         pci_write_config_word(dev, 0x40, 0);
 142
 143         /* Clear any pending Abort or external Interrupts
 144          * and enable interrupt processing */
 145         reg = sysRegRead(AR5315_PCI_INTEN_REG);
 146         reg &= ~AR5315_PCI_INT_ENABLE;
 147         sysRegWrite(AR5315_PCI_INTEN_REG, reg);
 148
 149         reg = sysRegRead(AR5315_PCI_INT_STATUS);
 150         reg |= (AR5315_PCI_ABORT_INT | AR5315_PCI_EXT_INT);
 151         sysRegWrite(AR5315_PCI_INT_STATUS, reg);
 152
 153         reg = sysRegRead(AR5315_PCI_INT_MASK);
 154         reg |= (AR5315_PCI_EXT_INT | AR5315_PCI_ABORT_INT);
 155         sysRegWrite(AR5315_PCI_INT_MASK, reg);
 156
 157         reg = sysRegRead(AR5315_PCI_INTEN_REG);
 158         reg |= AR5315_PCI_INT_ENABLE;
 159         sysRegWrite(AR5315_PCI_INTEN_REG, reg);
 160
 161         return 0;
 162 }
 163
 164 static void ar5315_pci_fixup(struct pci_dev *dev)
 165 {
 166         struct pci_bus *bus = dev->bus;
 167
 168         if ((PCI_SLOT(dev->devfn) != 3) || (PCI_FUNC(dev->devfn) != 0) || (bus->number != 0))
 169                 return;
 170
 171 #define _DEV    bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn)
 172         printk("PCI: fixing up device %d,%d,%d\n", _DEV);
 173         /* fix up mbars */
 174         config_access(_DEV, PCI_BASE_ADDRESS_0, 4, HOST_PCI_MBAR0, 1);
 175         config_access(_DEV, PCI_BASE_ADDRESS_1, 4, HOST_PCI_MBAR1, 1);
 176         config_access(_DEV, PCI_BASE_ADDRESS_2, 4, HOST_PCI_MBAR2, 1);
 177         config_access(_DEV, PCI_COMMAND, 4,
 178                 PCI_COMMAND_MEMORY|PCI_COMMAND_MASTER|PCI_COMMAND_SPECIAL|
 179                 PCI_COMMAND_INVALIDATE|PCI_COMMAND_PARITY|PCI_COMMAND_SERR|
 180                 PCI_COMMAND_FAST_BACK, 1);
 181 #undef _DEV
 182 }
 183 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, ar5315_pci_fixup);
 184
 185 int __init ar5315_pci_init(void)
 186 {
 187         u32 reg;
 188
 189         printk("AR531x PCI init... ");
 190
 191         cfgaddr = (u32) ioremap_nocache(0x80000000, 1*1024*1024); /* Remap PCI config space */
 192         set_io_port_base((unsigned long) ioremap_nocache(AR531X_MEM_BASE + AR531X_IO_SIZE - 1, AR531X_IO_SIZE)); /* PCI I/O space */
 193
 194         reg = sysRegRead(AR5315_RESET);
 195         sysRegWrite(AR5315_RESET, reg | AR5315_RESET_PCIDMA);
 196
 197         udelay(10*1000);
 198
 199         sysRegWrite(AR5315_RESET, reg & ~AR5315_RESET_PCIDMA);
 200         sysRegRead(AR5315_RESET);     /* read after */
 201
 202         udelay(10*1000);
 203
 204         reg = sysRegRead(AR5315_ENDIAN_CTL);
 205         reg |= AR5315_CONFIG_PCIAHB | AR5315_CONFIG_PCIAHB_BRIDGE;
 206
 207         sysRegWrite(AR5315_ENDIAN_CTL, reg);
 208
 209         reg = sysRegRead(AR5315_PCICLK);
 210         reg = 4;
 211         sysRegWrite(AR5315_PCICLK, reg);
 212
 213         reg = sysRegRead(AR5315_AHB_ARB_CTL);
 214         reg |= (ARB_PCI);
 215         sysRegWrite(AR5315_AHB_ARB_CTL, reg);
 216
 217         reg = sysRegRead(AR5315_IF_CTL);
 218         reg &= ~(IF_PCI_CLK_MASK | IF_MASK);
 219         reg |= (IF_PCI | IF_PCI_HOST | IF_PCI_INTR | (IF_PCI_CLK_OUTPUT_CLK << IF_PCI_CLK_SHIFT));
 220
 221         sysRegWrite(AR5315_IF_CTL, reg);
 222
 223         /* Reset the PCI bus by setting bits 5-4 in PCI_MCFG */
 224         reg = sysRegRead(AR5315_PCI_MISC_CONFIG);
 225         reg &= ~(AR5315_PCIMISC_RST_MODE);
 226         reg |= AR5315_PCIRST_LOW;
 227         sysRegWrite(AR5315_PCI_MISC_CONFIG, reg);
 228
 229         /* wait for 100 ms */
 230         udelay(100*1000);
 231
 232         /* Bring the PCI out of reset */
 233         reg = sysRegRead(AR5315_PCI_MISC_CONFIG);
 234         reg &= ~(AR5315_PCIMISC_RST_MODE);
 235         reg |= (AR5315_PCIRST_HIGH | AR5315_PCICACHE_DIS | 0x8);
 236         sysRegWrite(AR5315_PCI_MISC_CONFIG, reg);
 237
 238         sysRegWrite(AR5315_PCI_UNCACHE_CFG,
 239                         0x1E | /* 1GB uncached */
 240                         (1 << 5) | /* Enable uncached */
 241                         (0x2 << 30) /* Base: 0x80000000 */
 242         );
 243         (void)sysRegRead(AR5315_PCI_UNCACHE_CFG); /* flush */
 244
 245         udelay(500*1000);
 246
 247         register_pci_controller(&ar531x_pci_controller);
 248
 249         printk("done\n");
 250         return 0;
 251 }
 252
 253 arch_initcall(ar5315_pci_init);