atheros: split out the pci support patch
[openwrt/svn-archive/archive.git] / target / linux / atheros / patches-2.6.28 / 105-ar2315_pci.patch
1 --- a/arch/mips/ar231x/Makefile
2 +++ b/arch/mips/ar231x/Makefile
3 @@ -11,3 +11,4 @@
4 obj-y += board.o prom.o devices.o
5 obj-$(CONFIG_ATHEROS_AR5312) += ar5312.o
6 obj-$(CONFIG_ATHEROS_AR2315) += ar2315.o
7 +obj-$(CONFIG_ATHEROS_AR2315_PCI) += pci.o
8 --- /dev/null
9 +++ b/arch/mips/ar231x/pci.c
10 @@ -0,0 +1,231 @@
11 +/*
12 + * This program is free software; you can redistribute it and/or
13 + * modify it under the terms of the GNU General Public License
14 + * as published by the Free Software Foundation; either version 2
15 + * of the License, or (at your option) any later version.
16 + *
17 + * This program is distributed in the hope that it will be useful,
18 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 + * GNU General Public License for more details.
21 + *
22 + * You should have received a copy of the GNU General Public License
23 + * along with this program; if not, write to the Free Software
24 + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
25 + */
26 +
27 +#include <linux/types.h>
28 +#include <linux/pci.h>
29 +#include <linux/kernel.h>
30 +#include <linux/init.h>
31 +#include <linux/mm.h>
32 +#include <linux/spinlock.h>
33 +#include <linux/delay.h>
34 +#include <linux/irq.h>
35 +#include <asm/bootinfo.h>
36 +#include <asm/paccess.h>
37 +#include <asm/irq_cpu.h>
38 +#include <asm/io.h>
39 +#include <ar231x_platform.h>
40 +#include <ar231x.h>
41 +#include <ar2315_regs.h>
42 +
43 +#define AR531X_MEM_BASE 0x80800000UL
44 +#define AR531X_MEM_SIZE 0x00ffffffUL
45 +#define AR531X_IO_SIZE 0x00007fffUL
46 +
47 +#define IS_2315() (current_cpu_data.cputype == CPU_4KEC)
48 +
49 +static unsigned long configspace;
50 +
51 +static int config_access(int devfn, int where, int size, u32 *ptr, bool write)
52 +{
53 + unsigned long flags;
54 + int func = PCI_FUNC(devfn);
55 + int dev = PCI_SLOT(devfn);
56 + u32 value = 0;
57 + int err = 0;
58 + u32 addr;
59 +
60 + if (((dev != 0) && (dev != 3)) || (func > 2))
61 + return PCIBIOS_DEVICE_NOT_FOUND;
62 +
63 + /* Select Configuration access */
64 + local_irq_save(flags);
65 + ar231x_mask_reg(AR2315_PCI_MISC_CONFIG, 0, AR2315_PCIMISC_CFG_SEL);
66 + mb();
67 +
68 + addr = (u32) configspace + (1 << (13 + dev)) + (func << 8) + where;
69 + if (size == 1)
70 + addr ^= 0x3;
71 + else if (size == 2)
72 + addr ^= 0x2;
73 +
74 + if (write) {
75 + value = *ptr;
76 + if (size == 1)
77 + err = put_dbe(value, (u8 *) addr);
78 + else if (size == 2)
79 + err = put_dbe(value, (u16 *) addr);
80 + else if (size == 4)
81 + err = put_dbe(value, (u32 *) addr);
82 + } else {
83 + if (size == 1)
84 + err = get_dbe(value, (u8 *) addr);
85 + else if (size == 2)
86 + err = get_dbe(value, (u16 *) addr);
87 + else if (size == 4)
88 + err = get_dbe(value, (u32 *) addr);
89 + if (err)
90 + *ptr = 0xffffffff;
91 + else
92 + *ptr = value;
93 + }
94 +
95 + /* Select Memory access */
96 + ar231x_mask_reg(AR2315_PCI_MISC_CONFIG, AR2315_PCIMISC_CFG_SEL, 0);
97 + local_irq_restore(flags);
98 +
99 + return (err ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL);
100 +}
101 +
102 +static int ar231x_pci_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 * value)
103 +{
104 + return config_access(devfn, where, size, value, 0);
105 +}
106 +
107 +static int ar231x_pci_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 value)
108 +{
109 + return config_access(devfn, where, size, &value, 1);
110 +}
111 +
112 +struct pci_ops ar231x_pci_ops = {
113 + .read = ar231x_pci_read,
114 + .write = ar231x_pci_write,
115 +};
116 +
117 +static struct resource ar231x_mem_resource = {
118 + .name = "AR531x PCI MEM",
119 + .start = AR531X_MEM_BASE,
120 + .end = AR531X_MEM_BASE + AR531X_MEM_SIZE - AR531X_IO_SIZE - 1 + 0x4000000,
121 + .flags = IORESOURCE_MEM,
122 +};
123 +
124 +static struct resource ar231x_io_resource = {
125 + .name = "AR531x PCI I/O",
126 + .start = AR531X_MEM_BASE + AR531X_MEM_SIZE - AR531X_IO_SIZE,
127 + .end = AR531X_MEM_BASE + AR531X_MEM_SIZE - 1,
128 + .flags = IORESOURCE_IO,
129 +};
130 +
131 +struct pci_controller ar231x_pci_controller = {
132 + .pci_ops = &ar231x_pci_ops,
133 + .mem_resource = &ar231x_mem_resource,
134 + .io_resource = &ar231x_io_resource,
135 + .mem_offset = 0x00000000UL,
136 + .io_offset = 0x00000000UL,
137 +};
138 +
139 +int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
140 +{
141 + return AR2315_IRQ_LCBUS_PCI;
142 +}
143 +
144 +int pcibios_plat_dev_init(struct pci_dev *dev)
145 +{
146 + pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 5);
147 + pci_write_config_word(dev, 0x40, 0);
148 +
149 + /* Clear any pending Abort or external Interrupts
150 + * and enable interrupt processing */
151 + ar231x_mask_reg(AR2315_PCI_INTEN_REG, AR2315_PCI_INT_ENABLE, 0);
152 + ar231x_write_reg(AR2315_PCI_INT_STATUS, (AR2315_PCI_ABORT_INT | AR2315_PCI_EXT_INT));
153 + ar231x_write_reg(AR2315_PCI_INT_MASK, (AR2315_PCI_ABORT_INT | AR2315_PCI_EXT_INT));
154 + ar231x_mask_reg(AR2315_PCI_INTEN_REG, 0, AR2315_PCI_INT_ENABLE);
155 +
156 + return 0;
157 +}
158 +
159 +static void
160 +ar2315_pci_fixup(struct pci_dev *dev)
161 +{
162 + unsigned int devfn = dev->devfn;
163 +
164 + if (dev->bus->number != 0)
165 + return;
166 +
167 + /* Only fix up the PCI host settings */
168 + if ((PCI_SLOT(devfn) != 3) || (PCI_FUNC(devfn) != 0))
169 + return;
170 +
171 + /* Fix up MBARs */
172 + pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, HOST_PCI_MBAR0);
173 + pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, HOST_PCI_MBAR1);
174 + pci_write_config_dword(dev, PCI_BASE_ADDRESS_2, HOST_PCI_MBAR2);
175 + pci_write_config_dword(dev, PCI_COMMAND,
176 + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL |
177 + PCI_COMMAND_INVALIDATE | PCI_COMMAND_PARITY | PCI_COMMAND_SERR |
178 + PCI_COMMAND_FAST_BACK);
179 +}
180 +DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, ar2315_pci_fixup);
181 +
182 +static int __init
183 +ar2315_pci_init(void)
184 +{
185 + u32 reg;
186 +
187 + if (!IS_2315())
188 + return -ENODEV;
189 +
190 + configspace = (unsigned long) ioremap_nocache(0x80000000, 1*1024*1024); /* Remap PCI config space */
191 + ar231x_pci_controller.io_map_base =
192 + (unsigned long) ioremap_nocache(AR531X_MEM_BASE + AR531X_MEM_SIZE, AR531X_IO_SIZE);
193 + set_io_port_base(ar231x_pci_controller.io_map_base); /* PCI I/O space */
194 +
195 + reg = ar231x_mask_reg(AR2315_RESET, 0, AR2315_RESET_PCIDMA);
196 + msleep(10);
197 +
198 + reg &= ~AR2315_RESET_PCIDMA;
199 + ar231x_write_reg(AR2315_RESET, reg);
200 + msleep(10);
201 +
202 + ar231x_mask_reg(AR2315_ENDIAN_CTL, 0,
203 + AR2315_CONFIG_PCIAHB | AR2315_CONFIG_PCIAHB_BRIDGE);
204 +
205 + ar231x_write_reg(AR2315_PCICLK, AR2315_PCICLK_PLLC_CLKM |
206 + (AR2315_PCICLK_IN_FREQ_DIV_6 << AR2315_PCICLK_DIV_S));
207 + ar231x_mask_reg(AR2315_AHB_ARB_CTL, 0, AR2315_ARB_PCI);
208 + ar231x_mask_reg(AR2315_IF_CTL, AR2315_IF_PCI_CLK_MASK | AR2315_IF_MASK,
209 + AR2315_IF_PCI | AR2315_IF_PCI_HOST | AR2315_IF_PCI_INTR |
210 + (AR2315_IF_PCI_CLK_OUTPUT_CLK << AR2315_IF_PCI_CLK_SHIFT));
211 +
212 + /* Reset the PCI bus by setting bits 5-4 in PCI_MCFG */
213 + ar231x_mask_reg(AR2315_PCI_MISC_CONFIG, AR2315_PCIMISC_RST_MODE,
214 + AR2315_PCIRST_LOW);
215 + msleep(100);
216 +
217 + /* Bring the PCI out of reset */
218 + ar231x_mask_reg(AR2315_PCI_MISC_CONFIG, AR2315_PCIMISC_RST_MODE,
219 + AR2315_PCIRST_HIGH | AR2315_PCICACHE_DIS | 0x8);
220 +
221 + ar231x_write_reg(AR2315_PCI_UNCACHE_CFG,
222 + 0x1E | /* 1GB uncached */
223 + (1 << 5) | /* Enable uncached */
224 + (0x2 << 30) /* Base: 0x80000000 */
225 + );
226 + ar231x_read_reg(AR2315_PCI_UNCACHE_CFG);
227 +
228 + msleep(500);
229 +
230 + /* dirty hack - anyone with a datasheet that knows the memory map ? */
231 + ioport_resource.start = 0x10000000;
232 + ioport_resource.end = 0xffffffff;
233 + iomem_resource.start = 0x10000000;
234 + iomem_resource.end = 0xffffffff;
235 +
236 + register_pci_controller(&ar231x_pci_controller);
237 +
238 + return 0;
239 +}
240 +
241 +arch_initcall(ar2315_pci_init);
242 --- a/arch/mips/ar231x/Kconfig
243 +++ b/arch/mips/ar231x/Kconfig
244 @@ -15,3 +15,13 @@ config ATHEROS_AR2315
245 select SYS_SUPPORTS_BIG_ENDIAN
246 select GENERIC_GPIO
247 default y
248 +
249 +config ATHEROS_AR2315_PCI
250 + bool "PCI support"
251 + depends on ATHEROS_AR2315
252 + select HW_HAS_PCI
253 + select PCI
254 + select USB_ARCH_HAS_HCD
255 + select USB_ARCH_HAS_OHCI
256 + select USB_ARCH_HAS_EHCI
257 + default y
258 --- a/arch/mips/ar231x/ar2315.c
259 +++ b/arch/mips/ar231x/ar2315.c
260 @@ -61,6 +61,27 @@ static inline void ar2315_gpio_irq(void)
261 do_IRQ(AR531X_GPIO_IRQ_BASE + fls(pend) - 1);
262 }
263
264 +#ifdef CONFIG_ATHEROS_AR2315_PCI
265 +static inline void pci_abort_irq(void)
266 +{
267 + ar231x_write_reg(AR2315_PCI_INT_STATUS, AR2315_PCI_ABORT_INT);
268 +}
269 +
270 +static inline void pci_ack_irq(void)
271 +{
272 + ar231x_write_reg(AR2315_PCI_INT_STATUS, AR2315_PCI_EXT_INT);
273 +}
274 +
275 +void ar2315_pci_irq(int irq)
276 +{
277 + if (ar231x_read_reg(AR2315_PCI_INT_STATUS) == AR2315_PCI_ABORT_INT)
278 + pci_abort_irq();
279 + else {
280 + do_IRQ(irq);
281 + pci_ack_irq();
282 + }
283 +}
284 +#endif /* CONFIG_ATHEROS_AR2315_PCI */
285
286 /*
287 * Called when an interrupt is received, this function
288 @@ -79,6 +100,10 @@ ar2315_irq_dispatch(void)
289 do_IRQ(AR2315_IRQ_WLAN0_INTRS);
290 else if (pending & CAUSEF_IP4)
291 do_IRQ(AR2315_IRQ_ENET0_INTRS);
292 +#ifdef CONFIG_ATHEROS_AR2315_PCI
293 + else if (pending & CAUSEF_IP5)
294 + ar2315_pci_irq(AR2315_IRQ_LCBUS_PCI);
295 +#endif
296 else if (pending & CAUSEF_IP2) {
297 unsigned int misc_intr = ar231x_read_reg(AR2315_ISR) & ar231x_read_reg(AR2315_IMR);
298