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97d51f47982db55c3603c4f35dcd04518f02d71b
[openwrt/svn-archive/archive.git] / target / linux / atheros / patches-2.6.37 / 100-board.patch
1 --- a/arch/mips/Kconfig
2 +++ b/arch/mips/Kconfig
3 @@ -102,6 +102,19 @@ config BCM63XX
4 help
5 Support for BCM63XX based boards
6
7 +config ATHEROS_AR231X
8 + bool "Atheros 231x/531x SoC support"
9 + select CEVT_R4K
10 + select CSRC_R4K
11 + select DMA_NONCOHERENT
12 + select IRQ_CPU
13 + select SYS_HAS_CPU_MIPS32_R1
14 + select SYS_SUPPORTS_BIG_ENDIAN
15 + select SYS_SUPPORTS_32BIT_KERNEL
16 + select GENERIC_GPIO
17 + help
18 + Support for AR231x and AR531x based boards
19 +
20 config MIPS_COBALT
21 bool "Cobalt Server"
22 select CEVT_R4K
23 @@ -716,6 +729,7 @@ config CAVIUM_OCTEON_REFERENCE_BOARD
24
25 endchoice
26
27 +source "arch/mips/ar231x/Kconfig"
28 source "arch/mips/alchemy/Kconfig"
29 source "arch/mips/bcm63xx/Kconfig"
30 source "arch/mips/jazz/Kconfig"
31 --- a/arch/mips/Kbuild.platforms
32 +++ b/arch/mips/Kbuild.platforms
33 @@ -5,6 +5,7 @@ platforms += ar7
34 platforms += bcm47xx
35 platforms += bcm63xx
36 platforms += cavium-octeon
37 +platforms += ar231x
38 platforms += cobalt
39 platforms += dec
40 platforms += emma
41 --- /dev/null
42 +++ b/arch/mips/ar231x/Platform
43 @@ -0,0 +1,6 @@
44 +#
45 +# Atheros AR5312/AR2312 WiSoC
46 +#
47 +platform-$(CONFIG_ATHEROS_AR231X) += ar231x/
48 +cflags-$(CONFIG_ATHEROS_AR231X) += -I$(srctree)/arch/mips/include/asm/mach-ar231x
49 +load-$(CONFIG_ATHEROS_AR231X) += 0xffffffff80041000
50 --- /dev/null
51 +++ b/arch/mips/ar231x/Kconfig
52 @@ -0,0 +1,17 @@
53 +config ATHEROS_AR5312
54 + bool "Atheros 5312/2312+ support"
55 + depends on ATHEROS_AR231X
56 + default y
57 +
58 +config ATHEROS_AR2315
59 + bool "Atheros 2315+ support"
60 + depends on ATHEROS_AR231X
61 + select DMA_NONCOHERENT
62 + select CEVT_R4K
63 + select CSRC_R4K
64 + select IRQ_CPU
65 + select SYS_HAS_CPU_MIPS32_R1
66 + select SYS_SUPPORTS_32BIT_KERNEL
67 + select SYS_SUPPORTS_BIG_ENDIAN
68 + select GENERIC_GPIO
69 + default y
70 --- /dev/null
71 +++ b/arch/mips/ar231x/Makefile
72 @@ -0,0 +1,13 @@
73 +#
74 +# This file is subject to the terms and conditions of the GNU General Public
75 +# License. See the file "COPYING" in the main directory of this archive
76 +# for more details.
77 +#
78 +# Copyright (C) 2006 FON Technology, SL.
79 +# Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
80 +# Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
81 +#
82 +
83 +obj-y += board.o prom.o devices.o
84 +obj-$(CONFIG_ATHEROS_AR5312) += ar5312.o
85 +obj-$(CONFIG_ATHEROS_AR2315) += ar2315.o
86 --- /dev/null
87 +++ b/arch/mips/ar231x/board.c
88 @@ -0,0 +1,251 @@
89 +/*
90 + * This file is subject to the terms and conditions of the GNU General Public
91 + * License. See the file "COPYING" in the main directory of this archive
92 + * for more details.
93 + *
94 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
95 + * Copyright (C) 2006 FON Technology, SL.
96 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
97 + * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
98 + */
99 +
100 +#include <generated/autoconf.h>
101 +#include <linux/init.h>
102 +#include <linux/module.h>
103 +#include <linux/types.h>
104 +#include <linux/string.h>
105 +#include <linux/platform_device.h>
106 +#include <linux/kernel.h>
107 +#include <linux/random.h>
108 +#include <linux/etherdevice.h>
109 +#include <asm/irq_cpu.h>
110 +#include <asm/reboot.h>
111 +#include <asm/io.h>
112 +
113 +#include <ar231x_platform.h>
114 +#include "devices.h"
115 +#include "ar5312.h"
116 +#include "ar2315.h"
117 +
118 +void (*ar231x_irq_dispatch)(void);
119 +
120 +static inline bool
121 +check_radio_magic(u8 *addr)
122 +{
123 + addr += 0x7a; /* offset for flash magic */
124 + if ((addr[0] == 0x5a) && (addr[1] == 0xa5)) {
125 + return 1;
126 + }
127 + return 0;
128 +}
129 +
130 +static inline bool
131 +check_board_data(u8 *flash_limit, u8 *addr, bool broken)
132 +{
133 + /* config magic found */
134 + if (*((u32 *)addr) == AR531X_BD_MAGIC)
135 + return 1;
136 +
137 + if (!broken)
138 + return 0;
139 +
140 + if (check_radio_magic(addr + 0xf8))
141 + ar231x_board.radio = addr + 0xf8;
142 + if ((addr < flash_limit + 0x10000) &&
143 + check_radio_magic(addr + 0x10000))
144 + ar231x_board.radio = addr + 0x10000;
145 +
146 + if (ar231x_board.radio) {
147 + /* broken board data detected, use radio data to find the offset,
148 + * user will fix this */
149 + return 1;
150 + }
151 + return 0;
152 +}
153 +
154 +static u8 *
155 +find_board_config(u8 *flash_limit, bool broken)
156 +{
157 + u8 *addr;
158 + int found = 0;
159 +
160 + for (addr = flash_limit - 0x1000;
161 + addr >= flash_limit - 0x30000;
162 + addr -= 0x1000) {
163 +
164 + if (check_board_data(flash_limit, addr, broken)) {
165 + found = 1;
166 + break;
167 + }
168 + }
169 +
170 + if (!found)
171 + addr = NULL;
172 +
173 + return addr;
174 +}
175 +
176 +static u8 *
177 +find_radio_config(u8 *flash_limit, u8 *board_config)
178 +{
179 + int found;
180 + u8 *radio_config;
181 +
182 + /*
183 + * Now find the start of Radio Configuration data, using heuristics:
184 + * Search forward from Board Configuration data by 0x1000 bytes
185 + * at a time until we find non-0xffffffff.
186 + */
187 + found = 0;
188 + for (radio_config = board_config + 0x1000;
189 + (radio_config < flash_limit);
190 + radio_config += 0x1000) {
191 + if ((*(u32 *)radio_config != 0xffffffff) &&
192 + check_radio_magic(radio_config)) {
193 + found = 1;
194 + break;
195 + }
196 + }
197 +
198 + /* AR2316 relocates radio config to new location */
199 + if (!found) {
200 + for (radio_config = board_config + 0xf8;
201 + (radio_config < flash_limit - 0x1000 + 0xf8);
202 + radio_config += 0x1000) {
203 + if ((*(u32 *)radio_config != 0xffffffff) &&
204 + check_radio_magic(radio_config)) {
205 + found = 1;
206 + break;
207 + }
208 + }
209 + }
210 +
211 + if (!found) {
212 + printk("Could not find Radio Configuration data\n");
213 + radio_config = 0;
214 + }
215 +
216 + return (u8 *) radio_config;
217 +}
218 +
219 +int __init
220 +ar231x_find_config(u8 *flash_limit)
221 +{
222 + struct ar231x_boarddata *config;
223 + unsigned int rcfg_size;
224 + int broken_boarddata = 0;
225 + u8 *bcfg, *rcfg;
226 + u8 *board_data;
227 + u8 *radio_data;
228 + u32 offset;
229 +
230 + ar231x_board.config = NULL;
231 + ar231x_board.radio = NULL;
232 + /* Copy the board and radio data to RAM, because accessing the mapped
233 + * memory of the flash directly after booting is not safe */
234 +
235 + /* Try to find valid board and radio data */
236 + bcfg = find_board_config(flash_limit, false);
237 +
238 + /* If that fails, try to at least find valid radio data */
239 + if (!bcfg) {
240 + bcfg = find_board_config(flash_limit, true);
241 + broken_boarddata = 1;
242 + }
243 +
244 + if (!bcfg) {
245 + printk(KERN_WARNING "WARNING: No board configuration data found!\n");
246 + return -ENODEV;
247 + }
248 +
249 + board_data = kzalloc(BOARD_CONFIG_BUFSZ, GFP_KERNEL);
250 + ar231x_board.config = (struct ar231x_boarddata *) board_data;
251 + memcpy(board_data, bcfg, 0x100);
252 + if (broken_boarddata) {
253 + printk(KERN_WARNING "WARNING: broken board data detected\n");
254 + config = ar231x_board.config;
255 + if (!memcmp(config->enet0_mac, "\x00\x00\x00\x00\x00\x00", 6)) {
256 + printk(KERN_INFO "Fixing up empty mac addresses\n");
257 + config->resetConfigGpio = 0xffff;
258 + config->sysLedGpio = 0xffff;
259 + random_ether_addr(config->wlan0_mac);
260 + config->wlan0_mac[0] &= ~0x06;
261 + random_ether_addr(config->enet0_mac);
262 + random_ether_addr(config->enet1_mac);
263 + }
264 + }
265 +
266 +
267 + /* Radio config starts 0x100 bytes after board config, regardless
268 + * of what the physical layout on the flash chip looks like */
269 +
270 + if (ar231x_board.radio)
271 + rcfg = (u8 *) ar231x_board.radio;
272 + else
273 + rcfg = find_radio_config(flash_limit, bcfg);
274 +
275 + if (!rcfg)
276 + return -ENODEV;
277 +
278 + radio_data = board_data + 0x100 + ((rcfg - bcfg) & 0xfff);
279 + ar231x_board.radio = radio_data;
280 + offset = radio_data - board_data;
281 + printk(KERN_INFO "Radio config found at offset 0x%x(0x%x)\n", rcfg - bcfg, offset);
282 + rcfg_size = BOARD_CONFIG_BUFSZ - offset;
283 + memcpy(radio_data, rcfg, rcfg_size);
284 +
285 + return 0;
286 +}
287 +
288 +static void
289 +ar231x_halt(void)
290 +{
291 + local_irq_disable();
292 + while (1);
293 +}
294 +
295 +void __init
296 +plat_mem_setup(void)
297 +{
298 + _machine_halt = ar231x_halt;
299 + pm_power_off = ar231x_halt;
300 +
301 + ar5312_plat_setup();
302 + ar2315_plat_setup();
303 +
304 + /* Disable data watchpoints */
305 + write_c0_watchlo0(0);
306 +}
307 +
308 +
309 +asmlinkage void
310 +plat_irq_dispatch(void)
311 +{
312 + ar231x_irq_dispatch();
313 +}
314 +
315 +void __init
316 +plat_time_init(void)
317 +{
318 + ar5312_time_init();
319 + ar2315_time_init();
320 +}
321 +
322 +unsigned int __cpuinit
323 +get_c0_compare_int(void)
324 +{
325 + return CP0_LEGACY_COMPARE_IRQ;
326 +}
327 +
328 +void __init
329 +arch_init_irq(void)
330 +{
331 + clear_c0_status(ST0_IM);
332 + mips_cpu_irq_init();
333 +
334 + /* Initialize interrupt controllers */
335 + ar5312_irq_init();
336 + ar2315_irq_init();
337 +}
338 +
339 +
340 --- /dev/null
341 +++ b/arch/mips/ar231x/prom.c
342 @@ -0,0 +1,37 @@
343 +/*
344 + * This file is subject to the terms and conditions of the GNU General Public
345 + * License. See the file "COPYING" in the main directory of this archive
346 + * for more details.
347 + *
348 + * Copyright MontaVista Software Inc
349 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
350 + * Copyright (C) 2006 FON Technology, SL.
351 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
352 + * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
353 + */
354 +
355 +/*
356 + * Prom setup file for ar531x
357 + */
358 +
359 +#include <linux/init.h>
360 +#include <generated/autoconf.h>
361 +#include <linux/kernel.h>
362 +#include <linux/string.h>
363 +#include <linux/mm.h>
364 +#include <linux/bootmem.h>
365 +
366 +#include <asm/bootinfo.h>
367 +#include <asm/addrspace.h>
368 +#include "ar5312.h"
369 +#include "ar2315.h"
370 +
371 +void __init prom_init(void)
372 +{
373 + ar5312_prom_init();
374 + ar2315_prom_init();
375 +}
376 +
377 +void __init prom_free_prom_memory(void)
378 +{
379 +}
380 --- /dev/null
381 +++ b/arch/mips/include/asm/mach-ar231x/ar231x_platform.h
382 @@ -0,0 +1,83 @@
383 +#ifndef __AR531X_PLATFORM_H
384 +#define __AR531X_PLATFORM_H
385 +
386 +/*
387 + * This is board-specific data that is stored in a "fixed" location in flash.
388 + * It is shared across operating systems, so it should not be changed lightly.
389 + * The main reason we need it is in order to extract the ethernet MAC
390 + * address(es).
391 + */
392 +struct ar231x_boarddata {
393 + u32 magic; /* board data is valid */
394 +#define AR531X_BD_MAGIC 0x35333131 /* "5311", for all 531x platforms */
395 + u16 cksum; /* checksum (starting with BD_REV 2) */
396 + u16 rev; /* revision of this struct */
397 +#define BD_REV 4
398 + char boardName[64]; /* Name of board */
399 + u16 major; /* Board major number */
400 + u16 minor; /* Board minor number */
401 + u32 flags; /* Board configuration */
402 +#define BD_ENET0 0x00000001 /* ENET0 is stuffed */
403 +#define BD_ENET1 0x00000002 /* ENET1 is stuffed */
404 +#define BD_UART1 0x00000004 /* UART1 is stuffed */
405 +#define BD_UART0 0x00000008 /* UART0 is stuffed (dma) */
406 +#define BD_RSTFACTORY 0x00000010 /* Reset factory defaults stuffed */
407 +#define BD_SYSLED 0x00000020 /* System LED stuffed */
408 +#define BD_EXTUARTCLK 0x00000040 /* External UART clock */
409 +#define BD_CPUFREQ 0x00000080 /* cpu freq is valid in nvram */
410 +#define BD_SYSFREQ 0x00000100 /* sys freq is set in nvram */
411 +#define BD_WLAN0 0x00000200 /* Enable WLAN0 */
412 +#define BD_MEMCAP 0x00000400 /* CAP SDRAM @ memCap for testing */
413 +#define BD_DISWATCHDOG 0x00000800 /* disable system watchdog */
414 +#define BD_WLAN1 0x00001000 /* Enable WLAN1 (ar5212) */
415 +#define BD_ISCASPER 0x00002000 /* FLAG for AR2312 */
416 +#define BD_WLAN0_2G_EN 0x00004000 /* FLAG for radio0_2G */
417 +#define BD_WLAN0_5G_EN 0x00008000 /* FLAG for radio0_2G */
418 +#define BD_WLAN1_2G_EN 0x00020000 /* FLAG for radio0_2G */
419 +#define BD_WLAN1_5G_EN 0x00040000 /* FLAG for radio0_2G */
420 + u16 resetConfigGpio; /* Reset factory GPIO pin */
421 + u16 sysLedGpio; /* System LED GPIO pin */
422 +
423 + u32 cpuFreq; /* CPU core frequency in Hz */
424 + u32 sysFreq; /* System frequency in Hz */
425 + u32 cntFreq; /* Calculated C0_COUNT frequency */
426 +
427 + u8 wlan0_mac[6];
428 + u8 enet0_mac[6];
429 + u8 enet1_mac[6];
430 +
431 + u16 pciId; /* Pseudo PCIID for common code */
432 + u16 memCap; /* cap bank1 in MB */
433 +
434 + /* version 3 */
435 + u8 wlan1_mac[6]; /* (ar5212) */
436 +};
437 +
438 +#define BOARD_CONFIG_BUFSZ 0x1000
439 +
440 +/*
441 + * Platform device information for the Wireless MAC
442 + */
443 +struct ar231x_board_config {
444 + u16 devid;
445 +
446 + /* board config data */
447 + struct ar231x_boarddata *config;
448 +
449 + /* radio calibration data */
450 + const char *radio;
451 +};
452 +
453 +/*
454 + * Platform device information for the Ethernet MAC
455 + */
456 +struct ar231x_eth {
457 + u32 reset_base;
458 + u32 reset_mac;
459 + u32 reset_phy;
460 + u32 phy_base;
461 + struct ar231x_board_config *config;
462 + char *macaddr;
463 +};
464 +
465 +#endif /* __AR531X_PLATFORM_H */
466 --- /dev/null
467 +++ b/arch/mips/include/asm/mach-ar231x/cpu-feature-overrides.h
468 @@ -0,0 +1,84 @@
469 +/*
470 + * Atheros SoC specific CPU feature overrides
471 + *
472 + * Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
473 + *
474 + * This file was derived from: include/asm-mips/cpu-features.h
475 + * Copyright (C) 2003, 2004 Ralf Baechle
476 + * Copyright (C) 2004 Maciej W. Rozycki
477 + *
478 + * This program is free software; you can redistribute it and/or modify it
479 + * under the terms of the GNU General Public License version 2 as published
480 + * by the Free Software Foundation.
481 + *
482 + */
483 +#ifndef __ASM_MACH_ATHEROS_CPU_FEATURE_OVERRIDES_H
484 +#define __ASM_MACH_ATHEROS_CPU_FEATURE_OVERRIDES_H
485 +
486 +/*
487 + * The ATHEROS SoCs have MIPS 4Kc/4KEc core.
488 + */
489 +#define cpu_has_tlb 1
490 +#define cpu_has_4kex 1
491 +#define cpu_has_3k_cache 0
492 +#define cpu_has_4k_cache 1
493 +#define cpu_has_tx39_cache 0
494 +#define cpu_has_sb1_cache 0
495 +#define cpu_has_fpu 0
496 +#define cpu_has_32fpr 0
497 +#define cpu_has_counter 1
498 +/* #define cpu_has_watch ? */
499 +/* #define cpu_has_divec ? */
500 +/* #define cpu_has_vce ? */
501 +/* #define cpu_has_cache_cdex_p ? */
502 +/* #define cpu_has_cache_cdex_s ? */
503 +/* #define cpu_has_prefetch ? */
504 +/* #define cpu_has_mcheck ? */
505 +#define cpu_has_ejtag 1
506 +
507 +#if !defined(CONFIG_ATHEROS_AR5312)
508 +# define cpu_has_llsc 1
509 +#else
510 +/*
511 + * The MIPS 4Kc V0.9 core in the AR5312/AR2312 have problems with the
512 + * ll/sc instructions.
513 + */
514 +# define cpu_has_llsc 0
515 +#endif
516 +
517 +#define cpu_has_mips16 0
518 +#define cpu_has_mdmx 0
519 +#define cpu_has_mips3d 0
520 +#define cpu_has_smartmips 0
521 +
522 +/* #define cpu_has_vtag_icache ? */
523 +/* #define cpu_has_dc_aliases ? */
524 +/* #define cpu_has_ic_fills_f_dc ? */
525 +/* #define cpu_has_pindexed_dcache ? */
526 +
527 +/* #define cpu_icache_snoops_remote_store ? */
528 +
529 +#define cpu_has_mips32r1 1
530 +
531 +#if !defined(CONFIG_ATHEROS_AR5312)
532 +# define cpu_has_mips32r2 1
533 +#endif
534 +
535 +#define cpu_has_mips64r1 0
536 +#define cpu_has_mips64r2 0
537 +
538 +#define cpu_has_dsp 0
539 +#define cpu_has_mipsmt 0
540 +
541 +/* #define cpu_has_nofpuex ? */
542 +#define cpu_has_64bits 0
543 +#define cpu_has_64bit_zero_reg 0
544 +#define cpu_has_64bit_gp_regs 0
545 +#define cpu_has_64bit_addresses 0
546 +
547 +/* #define cpu_has_inclusive_pcaches ? */
548 +
549 +/* #define cpu_dcache_line_size() ? */
550 +/* #define cpu_icache_line_size() ? */
551 +
552 +#endif /* __ASM_MACH_ATHEROS_CPU_FEATURE_OVERRIDES_H */
553 --- /dev/null
554 +++ b/arch/mips/include/asm/mach-ar231x/dma-coherence.h
555 @@ -0,0 +1,76 @@
556 +/*
557 + * This file is subject to the terms and conditions of the GNU General Public
558 + * License. See the file "COPYING" in the main directory of this archive
559 + * for more details.
560 + *
561 + * Copyright (C) 2006 Ralf Baechle <ralf@linux-mips.org>
562 + * Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
563 + *
564 + */
565 +#ifndef __ASM_MACH_GENERIC_DMA_COHERENCE_H
566 +#define __ASM_MACH_GENERIC_DMA_COHERENCE_H
567 +
568 +#define PCI_DMA_OFFSET 0x20000000
569 +
570 +#include <linux/device.h>
571 +
572 +static inline dma_addr_t ar231x_dev_offset(struct device *dev)
573 +{
574 +#ifdef CONFIG_PCI
575 + extern struct bus_type pci_bus_type;
576 +
577 + if (dev && dev->bus == &pci_bus_type)
578 + return PCI_DMA_OFFSET;
579 + else
580 +#endif
581 + return 0;
582 +}
583 +
584 +static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr, size_t size)
585 +{
586 + return virt_to_phys(addr) + ar231x_dev_offset(dev);
587 +}
588 +
589 +static inline dma_addr_t plat_map_dma_mem_page(struct device *dev, struct page *page)
590 +{
591 + return page_to_phys(page) + ar231x_dev_offset(dev);
592 +}
593 +
594 +static inline unsigned long plat_dma_addr_to_phys(struct device *dev,
595 + dma_addr_t dma_addr)
596 +{
597 + return dma_addr - ar231x_dev_offset(dev);
598 +}
599 +
600 +static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr,
601 + size_t size, enum dma_data_direction direction)
602 +{
603 +}
604 +
605 +static inline int plat_dma_supported(struct device *dev, u64 mask)
606 +{
607 + return 1;
608 +}
609 +
610 +static inline void plat_extra_sync_for_device(struct device *dev)
611 +{
612 + return;
613 +}
614 +
615 +static inline int plat_dma_mapping_error(struct device *dev,
616 + dma_addr_t dma_addr)
617 +{
618 + return 0;
619 +}
620 +
621 +static inline int plat_device_is_coherent(struct device *dev)
622 +{
623 +#ifdef CONFIG_DMA_COHERENT
624 + return 1;
625 +#endif
626 +#ifdef CONFIG_DMA_NONCOHERENT
627 + return 0;
628 +#endif
629 +}
630 +
631 +#endif /* __ASM_MACH_GENERIC_DMA_COHERENCE_H */
632 --- /dev/null
633 +++ b/arch/mips/include/asm/mach-ar231x/gpio.h
634 @@ -0,0 +1,84 @@
635 +#ifndef _ATHEROS_GPIO_H_
636 +#define _ATHEROS_GPIO_H_
637 +
638 +#include <ar231x.h>
639 +
640 +struct ar231x_gpiodev {
641 + u32 valid_mask;
642 + u32 (*get_output)(void);
643 + u32 (*set_output)(u32 mask, u32 val);
644 + u32 (*get)(void);
645 + u32 (*set)(u32 mask, u32 val);
646 +};
647 +
648 +extern const struct ar231x_gpiodev *ar231x_gpiodev;
649 +
650 +/*
651 + * Wrappers for the generic GPIO layer
652 + */
653 +
654 +static inline int gpio_direction_input(unsigned gpio) {
655 + u32 mask = 1 << gpio;
656 +
657 + if (!(ar231x_gpiodev->valid_mask & mask))
658 + return -ENXIO;
659 +
660 + ar231x_gpiodev->set_output(mask, 0);
661 + return 0;
662 +}
663 +
664 +static inline void gpio_set_value(unsigned gpio, int value) {
665 + u32 mask = 1 << gpio;
666 +
667 + if (!(ar231x_gpiodev->valid_mask & mask))
668 + return;
669 +
670 + ar231x_gpiodev->set(mask, (!!value) * mask);
671 +}
672 +
673 +static inline int gpio_direction_output(unsigned gpio, int value) {
674 + u32 mask = 1 << gpio;
675 +
676 + if (!(ar231x_gpiodev->valid_mask & mask))
677 + return -ENXIO;
678 +
679 + ar231x_gpiodev->set_output(mask, mask);
680 + ar231x_gpiodev->set(mask, (!!value) * mask);
681 + return 0;
682 +}
683 +
684 +/* Reads the gpio pin. Unchecked function */
685 +static inline int gpio_get_value(unsigned gpio) {
686 + u32 mask = 1 << gpio;
687 +
688 + if (!(ar231x_gpiodev->valid_mask & mask))
689 + return 0;
690 +
691 + return !!(ar231x_gpiodev->get() & mask);
692 +}
693 +
694 +static inline int gpio_request(unsigned gpio, const char *label) {
695 + return 0;
696 +}
697 +
698 +static inline void gpio_free(unsigned gpio) {
699 +}
700 +
701 +/* Returns IRQ to attach for gpio. Unchecked function */
702 +static inline int gpio_to_irq(unsigned gpio) {
703 + return AR531X_GPIO_IRQ(gpio);
704 +}
705 +
706 +/* Returns gpio for IRQ attached. Unchecked function */
707 +static inline int irq_to_gpio(unsigned irq) {
708 + return (irq - (AR531X_GPIO_IRQ(0)));
709 +}
710 +
711 +static inline int gpio_set_debounce(unsigned gpio, unsigned debounce)
712 +{
713 + return -ENOSYS;
714 +}
715 +
716 +#include <asm-generic/gpio.h> /* cansleep wrappers */
717 +
718 +#endif
719 --- /dev/null
720 +++ b/arch/mips/include/asm/mach-ar231x/reset.h
721 @@ -0,0 +1,6 @@
722 +#ifndef __AR531X_RESET_H
723 +#define __AR531X_RESET_H
724 +
725 +void ar531x_disable_reset_button(void);
726 +
727 +#endif /* __AR531X_RESET_H */
728 --- /dev/null
729 +++ b/arch/mips/include/asm/mach-ar231x/war.h
730 @@ -0,0 +1,25 @@
731 +/*
732 + * This file is subject to the terms and conditions of the GNU General Public
733 + * License. See the file "COPYING" in the main directory of this archive
734 + * for more details.
735 + *
736 + * Copyright (C) 2008 Felix Fietkau <nbd@openwrt.org>
737 + */
738 +#ifndef __ASM_MIPS_MACH_ATHEROS_WAR_H
739 +#define __ASM_MIPS_MACH_ATHEROS_WAR_H
740 +
741 +#define R4600_V1_INDEX_ICACHEOP_WAR 0
742 +#define R4600_V1_HIT_CACHEOP_WAR 0
743 +#define R4600_V2_HIT_CACHEOP_WAR 0
744 +#define R5432_CP0_INTERRUPT_WAR 0
745 +#define BCM1250_M3_WAR 0
746 +#define SIBYTE_1956_WAR 0
747 +#define MIPS4K_ICACHE_REFILL_WAR 0
748 +#define MIPS_CACHE_SYNC_WAR 0
749 +#define TX49XX_ICACHE_INDEX_INV_WAR 0
750 +#define RM9000_CDEX_SMP_WAR 0
751 +#define ICACHE_REFILLS_WORKAROUND_WAR 0
752 +#define R10000_LLSC_WAR 0
753 +#define MIPS34K_MISSED_ITLB_WAR 0
754 +
755 +#endif /* __ASM_MIPS_MACH_ATHEROS_WAR_H */
756 --- /dev/null
757 +++ b/arch/mips/include/asm/mach-ar231x/ar2315_regs.h
758 @@ -0,0 +1,580 @@
759 +/*
760 + * Register definitions for AR2315+
761 + *
762 + * This file is subject to the terms and conditions of the GNU General Public
763 + * License. See the file "COPYING" in the main directory of this archive
764 + * for more details.
765 + *
766 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
767 + * Copyright (C) 2006 FON Technology, SL.
768 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
769 + * Copyright (C) 2006-2008 Felix Fietkau <nbd@openwrt.org>
770 + */
771 +
772 +#ifndef __AR2315_REG_H
773 +#define __AR2315_REG_H
774 +
775 +/*
776 + * IRQs
777 + */
778 +#define AR2315_IRQ_MISC_INTRS MIPS_CPU_IRQ_BASE+2 /* C0_CAUSE: 0x0400 */
779 +#define AR2315_IRQ_WLAN0_INTRS MIPS_CPU_IRQ_BASE+3 /* C0_CAUSE: 0x0800 */
780 +#define AR2315_IRQ_ENET0_INTRS MIPS_CPU_IRQ_BASE+4 /* C0_CAUSE: 0x1000 */
781 +#define AR2315_IRQ_LCBUS_PCI MIPS_CPU_IRQ_BASE+5 /* C0_CAUSE: 0x2000 */
782 +#define AR2315_IRQ_WLAN0_POLL MIPS_CPU_IRQ_BASE+6 /* C0_CAUSE: 0x4000 */
783 +
784 +/*
785 + * Address map
786 + */
787 +#define AR2315_SPI_READ 0x08000000 /* SPI FLASH */
788 +#define AR2315_WLAN0 0x10000000 /* Wireless MMR */
789 +#define AR2315_PCI 0x10100000 /* PCI MMR */
790 +#define AR2315_SDRAMCTL 0x10300000 /* SDRAM MMR */
791 +#define AR2315_LOCAL 0x10400000 /* LOCAL BUS MMR */
792 +#define AR2315_ENET0 0x10500000 /* ETHERNET MMR */
793 +#define AR2315_DSLBASE 0x11000000 /* RESET CONTROL MMR */
794 +#define AR2315_UART0 0x11100003 /* UART MMR */
795 +#define AR2315_SPI 0x11300000 /* SPI FLASH MMR */
796 +#define AR2315_PCIEXT 0x80000000 /* pci external */
797 +
798 +/*
799 + * Reset Register
800 + */
801 +#define AR2315_COLD_RESET (AR2315_DSLBASE + 0x0000)
802 +
803 +#define AR2315_RESET_COLD_AHB 0x00000001
804 +#define AR2315_RESET_COLD_APB 0x00000002
805 +#define AR2315_RESET_COLD_CPU 0x00000004
806 +#define AR2315_RESET_COLD_CPUWARM 0x00000008
807 +#define AR2315_RESET_SYSTEM (RESET_COLD_CPU | RESET_COLD_APB | RESET_COLD_AHB) /* full system */
808 +#define AR2317_RESET_SYSTEM 0x00000010
809 +
810 +
811 +#define AR2315_RESET (AR2315_DSLBASE + 0x0004)
812 +
813 +#define AR2315_RESET_WARM_WLAN0_MAC 0x00000001 /* warm reset WLAN0 MAC */
814 +#define AR2315_RESET_WARM_WLAN0_BB 0x00000002 /* warm reset WLAN0 BaseBand */
815 +#define AR2315_RESET_MPEGTS_RSVD 0x00000004 /* warm reset MPEG-TS */
816 +#define AR2315_RESET_PCIDMA 0x00000008 /* warm reset PCI ahb/dma */
817 +#define AR2315_RESET_MEMCTL 0x00000010 /* warm reset memory controller */
818 +#define AR2315_RESET_LOCAL 0x00000020 /* warm reset local bus */
819 +#define AR2315_RESET_I2C_RSVD 0x00000040 /* warm reset I2C bus */
820 +#define AR2315_RESET_SPI 0x00000080 /* warm reset SPI interface */
821 +#define AR2315_RESET_UART0 0x00000100 /* warm reset UART0 */
822 +#define AR2315_RESET_IR_RSVD 0x00000200 /* warm reset IR interface */
823 +#define AR2315_RESET_EPHY0 0x00000400 /* cold reset ENET0 phy */
824 +#define AR2315_RESET_ENET0 0x00000800 /* cold reset ENET0 mac */
825 +
826 +/*
827 + * AHB master arbitration control
828 + */
829 +#define AR2315_AHB_ARB_CTL (AR2315_DSLBASE + 0x0008)
830 +
831 +#define AR2315_ARB_CPU 0x00000001 /* CPU, default */
832 +#define AR2315_ARB_WLAN 0x00000002 /* WLAN */
833 +#define AR2315_ARB_MPEGTS_RSVD 0x00000004 /* MPEG-TS */
834 +#define AR2315_ARB_LOCAL 0x00000008 /* LOCAL */
835 +#define AR2315_ARB_PCI 0x00000010 /* PCI */
836 +#define AR2315_ARB_ETHERNET 0x00000020 /* Ethernet */
837 +#define AR2315_ARB_RETRY 0x00000100 /* retry policy, debug only */
838 +
839 +/*
840 + * Config Register
841 + */
842 +#define AR2315_ENDIAN_CTL (AR2315_DSLBASE + 0x000c)
843 +
844 +#define AR2315_CONFIG_AHB 0x00000001 /* EC - AHB bridge endianess */
845 +#define AR2315_CONFIG_WLAN 0x00000002 /* WLAN byteswap */
846 +#define AR2315_CONFIG_MPEGTS_RSVD 0x00000004 /* MPEG-TS byteswap */
847 +#define AR2315_CONFIG_PCI 0x00000008 /* PCI byteswap */
848 +#define AR2315_CONFIG_MEMCTL 0x00000010 /* Memory controller endianess */
849 +#define AR2315_CONFIG_LOCAL 0x00000020 /* Local bus byteswap */
850 +#define AR2315_CONFIG_ETHERNET 0x00000040 /* Ethernet byteswap */
851 +
852 +#define AR2315_CONFIG_MERGE 0x00000200 /* CPU write buffer merge */
853 +#define AR2315_CONFIG_CPU 0x00000400 /* CPU big endian */
854 +#define AR2315_CONFIG_PCIAHB 0x00000800
855 +#define AR2315_CONFIG_PCIAHB_BRIDGE 0x00001000
856 +#define AR2315_CONFIG_SPI 0x00008000 /* SPI byteswap */
857 +#define AR2315_CONFIG_CPU_DRAM 0x00010000
858 +#define AR2315_CONFIG_CPU_PCI 0x00020000
859 +#define AR2315_CONFIG_CPU_MMR 0x00040000
860 +#define AR2315_CONFIG_BIG 0x00000400
861 +
862 +
863 +/*
864 + * NMI control
865 + */
866 +#define AR2315_NMI_CTL (AR2315_DSLBASE + 0x0010)
867 +
868 +#define AR2315_NMI_EN 1
869 +
870 +/*
871 + * Revision Register - Initial value is 0x3010 (WMAC 3.0, AR531X 1.0).
872 + */
873 +#define AR2315_SREV (AR2315_DSLBASE + 0x0014)
874 +
875 +#define AR2315_REV_MAJ 0x00f0
876 +#define AR2315_REV_MAJ_S 4
877 +#define AR2315_REV_MIN 0x000f
878 +#define AR2315_REV_MIN_S 0
879 +#define AR2315_REV_CHIP (AR2315_REV_MAJ|AR2315_REV_MIN)
880 +
881 +/*
882 + * Interface Enable
883 + */
884 +#define AR2315_IF_CTL (AR2315_DSLBASE + 0x0018)
885 +
886 +#define AR2315_IF_MASK 0x00000007
887 +#define AR2315_IF_DISABLED 0
888 +#define AR2315_IF_PCI 1
889 +#define AR2315_IF_TS_LOCAL 2
890 +#define AR2315_IF_ALL 3 /* only for emulation with separate pins */
891 +#define AR2315_IF_LOCAL_HOST 0x00000008
892 +#define AR2315_IF_PCI_HOST 0x00000010
893 +#define AR2315_IF_PCI_INTR 0x00000020
894 +#define AR2315_IF_PCI_CLK_MASK 0x00030000
895 +#define AR2315_IF_PCI_CLK_INPUT 0
896 +#define AR2315_IF_PCI_CLK_OUTPUT_LOW 1
897 +#define AR2315_IF_PCI_CLK_OUTPUT_CLK 2
898 +#define AR2315_IF_PCI_CLK_OUTPUT_HIGH 3
899 +#define AR2315_IF_PCI_CLK_SHIFT 16
900 +
901 +/*
902 + * APB Interrupt control
903 + */
904 +
905 +#define AR2315_ISR (AR2315_DSLBASE + 0x0020)
906 +#define AR2315_IMR (AR2315_DSLBASE + 0x0024)
907 +#define AR2315_GISR (AR2315_DSLBASE + 0x0028)
908 +
909 +#define AR2315_ISR_UART0 0x0001 /* high speed UART */
910 +#define AR2315_ISR_I2C_RSVD 0x0002 /* I2C bus */
911 +#define AR2315_ISR_SPI 0x0004 /* SPI bus */
912 +#define AR2315_ISR_AHB 0x0008 /* AHB error */
913 +#define AR2315_ISR_APB 0x0010 /* APB error */
914 +#define AR2315_ISR_TIMER 0x0020 /* timer */
915 +#define AR2315_ISR_GPIO 0x0040 /* GPIO */
916 +#define AR2315_ISR_WD 0x0080 /* watchdog */
917 +#define AR2315_ISR_IR_RSVD 0x0100 /* IR */
918 +
919 +#define AR2315_GISR_MISC 0x0001
920 +#define AR2315_GISR_WLAN0 0x0002
921 +#define AR2315_GISR_MPEGTS_RSVD 0x0004
922 +#define AR2315_GISR_LOCALPCI 0x0008
923 +#define AR2315_GISR_WMACPOLL 0x0010
924 +#define AR2315_GISR_TIMER 0x0020
925 +#define AR2315_GISR_ETHERNET 0x0040
926 +
927 +/*
928 + * Interrupt routing from IO to the processor IP bits
929 + * Define our inter mask and level
930 + */
931 +#define AR2315_INTR_MISCIO SR_IBIT3
932 +#define AR2315_INTR_WLAN0 SR_IBIT4
933 +#define AR2315_INTR_ENET0 SR_IBIT5
934 +#define AR2315_INTR_LOCALPCI SR_IBIT6
935 +#define AR2315_INTR_WMACPOLL SR_IBIT7
936 +#define AR2315_INTR_COMPARE SR_IBIT8
937 +
938 +/*
939 + * Timers
940 + */
941 +#define AR2315_TIMER (AR2315_DSLBASE + 0x0030)
942 +#define AR2315_RELOAD (AR2315_DSLBASE + 0x0034)
943 +#define AR2315_WD (AR2315_DSLBASE + 0x0038)
944 +#define AR2315_WDC (AR2315_DSLBASE + 0x003c)
945 +
946 +#define AR2315_WDC_IGNORE_EXPIRATION 0x00000000
947 +#define AR2315_WDC_NMI 0x00000001 /* NMI on watchdog */
948 +#define AR2315_WDC_RESET 0x00000002 /* reset on watchdog */
949 +
950 +/*
951 + * CPU Performance Counters
952 + */
953 +#define AR2315_PERFCNT0 (AR2315_DSLBASE + 0x0048)
954 +#define AR2315_PERFCNT1 (AR2315_DSLBASE + 0x004c)
955 +
956 +#define AR2315_PERF0_DATAHIT 0x0001 /* Count Data Cache Hits */
957 +#define AR2315_PERF0_DATAMISS 0x0002 /* Count Data Cache Misses */
958 +#define AR2315_PERF0_INSTHIT 0x0004 /* Count Instruction Cache Hits */
959 +#define AR2315_PERF0_INSTMISS 0x0008 /* Count Instruction Cache Misses */
960 +#define AR2315_PERF0_ACTIVE 0x0010 /* Count Active Processor Cycles */
961 +#define AR2315_PERF0_WBHIT 0x0020 /* Count CPU Write Buffer Hits */
962 +#define AR2315_PERF0_WBMISS 0x0040 /* Count CPU Write Buffer Misses */
963 +
964 +#define AR2315_PERF1_EB_ARDY 0x0001 /* Count EB_ARdy signal */
965 +#define AR2315_PERF1_EB_AVALID 0x0002 /* Count EB_AValid signal */
966 +#define AR2315_PERF1_EB_WDRDY 0x0004 /* Count EB_WDRdy signal */
967 +#define AR2315_PERF1_EB_RDVAL 0x0008 /* Count EB_RdVal signal */
968 +#define AR2315_PERF1_VRADDR 0x0010 /* Count valid read address cycles */
969 +#define AR2315_PERF1_VWADDR 0x0020 /* Count valid write address cycles */
970 +#define AR2315_PERF1_VWDATA 0x0040 /* Count valid write data cycles */
971 +
972 +/*
973 + * AHB Error Reporting.
974 + */
975 +#define AR2315_AHB_ERR0 (AR2315_DSLBASE + 0x0050) /* error */
976 +#define AR2315_AHB_ERR1 (AR2315_DSLBASE + 0x0054) /* haddr */
977 +#define AR2315_AHB_ERR2 (AR2315_DSLBASE + 0x0058) /* hwdata */
978 +#define AR2315_AHB_ERR3 (AR2315_DSLBASE + 0x005c) /* hrdata */
979 +#define AR2315_AHB_ERR4 (AR2315_DSLBASE + 0x0060) /* status */
980 +
981 +#define AHB_ERROR_DET 1 /* AHB Error has been detected, */
982 + /* write 1 to clear all bits in ERR0 */
983 +#define AHB_ERROR_OVR 2 /* AHB Error overflow has been detected */
984 +#define AHB_ERROR_WDT 4 /* AHB Error due to wdt instead of hresp */
985 +
986 +#define AR2315_PROCERR_HMAST 0x0000000f
987 +#define AR2315_PROCERR_HMAST_DFLT 0
988 +#define AR2315_PROCERR_HMAST_WMAC 1
989 +#define AR2315_PROCERR_HMAST_ENET 2
990 +#define AR2315_PROCERR_HMAST_PCIENDPT 3
991 +#define AR2315_PROCERR_HMAST_LOCAL 4
992 +#define AR2315_PROCERR_HMAST_CPU 5
993 +#define AR2315_PROCERR_HMAST_PCITGT 6
994 +
995 +#define AR2315_PROCERR_HMAST_S 0
996 +#define AR2315_PROCERR_HWRITE 0x00000010
997 +#define AR2315_PROCERR_HSIZE 0x00000060
998 +#define AR2315_PROCERR_HSIZE_S 5
999 +#define AR2315_PROCERR_HTRANS 0x00000180
1000 +#define AR2315_PROCERR_HTRANS_S 7
1001 +#define AR2315_PROCERR_HBURST 0x00000e00
1002 +#define AR2315_PROCERR_HBURST_S 9
1003 +
1004 +/*
1005 + * Clock Control
1006 + */
1007 +#define AR2315_PLLC_CTL (AR2315_DSLBASE + 0x0064)
1008 +#define AR2315_PLLV_CTL (AR2315_DSLBASE + 0x0068)
1009 +#define AR2315_CPUCLK (AR2315_DSLBASE + 0x006c)
1010 +#define AR2315_AMBACLK (AR2315_DSLBASE + 0x0070)
1011 +#define AR2315_SYNCCLK (AR2315_DSLBASE + 0x0074)
1012 +#define AR2315_DSL_SLEEP_CTL (AR2315_DSLBASE + 0x0080)
1013 +#define AR2315_DSL_SLEEP_DUR (AR2315_DSLBASE + 0x0084)
1014 +
1015 +/* PLLc Control fields */
1016 +#define PLLC_REF_DIV_M 0x00000003
1017 +#define PLLC_REF_DIV_S 0
1018 +#define PLLC_FDBACK_DIV_M 0x0000007C
1019 +#define PLLC_FDBACK_DIV_S 2
1020 +#define PLLC_ADD_FDBACK_DIV_M 0x00000080
1021 +#define PLLC_ADD_FDBACK_DIV_S 7
1022 +#define PLLC_CLKC_DIV_M 0x0001c000
1023 +#define PLLC_CLKC_DIV_S 14
1024 +#define PLLC_CLKM_DIV_M 0x00700000
1025 +#define PLLC_CLKM_DIV_S 20
1026 +
1027 +/* CPU CLK Control fields */
1028 +#define CPUCLK_CLK_SEL_M 0x00000003
1029 +#define CPUCLK_CLK_SEL_S 0
1030 +#define CPUCLK_CLK_DIV_M 0x0000000c
1031 +#define CPUCLK_CLK_DIV_S 2
1032 +
1033 +/* AMBA CLK Control fields */
1034 +#define AMBACLK_CLK_SEL_M 0x00000003
1035 +#define AMBACLK_CLK_SEL_S 0
1036 +#define AMBACLK_CLK_DIV_M 0x0000000c
1037 +#define AMBACLK_CLK_DIV_S 2
1038 +
1039 +/*
1040 + * GPIO
1041 + */
1042 +#define AR2315_GPIO_DI (AR2315_DSLBASE + 0x0088)
1043 +#define AR2315_GPIO_DO (AR2315_DSLBASE + 0x0090)
1044 +#define AR2315_GPIO_CR (AR2315_DSLBASE + 0x0098)
1045 +#define AR2315_GPIO_INT (AR2315_DSLBASE + 0x00a0)
1046 +
1047 +#define AR2315_GPIO_CR_M(x) (1 << (x)) /* mask for i/o */
1048 +#define AR2315_GPIO_CR_O(x) (1 << (x)) /* output */
1049 +#define AR2315_GPIO_CR_I(x) (0) /* input */
1050 +
1051 +#define AR2315_GPIO_INT_S(x) (x) /* interrupt enable */
1052 +#define AR2315_GPIO_INT_M (0x3F) /* mask for int */
1053 +#define AR2315_GPIO_INT_LVL(x) ((x) << 6) /* interrupt level */
1054 +#define AR2315_GPIO_INT_LVL_M ((0x3) << 6) /* mask for int level */
1055 +
1056 +#define AR2315_GPIO_INT_MAX_Y 1 /* Maximum value of Y for AR5313_GPIO_INT_* macros */
1057 +#define AR2315_GPIO_INT_LVL_OFF 0 /* Triggerring off */
1058 +#define AR2315_GPIO_INT_LVL_LOW 1 /* Low Level Triggered */
1059 +#define AR2315_GPIO_INT_LVL_HIGH 2 /* High Level Triggered */
1060 +#define AR2315_GPIO_INT_LVL_EDGE 3 /* Edge Triggered */
1061 +
1062 +#define AR2315_RESET_GPIO 5
1063 +#define AR2315_NUM_GPIO 22
1064 +
1065 +/*
1066 + * PCI Clock Control
1067 + */
1068 +#define AR2315_PCICLK (AR2315_DSLBASE + 0x00a4)
1069 +
1070 +#define AR2315_PCICLK_INPUT_M 0x3
1071 +#define AR2315_PCICLK_INPUT_S 0
1072 +
1073 +#define AR2315_PCICLK_PLLC_CLKM 0
1074 +#define AR2315_PCICLK_PLLC_CLKM1 1
1075 +#define AR2315_PCICLK_PLLC_CLKC 2
1076 +#define AR2315_PCICLK_REF_CLK 3
1077 +
1078 +#define AR2315_PCICLK_DIV_M 0xc
1079 +#define AR2315_PCICLK_DIV_S 2
1080 +
1081 +#define AR2315_PCICLK_IN_FREQ 0
1082 +#define AR2315_PCICLK_IN_FREQ_DIV_6 1
1083 +#define AR2315_PCICLK_IN_FREQ_DIV_8 2
1084 +#define AR2315_PCICLK_IN_FREQ_DIV_10 3
1085 +
1086 +/*
1087 + * Observation Control Register
1088 + */
1089 +#define AR2315_OCR (AR2315_DSLBASE + 0x00b0)
1090 +#define OCR_GPIO0_IRIN 0x0040
1091 +#define OCR_GPIO1_IROUT 0x0080
1092 +#define OCR_GPIO3_RXCLR 0x0200
1093 +
1094 +/*
1095 + * General Clock Control
1096 + */
1097 +
1098 +#define AR2315_MISCCLK (AR2315_DSLBASE + 0x00b4)
1099 +#define MISCCLK_PLLBYPASS_EN 0x00000001
1100 +#define MISCCLK_PROCREFCLK 0x00000002
1101 +
1102 +/*
1103 + * SDRAM Controller
1104 + * - No read or write buffers are included.
1105 + */
1106 +#define AR2315_MEM_CFG (AR2315_SDRAMCTL + 0x00)
1107 +#define AR2315_MEM_CTRL (AR2315_SDRAMCTL + 0x0c)
1108 +#define AR2315_MEM_REF (AR2315_SDRAMCTL + 0x10)
1109 +
1110 +#define SDRAM_DATA_WIDTH_M 0x00006000
1111 +#define SDRAM_DATA_WIDTH_S 13
1112 +
1113 +#define SDRAM_COL_WIDTH_M 0x00001E00
1114 +#define SDRAM_COL_WIDTH_S 9
1115 +
1116 +#define SDRAM_ROW_WIDTH_M 0x000001E0
1117 +#define SDRAM_ROW_WIDTH_S 5
1118 +
1119 +#define SDRAM_BANKADDR_BITS_M 0x00000018
1120 +#define SDRAM_BANKADDR_BITS_S 3
1121 +
1122 +/*
1123 + * SPI Flash Interface Registers
1124 + */
1125 +
1126 +#define AR2315_SPI_CTL (AR2315_SPI + 0x00)
1127 +#define AR2315_SPI_OPCODE (AR2315_SPI + 0x04)
1128 +#define AR2315_SPI_DATA (AR2315_SPI + 0x08)
1129 +
1130 +#define SPI_CTL_START 0x00000100
1131 +#define SPI_CTL_BUSY 0x00010000
1132 +#define SPI_CTL_TXCNT_MASK 0x0000000f
1133 +#define SPI_CTL_RXCNT_MASK 0x000000f0
1134 +#define SPI_CTL_TX_RX_CNT_MASK 0x000000ff
1135 +#define SPI_CTL_SIZE_MASK 0x00060000
1136 +
1137 +#define SPI_CTL_CLK_SEL_MASK 0x03000000
1138 +#define SPI_OPCODE_MASK 0x000000ff
1139 +
1140 +/*
1141 + * PCI Bus Interface Registers
1142 + */
1143 +#define AR2315_PCI_1MS_REG (AR2315_PCI + 0x0008)
1144 +#define AR2315_PCI_1MS_MASK 0x3FFFF /* # of AHB clk cycles in 1ms */
1145 +
1146 +#define AR2315_PCI_MISC_CONFIG (AR2315_PCI + 0x000c)
1147 +#define AR2315_PCIMISC_TXD_EN 0x00000001 /* Enable TXD for fragments */
1148 +#define AR2315_PCIMISC_CFG_SEL 0x00000002 /* mem or config cycles */
1149 +#define AR2315_PCIMISC_GIG_MASK 0x0000000C /* bits 31-30 for pci req */
1150 +#define AR2315_PCIMISC_RST_MODE 0x00000030
1151 +#define AR2315_PCIRST_INPUT 0x00000000 /* 4:5=0 rst is input */
1152 +#define AR2315_PCIRST_LOW 0x00000010 /* 4:5=1 rst to GND */
1153 +#define AR2315_PCIRST_HIGH 0x00000020 /* 4:5=2 rst to VDD */
1154 +#define AR2315_PCIGRANT_EN 0x00000000 /* 6:7=0 early grant en */
1155 +#define AR2315_PCIGRANT_FRAME 0x00000040 /* 6:7=1 grant waits 4 frame */
1156 +#define AR2315_PCIGRANT_IDLE 0x00000080 /* 6:7=2 grant waits 4 idle */
1157 +#define AR2315_PCIGRANT_GAP 0x00000000 /* 6:7=2 grant waits 4 idle */
1158 +#define AR2315_PCICACHE_DIS 0x00001000 /* PCI external access cache disable */
1159 +
1160 +#define AR2315_PCI_OUT_TSTAMP (AR2315_PCI + 0x0010)
1161 +
1162 +#define AR2315_PCI_UNCACHE_CFG (AR2315_PCI + 0x0014)
1163 +
1164 +#define AR2315_PCI_IN_EN (AR2315_PCI + 0x0100)
1165 +#define AR2315_PCI_IN_EN0 0x01 /* Enable chain 0 */
1166 +#define AR2315_PCI_IN_EN1 0x02 /* Enable chain 1 */
1167 +#define AR2315_PCI_IN_EN2 0x04 /* Enable chain 2 */
1168 +#define AR2315_PCI_IN_EN3 0x08 /* Enable chain 3 */
1169 +
1170 +#define AR2315_PCI_IN_DIS (AR2315_PCI + 0x0104)
1171 +#define AR2315_PCI_IN_DIS0 0x01 /* Disable chain 0 */
1172 +#define AR2315_PCI_IN_DIS1 0x02 /* Disable chain 1 */
1173 +#define AR2315_PCI_IN_DIS2 0x04 /* Disable chain 2 */
1174 +#define AR2315_PCI_IN_DIS3 0x08 /* Disable chain 3 */
1175 +
1176 +#define AR2315_PCI_IN_PTR (AR2315_PCI + 0x0200)
1177 +
1178 +#define AR2315_PCI_OUT_EN (AR2315_PCI + 0x0400)
1179 +#define AR2315_PCI_OUT_EN0 0x01 /* Enable chain 0 */
1180 +
1181 +#define AR2315_PCI_OUT_DIS (AR2315_PCI + 0x0404)
1182 +#define AR2315_PCI_OUT_DIS0 0x01 /* Disable chain 0 */
1183 +
1184 +#define AR2315_PCI_OUT_PTR (AR2315_PCI + 0x0408)
1185 +
1186 +#define AR2315_PCI_INT_STATUS (AR2315_PCI + 0x0500) /* write one to clr */
1187 +#define AR2315_PCI_TXINT 0x00000001 /* Desc In Completed */
1188 +#define AR2315_PCI_TXOK 0x00000002 /* Desc In OK */
1189 +#define AR2315_PCI_TXERR 0x00000004 /* Desc In ERR */
1190 +#define AR2315_PCI_TXEOL 0x00000008 /* Desc In End-of-List */
1191 +#define AR2315_PCI_RXINT 0x00000010 /* Desc Out Completed */
1192 +#define AR2315_PCI_RXOK 0x00000020 /* Desc Out OK */
1193 +#define AR2315_PCI_RXERR 0x00000040 /* Desc Out ERR */
1194 +#define AR2315_PCI_RXEOL 0x00000080 /* Desc Out EOL */
1195 +#define AR2315_PCI_TXOOD 0x00000200 /* Desc In Out-of-Desc */
1196 +#define AR2315_PCI_MASK 0x0000FFFF /* Desc Mask */
1197 +#define AR2315_PCI_EXT_INT 0x02000000
1198 +#define AR2315_PCI_ABORT_INT 0x04000000
1199 +
1200 +#define AR2315_PCI_INT_MASK (AR2315_PCI + 0x0504) /* same as INT_STATUS */
1201 +
1202 +#define AR2315_PCI_INTEN_REG (AR2315_PCI + 0x0508)
1203 +#define AR2315_PCI_INT_DISABLE 0x00 /* disable pci interrupts */
1204 +#define AR2315_PCI_INT_ENABLE 0x01 /* enable pci interrupts */
1205 +
1206 +#define AR2315_PCI_HOST_IN_EN (AR2315_PCI + 0x0800)
1207 +#define AR2315_PCI_HOST_IN_DIS (AR2315_PCI + 0x0804)
1208 +#define AR2315_PCI_HOST_IN_PTR (AR2315_PCI + 0x0810)
1209 +#define AR2315_PCI_HOST_OUT_EN (AR2315_PCI + 0x0900)
1210 +#define AR2315_PCI_HOST_OUT_DIS (AR2315_PCI + 0x0904)
1211 +#define AR2315_PCI_HOST_OUT_PTR (AR2315_PCI + 0x0908)
1212 +
1213 +
1214 +/*
1215 + * Local Bus Interface Registers
1216 + */
1217 +#define AR2315_LB_CONFIG (AR2315_LOCAL + 0x0000)
1218 +#define AR2315_LBCONF_OE 0x00000001 /* =1 OE is low-true */
1219 +#define AR2315_LBCONF_CS0 0x00000002 /* =1 first CS is low-true */
1220 +#define AR2315_LBCONF_CS1 0x00000004 /* =1 2nd CS is low-true */
1221 +#define AR2315_LBCONF_RDY 0x00000008 /* =1 RDY is low-true */
1222 +#define AR2315_LBCONF_WE 0x00000010 /* =1 Write En is low-true */
1223 +#define AR2315_LBCONF_WAIT 0x00000020 /* =1 WAIT is low-true */
1224 +#define AR2315_LBCONF_ADS 0x00000040 /* =1 Adr Strobe is low-true */
1225 +#define AR2315_LBCONF_MOT 0x00000080 /* =0 Intel, =1 Motorola */
1226 +#define AR2315_LBCONF_8CS 0x00000100 /* =1 8 bits CS, 0= 16bits */
1227 +#define AR2315_LBCONF_8DS 0x00000200 /* =1 8 bits Data S, 0=16bits */
1228 +#define AR2315_LBCONF_ADS_EN 0x00000400 /* =1 Enable ADS */
1229 +#define AR2315_LBCONF_ADR_OE 0x00000800 /* =1 Adr cap on OE, WE or DS */
1230 +#define AR2315_LBCONF_ADDT_MUX 0x00001000 /* =1 Adr and Data share bus */
1231 +#define AR2315_LBCONF_DATA_OE 0x00002000 /* =1 Data cap on OE, WE, DS */
1232 +#define AR2315_LBCONF_16DATA 0x00004000 /* =1 Data is 16 bits wide */
1233 +#define AR2315_LBCONF_SWAPDT 0x00008000 /* =1 Byte swap data */
1234 +#define AR2315_LBCONF_SYNC 0x00010000 /* =1 Bus synchronous to clk */
1235 +#define AR2315_LBCONF_INT 0x00020000 /* =1 Intr is low true */
1236 +#define AR2315_LBCONF_INT_CTR0 0x00000000 /* GND high-Z, Vdd is high-Z */
1237 +#define AR2315_LBCONF_INT_CTR1 0x00040000 /* GND drive, Vdd is high-Z */
1238 +#define AR2315_LBCONF_INT_CTR2 0x00080000 /* GND high-Z, Vdd drive */
1239 +#define AR2315_LBCONF_INT_CTR3 0x000C0000 /* GND drive, Vdd drive */
1240 +#define AR2315_LBCONF_RDY_WAIT 0x00100000 /* =1 RDY is negative of WAIT */
1241 +#define AR2315_LBCONF_INT_PULSE 0x00200000 /* =1 Interrupt is a pulse */
1242 +#define AR2315_LBCONF_ENABLE 0x00400000 /* =1 Falcon respond to LB */
1243 +
1244 +#define AR2315_LB_CLKSEL (AR2315_LOCAL + 0x0004)
1245 +#define AR2315_LBCLK_EXT 0x0001 /* use external clk for lb */
1246 +
1247 +#define AR2315_LB_1MS (AR2315_LOCAL + 0x0008)
1248 +#define AR2315_LB1MS_MASK 0x3FFFF /* # of AHB clk cycles in 1ms */
1249 +
1250 +#define AR2315_LB_MISCCFG (AR2315_LOCAL + 0x000C)
1251 +#define AR2315_LBM_TXD_EN 0x00000001 /* Enable TXD for fragments */
1252 +#define AR2315_LBM_RX_INTEN 0x00000002 /* Enable LB ints on RX ready */
1253 +#define AR2315_LBM_MBOXWR_INTEN 0x00000004 /* Enable LB ints on mbox wr */
1254 +#define AR2315_LBM_MBOXRD_INTEN 0x00000008 /* Enable LB ints on mbox rd */
1255 +#define AR2315_LMB_DESCSWAP_EN 0x00000010 /* Byte swap desc enable */
1256 +#define AR2315_LBM_TIMEOUT_MASK 0x00FFFF80
1257 +#define AR2315_LBM_TIMEOUT_SHFT 7
1258 +#define AR2315_LBM_PORTMUX 0x07000000
1259 +
1260 +
1261 +#define AR2315_LB_RXTSOFF (AR2315_LOCAL + 0x0010)
1262 +
1263 +#define AR2315_LB_TX_CHAIN_EN (AR2315_LOCAL + 0x0100)
1264 +#define AR2315_LB_TXEN_0 0x01
1265 +#define AR2315_LB_TXEN_1 0x02
1266 +#define AR2315_LB_TXEN_2 0x04
1267 +#define AR2315_LB_TXEN_3 0x08
1268 +
1269 +#define AR2315_LB_TX_CHAIN_DIS (AR2315_LOCAL + 0x0104)
1270 +#define AR2315_LB_TX_DESC_PTR (AR2315_LOCAL + 0x0200)
1271 +
1272 +#define AR2315_LB_RX_CHAIN_EN (AR2315_LOCAL + 0x0400)
1273 +#define AR2315_LB_RXEN 0x01
1274 +
1275 +#define AR2315_LB_RX_CHAIN_DIS (AR2315_LOCAL + 0x0404)
1276 +#define AR2315_LB_RX_DESC_PTR (AR2315_LOCAL + 0x0408)
1277 +
1278 +#define AR2315_LB_INT_STATUS (AR2315_LOCAL + 0x0500)
1279 +#define AR2315_INT_TX_DESC 0x0001
1280 +#define AR2315_INT_TX_OK 0x0002
1281 +#define AR2315_INT_TX_ERR 0x0004
1282 +#define AR2315_INT_TX_EOF 0x0008
1283 +#define AR2315_INT_RX_DESC 0x0010
1284 +#define AR2315_INT_RX_OK 0x0020
1285 +#define AR2315_INT_RX_ERR 0x0040
1286 +#define AR2315_INT_RX_EOF 0x0080
1287 +#define AR2315_INT_TX_TRUNC 0x0100
1288 +#define AR2315_INT_TX_STARVE 0x0200
1289 +#define AR2315_INT_LB_TIMEOUT 0x0400
1290 +#define AR2315_INT_LB_ERR 0x0800
1291 +#define AR2315_INT_MBOX_WR 0x1000
1292 +#define AR2315_INT_MBOX_RD 0x2000
1293 +
1294 +/* Bit definitions for INT MASK are the same as INT_STATUS */
1295 +#define AR2315_LB_INT_MASK (AR2315_LOCAL + 0x0504)
1296 +
1297 +#define AR2315_LB_INT_EN (AR2315_LOCAL + 0x0508)
1298 +#define AR2315_LB_MBOX (AR2315_LOCAL + 0x0600)
1299 +
1300 +/*
1301 + * IR Interface Registers
1302 + */
1303 +#define AR2315_IR_PKTDATA (AR2315_IR + 0x0000)
1304 +
1305 +#define AR2315_IR_PKTLEN (AR2315_IR + 0x07fc) /* 0 - 63 */
1306 +
1307 +#define AR2315_IR_CONTROL (AR2315_IR + 0x0800)
1308 +#define AR2315_IRCTL_TX 0x00000000 /* use as tranmitter */
1309 +#define AR2315_IRCTL_RX 0x00000001 /* use as receiver */
1310 +#define AR2315_IRCTL_SAMPLECLK_MASK 0x00003ffe /* Sample clk divisor mask */
1311 +#define AR2315_IRCTL_SAMPLECLK_SHFT 1
1312 +#define AR2315_IRCTL_OUTPUTCLK_MASK 0x03ffc000 /* Output clk divisor mask */
1313 +#define AR2315_IRCTL_OUTPUTCLK_SHFT 14
1314 +
1315 +#define AR2315_IR_STATUS (AR2315_IR + 0x0804)
1316 +#define AR2315_IRSTS_RX 0x00000001 /* receive in progress */
1317 +#define AR2315_IRSTS_TX 0x00000002 /* transmit in progress */
1318 +
1319 +#define AR2315_IR_CONFIG (AR2315_IR + 0x0808)
1320 +#define AR2315_IRCFG_INVIN 0x00000001 /* invert input polarity */
1321 +#define AR2315_IRCFG_INVOUT 0x00000002 /* invert output polarity */
1322 +#define AR2315_IRCFG_SEQ_START_WIN_SEL 0x00000004 /* 1 => 28, 0 => 7 */
1323 +#define AR2315_IRCFG_SEQ_START_THRESH 0x000000f0 /* */
1324 +#define AR2315_IRCFG_SEQ_END_UNIT_SEL 0x00000100 /* */
1325 +#define AR2315_IRCFG_SEQ_END_UNIT_THRESH 0x00007e00 /* */
1326 +#define AR2315_IRCFG_SEQ_END_WIN_SEL 0x00008000 /* */
1327 +#define AR2315_IRCFG_SEQ_END_WIN_THRESH 0x001f0000 /* */
1328 +#define AR2315_IRCFG_NUM_BACKOFF_WORDS 0x01e00000 /* */
1329 +
1330 +#define HOST_PCI_DEV_ID 3
1331 +#define HOST_PCI_MBAR0 0x10000000
1332 +#define HOST_PCI_MBAR1 0x20000000
1333 +#define HOST_PCI_MBAR2 0x30000000
1334 +
1335 +#define HOST_PCI_SDRAM_BASEADDR HOST_PCI_MBAR1
1336 +#define PCI_DEVICE_MEM_SPACE 0x800000
1337 +
1338 +#endif /* __AR2315_REG_H */
1339 --- /dev/null
1340 +++ b/arch/mips/include/asm/mach-ar231x/ar5312_regs.h
1341 @@ -0,0 +1,236 @@
1342 +/*
1343 + * This file is subject to the terms and conditions of the GNU General Public
1344 + * License. See the file "COPYING" in the main directory of this archive
1345 + * for more details.
1346 + *
1347 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
1348 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
1349 + * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
1350 + */
1351 +
1352 +#ifndef AR5312_H
1353 +#define AR5312_H
1354 +
1355 +#include <asm/addrspace.h>
1356 +
1357 +/*
1358 + * IRQs
1359 + */
1360 +
1361 +#define AR5312_IRQ_WLAN0_INTRS MIPS_CPU_IRQ_BASE+2 /* C0_CAUSE: 0x0400 */
1362 +#define AR5312_IRQ_ENET0_INTRS MIPS_CPU_IRQ_BASE+3 /* C0_CAUSE: 0x0800 */
1363 +#define AR5312_IRQ_ENET1_INTRS MIPS_CPU_IRQ_BASE+4 /* C0_CAUSE: 0x1000 */
1364 +#define AR5312_IRQ_WLAN1_INTRS MIPS_CPU_IRQ_BASE+5 /* C0_CAUSE: 0x2000 */
1365 +#define AR5312_IRQ_MISC_INTRS MIPS_CPU_IRQ_BASE+6 /* C0_CAUSE: 0x4000 */
1366 +
1367 +
1368 +/* Address Map */
1369 +#define AR531X_WLAN0 0x18000000
1370 +#define AR531X_WLAN1 0x18500000
1371 +#define AR531X_ENET0 0x18100000
1372 +#define AR531X_ENET1 0x18200000
1373 +#define AR531X_SDRAMCTL 0x18300000
1374 +#define AR531X_FLASHCTL 0x18400000
1375 +#define AR531X_APBBASE 0x1c000000
1376 +#define AR531X_FLASH 0x1e000000
1377 +#define AR531X_UART0 0xbc000003 /* UART MMR */
1378 +
1379 +/*
1380 + * AR531X_NUM_ENET_MAC defines the number of ethernet MACs that
1381 + * should be considered available. The AR5312 supports 2 enet MACS,
1382 + * even though many reference boards only actually use 1 of them
1383 + * (i.e. Only MAC 0 is actually connected to an enet PHY or PHY switch.
1384 + * The AR2312 supports 1 enet MAC.
1385 + */
1386 +#define AR531X_NUM_ENET_MAC 2
1387 +
1388 +/*
1389 + * Need these defines to determine true number of ethernet MACs
1390 + */
1391 +#define AR5212_AR5312_REV2 0x0052 /* AR5312 WMAC (AP31) */
1392 +#define AR5212_AR5312_REV7 0x0057 /* AR5312 WMAC (AP30-040) */
1393 +#define AR5212_AR2313_REV8 0x0058 /* AR2313 WMAC (AP43-030) */
1394 +#define AR531X_RADIO_MASK_OFF 0xc8
1395 +#define AR531X_RADIO0_MASK 0x0003
1396 +#define AR531X_RADIO1_MASK 0x000c
1397 +#define AR531X_RADIO1_S 2
1398 +
1399 +/*
1400 + * AR531X_NUM_WMAC defines the number of Wireless MACs that\
1401 + * should be considered available.
1402 + */
1403 +#define AR531X_NUM_WMAC 2
1404 +
1405 +/* Reset/Timer Block Address Map */
1406 +#define AR531X_RESETTMR (AR531X_APBBASE + 0x3000)
1407 +#define AR531X_TIMER (AR531X_RESETTMR + 0x0000) /* countdown timer */
1408 +#define AR531X_WD_CTRL (AR531X_RESETTMR + 0x0008) /* watchdog cntrl */
1409 +#define AR531X_WD_TIMER (AR531X_RESETTMR + 0x000c) /* watchdog timer */
1410 +#define AR531X_ISR (AR531X_RESETTMR + 0x0010) /* Intr Status Reg */
1411 +#define AR531X_IMR (AR531X_RESETTMR + 0x0014) /* Intr Mask Reg */
1412 +#define AR531X_RESET (AR531X_RESETTMR + 0x0020)
1413 +#define AR5312_CLOCKCTL1 (AR531X_RESETTMR + 0x0064)
1414 +#define AR5312_SCRATCH (AR531X_RESETTMR + 0x006c)
1415 +#define AR531X_PROCADDR (AR531X_RESETTMR + 0x0070)
1416 +#define AR531X_PROC1 (AR531X_RESETTMR + 0x0074)
1417 +#define AR531X_DMAADDR (AR531X_RESETTMR + 0x0078)
1418 +#define AR531X_DMA1 (AR531X_RESETTMR + 0x007c)
1419 +#define AR531X_ENABLE (AR531X_RESETTMR + 0x0080) /* interface enb */
1420 +#define AR531X_REV (AR531X_RESETTMR + 0x0090) /* revision */
1421 +
1422 +/* AR531X_WD_CTRL register bit field definitions */
1423 +#define AR531X_WD_CTRL_IGNORE_EXPIRATION 0x0000
1424 +#define AR531X_WD_CTRL_NMI 0x0001
1425 +#define AR531X_WD_CTRL_RESET 0x0002
1426 +
1427 +/* AR531X_ISR register bit field definitions */
1428 +#define AR531X_ISR_NONE 0x0000
1429 +#define AR531X_ISR_TIMER 0x0001
1430 +#define AR531X_ISR_AHBPROC 0x0002
1431 +#define AR531X_ISR_AHBDMA 0x0004
1432 +#define AR531X_ISR_GPIO 0x0008
1433 +#define AR531X_ISR_UART0 0x0010
1434 +#define AR531X_ISR_UART0DMA 0x0020
1435 +#define AR531X_ISR_WD 0x0040
1436 +#define AR531X_ISR_LOCAL 0x0080
1437 +
1438 +/* AR531X_RESET register bit field definitions */
1439 +#define AR531X_RESET_SYSTEM 0x00000001 /* cold reset full system */
1440 +#define AR531X_RESET_PROC 0x00000002 /* cold reset MIPS core */
1441 +#define AR531X_RESET_WLAN0 0x00000004 /* cold reset WLAN MAC and BB */
1442 +#define AR531X_RESET_EPHY0 0x00000008 /* cold reset ENET0 phy */
1443 +#define AR531X_RESET_EPHY1 0x00000010 /* cold reset ENET1 phy */
1444 +#define AR531X_RESET_ENET0 0x00000020 /* cold reset ENET0 mac */
1445 +#define AR531X_RESET_ENET1 0x00000040 /* cold reset ENET1 mac */
1446 +#define AR531X_RESET_UART0 0x00000100 /* cold reset UART0 (high speed) */
1447 +#define AR531X_RESET_WLAN1 0x00000200 /* cold reset WLAN MAC/BB */
1448 +#define AR531X_RESET_APB 0x00000400 /* cold reset APB (ar5312) */
1449 +#define AR531X_RESET_WARM_PROC 0x00001000 /* warm reset MIPS core */
1450 +#define AR531X_RESET_WARM_WLAN0_MAC 0x00002000 /* warm reset WLAN0 MAC */
1451 +#define AR531X_RESET_WARM_WLAN0_BB 0x00004000 /* warm reset WLAN0 BaseBand */
1452 +#define AR531X_RESET_NMI 0x00010000 /* send an NMI to the processor */
1453 +#define AR531X_RESET_WARM_WLAN1_MAC 0x00020000 /* warm reset WLAN1 mac */
1454 +#define AR531X_RESET_WARM_WLAN1_BB 0x00040000 /* warm reset WLAN1 baseband */
1455 +#define AR531X_RESET_LOCAL_BUS 0x00080000 /* reset local bus */
1456 +#define AR531X_RESET_WDOG 0x00100000 /* last reset was a watchdog */
1457 +
1458 +#define AR531X_RESET_WMAC0_BITS \
1459 + AR531X_RESET_WLAN0 |\
1460 + AR531X_RESET_WARM_WLAN0_MAC |\
1461 + AR531X_RESET_WARM_WLAN0_BB
1462 +
1463 +#define AR531X_RESERT_WMAC1_BITS \
1464 + AR531X_RESET_WLAN1 |\
1465 + AR531X_RESET_WARM_WLAN1_MAC |\
1466 + AR531X_RESET_WARM_WLAN1_BB
1467 +
1468 +/* AR5312_CLOCKCTL1 register bit field definitions */
1469 +#define AR5312_CLOCKCTL1_PREDIVIDE_MASK 0x00000030
1470 +#define AR5312_CLOCKCTL1_PREDIVIDE_SHIFT 4
1471 +#define AR5312_CLOCKCTL1_MULTIPLIER_MASK 0x00001f00
1472 +#define AR5312_CLOCKCTL1_MULTIPLIER_SHIFT 8
1473 +#define AR5312_CLOCKCTL1_DOUBLER_MASK 0x00010000
1474 +
1475 +/* Valid for AR5312 and AR2312 */
1476 +#define AR5312_CLOCKCTL1_PREDIVIDE_MASK 0x00000030
1477 +#define AR5312_CLOCKCTL1_PREDIVIDE_SHIFT 4
1478 +#define AR5312_CLOCKCTL1_MULTIPLIER_MASK 0x00001f00
1479 +#define AR5312_CLOCKCTL1_MULTIPLIER_SHIFT 8
1480 +#define AR5312_CLOCKCTL1_DOUBLER_MASK 0x00010000
1481 +
1482 +/* Valid for AR2313 */
1483 +#define AR2313_CLOCKCTL1_PREDIVIDE_MASK 0x00003000
1484 +#define AR2313_CLOCKCTL1_PREDIVIDE_SHIFT 12
1485 +#define AR2313_CLOCKCTL1_MULTIPLIER_MASK 0x001f0000
1486 +#define AR2313_CLOCKCTL1_MULTIPLIER_SHIFT 16
1487 +#define AR2313_CLOCKCTL1_DOUBLER_MASK 0x00000000
1488 +
1489 +
1490 +/* AR531X_ENABLE register bit field definitions */
1491 +#define AR531X_ENABLE_WLAN0 0x0001
1492 +#define AR531X_ENABLE_ENET0 0x0002
1493 +#define AR531X_ENABLE_ENET1 0x0004
1494 +#define AR531X_ENABLE_UART_AND_WLAN1_PIO 0x0008 /* UART, and WLAN1 PIOs */
1495 +#define AR531X_ENABLE_WLAN1_DMA 0x0010 /* WLAN1 DMAs */
1496 +#define AR531X_ENABLE_WLAN1 \
1497 + (AR531X_ENABLE_UART_AND_WLAN1_PIO | AR531X_ENABLE_WLAN1_DMA)
1498 +
1499 +/* AR531X_REV register bit field definitions */
1500 +#define AR531X_REV_WMAC_MAJ 0xf000
1501 +#define AR531X_REV_WMAC_MAJ_S 12
1502 +#define AR531X_REV_WMAC_MIN 0x0f00
1503 +#define AR531X_REV_WMAC_MIN_S 8
1504 +#define AR531X_REV_MAJ 0x00f0
1505 +#define AR531X_REV_MAJ_S 4
1506 +#define AR531X_REV_MIN 0x000f
1507 +#define AR531X_REV_MIN_S 0
1508 +#define AR531X_REV_CHIP (AR531X_REV_MAJ|AR531X_REV_MIN)
1509 +
1510 +/* Major revision numbers, bits 7..4 of Revision ID register */
1511 +#define AR531X_REV_MAJ_AR5312 0x4
1512 +#define AR531X_REV_MAJ_AR2313 0x5
1513 +
1514 +/* Minor revision numbers, bits 3..0 of Revision ID register */
1515 +#define AR5312_REV_MIN_DUAL 0x0 /* Dual WLAN version */
1516 +#define AR5312_REV_MIN_SINGLE 0x1 /* Single WLAN version */
1517 +
1518 +/* AR531X_FLASHCTL register bit field definitions */
1519 +#define FLASHCTL_IDCY 0x0000000f /* Idle cycle turn around time */
1520 +#define FLASHCTL_IDCY_S 0
1521 +#define FLASHCTL_WST1 0x000003e0 /* Wait state 1 */
1522 +#define FLASHCTL_WST1_S 5
1523 +#define FLASHCTL_RBLE 0x00000400 /* Read byte lane enable */
1524 +#define FLASHCTL_WST2 0x0000f800 /* Wait state 2 */
1525 +#define FLASHCTL_WST2_S 11
1526 +#define FLASHCTL_AC 0x00070000 /* Flash address check (added) */
1527 +#define FLASHCTL_AC_S 16
1528 +#define FLASHCTL_AC_128K 0x00000000
1529 +#define FLASHCTL_AC_256K 0x00010000
1530 +#define FLASHCTL_AC_512K 0x00020000
1531 +#define FLASHCTL_AC_1M 0x00030000
1532 +#define FLASHCTL_AC_2M 0x00040000
1533 +#define FLASHCTL_AC_4M 0x00050000
1534 +#define FLASHCTL_AC_8M 0x00060000
1535 +#define FLASHCTL_AC_RES 0x00070000 /* 16MB is not supported */
1536 +#define FLASHCTL_E 0x00080000 /* Flash bank enable (added) */
1537 +#define FLASHCTL_BUSERR 0x01000000 /* Bus transfer error status flag */
1538 +#define FLASHCTL_WPERR 0x02000000 /* Write protect error status flag */
1539 +#define FLASHCTL_WP 0x04000000 /* Write protect */
1540 +#define FLASHCTL_BM 0x08000000 /* Burst mode */
1541 +#define FLASHCTL_MW 0x30000000 /* Memory width */
1542 +#define FLASHCTL_MWx8 0x00000000 /* Memory width x8 */
1543 +#define FLASHCTL_MWx16 0x10000000 /* Memory width x16 */
1544 +#define FLASHCTL_MWx32 0x20000000 /* Memory width x32 (not supported) */
1545 +#define FLASHCTL_ATNR 0x00000000 /* Access type == no retry */
1546 +#define FLASHCTL_ATR 0x80000000 /* Access type == retry every */
1547 +#define FLASHCTL_ATR4 0xc0000000 /* Access type == retry every 4 */
1548 +
1549 +/* ARM Flash Controller -- 3 flash banks with either x8 or x16 devices. */
1550 +#define AR531X_FLASHCTL0 (AR531X_FLASHCTL + 0x00)
1551 +#define AR531X_FLASHCTL1 (AR531X_FLASHCTL + 0x04)
1552 +#define AR531X_FLASHCTL2 (AR531X_FLASHCTL + 0x08)
1553 +
1554 +/* ARM SDRAM Controller -- just enough to determine memory size */
1555 +#define AR531X_MEM_CFG1 (AR531X_SDRAMCTL + 0x04)
1556 +#define MEM_CFG1_AC0 0x00000700 /* bank 0: SDRAM addr check (added) */
1557 +#define MEM_CFG1_AC0_S 8
1558 +#define MEM_CFG1_AC1 0x00007000 /* bank 1: SDRAM addr check (added) */
1559 +#define MEM_CFG1_AC1_S 12
1560 +
1561 +/* GPIO Address Map */
1562 +#define AR531X_GPIO (AR531X_APBBASE + 0x2000)
1563 +#define AR531X_GPIO_DO (AR531X_GPIO + 0x00) /* output register */
1564 +#define AR531X_GPIO_DI (AR531X_GPIO + 0x04) /* intput register */
1565 +#define AR531X_GPIO_CR (AR531X_GPIO + 0x08) /* control register */
1566 +
1567 +/* GPIO Control Register bit field definitions */
1568 +#define AR531X_GPIO_CR_M(x) (1 << (x)) /* mask for i/o */
1569 +#define AR531X_GPIO_CR_O(x) (0 << (x)) /* mask for output */
1570 +#define AR531X_GPIO_CR_I(x) (1 << (x)) /* mask for input */
1571 +#define AR531X_GPIO_CR_INT(x) (1 << ((x)+8)) /* mask for interrupt */
1572 +#define AR531X_GPIO_CR_UART(x) (1 << ((x)+16)) /* uart multiplex */
1573 +#define AR531X_NUM_GPIO 8
1574 +
1575 +
1576 +#endif
1577 +
1578 --- /dev/null
1579 +++ b/arch/mips/ar231x/ar5312.c
1580 @@ -0,0 +1,549 @@
1581 +/*
1582 + * This file is subject to the terms and conditions of the GNU General Public
1583 + * License. See the file "COPYING" in the main directory of this archive
1584 + * for more details.
1585 + *
1586 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
1587 + * Copyright (C) 2006 FON Technology, SL.
1588 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
1589 + * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
1590 + */
1591 +
1592 +/*
1593 + * Platform devices for Atheros SoCs
1594 + */
1595 +
1596 +#include <generated/autoconf.h>
1597 +#include <linux/init.h>
1598 +#include <linux/module.h>
1599 +#include <linux/types.h>
1600 +#include <linux/string.h>
1601 +#include <linux/mtd/physmap.h>
1602 +#include <linux/platform_device.h>
1603 +#include <linux/kernel.h>
1604 +#include <linux/reboot.h>
1605 +#include <linux/leds.h>
1606 +#include <asm/bootinfo.h>
1607 +#include <asm/reboot.h>
1608 +#include <asm/time.h>
1609 +#include <asm/irq.h>
1610 +#include <asm/io.h>
1611 +#include <gpio.h>
1612 +
1613 +#include <ar231x_platform.h>
1614 +#include <ar5312_regs.h>
1615 +#include <ar231x.h>
1616 +#include "devices.h"
1617 +#include "ar5312.h"
1618 +
1619 +static void
1620 +ar5312_misc_irq_dispatch(void)
1621 +{
1622 + unsigned int ar231x_misc_intrs = ar231x_read_reg(AR531X_ISR) & ar231x_read_reg(AR531X_IMR);
1623 +
1624 + if (ar231x_misc_intrs & AR531X_ISR_TIMER) {
1625 + do_IRQ(AR531X_MISC_IRQ_TIMER);
1626 + (void)ar231x_read_reg(AR531X_TIMER);
1627 + } else if (ar231x_misc_intrs & AR531X_ISR_AHBPROC)
1628 + do_IRQ(AR531X_MISC_IRQ_AHB_PROC);
1629 + else if ((ar231x_misc_intrs & AR531X_ISR_UART0))
1630 + do_IRQ(AR531X_MISC_IRQ_UART0);
1631 + else if (ar231x_misc_intrs & AR531X_ISR_WD)
1632 + do_IRQ(AR531X_MISC_IRQ_WATCHDOG);
1633 + else
1634 + do_IRQ(AR531X_MISC_IRQ_NONE);
1635 +}
1636 +
1637 +static asmlinkage void
1638 +ar5312_irq_dispatch(void)
1639 +{
1640 + int pending = read_c0_status() & read_c0_cause();
1641 +
1642 + if (pending & CAUSEF_IP2)
1643 + do_IRQ(AR5312_IRQ_WLAN0_INTRS);
1644 + else if (pending & CAUSEF_IP3)
1645 + do_IRQ(AR5312_IRQ_ENET0_INTRS);
1646 + else if (pending & CAUSEF_IP4)
1647 + do_IRQ(AR5312_IRQ_ENET1_INTRS);
1648 + else if (pending & CAUSEF_IP5)
1649 + do_IRQ(AR5312_IRQ_WLAN1_INTRS);
1650 + else if (pending & CAUSEF_IP6)
1651 + ar5312_misc_irq_dispatch();
1652 + else if (pending & CAUSEF_IP7)
1653 + do_IRQ(AR531X_IRQ_CPU_CLOCK);
1654 +}
1655 +
1656 +
1657 +/* Enable the specified AR531X_MISC_IRQ interrupt */
1658 +static void
1659 +ar5312_misc_intr_enable(unsigned int irq)
1660 +{
1661 + unsigned int imr;
1662 +
1663 + imr = ar231x_read_reg(AR531X_IMR);
1664 + imr |= (1 << (irq - AR531X_MISC_IRQ_BASE - 1));
1665 + ar231x_write_reg(AR531X_IMR, imr);
1666 +}
1667 +
1668 +/* Disable the specified AR531X_MISC_IRQ interrupt */
1669 +static void
1670 +ar5312_misc_intr_disable(unsigned int irq)
1671 +{
1672 + unsigned int imr;
1673 +
1674 + imr = ar231x_read_reg(AR531X_IMR);
1675 + imr &= ~(1 << (irq - AR531X_MISC_IRQ_BASE - 1));
1676 + ar231x_write_reg(AR531X_IMR, imr);
1677 + ar231x_read_reg(AR531X_IMR); /* flush write buffer */
1678 +}
1679 +
1680 +static void
1681 +ar5312_misc_intr_end(unsigned int irq)
1682 +{
1683 + if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
1684 + ar5312_misc_intr_enable(irq);
1685 +}
1686 +
1687 +static struct irq_chip ar5312_misc_intr_controller = {
1688 + .name = "AR5312-MISC",
1689 + .disable = ar5312_misc_intr_disable,
1690 + .ack = ar5312_misc_intr_disable,
1691 + .mask_ack = ar5312_misc_intr_disable,
1692 + .mask = ar5312_misc_intr_disable,
1693 + .unmask = ar5312_misc_intr_enable,
1694 + .end = ar5312_misc_intr_end,
1695 +};
1696 +
1697 +
1698 +static irqreturn_t ar5312_ahb_proc_handler(int cpl, void *dev_id)
1699 +{
1700 + u32 proc1 = ar231x_read_reg(AR531X_PROC1);
1701 + u32 procAddr = ar231x_read_reg(AR531X_PROCADDR); /* clears error state */
1702 + u32 dma1 = ar231x_read_reg(AR531X_DMA1);
1703 + u32 dmaAddr = ar231x_read_reg(AR531X_DMAADDR); /* clears error state */
1704 +
1705 + printk("AHB interrupt: PROCADDR=0x%8.8x PROC1=0x%8.8x DMAADDR=0x%8.8x DMA1=0x%8.8x\n",
1706 + procAddr, proc1, dmaAddr, dma1);
1707 +
1708 + machine_restart("AHB error"); /* Catastrophic failure */
1709 + return IRQ_HANDLED;
1710 +}
1711 +
1712 +
1713 +static struct irqaction ar5312_ahb_proc_interrupt = {
1714 + .handler = ar5312_ahb_proc_handler,
1715 + .flags = IRQF_DISABLED,
1716 + .name = "ar5312_ahb_proc_interrupt",
1717 +};
1718 +
1719 +
1720 +static struct irqaction cascade = {
1721 + .handler = no_action,
1722 + .flags = IRQF_DISABLED,
1723 + .name = "cascade",
1724 +};
1725 +
1726 +void __init ar5312_irq_init(void)
1727 +{
1728 + int i;
1729 +
1730 + if (!is_5312())
1731 + return;
1732 +
1733 + ar231x_irq_dispatch = ar5312_irq_dispatch;
1734 + for (i = 0; i < AR531X_MISC_IRQ_COUNT; i++) {
1735 + int irq = AR531X_MISC_IRQ_BASE + i;
1736 + set_irq_chip_and_handler(irq, &ar5312_misc_intr_controller,
1737 + handle_level_irq);
1738 + }
1739 + setup_irq(AR531X_MISC_IRQ_AHB_PROC, &ar5312_ahb_proc_interrupt);
1740 + setup_irq(AR5312_IRQ_MISC_INTRS, &cascade);
1741 +}
1742 +
1743 +const struct ar231x_gpiodev ar5312_gpiodev;
1744 +
1745 +static u32
1746 +ar5312_gpio_get_output(void)
1747 +{
1748 + u32 reg;
1749 + reg = ~(ar231x_read_reg(AR531X_GPIO_CR));
1750 + reg &= ar5312_gpiodev.valid_mask;
1751 + return reg;
1752 +}
1753 +
1754 +static u32
1755 +ar5312_gpio_set_output(u32 mask, u32 val)
1756 +{
1757 + u32 reg;
1758 +
1759 + reg = ar231x_read_reg(AR531X_GPIO_CR);
1760 + reg |= mask;
1761 + reg &= ~val;
1762 + ar231x_write_reg(AR531X_GPIO_CR, reg);
1763 + return reg;
1764 +}
1765 +
1766 +static u32
1767 +ar5312_gpio_get(void)
1768 +{
1769 + u32 reg;
1770 + reg = ar231x_read_reg(AR531X_GPIO_DI);
1771 + reg &= ar5312_gpiodev.valid_mask;
1772 + return reg;
1773 +}
1774 +
1775 +static u32
1776 +ar5312_gpio_set(u32 mask, u32 value)
1777 +{
1778 + u32 reg;
1779 + reg = ar231x_read_reg(AR531X_GPIO_DO);
1780 + reg &= ~mask;
1781 + reg |= value;
1782 + ar231x_write_reg(AR531X_GPIO_DO, reg);
1783 + return reg;
1784 +}
1785 +
1786 +const struct ar231x_gpiodev ar5312_gpiodev = {
1787 + .valid_mask = (1 << 8) - 1,
1788 + .get_output = ar5312_gpio_get_output,
1789 + .set_output = ar5312_gpio_set_output,
1790 + .get = ar5312_gpio_get,
1791 + .set = ar5312_gpio_set,
1792 +};
1793 +
1794 +static struct physmap_flash_data ar5312_flash_data = {
1795 + .width = 2,
1796 +};
1797 +
1798 +static struct resource ar5312_flash_resource = {
1799 + .start = AR531X_FLASH,
1800 + .end = AR531X_FLASH + 0x800000 - 1,
1801 + .flags = IORESOURCE_MEM,
1802 +};
1803 +
1804 +static struct ar231x_eth ar5312_eth0_data = {
1805 + .reset_base = AR531X_RESET,
1806 + .reset_mac = AR531X_RESET_ENET0,
1807 + .reset_phy = AR531X_RESET_EPHY0,
1808 + .phy_base = KSEG1ADDR(AR531X_ENET0),
1809 + .config = &ar231x_board,
1810 +};
1811 +
1812 +static struct ar231x_eth ar5312_eth1_data = {
1813 + .reset_base = AR531X_RESET,
1814 + .reset_mac = AR531X_RESET_ENET1,
1815 + .reset_phy = AR531X_RESET_EPHY1,
1816 + .phy_base = KSEG1ADDR(AR531X_ENET1),
1817 + .config = &ar231x_board,
1818 +};
1819 +
1820 +static struct platform_device ar5312_physmap_flash = {
1821 + .name = "physmap-flash",
1822 + .id = 0,
1823 + .dev.platform_data = &ar5312_flash_data,
1824 + .resource = &ar5312_flash_resource,
1825 + .num_resources = 1,
1826 +};
1827 +
1828 +#ifdef CONFIG_LEDS_GPIO
1829 +static struct gpio_led ar5312_leds[] = {
1830 + { .name = "wlan", .gpio = 0, .active_low = 1, },
1831 +};
1832 +
1833 +static const struct gpio_led_platform_data ar5312_led_data = {
1834 + .num_leds = ARRAY_SIZE(ar5312_leds),
1835 + .leds = (void *) ar5312_leds,
1836 +};
1837 +
1838 +static struct platform_device ar5312_gpio_leds = {
1839 + .name = "leds-gpio",
1840 + .id = -1,
1841 + .dev.platform_data = (void *) &ar5312_led_data,
1842 +};
1843 +#endif
1844 +
1845 +/*
1846 + * NB: This mapping size is larger than the actual flash size,
1847 + * but this shouldn't be a problem here, because the flash
1848 + * will simply be mapped multiple times.
1849 + */
1850 +static char __init *ar5312_flash_limit(void)
1851 +{
1852 + u32 ctl;
1853 + /*
1854 + * Configure flash bank 0.
1855 + * Assume 8M window size. Flash will be aliased if it's smaller
1856 + */
1857 + ctl = FLASHCTL_E |
1858 + FLASHCTL_AC_8M |
1859 + FLASHCTL_RBLE |
1860 + (0x01 << FLASHCTL_IDCY_S) |
1861 + (0x07 << FLASHCTL_WST1_S) |
1862 + (0x07 << FLASHCTL_WST2_S) |
1863 + (ar231x_read_reg(AR531X_FLASHCTL0) & FLASHCTL_MW);
1864 +
1865 + ar231x_write_reg(AR531X_FLASHCTL0, ctl);
1866 +
1867 + /* Disable other flash banks */
1868 + ar231x_write_reg(AR531X_FLASHCTL1,
1869 + ar231x_read_reg(AR531X_FLASHCTL1) & ~(FLASHCTL_E | FLASHCTL_AC));
1870 +
1871 + ar231x_write_reg(AR531X_FLASHCTL2,
1872 + ar231x_read_reg(AR531X_FLASHCTL2) & ~(FLASHCTL_E | FLASHCTL_AC));
1873 +
1874 + return (char *) KSEG1ADDR(AR531X_FLASH + 0x800000);
1875 +}
1876 +
1877 +int __init ar5312_init_devices(void)
1878 +{
1879 + struct ar231x_boarddata *config;
1880 + u32 fctl = 0;
1881 + const u8 *radio;
1882 + u8 *c;
1883 +
1884 + if (!is_5312())
1885 + return 0;
1886 +
1887 + /* Locate board/radio config data */
1888 + ar231x_find_config(ar5312_flash_limit());
1889 + config = ar231x_board.config;
1890 +
1891 +
1892 + /*
1893 + * Chip IDs and hardware detection for some Atheros
1894 + * models are really broken!
1895 + *
1896 + * Atheros uses a disabled WMAC0 and Silicon ID of AR5312
1897 + * as indication for AR2312, which is otherwise
1898 + * indistinguishable from the real AR5312.
1899 + */
1900 + if (ar231x_board.radio) {
1901 + radio = ar231x_board.radio + AR531X_RADIO_MASK_OFF;
1902 + if ((*((const u32 *) radio) & AR531X_RADIO0_MASK) == 0)
1903 + config->flags |= BD_ISCASPER;
1904 + } else
1905 + radio = NULL;
1906 +
1907 + /* AR2313 has CPU minor rev. 10 */
1908 + if ((current_cpu_data.processor_id & 0xff) == 0x0a)
1909 + ar231x_devtype = DEV_TYPE_AR2313;
1910 +
1911 + /* AR2312 shares the same Silicon ID as AR5312 */
1912 + else if (config->flags & BD_ISCASPER)
1913 + ar231x_devtype = DEV_TYPE_AR2312;
1914 +
1915 + /* Everything else is probably AR5312 or compatible */
1916 + else
1917 + ar231x_devtype = DEV_TYPE_AR5312;
1918 +
1919 + /* fixup flash width */
1920 + fctl = ar231x_read_reg(AR531X_FLASHCTL) & FLASHCTL_MW;
1921 + switch (fctl) {
1922 + case FLASHCTL_MWx16:
1923 + ar5312_flash_data.width = 2;
1924 + break;
1925 + case FLASHCTL_MWx8:
1926 + default:
1927 + ar5312_flash_data.width = 1;
1928 + break;
1929 + }
1930 +
1931 + platform_device_register(&ar5312_physmap_flash);
1932 +
1933 +#ifdef CONFIG_LEDS_GPIO
1934 + ar5312_leds[0].gpio = config->sysLedGpio;
1935 + platform_device_register(&ar5312_gpio_leds);
1936 +#endif
1937 +
1938 + /* Fix up MAC addresses if necessary */
1939 + if (!memcmp(config->enet0_mac, "\xff\xff\xff\xff\xff\xff", 6))
1940 + memcpy(config->enet0_mac, config->enet1_mac, 6);
1941 +
1942 + /* If ENET0 and ENET1 have the same mac address,
1943 + * increment the one from ENET1 */
1944 + if (memcmp(config->enet0_mac, config->enet1_mac, 6) == 0) {
1945 + c = config->enet1_mac + 5;
1946 + while ((c >= config->enet1_mac) && !(++(*c)))
1947 + c--;
1948 + }
1949 +
1950 + switch(ar231x_devtype) {
1951 + case DEV_TYPE_AR5312:
1952 + ar5312_eth0_data.macaddr = config->enet0_mac;
1953 + ar231x_add_ethernet(0, KSEG1ADDR(AR531X_ENET0),
1954 + AR5312_IRQ_ENET0_INTRS, &ar5312_eth0_data);
1955 +
1956 + ar5312_eth1_data.macaddr = config->enet1_mac;
1957 + ar231x_add_ethernet(1, KSEG1ADDR(AR531X_ENET1),
1958 + AR5312_IRQ_ENET1_INTRS, &ar5312_eth1_data);
1959 +
1960 + if (!ar231x_board.radio)
1961 + return 0;
1962 +
1963 + if ((*((u32 *) radio) & AR531X_RADIO0_MASK) &&
1964 + (config->flags & BD_WLAN0))
1965 + ar231x_add_wmac(0, AR531X_WLAN0,
1966 + AR5312_IRQ_WLAN0_INTRS);
1967 +
1968 + break;
1969 + /*
1970 + * AR2312/3 ethernet uses the PHY of ENET0, but the MAC
1971 + * of ENET1. Atheros calls it 'twisted' for a reason :)
1972 + */
1973 + case DEV_TYPE_AR2312:
1974 + case DEV_TYPE_AR2313:
1975 + ar5312_eth1_data.phy_base = ar5312_eth0_data.phy_base;
1976 + ar5312_eth1_data.reset_phy = ar5312_eth0_data.reset_phy;
1977 + ar5312_eth1_data.macaddr = config->enet0_mac;
1978 + ar231x_add_ethernet(0, KSEG1ADDR(AR531X_ENET1),
1979 + AR5312_IRQ_ENET1_INTRS, &ar5312_eth1_data);
1980 +
1981 + if (!ar231x_board.radio)
1982 + return 0;
1983 + break;
1984 + default:
1985 + break;
1986 + }
1987 +
1988 + if ((*((u32 *) radio) & AR531X_RADIO1_MASK) &&
1989 + (config->flags & BD_WLAN1))
1990 + ar231x_add_wmac(1, AR531X_WLAN1,
1991 + AR5312_IRQ_WLAN1_INTRS);
1992 +
1993 + return 0;
1994 +}
1995 +
1996 +
1997 +static void ar5312_restart(char *command)
1998 +{
1999 + /* reset the system */
2000 + local_irq_disable();
2001 + while(1) {
2002 + ar231x_write_reg(AR531X_RESET, AR531X_RESET_SYSTEM);
2003 + }
2004 +}
2005 +
2006 +
2007 +/*
2008 + * This table is indexed by bits 5..4 of the CLOCKCTL1 register
2009 + * to determine the predevisor value.
2010 + */
2011 +static int __initdata CLOCKCTL1_PREDIVIDE_TABLE[4] = { 1, 2, 4, 5 };
2012 +
2013 +
2014 +static int __init
2015 +ar5312_cpu_frequency(void)
2016 +{
2017 + unsigned int result;
2018 + unsigned int predivide_mask, predivide_shift;
2019 + unsigned int multiplier_mask, multiplier_shift;
2020 + unsigned int clockCtl1, preDivideSelect, preDivisor, multiplier;
2021 + unsigned int doubler_mask;
2022 + u16 devid;
2023 +
2024 + /* Trust the bootrom's idea of cpu frequency. */
2025 + if ((result = ar231x_read_reg(AR5312_SCRATCH)))
2026 + return result;
2027 +
2028 + devid = ar231x_read_reg(AR531X_REV);
2029 + devid &= AR531X_REV_MAJ;
2030 + devid >>= AR531X_REV_MAJ_S;
2031 + if (devid == AR531X_REV_MAJ_AR2313) {
2032 + predivide_mask = AR2313_CLOCKCTL1_PREDIVIDE_MASK;
2033 + predivide_shift = AR2313_CLOCKCTL1_PREDIVIDE_SHIFT;
2034 + multiplier_mask = AR2313_CLOCKCTL1_MULTIPLIER_MASK;
2035 + multiplier_shift = AR2313_CLOCKCTL1_MULTIPLIER_SHIFT;
2036 + doubler_mask = AR2313_CLOCKCTL1_DOUBLER_MASK;
2037 + } else { /* AR5312 and AR2312 */
2038 + predivide_mask = AR5312_CLOCKCTL1_PREDIVIDE_MASK;
2039 + predivide_shift = AR5312_CLOCKCTL1_PREDIVIDE_SHIFT;
2040 + multiplier_mask = AR5312_CLOCKCTL1_MULTIPLIER_MASK;
2041 + multiplier_shift = AR5312_CLOCKCTL1_MULTIPLIER_SHIFT;
2042 + doubler_mask = AR5312_CLOCKCTL1_DOUBLER_MASK;
2043 + }
2044 +
2045 + /*
2046 + * Clocking is derived from a fixed 40MHz input clock.
2047 + *
2048 + * cpuFreq = InputClock * MULT (where MULT is PLL multiplier)
2049 + * sysFreq = cpuFreq / 4 (used for APB clock, serial,
2050 + * flash, Timer, Watchdog Timer)
2051 + *
2052 + * cntFreq = cpuFreq / 2 (use for CPU count/compare)
2053 + *
2054 + * So, for example, with a PLL multiplier of 5, we have
2055 + *
2056 + * cpuFreq = 200MHz
2057 + * sysFreq = 50MHz
2058 + * cntFreq = 100MHz
2059 + *
2060 + * We compute the CPU frequency, based on PLL settings.
2061 + */
2062 +
2063 + clockCtl1 = ar231x_read_reg(AR5312_CLOCKCTL1);
2064 + preDivideSelect = (clockCtl1 & predivide_mask) >> predivide_shift;
2065 + preDivisor = CLOCKCTL1_PREDIVIDE_TABLE[preDivideSelect];
2066 + multiplier = (clockCtl1 & multiplier_mask) >> multiplier_shift;
2067 +
2068 + if (clockCtl1 & doubler_mask) {
2069 + multiplier = multiplier << 1;
2070 + }
2071 + return (40000000 / preDivisor) * multiplier;
2072 +}
2073 +
2074 +static inline int
2075 +ar5312_sys_frequency(void)
2076 +{
2077 + return ar5312_cpu_frequency() / 4;
2078 +}
2079 +
2080 +void __init
2081 +ar5312_time_init(void)
2082 +{
2083 + if (!is_5312())
2084 + return;
2085 +
2086 + mips_hpt_frequency = ar5312_cpu_frequency() / 2;
2087 +}
2088 +
2089 +
2090 +void __init
2091 +ar5312_prom_init(void)
2092 +{
2093 + u32 memsize, memcfg, bank0AC, bank1AC;
2094 + u32 devid;
2095 +
2096 + if (!is_5312())
2097 + return;
2098 +
2099 + /* Detect memory size */
2100 + memcfg = ar231x_read_reg(AR531X_MEM_CFG1);
2101 + bank0AC = (memcfg & MEM_CFG1_AC0) >> MEM_CFG1_AC0_S;
2102 + bank1AC = (memcfg & MEM_CFG1_AC1) >> MEM_CFG1_AC1_S;
2103 + memsize = (bank0AC ? (1 << (bank0AC+1)) : 0)
2104 + + (bank1AC ? (1 << (bank1AC+1)) : 0);
2105 + memsize <<= 20;
2106 + add_memory_region(0, memsize, BOOT_MEM_RAM);
2107 +
2108 + devid = ar231x_read_reg(AR531X_REV);
2109 + devid >>= AR531X_REV_WMAC_MIN_S;
2110 + devid &= AR531X_REV_CHIP;
2111 + ar231x_board.devid = (u16) devid;
2112 + ar231x_gpiodev = &ar5312_gpiodev;
2113 +}
2114 +
2115 +void __init
2116 +ar5312_plat_setup(void)
2117 +{
2118 + if (!is_5312())
2119 + return;
2120 +
2121 + /* Clear any lingering AHB errors */
2122 + ar231x_read_reg(AR531X_PROCADDR);
2123 + ar231x_read_reg(AR531X_DMAADDR);
2124 + ar231x_write_reg(AR531X_WD_CTRL, AR531X_WD_CTRL_IGNORE_EXPIRATION);
2125 +
2126 + _machine_restart = ar5312_restart;
2127 + ar231x_serial_setup(KSEG1ADDR(AR531X_UART0), ar5312_sys_frequency());
2128 +}
2129 +
2130 --- /dev/null
2131 +++ b/arch/mips/ar231x/ar2315.c
2132 @@ -0,0 +1,658 @@
2133 +/*
2134 + * This file is subject to the terms and conditions of the GNU General Public
2135 + * License. See the file "COPYING" in the main directory of this archive
2136 + * for more details.
2137 + *
2138 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
2139 + * Copyright (C) 2006 FON Technology, SL.
2140 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
2141 + * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
2142 + */
2143 +
2144 +/*
2145 + * Platform devices for Atheros SoCs
2146 + */
2147 +
2148 +#include <generated/autoconf.h>
2149 +#include <linux/init.h>
2150 +#include <linux/module.h>
2151 +#include <linux/types.h>
2152 +#include <linux/string.h>
2153 +#include <linux/platform_device.h>
2154 +#include <linux/kernel.h>
2155 +#include <linux/reboot.h>
2156 +#include <linux/delay.h>
2157 +#include <linux/leds.h>
2158 +#include <asm/bootinfo.h>
2159 +#include <asm/reboot.h>
2160 +#include <asm/time.h>
2161 +#include <asm/irq.h>
2162 +#include <asm/io.h>
2163 +#include <asm/gpio.h>
2164 +
2165 +#include <ar231x_platform.h>
2166 +#include <ar2315_regs.h>
2167 +#include <ar231x.h>
2168 +#include "devices.h"
2169 +#include "ar2315.h"
2170 +
2171 +static u32 gpiointmask = 0, gpiointval = 0;
2172 +
2173 +static inline void ar2315_gpio_irq(void)
2174 +{
2175 + u32 pend;
2176 + int bit = -1;
2177 +
2178 + /* only do one gpio interrupt at a time */
2179 + pend = (ar231x_read_reg(AR2315_GPIO_DI) ^ gpiointval) & gpiointmask;
2180 +
2181 + if (pend) {
2182 + bit = fls(pend) - 1;
2183 + pend &= ~(1 << bit);
2184 + gpiointval ^= (1 << bit);
2185 + }
2186 +
2187 + if (!pend)
2188 + ar231x_write_reg(AR2315_ISR, AR2315_ISR_GPIO);
2189 +
2190 + /* Enable interrupt with edge detection */
2191 + if ((ar231x_read_reg(AR2315_GPIO_CR) & AR2315_GPIO_CR_M(bit)) != AR2315_GPIO_CR_I(bit))
2192 + return;
2193 +
2194 + if (bit >= 0)
2195 + do_IRQ(AR531X_GPIO_IRQ_BASE + bit);
2196 +}
2197 +
2198 +
2199 +/*
2200 + * Called when an interrupt is received, this function
2201 + * determines exactly which interrupt it was, and it
2202 + * invokes the appropriate handler.
2203 + *
2204 + * Implicitly, we also define interrupt priority by
2205 + * choosing which to dispatch first.
2206 + */
2207 +static asmlinkage void
2208 +ar2315_irq_dispatch(void)
2209 +{
2210 + int pending = read_c0_status() & read_c0_cause();
2211 +
2212 + if (pending & CAUSEF_IP3)
2213 + do_IRQ(AR2315_IRQ_WLAN0_INTRS);
2214 + else if (pending & CAUSEF_IP4)
2215 + do_IRQ(AR2315_IRQ_ENET0_INTRS);
2216 + else if (pending & CAUSEF_IP2) {
2217 + unsigned int misc_intr = ar231x_read_reg(AR2315_ISR) & ar231x_read_reg(AR2315_IMR);
2218 +
2219 + if (misc_intr & AR2315_ISR_SPI)
2220 + do_IRQ(AR531X_MISC_IRQ_SPI);
2221 + else if (misc_intr & AR2315_ISR_TIMER)
2222 + do_IRQ(AR531X_MISC_IRQ_TIMER);
2223 + else if (misc_intr & AR2315_ISR_AHB)
2224 + do_IRQ(AR531X_MISC_IRQ_AHB_PROC);
2225 + else if (misc_intr & AR2315_ISR_GPIO)
2226 + ar2315_gpio_irq();
2227 + else if (misc_intr & AR2315_ISR_UART0)
2228 + do_IRQ(AR531X_MISC_IRQ_UART0);
2229 + else if (misc_intr & AR2315_ISR_WD)
2230 + do_IRQ(AR531X_MISC_IRQ_WATCHDOG);
2231 + else
2232 + do_IRQ(AR531X_MISC_IRQ_NONE);
2233 + } else if (pending & CAUSEF_IP7)
2234 + do_IRQ(AR531X_IRQ_CPU_CLOCK);
2235 +}
2236 +
2237 +static void ar2315_set_gpiointmask(int gpio, int level)
2238 +{
2239 + u32 reg;
2240 +
2241 + reg = ar231x_read_reg(AR2315_GPIO_INT);
2242 + reg &= ~(AR2315_GPIO_INT_M | AR2315_GPIO_INT_LVL_M);
2243 + reg |= gpio | AR2315_GPIO_INT_LVL(level);
2244 + ar231x_write_reg(AR2315_GPIO_INT, reg);
2245 +}
2246 +
2247 +static void ar2315_gpio_intr_enable(unsigned int irq)
2248 +{
2249 + unsigned int gpio = irq - AR531X_GPIO_IRQ_BASE;
2250 +
2251 + /* Enable interrupt with edge detection */
2252 + if ((ar231x_read_reg(AR2315_GPIO_CR) & AR2315_GPIO_CR_M(gpio)) != AR2315_GPIO_CR_I(gpio))
2253 + return;
2254 +
2255 + gpiointmask |= (1 << gpio);
2256 + ar2315_set_gpiointmask(gpio, 3);
2257 +}
2258 +
2259 +static unsigned int ar2315_gpio_intr_startup(unsigned int irq)
2260 +{
2261 + unsigned int gpio = irq - AR531X_GPIO_IRQ_BASE;
2262 +
2263 + /* reconfigure GPIO line as input */
2264 + ar231x_mask_reg(AR2315_GPIO_CR, AR2315_GPIO_CR_M(gpio), AR2315_GPIO_CR_I(gpio));
2265 + ar2315_gpio_intr_enable(irq);
2266 + return 0;
2267 +}
2268 +
2269 +static void ar2315_gpio_intr_disable(unsigned int irq)
2270 +{
2271 + unsigned int gpio = irq - AR531X_GPIO_IRQ_BASE;
2272 +
2273 + /* Disable interrupt */
2274 + gpiointmask &= ~(1 << gpio);
2275 + ar2315_set_gpiointmask(gpio, 0);
2276 +}
2277 +
2278 +static void
2279 +ar2315_gpio_intr_end(unsigned int irq)
2280 +{
2281 + if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
2282 + ar2315_gpio_intr_enable(irq);
2283 +}
2284 +
2285 +static struct irq_chip ar2315_gpio_intr_controller = {
2286 + .name = "AR2315-GPIO",
2287 + .startup = ar2315_gpio_intr_startup,
2288 + .ack = ar2315_gpio_intr_disable,
2289 + .mask_ack = ar2315_gpio_intr_disable,
2290 + .mask = ar2315_gpio_intr_disable,
2291 + .unmask = ar2315_gpio_intr_enable,
2292 + .end = ar2315_gpio_intr_end,
2293 +};
2294 +
2295 +static void
2296 +ar2315_misc_intr_enable(unsigned int irq)
2297 +{
2298 + unsigned int imr;
2299 +
2300 + imr = ar231x_read_reg(AR2315_IMR);
2301 + switch(irq) {
2302 + case AR531X_MISC_IRQ_SPI:
2303 + imr |= AR2315_ISR_SPI;
2304 + break;
2305 + case AR531X_MISC_IRQ_TIMER:
2306 + imr |= AR2315_ISR_TIMER;
2307 + break;
2308 + case AR531X_MISC_IRQ_AHB_PROC:
2309 + imr |= AR2315_ISR_AHB;
2310 + break;
2311 + case AR531X_MISC_IRQ_GPIO:
2312 + imr |= AR2315_ISR_GPIO;
2313 + break;
2314 + case AR531X_MISC_IRQ_UART0:
2315 + imr |= AR2315_ISR_UART0;
2316 + break;
2317 + case AR531X_MISC_IRQ_WATCHDOG:
2318 + imr |= AR2315_ISR_WD;
2319 + break;
2320 + default:
2321 + break;
2322 + }
2323 + ar231x_write_reg(AR2315_IMR, imr);
2324 +}
2325 +
2326 +static void
2327 +ar2315_misc_intr_disable(unsigned int irq)
2328 +{
2329 + unsigned int imr;
2330 +
2331 + imr = ar231x_read_reg(AR2315_IMR);
2332 + switch(irq) {
2333 + case AR531X_MISC_IRQ_SPI:
2334 + imr &= ~AR2315_ISR_SPI;
2335 + break;
2336 + case AR531X_MISC_IRQ_TIMER:
2337 + imr &= ~AR2315_ISR_TIMER;
2338 + break;
2339 + case AR531X_MISC_IRQ_AHB_PROC:
2340 + imr &= ~AR2315_ISR_AHB;
2341 + break;
2342 + case AR531X_MISC_IRQ_GPIO:
2343 + imr &= ~AR2315_ISR_GPIO;
2344 + break;
2345 + case AR531X_MISC_IRQ_UART0:
2346 + imr &= ~AR2315_ISR_UART0;
2347 + break;
2348 + case AR531X_MISC_IRQ_WATCHDOG:
2349 + imr &= ~AR2315_ISR_WD;
2350 + break;
2351 + default:
2352 + break;
2353 + }
2354 + ar231x_write_reg(AR2315_IMR, imr);
2355 +}
2356 +
2357 +static void
2358 +ar2315_misc_intr_end(unsigned int irq)
2359 +{
2360 + if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
2361 + ar2315_misc_intr_enable(irq);
2362 +}
2363 +
2364 +
2365 +static struct irq_chip ar2315_misc_intr_controller = {
2366 + .name = "AR2315-MISC",
2367 + .ack = ar2315_misc_intr_disable,
2368 + .mask_ack = ar2315_misc_intr_disable,
2369 + .mask = ar2315_misc_intr_disable,
2370 + .unmask = ar2315_misc_intr_enable,
2371 + .end = ar2315_misc_intr_end,
2372 +};
2373 +
2374 +static irqreturn_t ar2315_ahb_proc_handler(int cpl, void *dev_id)
2375 +{
2376 + ar231x_write_reg(AR2315_AHB_ERR0, AHB_ERROR_DET);
2377 + ar231x_read_reg(AR2315_AHB_ERR1);
2378 +
2379 + printk(KERN_ERR "AHB fatal error\n");
2380 + machine_restart("AHB error"); /* Catastrophic failure */
2381 +
2382 + return IRQ_HANDLED;
2383 +}
2384 +
2385 +static struct irqaction ar2315_ahb_proc_interrupt = {
2386 + .handler = ar2315_ahb_proc_handler,
2387 + .flags = IRQF_DISABLED,
2388 + .name = "ar2315_ahb_proc_interrupt",
2389 +};
2390 +
2391 +static struct irqaction cascade = {
2392 + .handler = no_action,
2393 + .flags = IRQF_DISABLED,
2394 + .name = "cascade",
2395 +};
2396 +
2397 +void
2398 +ar2315_irq_init(void)
2399 +{
2400 + int i;
2401 +
2402 + if (!is_2315())
2403 + return;
2404 +
2405 + ar231x_irq_dispatch = ar2315_irq_dispatch;
2406 + gpiointval = ar231x_read_reg(AR2315_GPIO_DI);
2407 + for (i = 0; i < AR531X_MISC_IRQ_COUNT; i++) {
2408 + int irq = AR531X_MISC_IRQ_BASE + i;
2409 + set_irq_chip_and_handler(irq, &ar2315_misc_intr_controller,
2410 + handle_level_irq);
2411 + }
2412 + for (i = 0; i < AR531X_GPIO_IRQ_COUNT; i++) {
2413 + int irq = AR531X_GPIO_IRQ_BASE + i;
2414 + set_irq_chip_and_handler(irq, &ar2315_gpio_intr_controller,
2415 + handle_level_irq);
2416 + }
2417 + setup_irq(AR531X_MISC_IRQ_GPIO, &cascade);
2418 + setup_irq(AR531X_MISC_IRQ_AHB_PROC, &ar2315_ahb_proc_interrupt);
2419 + setup_irq(AR2315_IRQ_MISC_INTRS, &cascade);
2420 +}
2421 +
2422 +const struct ar231x_gpiodev ar2315_gpiodev;
2423 +
2424 +static u32
2425 +ar2315_gpio_get_output(void)
2426 +{
2427 + u32 reg;
2428 + reg = ar231x_read_reg(AR2315_GPIO_CR);
2429 + reg &= ar2315_gpiodev.valid_mask;
2430 + return reg;
2431 +}
2432 +
2433 +static u32
2434 +ar2315_gpio_set_output(u32 mask, u32 val)
2435 +{
2436 + u32 reg;
2437 +
2438 + reg = ar231x_read_reg(AR2315_GPIO_CR);
2439 + reg &= ~mask;
2440 + reg |= val;
2441 + ar231x_write_reg(AR2315_GPIO_CR, reg);
2442 + return reg;
2443 +}
2444 +
2445 +static u32
2446 +ar2315_gpio_get(void)
2447 +{
2448 + u32 reg;
2449 + reg = ar231x_read_reg(AR2315_GPIO_DI);
2450 + reg &= ar2315_gpiodev.valid_mask;
2451 + return reg;
2452 +}
2453 +
2454 +static u32
2455 +ar2315_gpio_set(u32 mask, u32 value)
2456 +{
2457 + u32 reg;
2458 + reg = ar231x_read_reg(AR2315_GPIO_DO);
2459 + reg &= ~mask;
2460 + reg |= value;
2461 + ar231x_write_reg(AR2315_GPIO_DO, reg);
2462 + return reg;
2463 +}
2464 +
2465 +const struct ar231x_gpiodev ar2315_gpiodev = {
2466 + .valid_mask = (1 << 22) - 1,
2467 + .get_output = ar2315_gpio_get_output,
2468 + .set_output = ar2315_gpio_set_output,
2469 + .get = ar2315_gpio_get,
2470 + .set = ar2315_gpio_set,
2471 +};
2472 +
2473 +static struct ar231x_eth ar2315_eth_data = {
2474 + .reset_base = AR2315_RESET,
2475 + .reset_mac = AR2315_RESET_ENET0,
2476 + .reset_phy = AR2315_RESET_EPHY0,
2477 + .phy_base = KSEG1ADDR(AR2315_ENET0),
2478 + .config = &ar231x_board,
2479 +};
2480 +
2481 +static struct resource ar2315_spiflash_res[] = {
2482 + {
2483 + .name = "flash_base",
2484 + .flags = IORESOURCE_MEM,
2485 + .start = KSEG1ADDR(AR2315_SPI_READ),
2486 + .end = KSEG1ADDR(AR2315_SPI_READ) + 0x1000000 - 1,
2487 + },
2488 + {
2489 + .name = "flash_regs",
2490 + .flags = IORESOURCE_MEM,
2491 + .start = 0x11300000,
2492 + .end = 0x11300012,
2493 + },
2494 +};
2495 +
2496 +static struct platform_device ar2315_spiflash = {
2497 + .id = 0,
2498 + .name = "spiflash",
2499 + .resource = ar2315_spiflash_res,
2500 + .num_resources = ARRAY_SIZE(ar2315_spiflash_res)
2501 +};
2502 +
2503 +static struct platform_device ar2315_wdt = {
2504 + .id = 0,
2505 + .name = "ar2315_wdt",
2506 +};
2507 +
2508 +#define SPI_FLASH_CTL 0x00
2509 +#define SPI_FLASH_OPCODE 0x04
2510 +#define SPI_FLASH_DATA 0x08
2511 +
2512 +static inline u32
2513 +spiflash_read_reg(int reg)
2514 +{
2515 + return ar231x_read_reg(AR2315_SPI + reg);
2516 +}
2517 +
2518 +static inline void
2519 +spiflash_write_reg(int reg, u32 data)
2520 +{
2521 + ar231x_write_reg(AR2315_SPI + reg, data);
2522 +}
2523 +
2524 +static u32
2525 +spiflash_wait_status(void)
2526 +{
2527 + u32 reg;
2528 +
2529 + do {
2530 + reg = spiflash_read_reg(SPI_FLASH_CTL);
2531 + } while (reg & SPI_CTL_BUSY);
2532 +
2533 + return reg;
2534 +}
2535 +
2536 +static u8
2537 +spiflash_probe(void)
2538 +{
2539 + u32 reg;
2540 +
2541 + reg = spiflash_wait_status();
2542 + reg &= ~SPI_CTL_TX_RX_CNT_MASK;
2543 + reg |= (1 << 4) | 4 | SPI_CTL_START;
2544 +
2545 + spiflash_write_reg(SPI_FLASH_OPCODE, 0xab);
2546 + spiflash_write_reg(SPI_FLASH_CTL, reg);
2547 +
2548 + reg = spiflash_wait_status();
2549 + reg = spiflash_read_reg(SPI_FLASH_DATA);
2550 + reg &= 0xff;
2551 +
2552 + return (u8) reg;
2553 +}
2554 +
2555 +
2556 +#define STM_8MBIT_SIGNATURE 0x13
2557 +#define STM_16MBIT_SIGNATURE 0x14
2558 +#define STM_32MBIT_SIGNATURE 0x15
2559 +#define STM_64MBIT_SIGNATURE 0x16
2560 +#define STM_128MBIT_SIGNATURE 0x17
2561 +
2562 +static u8 __init *
2563 +ar2315_flash_limit(void)
2564 +{
2565 + u32 flash_size = 0;
2566 +
2567 + /* probe the flash chip size */
2568 + switch(spiflash_probe()) {
2569 + case STM_8MBIT_SIGNATURE:
2570 + flash_size = 0x00100000;
2571 + break;
2572 + case STM_16MBIT_SIGNATURE:
2573 + flash_size = 0x00200000;
2574 + break;
2575 + case STM_32MBIT_SIGNATURE:
2576 + flash_size = 0x00400000;
2577 + break;
2578 + case STM_64MBIT_SIGNATURE:
2579 + flash_size = 0x00800000;
2580 + break;
2581 + case STM_128MBIT_SIGNATURE:
2582 + flash_size = 0x01000000;
2583 + break;
2584 + }
2585 +
2586 + ar2315_spiflash_res[0].end = ar2315_spiflash_res[0].start +
2587 + flash_size - 1;
2588 + return (u8 *) ar2315_spiflash_res[0].end + 1;
2589 +}
2590 +
2591 +#ifdef CONFIG_LEDS_GPIO
2592 +static struct gpio_led ar2315_leds[6];
2593 +static struct gpio_led_platform_data ar2315_led_data = {
2594 + .leds = (void *) ar2315_leds,
2595 +};
2596 +
2597 +static struct platform_device ar2315_gpio_leds = {
2598 + .name = "leds-gpio",
2599 + .id = -1,
2600 + .dev = {
2601 + .platform_data = (void *) &ar2315_led_data,
2602 + }
2603 +};
2604 +
2605 +static void __init
2606 +ar2315_init_gpio(void)
2607 +{
2608 + static char led_names[6][6];
2609 + int i, led = 0;
2610 +
2611 + ar2315_led_data.num_leds = 0;
2612 + for(i = 1; i < 8; i++)
2613 + {
2614 + if((i == AR2315_RESET_GPIO) ||
2615 + (i == ar231x_board.config->resetConfigGpio))
2616 + continue;
2617 +
2618 + if(i == ar231x_board.config->sysLedGpio)
2619 + strcpy(led_names[led], "wlan");
2620 + else
2621 + sprintf(led_names[led], "gpio%d", i);
2622 +
2623 + ar2315_leds[led].name = led_names[led];
2624 + ar2315_leds[led].gpio = i;
2625 + ar2315_leds[led].active_low = 0;
2626 + led++;
2627 + }
2628 + ar2315_led_data.num_leds = led;
2629 + platform_device_register(&ar2315_gpio_leds);
2630 +}
2631 +#else
2632 +static inline void ar2315_init_gpio(void)
2633 +{
2634 +}
2635 +#endif
2636 +
2637 +int __init
2638 +ar2315_init_devices(void)
2639 +{
2640 + if (!is_2315())
2641 + return 0;
2642 +
2643 + /* Find board configuration */
2644 + ar231x_find_config(ar2315_flash_limit());
2645 + ar2315_eth_data.macaddr = ar231x_board.config->enet0_mac;
2646 +
2647 + ar2315_init_gpio();
2648 + platform_device_register(&ar2315_wdt);
2649 + platform_device_register(&ar2315_spiflash);
2650 + ar231x_add_ethernet(0, KSEG1ADDR(AR2315_ENET0), AR2315_IRQ_ENET0_INTRS,
2651 + &ar2315_eth_data);
2652 + ar231x_add_wmac(0, AR2315_WLAN0, AR2315_IRQ_WLAN0_INTRS);
2653 +
2654 + return 0;
2655 +}
2656 +
2657 +static void
2658 +ar2315_restart(char *command)
2659 +{
2660 + void (*mips_reset_vec)(void) = (void *) 0xbfc00000;
2661 +
2662 + local_irq_disable();
2663 +
2664 + /* try reset the system via reset control */
2665 + ar231x_write_reg(AR2315_COLD_RESET,AR2317_RESET_SYSTEM);
2666 +
2667 + /* Cold reset does not work on the AR2315/6, use the GPIO reset bits a workaround.
2668 + * give it some time to attempt a gpio based hardware reset
2669 + * (atheros reference design workaround) */
2670 + gpio_direction_output(AR2315_RESET_GPIO, 0);
2671 + mdelay(100);
2672 +
2673 + /* Some boards (e.g. Senao EOC-2610) don't implement the reset logic
2674 + * workaround. Attempt to jump to the mips reset location -
2675 + * the boot loader itself might be able to recover the system */
2676 + mips_reset_vec();
2677 +}
2678 +
2679 +
2680 +/*
2681 + * This table is indexed by bits 5..4 of the CLOCKCTL1 register
2682 + * to determine the predevisor value.
2683 + */
2684 +static int __initdata CLOCKCTL1_PREDIVIDE_TABLE[4] = { 1, 2, 4, 5 };
2685 +static int __initdata PLLC_DIVIDE_TABLE[5] = { 2, 3, 4, 6, 3 };
2686 +
2687 +static unsigned int __init
2688 +ar2315_sys_clk(unsigned int clockCtl)
2689 +{
2690 + unsigned int pllcCtrl,cpuDiv;
2691 + unsigned int pllcOut,refdiv,fdiv,divby2;
2692 + unsigned int clkDiv;
2693 +
2694 + pllcCtrl = ar231x_read_reg(AR2315_PLLC_CTL);
2695 + refdiv = (pllcCtrl & PLLC_REF_DIV_M) >> PLLC_REF_DIV_S;
2696 + refdiv = CLOCKCTL1_PREDIVIDE_TABLE[refdiv];
2697 + fdiv = (pllcCtrl & PLLC_FDBACK_DIV_M) >> PLLC_FDBACK_DIV_S;
2698 + divby2 = (pllcCtrl & PLLC_ADD_FDBACK_DIV_M) >> PLLC_ADD_FDBACK_DIV_S;
2699 + divby2 += 1;
2700 + pllcOut = (40000000/refdiv)*(2*divby2)*fdiv;
2701 +
2702 +
2703 + /* clkm input selected */
2704 + switch(clockCtl & CPUCLK_CLK_SEL_M) {
2705 + case 0:
2706 + case 1:
2707 + clkDiv = PLLC_DIVIDE_TABLE[(pllcCtrl & PLLC_CLKM_DIV_M) >> PLLC_CLKM_DIV_S];
2708 + break;
2709 + case 2:
2710 + clkDiv = PLLC_DIVIDE_TABLE[(pllcCtrl & PLLC_CLKC_DIV_M) >> PLLC_CLKC_DIV_S];
2711 + break;
2712 + default:
2713 + pllcOut = 40000000;
2714 + clkDiv = 1;
2715 + break;
2716 + }
2717 + cpuDiv = (clockCtl & CPUCLK_CLK_DIV_M) >> CPUCLK_CLK_DIV_S;
2718 + cpuDiv = cpuDiv * 2 ?: 1;
2719 + return (pllcOut/(clkDiv * cpuDiv));
2720 +}
2721 +
2722 +static inline unsigned int
2723 +ar2315_cpu_frequency(void)
2724 +{
2725 + return ar2315_sys_clk(ar231x_read_reg(AR2315_CPUCLK));
2726 +}
2727 +
2728 +static inline unsigned int
2729 +ar2315_apb_frequency(void)
2730 +{
2731 + return ar2315_sys_clk(ar231x_read_reg(AR2315_AMBACLK));
2732 +}
2733 +
2734 +void __init
2735 +ar2315_time_init(void)
2736 +{
2737 + if (!is_2315())
2738 + return;
2739 +
2740 + mips_hpt_frequency = ar2315_cpu_frequency() / 2;
2741 +}
2742 +
2743 +void __init
2744 +ar2315_prom_init(void)
2745 +{
2746 + u32 memsize, memcfg, devid;
2747 +
2748 + if (!is_2315())
2749 + return;
2750 +
2751 + memcfg = ar231x_read_reg(AR2315_MEM_CFG);
2752 + memsize = 1 + ((memcfg & SDRAM_DATA_WIDTH_M) >> SDRAM_DATA_WIDTH_S);
2753 + memsize <<= 1 + ((memcfg & SDRAM_COL_WIDTH_M) >> SDRAM_COL_WIDTH_S);
2754 + memsize <<= 1 + ((memcfg & SDRAM_ROW_WIDTH_M) >> SDRAM_ROW_WIDTH_S);
2755 + memsize <<= 3;
2756 + add_memory_region(0, memsize, BOOT_MEM_RAM);
2757 +
2758 + /* Detect the hardware based on the device ID */
2759 + devid = ar231x_read_reg(AR2315_SREV) & AR2315_REV_CHIP;
2760 + switch(devid) {
2761 + case 0x90:
2762 + case 0x91:
2763 + ar231x_devtype = DEV_TYPE_AR2317;
2764 + break;
2765 + default:
2766 + ar231x_devtype = DEV_TYPE_AR2315;
2767 + break;
2768 + }
2769 + ar231x_gpiodev = &ar2315_gpiodev;
2770 + ar231x_board.devid = devid;
2771 +}
2772 +
2773 +void __init
2774 +ar2315_plat_setup(void)
2775 +{
2776 + u32 config;
2777 +
2778 + if (!is_2315())
2779 + return;
2780 +
2781 + /* Clear any lingering AHB errors */
2782 + config = read_c0_config();
2783 + write_c0_config(config & ~0x3);
2784 + ar231x_write_reg(AR2315_AHB_ERR0,AHB_ERROR_DET);
2785 + ar231x_read_reg(AR2315_AHB_ERR1);
2786 + ar231x_write_reg(AR2315_WDC, AR2315_WDC_IGNORE_EXPIRATION);
2787 +
2788 + _machine_restart = ar2315_restart;
2789 + ar231x_serial_setup(KSEG1ADDR(AR2315_UART0), ar2315_apb_frequency());
2790 +}
2791 --- /dev/null
2792 +++ b/arch/mips/ar231x/ar2315.h
2793 @@ -0,0 +1,37 @@
2794 +#ifndef __AR2315_H
2795 +#define __AR2315_H
2796 +
2797 +#ifdef CONFIG_ATHEROS_AR2315
2798 +
2799 +extern void ar2315_irq_init(void);
2800 +extern int ar2315_init_devices(void);
2801 +extern void ar2315_prom_init(void);
2802 +extern void ar2315_plat_setup(void);
2803 +extern void ar2315_time_init(void);
2804 +
2805 +#else
2806 +
2807 +static inline void ar2315_irq_init(void)
2808 +{
2809 +}
2810 +
2811 +static inline int ar2315_init_devices(void)
2812 +{
2813 + return 0;
2814 +}
2815 +
2816 +static inline void ar2315_prom_init(void)
2817 +{
2818 +}
2819 +
2820 +static inline void ar2315_plat_setup(void)
2821 +{
2822 +}
2823 +
2824 +static inline void ar2315_time_init(void)
2825 +{
2826 +}
2827 +
2828 +#endif
2829 +
2830 +#endif
2831 --- /dev/null
2832 +++ b/arch/mips/ar231x/ar5312.h
2833 @@ -0,0 +1,38 @@
2834 +#ifndef __AR5312_H
2835 +#define __AR5312_H
2836 +
2837 +#ifdef CONFIG_ATHEROS_AR5312
2838 +
2839 +extern void ar5312_irq_init(void);
2840 +extern int ar5312_init_devices(void);
2841 +extern void ar5312_prom_init(void);
2842 +extern void ar5312_plat_setup(void);
2843 +extern void ar5312_time_init(void);
2844 +extern void ar5312_time_init(void);
2845 +
2846 +#else
2847 +
2848 +static inline void ar5312_irq_init(void)
2849 +{
2850 +}
2851 +
2852 +static inline int ar5312_init_devices(void)
2853 +{
2854 + return 0;
2855 +}
2856 +
2857 +static inline void ar5312_prom_init(void)
2858 +{
2859 +}
2860 +
2861 +static inline void ar5312_plat_setup(void)
2862 +{
2863 +}
2864 +
2865 +static inline void ar5312_time_init(void)
2866 +{
2867 +}
2868 +
2869 +#endif
2870 +
2871 +#endif
2872 --- /dev/null
2873 +++ b/arch/mips/include/asm/mach-ar231x/ar231x.h
2874 @@ -0,0 +1,54 @@
2875 +#ifndef __AR531X_H
2876 +#define __AR531X_H
2877 +
2878 +#define AR531X_MISC_IRQ_BASE 0x20
2879 +#define AR531X_GPIO_IRQ_BASE 0x30
2880 +
2881 +/* Software's idea of interrupts handled by "CPU Interrupt Controller" */
2882 +#define AR531X_IRQ_NONE MIPS_CPU_IRQ_BASE+0
2883 +#define AR531X_IRQ_CPU_CLOCK MIPS_CPU_IRQ_BASE+7 /* C0_CAUSE: 0x8000 */
2884 +
2885 +/* Miscellaneous interrupts, which share IP6 */
2886 +#define AR531X_MISC_IRQ_NONE AR531X_MISC_IRQ_BASE+0
2887 +#define AR531X_MISC_IRQ_TIMER AR531X_MISC_IRQ_BASE+1
2888 +#define AR531X_MISC_IRQ_AHB_PROC AR531X_MISC_IRQ_BASE+2
2889 +#define AR531X_MISC_IRQ_AHB_DMA AR531X_MISC_IRQ_BASE+3
2890 +#define AR531X_MISC_IRQ_GPIO AR531X_MISC_IRQ_BASE+4
2891 +#define AR531X_MISC_IRQ_UART0 AR531X_MISC_IRQ_BASE+5
2892 +#define AR531X_MISC_IRQ_UART0_DMA AR531X_MISC_IRQ_BASE+6
2893 +#define AR531X_MISC_IRQ_WATCHDOG AR531X_MISC_IRQ_BASE+7
2894 +#define AR531X_MISC_IRQ_LOCAL AR531X_MISC_IRQ_BASE+8
2895 +#define AR531X_MISC_IRQ_SPI AR531X_MISC_IRQ_BASE+9
2896 +#define AR531X_MISC_IRQ_COUNT 10
2897 +
2898 +/* GPIO Interrupts [0..7], share AR531X_MISC_IRQ_GPIO */
2899 +#define AR531X_GPIO_IRQ_NONE AR531X_GPIO_IRQ_BASE+0
2900 +#define AR531X_GPIO_IRQ(n) AR531X_GPIO_IRQ_BASE+n
2901 +#define AR531X_GPIO_IRQ_COUNT 22
2902 +
2903 +static inline u32
2904 +ar231x_read_reg(u32 reg)
2905 +{
2906 + return __raw_readl((u32 *) KSEG1ADDR(reg));
2907 +}
2908 +
2909 +static inline void
2910 +ar231x_write_reg(u32 reg, u32 val)
2911 +{
2912 + __raw_writel(val, (u32 *) KSEG1ADDR(reg));
2913 +}
2914 +
2915 +static inline u32
2916 +ar231x_mask_reg(u32 reg, u32 mask, u32 val)
2917 +{
2918 + u32 ret;
2919 +
2920 + ret = ar231x_read_reg(reg);
2921 + ret &= ~mask;
2922 + ret |= val;
2923 + ar231x_write_reg(reg, ret);
2924 +
2925 + return ret;
2926 +}
2927 +
2928 +#endif
2929 --- /dev/null
2930 +++ b/arch/mips/ar231x/devices.h
2931 @@ -0,0 +1,37 @@
2932 +#ifndef __AR231X_DEVICES_H
2933 +#define __AR231X_DEVICES_H
2934 +
2935 +enum {
2936 + /* handled by ar5312.c */
2937 + DEV_TYPE_AR2312,
2938 + DEV_TYPE_AR2313,
2939 + DEV_TYPE_AR5312,
2940 +
2941 + /* handled by ar2315.c */
2942 + DEV_TYPE_AR2315,
2943 + DEV_TYPE_AR2316,
2944 + DEV_TYPE_AR2317,
2945 +
2946 + DEV_TYPE_UNKNOWN
2947 +};
2948 +
2949 +extern int ar231x_devtype;
2950 +extern struct ar231x_board_config ar231x_board;
2951 +extern asmlinkage void (*ar231x_irq_dispatch)(void);
2952 +
2953 +extern int ar231x_find_config(u8 *flash_limit);
2954 +extern void ar231x_serial_setup(u32 mapbase, unsigned int uartclk);
2955 +extern int ar231x_add_wmac(int nr, u32 base, int irq);
2956 +extern int ar231x_add_ethernet(int nr, u32 base, int irq, void *pdata);
2957 +
2958 +static inline bool is_2315(void)
2959 +{
2960 + return (current_cpu_data.cputype == CPU_4KEC);
2961 +}
2962 +
2963 +static inline bool is_5312(void)
2964 +{
2965 + return !is_2315();
2966 +}
2967 +
2968 +#endif
2969 --- /dev/null
2970 +++ b/arch/mips/ar231x/devices.c
2971 @@ -0,0 +1,175 @@
2972 +#include <linux/kernel.h>
2973 +#include <linux/init.h>
2974 +#include <linux/serial.h>
2975 +#include <linux/serial_core.h>
2976 +#include <linux/serial_8250.h>
2977 +#include <linux/platform_device.h>
2978 +#include <ar231x_platform.h>
2979 +#include <ar231x.h>
2980 +#include "devices.h"
2981 +#include "ar5312.h"
2982 +#include "ar2315.h"
2983 +
2984 +struct ar231x_board_config ar231x_board;
2985 +int ar231x_devtype = DEV_TYPE_UNKNOWN;
2986 +const struct ar231x_gpiodev *ar231x_gpiodev;
2987 +EXPORT_SYMBOL(ar231x_gpiodev);
2988 +
2989 +static struct resource ar231x_eth0_res[] = {
2990 + {
2991 + .name = "eth0_membase",
2992 + .flags = IORESOURCE_MEM,
2993 + },
2994 + {
2995 + .name = "eth0_irq",
2996 + .flags = IORESOURCE_IRQ,
2997 + }
2998 +};
2999 +
3000 +static struct resource ar231x_eth1_res[] = {
3001 + {
3002 + .name = "eth1_membase",
3003 + .flags = IORESOURCE_MEM,
3004 + },
3005 + {
3006 + .name = "eth1_irq",
3007 + .flags = IORESOURCE_IRQ,
3008 + }
3009 +};
3010 +
3011 +static struct platform_device ar231x_eth[] = {
3012 + {
3013 + .id = 0,
3014 + .name = "ar231x-eth",
3015 + .resource = ar231x_eth0_res,
3016 + .num_resources = ARRAY_SIZE(ar231x_eth0_res)
3017 + },
3018 + {
3019 + .id = 1,
3020 + .name = "ar231x-eth",
3021 + .resource = ar231x_eth1_res,
3022 + .num_resources = ARRAY_SIZE(ar231x_eth1_res)
3023 + }
3024 +};
3025 +
3026 +static struct resource ar231x_wmac0_res[] = {
3027 + {
3028 + .name = "wmac0_membase",
3029 + .flags = IORESOURCE_MEM,
3030 + },
3031 + {
3032 + .name = "wmac0_irq",
3033 + .flags = IORESOURCE_IRQ,
3034 + }
3035 +};
3036 +
3037 +static struct resource ar231x_wmac1_res[] = {
3038 + {
3039 + .name = "wmac1_membase",
3040 + .flags = IORESOURCE_MEM,
3041 + },
3042 + {
3043 + .name = "wmac1_irq",
3044 + .flags = IORESOURCE_IRQ,
3045 + }
3046 +};
3047 +
3048 +
3049 +static struct platform_device ar231x_wmac[] = {
3050 + {
3051 + .id = 0,
3052 + .name = "ar231x-wmac",
3053 + .resource = ar231x_wmac0_res,
3054 + .num_resources = ARRAY_SIZE(ar231x_wmac0_res),
3055 + .dev.platform_data = &ar231x_board,
3056 + },
3057 + {
3058 + .id = 1,
3059 + .name = "ar231x-wmac",
3060 + .resource = ar231x_wmac1_res,
3061 + .num_resources = ARRAY_SIZE(ar231x_wmac1_res),
3062 + .dev.platform_data = &ar231x_board,
3063 + },
3064 +};
3065 +
3066 +static const char *devtype_strings[] = {
3067 + [DEV_TYPE_AR5312] = "Atheros AR5312",
3068 + [DEV_TYPE_AR2312] = "Atheros AR2312",
3069 + [DEV_TYPE_AR2313] = "Atheros AR2313",
3070 + [DEV_TYPE_AR2315] = "Atheros AR2315",
3071 + [DEV_TYPE_AR2316] = "Atheros AR2316",
3072 + [DEV_TYPE_AR2317] = "Atheros AR2317",
3073 + [DEV_TYPE_UNKNOWN] = "Atheros (unknown)",
3074 +};
3075 +
3076 +const char *get_system_type(void)
3077 +{
3078 + if ((ar231x_devtype >= ARRAY_SIZE(devtype_strings)) ||
3079 + !devtype_strings[ar231x_devtype])
3080 + return devtype_strings[DEV_TYPE_UNKNOWN];
3081 + return devtype_strings[ar231x_devtype];
3082 +}
3083 +
3084 +
3085 +int __init
3086 +ar231x_add_ethernet(int nr, u32 base, int irq, void *pdata)
3087 +{
3088 + struct resource *res;
3089 +
3090 + ar231x_eth[nr].dev.platform_data = pdata;
3091 + res = &ar231x_eth[nr].resource[0];
3092 + res->start = base;
3093 + res->end = base + 0x2000 - 1;
3094 + res++;
3095 + res->start = irq;
3096 + res->end = irq;
3097 + return platform_device_register(&ar231x_eth[nr]);
3098 +}
3099 +
3100 +void __init
3101 +ar231x_serial_setup(u32 mapbase, unsigned int uartclk)
3102 +{
3103 + struct uart_port s;
3104 +
3105 + memset(&s, 0, sizeof(s));
3106 +
3107 + s.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
3108 + s.iotype = UPIO_MEM;
3109 + s.irq = AR531X_MISC_IRQ_UART0;
3110 + s.regshift = 2;
3111 + s.mapbase = mapbase;
3112 + s.uartclk = uartclk;
3113 + s.membase = (void __iomem *)s.mapbase;
3114 +
3115 + early_serial_setup(&s);
3116 +}
3117 +
3118 +int __init
3119 +ar231x_add_wmac(int nr, u32 base, int irq)
3120 +{
3121 + struct resource *res;
3122 +
3123 + ar231x_wmac[nr].dev.platform_data = &ar231x_board;
3124 + res = &ar231x_wmac[nr].resource[0];
3125 + res->start = base;
3126 + res->end = base + 0x10000 - 1;
3127 + res++;
3128 + res->start = irq;
3129 + res->end = irq;
3130 + return platform_device_register(&ar231x_wmac[nr]);
3131 +}
3132 +
3133 +static int __init ar231x_register_devices(void)
3134 +{
3135 + static struct resource res = {
3136 + .start = 0xFFFFFFFF,
3137 + };
3138 +
3139 + platform_device_register_simple("GPIODEV", 0, &res, 1);
3140 + ar5312_init_devices();
3141 + ar2315_init_devices();
3142 +
3143 + return 0;
3144 +}
3145 +
3146 +device_initcall(ar231x_register_devices);
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