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atheros[ar2315-wdt]: update I/O handling
[openwrt/svn-archive/archive.git] / target / linux / atheros / patches-3.10 / 100-board.patch
1 --- a/arch/mips/Kconfig
2 +++ b/arch/mips/Kconfig
3 @@ -138,6 +138,19 @@ config BCM63XX
4 help
5 Support for BCM63XX based boards
6
7 +config ATHEROS_AR231X
8 + bool "Atheros 231x/531x SoC support"
9 + select CEVT_R4K
10 + select CSRC_R4K
11 + select DMA_NONCOHERENT
12 + select IRQ_CPU
13 + select SYS_HAS_CPU_MIPS32_R1
14 + select SYS_SUPPORTS_BIG_ENDIAN
15 + select SYS_SUPPORTS_32BIT_KERNEL
16 + select ARCH_REQUIRE_GPIOLIB
17 + help
18 + Support for AR231x and AR531x based boards
19 +
20 config MIPS_COBALT
21 bool "Cobalt Server"
22 select CEVT_R4K
23 @@ -838,6 +851,7 @@ config NLM_XLP_BOARD
24
25 endchoice
26
27 +source "arch/mips/ar231x/Kconfig"
28 source "arch/mips/alchemy/Kconfig"
29 source "arch/mips/ath79/Kconfig"
30 source "arch/mips/bcm47xx/Kconfig"
31 --- a/arch/mips/Kbuild.platforms
32 +++ b/arch/mips/Kbuild.platforms
33 @@ -6,6 +6,7 @@ platforms += ath79
34 platforms += bcm47xx
35 platforms += bcm63xx
36 platforms += cavium-octeon
37 +platforms += ar231x
38 platforms += cobalt
39 platforms += dec
40 platforms += emma
41 --- /dev/null
42 +++ b/arch/mips/ar231x/Platform
43 @@ -0,0 +1,6 @@
44 +#
45 +# Atheros AR5312/AR2312 WiSoC
46 +#
47 +platform-$(CONFIG_ATHEROS_AR231X) += ar231x/
48 +cflags-$(CONFIG_ATHEROS_AR231X) += -I$(srctree)/arch/mips/include/asm/mach-ar231x
49 +load-$(CONFIG_ATHEROS_AR231X) += 0xffffffff80041000
50 --- /dev/null
51 +++ b/arch/mips/ar231x/Kconfig
52 @@ -0,0 +1,16 @@
53 +config ATHEROS_AR5312
54 + bool "Atheros 5312/2312+ support"
55 + depends on ATHEROS_AR231X
56 + default y
57 +
58 +config ATHEROS_AR2315
59 + bool "Atheros 2315+ support"
60 + depends on ATHEROS_AR231X
61 + select DMA_NONCOHERENT
62 + select CEVT_R4K
63 + select CSRC_R4K
64 + select IRQ_CPU
65 + select SYS_HAS_CPU_MIPS32_R1
66 + select SYS_SUPPORTS_32BIT_KERNEL
67 + select SYS_SUPPORTS_BIG_ENDIAN
68 + default y
69 --- /dev/null
70 +++ b/arch/mips/ar231x/Makefile
71 @@ -0,0 +1,13 @@
72 +#
73 +# This file is subject to the terms and conditions of the GNU General Public
74 +# License. See the file "COPYING" in the main directory of this archive
75 +# for more details.
76 +#
77 +# Copyright (C) 2006 FON Technology, SL.
78 +# Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
79 +# Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
80 +#
81 +
82 +obj-y += board.o prom.o devices.o
83 +obj-$(CONFIG_ATHEROS_AR5312) += ar5312.o
84 +obj-$(CONFIG_ATHEROS_AR2315) += ar2315.o
85 --- /dev/null
86 +++ b/arch/mips/ar231x/board.c
87 @@ -0,0 +1,261 @@
88 +/*
89 + * This file is subject to the terms and conditions of the GNU General Public
90 + * License. See the file "COPYING" in the main directory of this archive
91 + * for more details.
92 + *
93 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
94 + * Copyright (C) 2006 FON Technology, SL.
95 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
96 + * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
97 + */
98 +
99 +#include <generated/autoconf.h>
100 +#include <linux/init.h>
101 +#include <linux/module.h>
102 +#include <linux/types.h>
103 +#include <linux/string.h>
104 +#include <linux/platform_device.h>
105 +#include <linux/kernel.h>
106 +#include <linux/random.h>
107 +#include <linux/etherdevice.h>
108 +#include <linux/irq.h>
109 +#include <linux/io.h>
110 +#include <asm/irq_cpu.h>
111 +#include <asm/reboot.h>
112 +
113 +#include <ar231x_platform.h>
114 +#include "devices.h"
115 +#include "ar5312.h"
116 +#include "ar2315.h"
117 +
118 +void (*ar231x_irq_dispatch)(void);
119 +
120 +static inline bool
121 +check_radio_magic(u8 *addr)
122 +{
123 + addr += 0x7a; /* offset for flash magic */
124 + if ((addr[0] == 0x5a) && (addr[1] == 0xa5))
125 + return 1;
126 +
127 + return 0;
128 +}
129 +
130 +static inline bool
131 +check_board_data(u8 *flash_limit, u8 *addr, bool broken)
132 +{
133 + /* config magic found */
134 + if (*((u32 *)addr) == AR531X_BD_MAGIC)
135 + return 1;
136 +
137 + if (!broken)
138 + return 0;
139 +
140 + if (check_radio_magic(addr + 0xf8))
141 + ar231x_board.radio = addr + 0xf8;
142 + if ((addr < flash_limit + 0x10000) &&
143 + check_radio_magic(addr + 0x10000))
144 + ar231x_board.radio = addr + 0x10000;
145 +
146 + if (ar231x_board.radio) {
147 + /* broken board data detected, use radio data to find the
148 + * offset, user will fix this */
149 + return 1;
150 + }
151 + return 0;
152 +}
153 +
154 +static u8 *
155 +find_board_config(u8 *flash_limit, bool broken)
156 +{
157 + u8 *addr;
158 + int found = 0;
159 +
160 + for (addr = flash_limit - 0x1000;
161 + addr >= flash_limit - 0x30000;
162 + addr -= 0x1000) {
163 +
164 + if (check_board_data(flash_limit, addr, broken)) {
165 + found = 1;
166 + break;
167 + }
168 + }
169 +
170 + if (!found)
171 + addr = NULL;
172 +
173 + return addr;
174 +}
175 +
176 +static u8 *
177 +find_radio_config(u8 *flash_limit, u8 *board_config)
178 +{
179 + int found;
180 + u8 *radio_config;
181 +
182 + /*
183 + * Now find the start of Radio Configuration data, using heuristics:
184 + * Search forward from Board Configuration data by 0x1000 bytes
185 + * at a time until we find non-0xffffffff.
186 + */
187 + found = 0;
188 + for (radio_config = board_config + 0x1000;
189 + (radio_config < flash_limit);
190 + radio_config += 0x1000) {
191 + if ((*(u32 *)radio_config != 0xffffffff) &&
192 + check_radio_magic(radio_config)) {
193 + found = 1;
194 + break;
195 + }
196 + }
197 +
198 + /* AR2316 relocates radio config to new location */
199 + if (!found) {
200 + for (radio_config = board_config + 0xf8;
201 + (radio_config < flash_limit - 0x1000 + 0xf8);
202 + radio_config += 0x1000) {
203 + if ((*(u32 *)radio_config != 0xffffffff) &&
204 + check_radio_magic(radio_config)) {
205 + found = 1;
206 + break;
207 + }
208 + }
209 + }
210 +
211 + if (!found) {
212 + pr_warn("WARNING: Could not find Radio Configuration data\n");
213 + radio_config = 0;
214 + }
215 +
216 + return radio_config;
217 +}
218 +
219 +int __init
220 +ar231x_find_config(u8 *flash_limit)
221 +{
222 + struct ar231x_boarddata *config;
223 + unsigned int rcfg_size;
224 + int broken_boarddata = 0;
225 + u8 *bcfg, *rcfg;
226 + u8 *board_data;
227 + u8 *radio_data;
228 + u8 *mac_addr;
229 + u32 offset;
230 +
231 + ar231x_board.config = NULL;
232 + ar231x_board.radio = NULL;
233 + /* Copy the board and radio data to RAM, because accessing the mapped
234 + * memory of the flash directly after booting is not safe */
235 +
236 + /* Try to find valid board and radio data */
237 + bcfg = find_board_config(flash_limit, false);
238 +
239 + /* If that fails, try to at least find valid radio data */
240 + if (!bcfg) {
241 + bcfg = find_board_config(flash_limit, true);
242 + broken_boarddata = 1;
243 + }
244 +
245 + if (!bcfg) {
246 + pr_warn("WARNING: No board configuration data found!\n");
247 + return -ENODEV;
248 + }
249 +
250 + board_data = kzalloc(BOARD_CONFIG_BUFSZ, GFP_KERNEL);
251 + ar231x_board.config = (struct ar231x_boarddata *)board_data;
252 + memcpy(board_data, bcfg, 0x100);
253 + if (broken_boarddata) {
254 + pr_warn("WARNING: broken board data detected\n");
255 + config = ar231x_board.config;
256 + if (!memcmp(config->enet0_mac, "\x00\x00\x00\x00\x00\x00", 6)) {
257 + pr_info("Fixing up empty mac addresses\n");
258 + config->reset_config_gpio = 0xffff;
259 + config->sys_led_gpio = 0xffff;
260 + random_ether_addr(config->wlan0_mac);
261 + config->wlan0_mac[0] &= ~0x06;
262 + random_ether_addr(config->enet0_mac);
263 + random_ether_addr(config->enet1_mac);
264 + }
265 + }
266 +
267 +
268 + /* Radio config starts 0x100 bytes after board config, regardless
269 + * of what the physical layout on the flash chip looks like */
270 +
271 + if (ar231x_board.radio)
272 + rcfg = (u8 *)ar231x_board.radio;
273 + else
274 + rcfg = find_radio_config(flash_limit, bcfg);
275 +
276 + if (!rcfg)
277 + return -ENODEV;
278 +
279 + radio_data = board_data + 0x100 + ((rcfg - bcfg) & 0xfff);
280 + ar231x_board.radio = radio_data;
281 + offset = radio_data - board_data;
282 + pr_info("Radio config found at offset 0x%x (0x%x)\n", rcfg - bcfg,
283 + offset);
284 + rcfg_size = BOARD_CONFIG_BUFSZ - offset;
285 + memcpy(radio_data, rcfg, rcfg_size);
286 +
287 + mac_addr = &radio_data[0x1d * 2];
288 + if (is_broadcast_ether_addr(mac_addr)) {
289 + pr_info("Radio MAC is blank; using board-data\n");
290 + memcpy(mac_addr, ar231x_board.config->wlan0_mac, ETH_ALEN);
291 + }
292 +
293 + return 0;
294 +}
295 +
296 +static void
297 +ar231x_halt(void)
298 +{
299 + local_irq_disable();
300 + while (1)
301 + ;
302 +}
303 +
304 +void __init
305 +plat_mem_setup(void)
306 +{
307 + _machine_halt = ar231x_halt;
308 + pm_power_off = ar231x_halt;
309 +
310 + ar5312_plat_setup();
311 + ar2315_plat_setup();
312 +
313 + /* Disable data watchpoints */
314 + write_c0_watchlo0(0);
315 +}
316 +
317 +
318 +asmlinkage void
319 +plat_irq_dispatch(void)
320 +{
321 + ar231x_irq_dispatch();
322 +}
323 +
324 +void __init
325 +plat_time_init(void)
326 +{
327 + ar5312_time_init();
328 + ar2315_time_init();
329 +}
330 +
331 +unsigned int __cpuinit
332 +get_c0_compare_int(void)
333 +{
334 + return CP0_LEGACY_COMPARE_IRQ;
335 +}
336 +
337 +void __init
338 +arch_init_irq(void)
339 +{
340 + clear_c0_status(ST0_IM);
341 + mips_cpu_irq_init();
342 +
343 + /* Initialize interrupt controllers */
344 + ar5312_irq_init();
345 + ar2315_irq_init();
346 +}
347 +
348 +
349 --- /dev/null
350 +++ b/arch/mips/ar231x/prom.c
351 @@ -0,0 +1,37 @@
352 +/*
353 + * This file is subject to the terms and conditions of the GNU General Public
354 + * License. See the file "COPYING" in the main directory of this archive
355 + * for more details.
356 + *
357 + * Copyright MontaVista Software Inc
358 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
359 + * Copyright (C) 2006 FON Technology, SL.
360 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
361 + * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
362 + */
363 +
364 +/*
365 + * Prom setup file for ar531x
366 + */
367 +
368 +#include <linux/init.h>
369 +#include <generated/autoconf.h>
370 +#include <linux/kernel.h>
371 +#include <linux/string.h>
372 +#include <linux/mm.h>
373 +#include <linux/bootmem.h>
374 +
375 +#include <asm/bootinfo.h>
376 +#include <asm/addrspace.h>
377 +#include "ar5312.h"
378 +#include "ar2315.h"
379 +
380 +void __init prom_init(void)
381 +{
382 + ar5312_prom_init();
383 + ar2315_prom_init();
384 +}
385 +
386 +void __init prom_free_prom_memory(void)
387 +{
388 +}
389 --- /dev/null
390 +++ b/arch/mips/include/asm/mach-ar231x/ar231x_platform.h
391 @@ -0,0 +1,83 @@
392 +#ifndef __AR531X_PLATFORM_H
393 +#define __AR531X_PLATFORM_H
394 +
395 +/*
396 + * This is board-specific data that is stored in a "fixed" location in flash.
397 + * It is shared across operating systems, so it should not be changed lightly.
398 + * The main reason we need it is in order to extract the ethernet MAC
399 + * address(es).
400 + */
401 +struct ar231x_boarddata {
402 + u32 magic; /* board data is valid */
403 +#define AR531X_BD_MAGIC 0x35333131 /* "5311", for all 531x platforms */
404 + u16 cksum; /* checksum (starting with BD_REV 2) */
405 + u16 rev; /* revision of this struct */
406 +#define BD_REV 4
407 + char board_name[64]; /* Name of board */
408 + u16 major; /* Board major number */
409 + u16 minor; /* Board minor number */
410 + u32 flags; /* Board configuration */
411 +#define BD_ENET0 0x00000001 /* ENET0 is stuffed */
412 +#define BD_ENET1 0x00000002 /* ENET1 is stuffed */
413 +#define BD_UART1 0x00000004 /* UART1 is stuffed */
414 +#define BD_UART0 0x00000008 /* UART0 is stuffed (dma) */
415 +#define BD_RSTFACTORY 0x00000010 /* Reset factory defaults stuffed */
416 +#define BD_SYSLED 0x00000020 /* System LED stuffed */
417 +#define BD_EXTUARTCLK 0x00000040 /* External UART clock */
418 +#define BD_CPUFREQ 0x00000080 /* cpu freq is valid in nvram */
419 +#define BD_SYSFREQ 0x00000100 /* sys freq is set in nvram */
420 +#define BD_WLAN0 0x00000200 /* Enable WLAN0 */
421 +#define BD_MEMCAP 0x00000400 /* CAP SDRAM @ mem_cap for testing */
422 +#define BD_DISWATCHDOG 0x00000800 /* disable system watchdog */
423 +#define BD_WLAN1 0x00001000 /* Enable WLAN1 (ar5212) */
424 +#define BD_ISCASPER 0x00002000 /* FLAG for AR2312 */
425 +#define BD_WLAN0_2G_EN 0x00004000 /* FLAG for radio0_2G */
426 +#define BD_WLAN0_5G_EN 0x00008000 /* FLAG for radio0_2G */
427 +#define BD_WLAN1_2G_EN 0x00020000 /* FLAG for radio0_2G */
428 +#define BD_WLAN1_5G_EN 0x00040000 /* FLAG for radio0_2G */
429 + u16 reset_config_gpio; /* Reset factory GPIO pin */
430 + u16 sys_led_gpio; /* System LED GPIO pin */
431 +
432 + u32 cpu_freq; /* CPU core frequency in Hz */
433 + u32 sys_freq; /* System frequency in Hz */
434 + u32 cnt_freq; /* Calculated C0_COUNT frequency */
435 +
436 + u8 wlan0_mac[6];
437 + u8 enet0_mac[6];
438 + u8 enet1_mac[6];
439 +
440 + u16 pci_id; /* Pseudo PCIID for common code */
441 + u16 mem_cap; /* cap bank1 in MB */
442 +
443 + /* version 3 */
444 + u8 wlan1_mac[6]; /* (ar5212) */
445 +};
446 +
447 +#define BOARD_CONFIG_BUFSZ 0x1000
448 +
449 +/*
450 + * Platform device information for the Wireless MAC
451 + */
452 +struct ar231x_board_config {
453 + u16 devid;
454 +
455 + /* board config data */
456 + struct ar231x_boarddata *config;
457 +
458 + /* radio calibration data */
459 + const char *radio;
460 +};
461 +
462 +/*
463 + * Platform device information for the Ethernet MAC
464 + */
465 +struct ar231x_eth {
466 + u32 reset_base;
467 + u32 reset_mac;
468 + u32 reset_phy;
469 + u32 phy_base;
470 + struct ar231x_board_config *config;
471 + char *macaddr;
472 +};
473 +
474 +#endif /* __AR531X_PLATFORM_H */
475 --- /dev/null
476 +++ b/arch/mips/include/asm/mach-ar231x/cpu-feature-overrides.h
477 @@ -0,0 +1,84 @@
478 +/*
479 + * Atheros SoC specific CPU feature overrides
480 + *
481 + * Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
482 + *
483 + * This file was derived from: include/asm-mips/cpu-features.h
484 + * Copyright (C) 2003, 2004 Ralf Baechle
485 + * Copyright (C) 2004 Maciej W. Rozycki
486 + *
487 + * This program is free software; you can redistribute it and/or modify it
488 + * under the terms of the GNU General Public License version 2 as published
489 + * by the Free Software Foundation.
490 + *
491 + */
492 +#ifndef __ASM_MACH_ATHEROS_CPU_FEATURE_OVERRIDES_H
493 +#define __ASM_MACH_ATHEROS_CPU_FEATURE_OVERRIDES_H
494 +
495 +/*
496 + * The ATHEROS SoCs have MIPS 4Kc/4KEc core.
497 + */
498 +#define cpu_has_tlb 1
499 +#define cpu_has_4kex 1
500 +#define cpu_has_3k_cache 0
501 +#define cpu_has_4k_cache 1
502 +#define cpu_has_tx39_cache 0
503 +#define cpu_has_sb1_cache 0
504 +#define cpu_has_fpu 0
505 +#define cpu_has_32fpr 0
506 +#define cpu_has_counter 1
507 +/* #define cpu_has_watch ? */
508 +/* #define cpu_has_divec ? */
509 +/* #define cpu_has_vce ? */
510 +/* #define cpu_has_cache_cdex_p ? */
511 +/* #define cpu_has_cache_cdex_s ? */
512 +/* #define cpu_has_prefetch ? */
513 +/* #define cpu_has_mcheck ? */
514 +#define cpu_has_ejtag 1
515 +
516 +#if !defined(CONFIG_ATHEROS_AR5312)
517 +# define cpu_has_llsc 1
518 +#else
519 +/*
520 + * The MIPS 4Kc V0.9 core in the AR5312/AR2312 have problems with the
521 + * ll/sc instructions.
522 + */
523 +# define cpu_has_llsc 0
524 +#endif
525 +
526 +#define cpu_has_mips16 0
527 +#define cpu_has_mdmx 0
528 +#define cpu_has_mips3d 0
529 +#define cpu_has_smartmips 0
530 +
531 +/* #define cpu_has_vtag_icache ? */
532 +/* #define cpu_has_dc_aliases ? */
533 +/* #define cpu_has_ic_fills_f_dc ? */
534 +/* #define cpu_has_pindexed_dcache ? */
535 +
536 +/* #define cpu_icache_snoops_remote_store ? */
537 +
538 +#define cpu_has_mips32r1 1
539 +
540 +#if !defined(CONFIG_ATHEROS_AR5312)
541 +# define cpu_has_mips32r2 1
542 +#endif
543 +
544 +#define cpu_has_mips64r1 0
545 +#define cpu_has_mips64r2 0
546 +
547 +#define cpu_has_dsp 0
548 +#define cpu_has_mipsmt 0
549 +
550 +/* #define cpu_has_nofpuex ? */
551 +#define cpu_has_64bits 0
552 +#define cpu_has_64bit_zero_reg 0
553 +#define cpu_has_64bit_gp_regs 0
554 +#define cpu_has_64bit_addresses 0
555 +
556 +/* #define cpu_has_inclusive_pcaches ? */
557 +
558 +/* #define cpu_dcache_line_size() ? */
559 +/* #define cpu_icache_line_size() ? */
560 +
561 +#endif /* __ASM_MACH_ATHEROS_CPU_FEATURE_OVERRIDES_H */
562 --- /dev/null
563 +++ b/arch/mips/include/asm/mach-ar231x/dma-coherence.h
564 @@ -0,0 +1,79 @@
565 +/*
566 + * This file is subject to the terms and conditions of the GNU General Public
567 + * License. See the file "COPYING" in the main directory of this archive
568 + * for more details.
569 + *
570 + * Copyright (C) 2006 Ralf Baechle <ralf@linux-mips.org>
571 + * Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
572 + *
573 + */
574 +#ifndef __ASM_MACH_GENERIC_DMA_COHERENCE_H
575 +#define __ASM_MACH_GENERIC_DMA_COHERENCE_H
576 +
577 +#define PCI_DMA_OFFSET 0x20000000
578 +
579 +#include <linux/device.h>
580 +
581 +static inline dma_addr_t ar231x_dev_offset(struct device *dev)
582 +{
583 +#ifdef CONFIG_PCI
584 + extern struct bus_type pci_bus_type;
585 +
586 + if (dev && dev->bus == &pci_bus_type)
587 + return PCI_DMA_OFFSET;
588 + else
589 +#endif
590 + return 0;
591 +}
592 +
593 +static inline dma_addr_t
594 +plat_map_dma_mem(struct device *dev, void *addr, size_t size)
595 +{
596 + return virt_to_phys(addr) + ar231x_dev_offset(dev);
597 +}
598 +
599 +static inline dma_addr_t
600 +plat_map_dma_mem_page(struct device *dev, struct page *page)
601 +{
602 + return page_to_phys(page) + ar231x_dev_offset(dev);
603 +}
604 +
605 +static inline unsigned long
606 +plat_dma_addr_to_phys(struct device *dev, dma_addr_t dma_addr)
607 +{
608 + return dma_addr - ar231x_dev_offset(dev);
609 +}
610 +
611 +static inline void
612 +plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr, size_t size,
613 + enum dma_data_direction direction)
614 +{
615 +}
616 +
617 +static inline int plat_dma_supported(struct device *dev, u64 mask)
618 +{
619 + return 1;
620 +}
621 +
622 +static inline void plat_extra_sync_for_device(struct device *dev)
623 +{
624 + return;
625 +}
626 +
627 +static inline int plat_dma_mapping_error(struct device *dev,
628 + dma_addr_t dma_addr)
629 +{
630 + return 0;
631 +}
632 +
633 +static inline int plat_device_is_coherent(struct device *dev)
634 +{
635 +#ifdef CONFIG_DMA_COHERENT
636 + return 1;
637 +#endif
638 +#ifdef CONFIG_DMA_NONCOHERENT
639 + return 0;
640 +#endif
641 +}
642 +
643 +#endif /* __ASM_MACH_GENERIC_DMA_COHERENCE_H */
644 --- /dev/null
645 +++ b/arch/mips/include/asm/mach-ar231x/gpio.h
646 @@ -0,0 +1,30 @@
647 +#ifndef _ATHEROS_GPIO_H_
648 +#define _ATHEROS_GPIO_H_
649 +
650 +#include <ar231x.h>
651 +
652 +#define gpio_get_value __gpio_get_value
653 +#define gpio_set_value __gpio_set_value
654 +#define gpio_cansleep __gpio_cansleep
655 +
656 +/*
657 + * Wrappers for the generic GPIO layer
658 + */
659 +
660 +/* not sure if these are used? */
661 +
662 +/* Returns IRQ to attach for gpio. Unchecked function */
663 +static inline int gpio_to_irq(unsigned gpio)
664 +{
665 + return AR531X_GPIO_IRQ(gpio);
666 +}
667 +
668 +/* Returns gpio for IRQ attached. Unchecked function */
669 +static inline int irq_to_gpio(unsigned irq)
670 +{
671 + return irq - AR531X_GPIO_IRQ(0);
672 +}
673 +
674 +#include <asm-generic/gpio.h> /* cansleep wrappers */
675 +
676 +#endif
677 --- /dev/null
678 +++ b/arch/mips/include/asm/mach-ar231x/reset.h
679 @@ -0,0 +1,6 @@
680 +#ifndef __AR531X_RESET_H
681 +#define __AR531X_RESET_H
682 +
683 +void ar531x_disable_reset_button(void);
684 +
685 +#endif /* __AR531X_RESET_H */
686 --- /dev/null
687 +++ b/arch/mips/include/asm/mach-ar231x/war.h
688 @@ -0,0 +1,25 @@
689 +/*
690 + * This file is subject to the terms and conditions of the GNU General Public
691 + * License. See the file "COPYING" in the main directory of this archive
692 + * for more details.
693 + *
694 + * Copyright (C) 2008 Felix Fietkau <nbd@openwrt.org>
695 + */
696 +#ifndef __ASM_MIPS_MACH_ATHEROS_WAR_H
697 +#define __ASM_MIPS_MACH_ATHEROS_WAR_H
698 +
699 +#define R4600_V1_INDEX_ICACHEOP_WAR 0
700 +#define R4600_V1_HIT_CACHEOP_WAR 0
701 +#define R4600_V2_HIT_CACHEOP_WAR 0
702 +#define R5432_CP0_INTERRUPT_WAR 0
703 +#define BCM1250_M3_WAR 0
704 +#define SIBYTE_1956_WAR 0
705 +#define MIPS4K_ICACHE_REFILL_WAR 0
706 +#define MIPS_CACHE_SYNC_WAR 0
707 +#define TX49XX_ICACHE_INDEX_INV_WAR 0
708 +#define RM9000_CDEX_SMP_WAR 0
709 +#define ICACHE_REFILLS_WORKAROUND_WAR 0
710 +#define R10000_LLSC_WAR 0
711 +#define MIPS34K_MISSED_ITLB_WAR 0
712 +
713 +#endif /* __ASM_MIPS_MACH_ATHEROS_WAR_H */
714 --- /dev/null
715 +++ b/arch/mips/include/asm/mach-ar231x/ar2315_regs.h
716 @@ -0,0 +1,597 @@
717 +/*
718 + * Register definitions for AR2315+
719 + *
720 + * This file is subject to the terms and conditions of the GNU General Public
721 + * License. See the file "COPYING" in the main directory of this archive
722 + * for more details.
723 + *
724 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
725 + * Copyright (C) 2006 FON Technology, SL.
726 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
727 + * Copyright (C) 2006-2008 Felix Fietkau <nbd@openwrt.org>
728 + */
729 +
730 +#ifndef __AR2315_REG_H
731 +#define __AR2315_REG_H
732 +
733 +/*
734 + * IRQs
735 + */
736 +#define AR2315_IRQ_MISC_INTRS (MIPS_CPU_IRQ_BASE+2) /* C0_CAUSE: 0x0400 */
737 +#define AR2315_IRQ_WLAN0_INTRS (MIPS_CPU_IRQ_BASE+3) /* C0_CAUSE: 0x0800 */
738 +#define AR2315_IRQ_ENET0_INTRS (MIPS_CPU_IRQ_BASE+4) /* C0_CAUSE: 0x1000 */
739 +#define AR2315_IRQ_LCBUS_PCI (MIPS_CPU_IRQ_BASE+5) /* C0_CAUSE: 0x2000 */
740 +#define AR2315_IRQ_WLAN0_POLL (MIPS_CPU_IRQ_BASE+6) /* C0_CAUSE: 0x4000 */
741 +
742 +/*
743 + * Address map
744 + */
745 +#define AR2315_SPI_READ 0x08000000 /* SPI FLASH */
746 +#define AR2315_WLAN0 0x10000000 /* Wireless MMR */
747 +#define AR2315_PCI 0x10100000 /* PCI MMR */
748 +#define AR2315_SDRAMCTL 0x10300000 /* SDRAM MMR */
749 +#define AR2315_LOCAL 0x10400000 /* LOCAL BUS MMR */
750 +#define AR2315_ENET0 0x10500000 /* ETHERNET MMR */
751 +#define AR2315_DSLBASE 0x11000000 /* RESET CONTROL MMR */
752 +#define AR2315_UART0 0x11100003 /* UART MMR */
753 +#define AR2315_SPI_MMR 0x11300000 /* SPI FLASH MMR */
754 +#define AR2315_PCIEXT 0x80000000 /* pci external */
755 +
756 +/*
757 + * Reset Register
758 + */
759 +#define AR2315_COLD_RESET (AR2315_DSLBASE + 0x0000)
760 +
761 +#define AR2315_RESET_COLD_AHB 0x00000001
762 +#define AR2315_RESET_COLD_APB 0x00000002
763 +#define AR2315_RESET_COLD_CPU 0x00000004
764 +#define AR2315_RESET_COLD_CPUWARM 0x00000008
765 +#define AR2315_RESET_SYSTEM \
766 + (RESET_COLD_CPU |\
767 + RESET_COLD_APB |\
768 + RESET_COLD_AHB) /* full system */
769 +#define AR2317_RESET_SYSTEM 0x00000010
770 +
771 +
772 +#define AR2315_RESET (AR2315_DSLBASE + 0x0004)
773 +
774 +/* warm reset WLAN0 MAC */
775 +#define AR2315_RESET_WARM_WLAN0_MAC 0x00000001
776 +/* warm reset WLAN0 BaseBand */
777 +#define AR2315_RESET_WARM_WLAN0_BB 0x00000002
778 +/* warm reset MPEG-TS */
779 +#define AR2315_RESET_MPEGTS_RSVD 0x00000004
780 +/* warm reset PCI ahb/dma */
781 +#define AR2315_RESET_PCIDMA 0x00000008
782 +/* warm reset memory controller */
783 +#define AR2315_RESET_MEMCTL 0x00000010
784 +/* warm reset local bus */
785 +#define AR2315_RESET_LOCAL 0x00000020
786 +/* warm reset I2C bus */
787 +#define AR2315_RESET_I2C_RSVD 0x00000040
788 +/* warm reset SPI interface */
789 +#define AR2315_RESET_SPI 0x00000080
790 +/* warm reset UART0 */
791 +#define AR2315_RESET_UART0 0x00000100
792 +/* warm reset IR interface */
793 +#define AR2315_RESET_IR_RSVD 0x00000200
794 +/* cold reset ENET0 phy */
795 +#define AR2315_RESET_EPHY0 0x00000400
796 +/* cold reset ENET0 mac */
797 +#define AR2315_RESET_ENET0 0x00000800
798 +
799 +/*
800 + * AHB master arbitration control
801 + */
802 +#define AR2315_AHB_ARB_CTL (AR2315_DSLBASE + 0x0008)
803 +
804 +/* CPU, default */
805 +#define AR2315_ARB_CPU 0x00000001
806 +/* WLAN */
807 +#define AR2315_ARB_WLAN 0x00000002
808 +/* MPEG-TS */
809 +#define AR2315_ARB_MPEGTS_RSVD 0x00000004
810 +/* LOCAL */
811 +#define AR2315_ARB_LOCAL 0x00000008
812 +/* PCI */
813 +#define AR2315_ARB_PCI 0x00000010
814 +/* Ethernet */
815 +#define AR2315_ARB_ETHERNET 0x00000020
816 +/* retry policy, debug only */
817 +#define AR2315_ARB_RETRY 0x00000100
818 +
819 +/*
820 + * Config Register
821 + */
822 +#define AR2315_ENDIAN_CTL (AR2315_DSLBASE + 0x000c)
823 +
824 +/* EC - AHB bridge endianess */
825 +#define AR2315_CONFIG_AHB 0x00000001
826 +/* WLAN byteswap */
827 +#define AR2315_CONFIG_WLAN 0x00000002
828 +/* MPEG-TS byteswap */
829 +#define AR2315_CONFIG_MPEGTS_RSVD 0x00000004
830 +/* PCI byteswap */
831 +#define AR2315_CONFIG_PCI 0x00000008
832 +/* Memory controller endianess */
833 +#define AR2315_CONFIG_MEMCTL 0x00000010
834 +/* Local bus byteswap */
835 +#define AR2315_CONFIG_LOCAL 0x00000020
836 +/* Ethernet byteswap */
837 +#define AR2315_CONFIG_ETHERNET 0x00000040
838 +
839 +/* CPU write buffer merge */
840 +#define AR2315_CONFIG_MERGE 0x00000200
841 +/* CPU big endian */
842 +#define AR2315_CONFIG_CPU 0x00000400
843 +#define AR2315_CONFIG_PCIAHB 0x00000800
844 +#define AR2315_CONFIG_PCIAHB_BRIDGE 0x00001000
845 +/* SPI byteswap */
846 +#define AR2315_CONFIG_SPI 0x00008000
847 +#define AR2315_CONFIG_CPU_DRAM 0x00010000
848 +#define AR2315_CONFIG_CPU_PCI 0x00020000
849 +#define AR2315_CONFIG_CPU_MMR 0x00040000
850 +#define AR2315_CONFIG_BIG 0x00000400
851 +
852 +
853 +/*
854 + * NMI control
855 + */
856 +#define AR2315_NMI_CTL (AR2315_DSLBASE + 0x0010)
857 +
858 +#define AR2315_NMI_EN 1
859 +
860 +/*
861 + * Revision Register - Initial value is 0x3010 (WMAC 3.0, AR531X 1.0).
862 + */
863 +#define AR2315_SREV (AR2315_DSLBASE + 0x0014)
864 +
865 +#define AR2315_REV_MAJ 0x00f0
866 +#define AR2315_REV_MAJ_S 4
867 +#define AR2315_REV_MIN 0x000f
868 +#define AR2315_REV_MIN_S 0
869 +#define AR2315_REV_CHIP (AR2315_REV_MAJ|AR2315_REV_MIN)
870 +
871 +/*
872 + * Interface Enable
873 + */
874 +#define AR2315_IF_CTL (AR2315_DSLBASE + 0x0018)
875 +
876 +#define AR2315_IF_MASK 0x00000007
877 +#define AR2315_IF_DISABLED 0
878 +#define AR2315_IF_PCI 1
879 +#define AR2315_IF_TS_LOCAL 2
880 +/* only for emulation with separate pins */
881 +#define AR2315_IF_ALL 3
882 +#define AR2315_IF_LOCAL_HOST 0x00000008
883 +#define AR2315_IF_PCI_HOST 0x00000010
884 +#define AR2315_IF_PCI_INTR 0x00000020
885 +#define AR2315_IF_PCI_CLK_MASK 0x00030000
886 +#define AR2315_IF_PCI_CLK_INPUT 0
887 +#define AR2315_IF_PCI_CLK_OUTPUT_LOW 1
888 +#define AR2315_IF_PCI_CLK_OUTPUT_CLK 2
889 +#define AR2315_IF_PCI_CLK_OUTPUT_HIGH 3
890 +#define AR2315_IF_PCI_CLK_SHIFT 16
891 +
892 +/*
893 + * APB Interrupt control
894 + */
895 +
896 +#define AR2315_ISR (AR2315_DSLBASE + 0x0020)
897 +#define AR2315_IMR (AR2315_DSLBASE + 0x0024)
898 +#define AR2315_GISR (AR2315_DSLBASE + 0x0028)
899 +
900 +#define AR2315_ISR_UART0 0x0001 /* high speed UART */
901 +#define AR2315_ISR_I2C_RSVD 0x0002 /* I2C bus */
902 +#define AR2315_ISR_SPI 0x0004 /* SPI bus */
903 +#define AR2315_ISR_AHB 0x0008 /* AHB error */
904 +#define AR2315_ISR_APB 0x0010 /* APB error */
905 +#define AR2315_ISR_TIMER 0x0020 /* timer */
906 +#define AR2315_ISR_GPIO 0x0040 /* GPIO */
907 +#define AR2315_ISR_WD 0x0080 /* watchdog */
908 +#define AR2315_ISR_IR_RSVD 0x0100 /* IR */
909 +
910 +#define AR2315_GISR_MISC 0x0001
911 +#define AR2315_GISR_WLAN0 0x0002
912 +#define AR2315_GISR_MPEGTS_RSVD 0x0004
913 +#define AR2315_GISR_LOCALPCI 0x0008
914 +#define AR2315_GISR_WMACPOLL 0x0010
915 +#define AR2315_GISR_TIMER 0x0020
916 +#define AR2315_GISR_ETHERNET 0x0040
917 +
918 +/*
919 + * Interrupt routing from IO to the processor IP bits
920 + * Define our inter mask and level
921 + */
922 +#define AR2315_INTR_MISCIO SR_IBIT3
923 +#define AR2315_INTR_WLAN0 SR_IBIT4
924 +#define AR2315_INTR_ENET0 SR_IBIT5
925 +#define AR2315_INTR_LOCALPCI SR_IBIT6
926 +#define AR2315_INTR_WMACPOLL SR_IBIT7
927 +#define AR2315_INTR_COMPARE SR_IBIT8
928 +
929 +/*
930 + * Timers
931 + */
932 +#define AR2315_TIMER (AR2315_DSLBASE + 0x0030)
933 +#define AR2315_RELOAD (AR2315_DSLBASE + 0x0034)
934 +#define AR2315_WD (AR2315_DSLBASE + 0x0038)
935 +#define AR2315_WDC (AR2315_DSLBASE + 0x003c)
936 +
937 +#define AR2315_WDC_IGNORE_EXPIRATION 0x00000000
938 +#define AR2315_WDC_NMI 0x00000001 /* NMI on watchdog */
939 +#define AR2315_WDC_RESET 0x00000002 /* reset on watchdog */
940 +
941 +/*
942 + * CPU Performance Counters
943 + */
944 +#define AR2315_PERFCNT0 (AR2315_DSLBASE + 0x0048)
945 +#define AR2315_PERFCNT1 (AR2315_DSLBASE + 0x004c)
946 +
947 +#define AR2315_PERF0_DATAHIT 0x0001 /* Count Data Cache Hits */
948 +#define AR2315_PERF0_DATAMISS 0x0002 /* Count Data Cache Misses */
949 +#define AR2315_PERF0_INSTHIT 0x0004 /* Count Instruction Cache Hits */
950 +#define AR2315_PERF0_INSTMISS 0x0008 /* Count Instruction Cache Misses */
951 +#define AR2315_PERF0_ACTIVE 0x0010 /* Count Active Processor Cycles */
952 +#define AR2315_PERF0_WBHIT 0x0020 /* Count CPU Write Buffer Hits */
953 +#define AR2315_PERF0_WBMISS 0x0040 /* Count CPU Write Buffer Misses */
954 +
955 +#define AR2315_PERF1_EB_ARDY 0x0001 /* Count EB_ARdy signal */
956 +#define AR2315_PERF1_EB_AVALID 0x0002 /* Count EB_AValid signal */
957 +#define AR2315_PERF1_EB_WDRDY 0x0004 /* Count EB_WDRdy signal */
958 +#define AR2315_PERF1_EB_RDVAL 0x0008 /* Count EB_RdVal signal */
959 +#define AR2315_PERF1_VRADDR 0x0010 /* Count valid read address cycles */
960 +#define AR2315_PERF1_VWADDR 0x0020 /* Count valid write address cycles */
961 +#define AR2315_PERF1_VWDATA 0x0040 /* Count valid write data cycles */
962 +
963 +/*
964 + * AHB Error Reporting.
965 + */
966 +#define AR2315_AHB_ERR0 (AR2315_DSLBASE + 0x0050) /* error */
967 +#define AR2315_AHB_ERR1 (AR2315_DSLBASE + 0x0054) /* haddr */
968 +#define AR2315_AHB_ERR2 (AR2315_DSLBASE + 0x0058) /* hwdata */
969 +#define AR2315_AHB_ERR3 (AR2315_DSLBASE + 0x005c) /* hrdata */
970 +#define AR2315_AHB_ERR4 (AR2315_DSLBASE + 0x0060) /* status */
971 +
972 +#define AHB_ERROR_DET 1 /* AHB Error has been detected, */
973 + /* write 1 to clear all bits in ERR0 */
974 +#define AHB_ERROR_OVR 2 /* AHB Error overflow has been detected */
975 +#define AHB_ERROR_WDT 4 /* AHB Error due to wdt instead of hresp */
976 +
977 +#define AR2315_PROCERR_HMAST 0x0000000f
978 +#define AR2315_PROCERR_HMAST_DFLT 0
979 +#define AR2315_PROCERR_HMAST_WMAC 1
980 +#define AR2315_PROCERR_HMAST_ENET 2
981 +#define AR2315_PROCERR_HMAST_PCIENDPT 3
982 +#define AR2315_PROCERR_HMAST_LOCAL 4
983 +#define AR2315_PROCERR_HMAST_CPU 5
984 +#define AR2315_PROCERR_HMAST_PCITGT 6
985 +
986 +#define AR2315_PROCERR_HMAST_S 0
987 +#define AR2315_PROCERR_HWRITE 0x00000010
988 +#define AR2315_PROCERR_HSIZE 0x00000060
989 +#define AR2315_PROCERR_HSIZE_S 5
990 +#define AR2315_PROCERR_HTRANS 0x00000180
991 +#define AR2315_PROCERR_HTRANS_S 7
992 +#define AR2315_PROCERR_HBURST 0x00000e00
993 +#define AR2315_PROCERR_HBURST_S 9
994 +
995 +/*
996 + * Clock Control
997 + */
998 +#define AR2315_PLLC_CTL (AR2315_DSLBASE + 0x0064)
999 +#define AR2315_PLLV_CTL (AR2315_DSLBASE + 0x0068)
1000 +#define AR2315_CPUCLK (AR2315_DSLBASE + 0x006c)
1001 +#define AR2315_AMBACLK (AR2315_DSLBASE + 0x0070)
1002 +#define AR2315_SYNCCLK (AR2315_DSLBASE + 0x0074)
1003 +#define AR2315_DSL_SLEEP_CTL (AR2315_DSLBASE + 0x0080)
1004 +#define AR2315_DSL_SLEEP_DUR (AR2315_DSLBASE + 0x0084)
1005 +
1006 +/* PLLc Control fields */
1007 +#define PLLC_REF_DIV_M 0x00000003
1008 +#define PLLC_REF_DIV_S 0
1009 +#define PLLC_FDBACK_DIV_M 0x0000007C
1010 +#define PLLC_FDBACK_DIV_S 2
1011 +#define PLLC_ADD_FDBACK_DIV_M 0x00000080
1012 +#define PLLC_ADD_FDBACK_DIV_S 7
1013 +#define PLLC_CLKC_DIV_M 0x0001c000
1014 +#define PLLC_CLKC_DIV_S 14
1015 +#define PLLC_CLKM_DIV_M 0x00700000
1016 +#define PLLC_CLKM_DIV_S 20
1017 +
1018 +/* CPU CLK Control fields */
1019 +#define CPUCLK_CLK_SEL_M 0x00000003
1020 +#define CPUCLK_CLK_SEL_S 0
1021 +#define CPUCLK_CLK_DIV_M 0x0000000c
1022 +#define CPUCLK_CLK_DIV_S 2
1023 +
1024 +/* AMBA CLK Control fields */
1025 +#define AMBACLK_CLK_SEL_M 0x00000003
1026 +#define AMBACLK_CLK_SEL_S 0
1027 +#define AMBACLK_CLK_DIV_M 0x0000000c
1028 +#define AMBACLK_CLK_DIV_S 2
1029 +
1030 +/*
1031 + * GPIO
1032 + */
1033 +#define AR2315_GPIO_DI (AR2315_DSLBASE + 0x0088)
1034 +#define AR2315_GPIO_DO (AR2315_DSLBASE + 0x0090)
1035 +#define AR2315_GPIO_CR (AR2315_DSLBASE + 0x0098)
1036 +#define AR2315_GPIO_INT (AR2315_DSLBASE + 0x00a0)
1037 +
1038 +#define AR2315_GPIO_CR_M(x) (1 << (x)) /* mask for i/o */
1039 +#define AR2315_GPIO_CR_O(x) (1 << (x)) /* output */
1040 +#define AR2315_GPIO_CR_I(x) (0) /* input */
1041 +
1042 +#define AR2315_GPIO_INT_S(x) (x) /* interrupt enable */
1043 +#define AR2315_GPIO_INT_M (0x3F) /* mask for int */
1044 +#define AR2315_GPIO_INT_LVL(x) ((x) << 6) /* interrupt level */
1045 +#define AR2315_GPIO_INT_LVL_M ((0x3) << 6) /* mask for int level */
1046 +
1047 +#define AR2315_GPIO_INT_MAX_Y 1 /* Maximum value of Y for
1048 + * AR5313_GPIO_INT_* macros */
1049 +#define AR2315_GPIO_INT_LVL_OFF 0 /* Triggerring off */
1050 +#define AR2315_GPIO_INT_LVL_LOW 1 /* Low Level Triggered */
1051 +#define AR2315_GPIO_INT_LVL_HIGH 2 /* High Level Triggered */
1052 +#define AR2315_GPIO_INT_LVL_EDGE 3 /* Edge Triggered */
1053 +
1054 +#define AR2315_RESET_GPIO 5
1055 +#define AR2315_NUM_GPIO 22
1056 +
1057 +/*
1058 + * PCI Clock Control
1059 + */
1060 +#define AR2315_PCICLK (AR2315_DSLBASE + 0x00a4)
1061 +
1062 +#define AR2315_PCICLK_INPUT_M 0x3
1063 +#define AR2315_PCICLK_INPUT_S 0
1064 +
1065 +#define AR2315_PCICLK_PLLC_CLKM 0
1066 +#define AR2315_PCICLK_PLLC_CLKM1 1
1067 +#define AR2315_PCICLK_PLLC_CLKC 2
1068 +#define AR2315_PCICLK_REF_CLK 3
1069 +
1070 +#define AR2315_PCICLK_DIV_M 0xc
1071 +#define AR2315_PCICLK_DIV_S 2
1072 +
1073 +#define AR2315_PCICLK_IN_FREQ 0
1074 +#define AR2315_PCICLK_IN_FREQ_DIV_6 1
1075 +#define AR2315_PCICLK_IN_FREQ_DIV_8 2
1076 +#define AR2315_PCICLK_IN_FREQ_DIV_10 3
1077 +
1078 +/*
1079 + * Observation Control Register
1080 + */
1081 +#define AR2315_OCR (AR2315_DSLBASE + 0x00b0)
1082 +#define OCR_GPIO0_IRIN 0x0040
1083 +#define OCR_GPIO1_IROUT 0x0080
1084 +#define OCR_GPIO3_RXCLR 0x0200
1085 +
1086 +/*
1087 + * General Clock Control
1088 + */
1089 +
1090 +#define AR2315_MISCCLK (AR2315_DSLBASE + 0x00b4)
1091 +#define MISCCLK_PLLBYPASS_EN 0x00000001
1092 +#define MISCCLK_PROCREFCLK 0x00000002
1093 +
1094 +/*
1095 + * SDRAM Controller
1096 + * - No read or write buffers are included.
1097 + */
1098 +#define AR2315_MEM_CFG (AR2315_SDRAMCTL + 0x00)
1099 +#define AR2315_MEM_CTRL (AR2315_SDRAMCTL + 0x0c)
1100 +#define AR2315_MEM_REF (AR2315_SDRAMCTL + 0x10)
1101 +
1102 +#define SDRAM_DATA_WIDTH_M 0x00006000
1103 +#define SDRAM_DATA_WIDTH_S 13
1104 +
1105 +#define SDRAM_COL_WIDTH_M 0x00001E00
1106 +#define SDRAM_COL_WIDTH_S 9
1107 +
1108 +#define SDRAM_ROW_WIDTH_M 0x000001E0
1109 +#define SDRAM_ROW_WIDTH_S 5
1110 +
1111 +#define SDRAM_BANKADDR_BITS_M 0x00000018
1112 +#define SDRAM_BANKADDR_BITS_S 3
1113 +
1114 +/*
1115 + * PCI Bus Interface Registers
1116 + */
1117 +#define AR2315_PCI_1MS_REG (AR2315_PCI + 0x0008)
1118 +#define AR2315_PCI_1MS_MASK 0x3FFFF /* # of AHB clk cycles in 1ms */
1119 +
1120 +#define AR2315_PCI_MISC_CONFIG (AR2315_PCI + 0x000c)
1121 +#define AR2315_PCIMISC_TXD_EN 0x00000001 /* Enable TXD for fragments */
1122 +#define AR2315_PCIMISC_CFG_SEL 0x00000002 /* mem or config cycles */
1123 +#define AR2315_PCIMISC_GIG_MASK 0x0000000C /* bits 31-30 for pci req */
1124 +#define AR2315_PCIMISC_RST_MODE 0x00000030
1125 +#define AR2315_PCIRST_INPUT 0x00000000 /* 4:5=0 rst is input */
1126 +#define AR2315_PCIRST_LOW 0x00000010 /* 4:5=1 rst to GND */
1127 +#define AR2315_PCIRST_HIGH 0x00000020 /* 4:5=2 rst to VDD */
1128 +#define AR2315_PCIGRANT_EN 0x00000000 /* 6:7=0 early grant en */
1129 +#define AR2315_PCIGRANT_FRAME 0x00000040 /* 6:7=1 grant waits 4 frame */
1130 +#define AR2315_PCIGRANT_IDLE 0x00000080 /* 6:7=2 grant waits 4 idle */
1131 +#define AR2315_PCIGRANT_GAP 0x00000000 /* 6:7=2 grant waits 4 idle */
1132 +#define AR2315_PCICACHE_DIS 0x00001000 /* PCI external access cache
1133 + * disable */
1134 +
1135 +#define AR2315_PCI_OUT_TSTAMP (AR2315_PCI + 0x0010)
1136 +
1137 +#define AR2315_PCI_UNCACHE_CFG (AR2315_PCI + 0x0014)
1138 +
1139 +#define AR2315_PCI_IN_EN (AR2315_PCI + 0x0100)
1140 +#define AR2315_PCI_IN_EN0 0x01 /* Enable chain 0 */
1141 +#define AR2315_PCI_IN_EN1 0x02 /* Enable chain 1 */
1142 +#define AR2315_PCI_IN_EN2 0x04 /* Enable chain 2 */
1143 +#define AR2315_PCI_IN_EN3 0x08 /* Enable chain 3 */
1144 +
1145 +#define AR2315_PCI_IN_DIS (AR2315_PCI + 0x0104)
1146 +#define AR2315_PCI_IN_DIS0 0x01 /* Disable chain 0 */
1147 +#define AR2315_PCI_IN_DIS1 0x02 /* Disable chain 1 */
1148 +#define AR2315_PCI_IN_DIS2 0x04 /* Disable chain 2 */
1149 +#define AR2315_PCI_IN_DIS3 0x08 /* Disable chain 3 */
1150 +
1151 +#define AR2315_PCI_IN_PTR (AR2315_PCI + 0x0200)
1152 +
1153 +#define AR2315_PCI_OUT_EN (AR2315_PCI + 0x0400)
1154 +#define AR2315_PCI_OUT_EN0 0x01 /* Enable chain 0 */
1155 +
1156 +#define AR2315_PCI_OUT_DIS (AR2315_PCI + 0x0404)
1157 +#define AR2315_PCI_OUT_DIS0 0x01 /* Disable chain 0 */
1158 +
1159 +#define AR2315_PCI_OUT_PTR (AR2315_PCI + 0x0408)
1160 +
1161 +#define AR2315_PCI_INT_STATUS (AR2315_PCI + 0x0500) /* write one to clr */
1162 +#define AR2315_PCI_TXINT 0x00000001 /* Desc In Completed */
1163 +#define AR2315_PCI_TXOK 0x00000002 /* Desc In OK */
1164 +#define AR2315_PCI_TXERR 0x00000004 /* Desc In ERR */
1165 +#define AR2315_PCI_TXEOL 0x00000008 /* Desc In End-of-List */
1166 +#define AR2315_PCI_RXINT 0x00000010 /* Desc Out Completed */
1167 +#define AR2315_PCI_RXOK 0x00000020 /* Desc Out OK */
1168 +#define AR2315_PCI_RXERR 0x00000040 /* Desc Out ERR */
1169 +#define AR2315_PCI_RXEOL 0x00000080 /* Desc Out EOL */
1170 +#define AR2315_PCI_TXOOD 0x00000200 /* Desc In Out-of-Desc */
1171 +#define AR2315_PCI_MASK 0x0000FFFF /* Desc Mask */
1172 +#define AR2315_PCI_EXT_INT 0x02000000
1173 +#define AR2315_PCI_ABORT_INT 0x04000000
1174 +
1175 +#define AR2315_PCI_INT_MASK (AR2315_PCI + 0x0504) /* same as INT_STATUS */
1176 +
1177 +#define AR2315_PCI_INTEN_REG (AR2315_PCI + 0x0508)
1178 +#define AR2315_PCI_INT_DISABLE 0x00 /* disable pci interrupts */
1179 +#define AR2315_PCI_INT_ENABLE 0x01 /* enable pci interrupts */
1180 +
1181 +#define AR2315_PCI_HOST_IN_EN (AR2315_PCI + 0x0800)
1182 +#define AR2315_PCI_HOST_IN_DIS (AR2315_PCI + 0x0804)
1183 +#define AR2315_PCI_HOST_IN_PTR (AR2315_PCI + 0x0810)
1184 +#define AR2315_PCI_HOST_OUT_EN (AR2315_PCI + 0x0900)
1185 +#define AR2315_PCI_HOST_OUT_DIS (AR2315_PCI + 0x0904)
1186 +#define AR2315_PCI_HOST_OUT_PTR (AR2315_PCI + 0x0908)
1187 +
1188 +
1189 +/*
1190 + * Local Bus Interface Registers
1191 + */
1192 +#define AR2315_LB_CONFIG (AR2315_LOCAL + 0x0000)
1193 +#define AR2315_LBCONF_OE 0x00000001 /* =1 OE is low-true */
1194 +#define AR2315_LBCONF_CS0 0x00000002 /* =1 first CS is low-true */
1195 +#define AR2315_LBCONF_CS1 0x00000004 /* =1 2nd CS is low-true */
1196 +#define AR2315_LBCONF_RDY 0x00000008 /* =1 RDY is low-true */
1197 +#define AR2315_LBCONF_WE 0x00000010 /* =1 Write En is low-true */
1198 +#define AR2315_LBCONF_WAIT 0x00000020 /* =1 WAIT is low-true */
1199 +#define AR2315_LBCONF_ADS 0x00000040 /* =1 Adr Strobe is low-true */
1200 +#define AR2315_LBCONF_MOT 0x00000080 /* =0 Intel, =1 Motorola */
1201 +#define AR2315_LBCONF_8CS 0x00000100 /* =1 8 bits CS, 0= 16bits */
1202 +#define AR2315_LBCONF_8DS 0x00000200 /* =1 8 bits Data S, 0=16bits */
1203 +#define AR2315_LBCONF_ADS_EN 0x00000400 /* =1 Enable ADS */
1204 +#define AR2315_LBCONF_ADR_OE 0x00000800 /* =1 Adr cap on OE, WE or DS */
1205 +#define AR2315_LBCONF_ADDT_MUX 0x00001000 /* =1 Adr and Data share bus */
1206 +#define AR2315_LBCONF_DATA_OE 0x00002000 /* =1 Data cap on OE, WE, DS */
1207 +#define AR2315_LBCONF_16DATA 0x00004000 /* =1 Data is 16 bits wide */
1208 +#define AR2315_LBCONF_SWAPDT 0x00008000 /* =1 Byte swap data */
1209 +#define AR2315_LBCONF_SYNC 0x00010000 /* =1 Bus synchronous to clk */
1210 +#define AR2315_LBCONF_INT 0x00020000 /* =1 Intr is low true */
1211 +#define AR2315_LBCONF_INT_CTR0 0x00000000 /* GND high-Z, Vdd is high-Z */
1212 +#define AR2315_LBCONF_INT_CTR1 0x00040000 /* GND drive, Vdd is high-Z */
1213 +#define AR2315_LBCONF_INT_CTR2 0x00080000 /* GND high-Z, Vdd drive */
1214 +#define AR2315_LBCONF_INT_CTR3 0x000C0000 /* GND drive, Vdd drive */
1215 +#define AR2315_LBCONF_RDY_WAIT 0x00100000 /* =1 RDY is negative of WAIT */
1216 +#define AR2315_LBCONF_INT_PULSE 0x00200000 /* =1 Interrupt is a pulse */
1217 +#define AR2315_LBCONF_ENABLE 0x00400000 /* =1 Falcon respond to LB */
1218 +
1219 +#define AR2315_LB_CLKSEL (AR2315_LOCAL + 0x0004)
1220 +#define AR2315_LBCLK_EXT 0x0001 /* use external clk for lb */
1221 +
1222 +#define AR2315_LB_1MS (AR2315_LOCAL + 0x0008)
1223 +#define AR2315_LB1MS_MASK 0x3FFFF /* # of AHB clk cycles in 1ms */
1224 +
1225 +#define AR2315_LB_MISCCFG (AR2315_LOCAL + 0x000C)
1226 +#define AR2315_LBM_TXD_EN 0x00000001 /* Enable TXD for fragments */
1227 +#define AR2315_LBM_RX_INTEN 0x00000002 /* Enable LB ints on RX ready */
1228 +#define AR2315_LBM_MBOXWR_INTEN 0x00000004 /* Enable LB ints on mbox wr */
1229 +#define AR2315_LBM_MBOXRD_INTEN 0x00000008 /* Enable LB ints on mbox rd */
1230 +#define AR2315_LMB_DESCSWAP_EN 0x00000010 /* Byte swap desc enable */
1231 +#define AR2315_LBM_TIMEOUT_MASK 0x00FFFF80
1232 +#define AR2315_LBM_TIMEOUT_SHFT 7
1233 +#define AR2315_LBM_PORTMUX 0x07000000
1234 +
1235 +
1236 +#define AR2315_LB_RXTSOFF (AR2315_LOCAL + 0x0010)
1237 +
1238 +#define AR2315_LB_TX_CHAIN_EN (AR2315_LOCAL + 0x0100)
1239 +#define AR2315_LB_TXEN_0 0x01
1240 +#define AR2315_LB_TXEN_1 0x02
1241 +#define AR2315_LB_TXEN_2 0x04
1242 +#define AR2315_LB_TXEN_3 0x08
1243 +
1244 +#define AR2315_LB_TX_CHAIN_DIS (AR2315_LOCAL + 0x0104)
1245 +#define AR2315_LB_TX_DESC_PTR (AR2315_LOCAL + 0x0200)
1246 +
1247 +#define AR2315_LB_RX_CHAIN_EN (AR2315_LOCAL + 0x0400)
1248 +#define AR2315_LB_RXEN 0x01
1249 +
1250 +#define AR2315_LB_RX_CHAIN_DIS (AR2315_LOCAL + 0x0404)
1251 +#define AR2315_LB_RX_DESC_PTR (AR2315_LOCAL + 0x0408)
1252 +
1253 +#define AR2315_LB_INT_STATUS (AR2315_LOCAL + 0x0500)
1254 +#define AR2315_INT_TX_DESC 0x0001
1255 +#define AR2315_INT_TX_OK 0x0002
1256 +#define AR2315_INT_TX_ERR 0x0004
1257 +#define AR2315_INT_TX_EOF 0x0008
1258 +#define AR2315_INT_RX_DESC 0x0010
1259 +#define AR2315_INT_RX_OK 0x0020
1260 +#define AR2315_INT_RX_ERR 0x0040
1261 +#define AR2315_INT_RX_EOF 0x0080
1262 +#define AR2315_INT_TX_TRUNC 0x0100
1263 +#define AR2315_INT_TX_STARVE 0x0200
1264 +#define AR2315_INT_LB_TIMEOUT 0x0400
1265 +#define AR2315_INT_LB_ERR 0x0800
1266 +#define AR2315_INT_MBOX_WR 0x1000
1267 +#define AR2315_INT_MBOX_RD 0x2000
1268 +
1269 +/* Bit definitions for INT MASK are the same as INT_STATUS */
1270 +#define AR2315_LB_INT_MASK (AR2315_LOCAL + 0x0504)
1271 +
1272 +#define AR2315_LB_INT_EN (AR2315_LOCAL + 0x0508)
1273 +#define AR2315_LB_MBOX (AR2315_LOCAL + 0x0600)
1274 +
1275 +/*
1276 + * IR Interface Registers
1277 + */
1278 +#define AR2315_IR_PKTDATA (AR2315_IR + 0x0000)
1279 +
1280 +#define AR2315_IR_PKTLEN (AR2315_IR + 0x07fc) /* 0 - 63 */
1281 +
1282 +#define AR2315_IR_CONTROL (AR2315_IR + 0x0800)
1283 +#define AR2315_IRCTL_TX 0x00000000 /* use as tranmitter */
1284 +#define AR2315_IRCTL_RX 0x00000001 /* use as receiver */
1285 +#define AR2315_IRCTL_SAMPLECLK_MASK 0x00003ffe /* Sample clk divisor */
1286 +#define AR2315_IRCTL_SAMPLECLK_SHFT 1
1287 +#define AR2315_IRCTL_OUTPUTCLK_MASK 0x03ffc000 /* Output clk div */
1288 +#define AR2315_IRCTL_OUTPUTCLK_SHFT 14
1289 +
1290 +#define AR2315_IR_STATUS (AR2315_IR + 0x0804)
1291 +#define AR2315_IRSTS_RX 0x00000001 /* receive in progress */
1292 +#define AR2315_IRSTS_TX 0x00000002 /* transmit in progress */
1293 +
1294 +#define AR2315_IR_CONFIG (AR2315_IR + 0x0808)
1295 +#define AR2315_IRCFG_INVIN 0x00000001 /* invert in polarity */
1296 +#define AR2315_IRCFG_INVOUT 0x00000002 /* invert out polarity */
1297 +#define AR2315_IRCFG_SEQ_START_WIN_SEL 0x00000004 /* 1 => 28, 0 => 7 */
1298 +#define AR2315_IRCFG_SEQ_START_THRESH 0x000000f0
1299 +#define AR2315_IRCFG_SEQ_END_UNIT_SEL 0x00000100
1300 +#define AR2315_IRCFG_SEQ_END_UNIT_THRESH 0x00007e00
1301 +#define AR2315_IRCFG_SEQ_END_WIN_SEL 0x00008000
1302 +#define AR2315_IRCFG_SEQ_END_WIN_THRESH 0x001f0000
1303 +#define AR2315_IRCFG_NUM_BACKOFF_WORDS 0x01e00000
1304 +
1305 +#define HOST_PCI_DEV_ID 3
1306 +#define HOST_PCI_MBAR0 0x10000000
1307 +#define HOST_PCI_MBAR1 0x20000000
1308 +#define HOST_PCI_MBAR2 0x30000000
1309 +
1310 +#define HOST_PCI_SDRAM_BASEADDR HOST_PCI_MBAR1
1311 +#define PCI_DEVICE_MEM_SPACE 0x800000
1312 +
1313 +#endif /* __AR2315_REG_H */
1314 --- /dev/null
1315 +++ b/arch/mips/include/asm/mach-ar231x/ar5312_regs.h
1316 @@ -0,0 +1,233 @@
1317 +/*
1318 + * This file is subject to the terms and conditions of the GNU General Public
1319 + * License. See the file "COPYING" in the main directory of this archive
1320 + * for more details.
1321 + *
1322 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
1323 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
1324 + * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
1325 + */
1326 +
1327 +#ifndef AR5312_H
1328 +#define AR5312_H
1329 +
1330 +#include <asm/addrspace.h>
1331 +
1332 +/*
1333 + * IRQs
1334 + */
1335 +
1336 +#define AR5312_IRQ_WLAN0_INTRS (MIPS_CPU_IRQ_BASE+2) /* C0_CAUSE: 0x0400 */
1337 +#define AR5312_IRQ_ENET0_INTRS (MIPS_CPU_IRQ_BASE+3) /* C0_CAUSE: 0x0800 */
1338 +#define AR5312_IRQ_ENET1_INTRS (MIPS_CPU_IRQ_BASE+4) /* C0_CAUSE: 0x1000 */
1339 +#define AR5312_IRQ_WLAN1_INTRS (MIPS_CPU_IRQ_BASE+5) /* C0_CAUSE: 0x2000 */
1340 +#define AR5312_IRQ_MISC_INTRS (MIPS_CPU_IRQ_BASE+6) /* C0_CAUSE: 0x4000 */
1341 +
1342 +
1343 +/* Address Map */
1344 +#define AR531X_WLAN0 0x18000000
1345 +#define AR531X_WLAN1 0x18500000
1346 +#define AR531X_ENET0 0x18100000
1347 +#define AR531X_ENET1 0x18200000
1348 +#define AR531X_SDRAMCTL 0x18300000
1349 +#define AR531X_FLASHCTL 0x18400000
1350 +#define AR531X_APBBASE 0x1c000000
1351 +#define AR531X_FLASH 0x1e000000
1352 +#define AR531X_UART0 0xbc000003 /* UART MMR */
1353 +
1354 +/*
1355 + * AR531X_NUM_ENET_MAC defines the number of ethernet MACs that
1356 + * should be considered available. The AR5312 supports 2 enet MACS,
1357 + * even though many reference boards only actually use 1 of them
1358 + * (i.e. Only MAC 0 is actually connected to an enet PHY or PHY switch.
1359 + * The AR2312 supports 1 enet MAC.
1360 + */
1361 +#define AR531X_NUM_ENET_MAC 2
1362 +
1363 +/*
1364 + * Need these defines to determine true number of ethernet MACs
1365 + */
1366 +#define AR5212_AR5312_REV2 0x0052 /* AR5312 WMAC (AP31) */
1367 +#define AR5212_AR5312_REV7 0x0057 /* AR5312 WMAC (AP30-040) */
1368 +#define AR5212_AR2313_REV8 0x0058 /* AR2313 WMAC (AP43-030) */
1369 +
1370 +/*
1371 + * AR531X_NUM_WMAC defines the number of Wireless MACs that\
1372 + * should be considered available.
1373 + */
1374 +#define AR531X_NUM_WMAC 2
1375 +
1376 +/* Reset/Timer Block Address Map */
1377 +#define AR531X_RESETTMR (AR531X_APBBASE + 0x3000)
1378 +#define AR531X_TIMER (AR531X_RESETTMR + 0x0000) /* countdown timer */
1379 +#define AR531X_WD_CTRL (AR531X_RESETTMR + 0x0008) /* watchdog cntrl */
1380 +#define AR531X_WD_TIMER (AR531X_RESETTMR + 0x000c) /* watchdog timer */
1381 +#define AR531X_ISR (AR531X_RESETTMR + 0x0010) /* Intr Status Reg */
1382 +#define AR531X_IMR (AR531X_RESETTMR + 0x0014) /* Intr Mask Reg */
1383 +#define AR531X_RESET (AR531X_RESETTMR + 0x0020)
1384 +#define AR5312_CLOCKCTL1 (AR531X_RESETTMR + 0x0064)
1385 +#define AR5312_SCRATCH (AR531X_RESETTMR + 0x006c)
1386 +#define AR531X_PROCADDR (AR531X_RESETTMR + 0x0070)
1387 +#define AR531X_PROC1 (AR531X_RESETTMR + 0x0074)
1388 +#define AR531X_DMAADDR (AR531X_RESETTMR + 0x0078)
1389 +#define AR531X_DMA1 (AR531X_RESETTMR + 0x007c)
1390 +#define AR531X_ENABLE (AR531X_RESETTMR + 0x0080) /* interface enb */
1391 +#define AR531X_REV (AR531X_RESETTMR + 0x0090) /* revision */
1392 +
1393 +/* AR531X_WD_CTRL register bit field definitions */
1394 +#define AR531X_WD_CTRL_IGNORE_EXPIRATION 0x0000
1395 +#define AR531X_WD_CTRL_NMI 0x0001
1396 +#define AR531X_WD_CTRL_RESET 0x0002
1397 +
1398 +/* AR531X_ISR register bit field definitions */
1399 +#define AR531X_ISR_NONE 0x0000
1400 +#define AR531X_ISR_TIMER 0x0001
1401 +#define AR531X_ISR_AHBPROC 0x0002
1402 +#define AR531X_ISR_AHBDMA 0x0004
1403 +#define AR531X_ISR_GPIO 0x0008
1404 +#define AR531X_ISR_UART0 0x0010
1405 +#define AR531X_ISR_UART0DMA 0x0020
1406 +#define AR531X_ISR_WD 0x0040
1407 +#define AR531X_ISR_LOCAL 0x0080
1408 +
1409 +/* AR531X_RESET register bit field definitions */
1410 +#define AR531X_RESET_SYSTEM 0x00000001 /* cold reset full system */
1411 +#define AR531X_RESET_PROC 0x00000002 /* cold reset MIPS core */
1412 +#define AR531X_RESET_WLAN0 0x00000004 /* cold reset WLAN MAC and BB */
1413 +#define AR531X_RESET_EPHY0 0x00000008 /* cold reset ENET0 phy */
1414 +#define AR531X_RESET_EPHY1 0x00000010 /* cold reset ENET1 phy */
1415 +#define AR531X_RESET_ENET0 0x00000020 /* cold reset ENET0 mac */
1416 +#define AR531X_RESET_ENET1 0x00000040 /* cold reset ENET1 mac */
1417 +#define AR531X_RESET_UART0 0x00000100 /* cold reset UART0 (high speed) */
1418 +#define AR531X_RESET_WLAN1 0x00000200 /* cold reset WLAN MAC/BB */
1419 +#define AR531X_RESET_APB 0x00000400 /* cold reset APB (ar5312) */
1420 +#define AR531X_RESET_WARM_PROC 0x00001000 /* warm reset MIPS core */
1421 +#define AR531X_RESET_WARM_WLAN0_MAC 0x00002000 /* warm reset WLAN0 MAC */
1422 +#define AR531X_RESET_WARM_WLAN0_BB 0x00004000 /* warm reset WLAN0 BaseBand */
1423 +#define AR531X_RESET_NMI 0x00010000 /* send an NMI to the processor */
1424 +#define AR531X_RESET_WARM_WLAN1_MAC 0x00020000 /* warm reset WLAN1 mac */
1425 +#define AR531X_RESET_WARM_WLAN1_BB 0x00040000 /* warm reset WLAN1 baseband */
1426 +#define AR531X_RESET_LOCAL_BUS 0x00080000 /* reset local bus */
1427 +#define AR531X_RESET_WDOG 0x00100000 /* last reset was a watchdog */
1428 +
1429 +#define AR531X_RESET_WMAC0_BITS \
1430 + (AR531X_RESET_WLAN0 |\
1431 + AR531X_RESET_WARM_WLAN0_MAC |\
1432 + AR531X_RESET_WARM_WLAN0_BB)
1433 +
1434 +#define AR531X_RESERT_WMAC1_BITS \
1435 + (AR531X_RESET_WLAN1 |\
1436 + AR531X_RESET_WARM_WLAN1_MAC |\
1437 + AR531X_RESET_WARM_WLAN1_BB)
1438 +
1439 +/* AR5312_CLOCKCTL1 register bit field definitions */
1440 +#define AR5312_CLOCKCTL1_PREDIVIDE_MASK 0x00000030
1441 +#define AR5312_CLOCKCTL1_PREDIVIDE_SHIFT 4
1442 +#define AR5312_CLOCKCTL1_MULTIPLIER_MASK 0x00001f00
1443 +#define AR5312_CLOCKCTL1_MULTIPLIER_SHIFT 8
1444 +#define AR5312_CLOCKCTL1_DOUBLER_MASK 0x00010000
1445 +
1446 +/* Valid for AR5312 and AR2312 */
1447 +#define AR5312_CLOCKCTL1_PREDIVIDE_MASK 0x00000030
1448 +#define AR5312_CLOCKCTL1_PREDIVIDE_SHIFT 4
1449 +#define AR5312_CLOCKCTL1_MULTIPLIER_MASK 0x00001f00
1450 +#define AR5312_CLOCKCTL1_MULTIPLIER_SHIFT 8
1451 +#define AR5312_CLOCKCTL1_DOUBLER_MASK 0x00010000
1452 +
1453 +/* Valid for AR2313 */
1454 +#define AR2313_CLOCKCTL1_PREDIVIDE_MASK 0x00003000
1455 +#define AR2313_CLOCKCTL1_PREDIVIDE_SHIFT 12
1456 +#define AR2313_CLOCKCTL1_MULTIPLIER_MASK 0x001f0000
1457 +#define AR2313_CLOCKCTL1_MULTIPLIER_SHIFT 16
1458 +#define AR2313_CLOCKCTL1_DOUBLER_MASK 0x00000000
1459 +
1460 +
1461 +/* AR531X_ENABLE register bit field definitions */
1462 +#define AR531X_ENABLE_WLAN0 0x0001
1463 +#define AR531X_ENABLE_ENET0 0x0002
1464 +#define AR531X_ENABLE_ENET1 0x0004
1465 +#define AR531X_ENABLE_UART_AND_WLAN1_PIO 0x0008 /* UART, and WLAN1 PIOs */
1466 +#define AR531X_ENABLE_WLAN1_DMA 0x0010 /* WLAN1 DMAs */
1467 +#define AR531X_ENABLE_WLAN1 \
1468 + (AR531X_ENABLE_UART_AND_WLAN1_PIO |\
1469 + AR531X_ENABLE_WLAN1_DMA)
1470 +
1471 +/* AR531X_REV register bit field definitions */
1472 +#define AR531X_REV_WMAC_MAJ 0xf000
1473 +#define AR531X_REV_WMAC_MAJ_S 12
1474 +#define AR531X_REV_WMAC_MIN 0x0f00
1475 +#define AR531X_REV_WMAC_MIN_S 8
1476 +#define AR531X_REV_MAJ 0x00f0
1477 +#define AR531X_REV_MAJ_S 4
1478 +#define AR531X_REV_MIN 0x000f
1479 +#define AR531X_REV_MIN_S 0
1480 +#define AR531X_REV_CHIP (AR531X_REV_MAJ|AR531X_REV_MIN)
1481 +
1482 +/* Major revision numbers, bits 7..4 of Revision ID register */
1483 +#define AR531X_REV_MAJ_AR5312 0x4
1484 +#define AR531X_REV_MAJ_AR2313 0x5
1485 +
1486 +/* Minor revision numbers, bits 3..0 of Revision ID register */
1487 +#define AR5312_REV_MIN_DUAL 0x0 /* Dual WLAN version */
1488 +#define AR5312_REV_MIN_SINGLE 0x1 /* Single WLAN version */
1489 +
1490 +/* AR531X_FLASHCTL register bit field definitions */
1491 +#define FLASHCTL_IDCY 0x0000000f /* Idle cycle turn around time */
1492 +#define FLASHCTL_IDCY_S 0
1493 +#define FLASHCTL_WST1 0x000003e0 /* Wait state 1 */
1494 +#define FLASHCTL_WST1_S 5
1495 +#define FLASHCTL_RBLE 0x00000400 /* Read byte lane enable */
1496 +#define FLASHCTL_WST2 0x0000f800 /* Wait state 2 */
1497 +#define FLASHCTL_WST2_S 11
1498 +#define FLASHCTL_AC 0x00070000 /* Flash address check (added) */
1499 +#define FLASHCTL_AC_S 16
1500 +#define FLASHCTL_AC_128K 0x00000000
1501 +#define FLASHCTL_AC_256K 0x00010000
1502 +#define FLASHCTL_AC_512K 0x00020000
1503 +#define FLASHCTL_AC_1M 0x00030000
1504 +#define FLASHCTL_AC_2M 0x00040000
1505 +#define FLASHCTL_AC_4M 0x00050000
1506 +#define FLASHCTL_AC_8M 0x00060000
1507 +#define FLASHCTL_AC_RES 0x00070000 /* 16MB is not supported */
1508 +#define FLASHCTL_E 0x00080000 /* Flash bank enable (added) */
1509 +#define FLASHCTL_BUSERR 0x01000000 /* Bus transfer error status flag */
1510 +#define FLASHCTL_WPERR 0x02000000 /* Write protect error status flag */
1511 +#define FLASHCTL_WP 0x04000000 /* Write protect */
1512 +#define FLASHCTL_BM 0x08000000 /* Burst mode */
1513 +#define FLASHCTL_MW 0x30000000 /* Memory width */
1514 +#define FLASHCTL_MWx8 0x00000000 /* Memory width x8 */
1515 +#define FLASHCTL_MWx16 0x10000000 /* Memory width x16 */
1516 +#define FLASHCTL_MWx32 0x20000000 /* Memory width x32 (not supported) */
1517 +#define FLASHCTL_ATNR 0x00000000 /* Access type == no retry */
1518 +#define FLASHCTL_ATR 0x80000000 /* Access type == retry every */
1519 +#define FLASHCTL_ATR4 0xc0000000 /* Access type == retry every 4 */
1520 +
1521 +/* ARM Flash Controller -- 3 flash banks with either x8 or x16 devices. */
1522 +#define AR531X_FLASHCTL0 (AR531X_FLASHCTL + 0x00)
1523 +#define AR531X_FLASHCTL1 (AR531X_FLASHCTL + 0x04)
1524 +#define AR531X_FLASHCTL2 (AR531X_FLASHCTL + 0x08)
1525 +
1526 +/* ARM SDRAM Controller -- just enough to determine memory size */
1527 +#define AR531X_MEM_CFG1 (AR531X_SDRAMCTL + 0x04)
1528 +#define MEM_CFG1_AC0 0x00000700 /* bank 0: SDRAM addr check (added) */
1529 +#define MEM_CFG1_AC0_S 8
1530 +#define MEM_CFG1_AC1 0x00007000 /* bank 1: SDRAM addr check (added) */
1531 +#define MEM_CFG1_AC1_S 12
1532 +
1533 +/* GPIO Address Map */
1534 +#define AR531X_GPIO (AR531X_APBBASE + 0x2000)
1535 +#define AR531X_GPIO_DO (AR531X_GPIO + 0x00) /* output register */
1536 +#define AR531X_GPIO_DI (AR531X_GPIO + 0x04) /* intput register */
1537 +#define AR531X_GPIO_CR (AR531X_GPIO + 0x08) /* control register */
1538 +
1539 +/* GPIO Control Register bit field definitions */
1540 +#define AR531X_GPIO_CR_M(x) (1 << (x)) /* mask for i/o */
1541 +#define AR531X_GPIO_CR_O(x) (0 << (x)) /* mask for output */
1542 +#define AR531X_GPIO_CR_I(x) (1 << (x)) /* mask for input */
1543 +#define AR531X_GPIO_CR_INT(x) (1 << ((x)+8)) /* mask for interrupt*/
1544 +#define AR531X_GPIO_CR_UART(x) (1 << ((x)+16)) /* uart multiplex */
1545 +#define AR531X_NUM_GPIO 8
1546 +
1547 +
1548 +#endif
1549 +
1550 --- /dev/null
1551 +++ b/arch/mips/ar231x/ar5312.c
1552 @@ -0,0 +1,582 @@
1553 +/*
1554 + * This file is subject to the terms and conditions of the GNU General Public
1555 + * License. See the file "COPYING" in the main directory of this archive
1556 + * for more details.
1557 + *
1558 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
1559 + * Copyright (C) 2006 FON Technology, SL.
1560 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
1561 + * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
1562 + * Copyright (C) 2012 Alexandros C. Couloumbis <alex@ozo.com>
1563 + */
1564 +
1565 +/*
1566 + * Platform devices for Atheros SoCs
1567 + */
1568 +
1569 +#include <generated/autoconf.h>
1570 +#include <linux/init.h>
1571 +#include <linux/module.h>
1572 +#include <linux/types.h>
1573 +#include <linux/string.h>
1574 +#include <linux/mtd/physmap.h>
1575 +#include <linux/platform_device.h>
1576 +#include <linux/kernel.h>
1577 +#include <linux/reboot.h>
1578 +#include <linux/leds.h>
1579 +#include <linux/gpio.h>
1580 +#include <asm/bootinfo.h>
1581 +#include <asm/reboot.h>
1582 +#include <asm/time.h>
1583 +#include <linux/irq.h>
1584 +#include <linux/io.h>
1585 +
1586 +#include <ar231x_platform.h>
1587 +#include <ar5312_regs.h>
1588 +#include <ar231x.h>
1589 +#include "devices.h"
1590 +#include "ar5312.h"
1591 +
1592 +static void
1593 +ar5312_misc_irq_dispatch(void)
1594 +{
1595 + unsigned int ar231x_misc_intrs = ar231x_read_reg(AR531X_ISR) &
1596 + ar231x_read_reg(AR531X_IMR);
1597 +
1598 + if (ar231x_misc_intrs & AR531X_ISR_TIMER) {
1599 + do_IRQ(AR531X_MISC_IRQ_TIMER);
1600 + (void)ar231x_read_reg(AR531X_TIMER);
1601 + } else if (ar231x_misc_intrs & AR531X_ISR_AHBPROC)
1602 + do_IRQ(AR531X_MISC_IRQ_AHB_PROC);
1603 + else if ((ar231x_misc_intrs & AR531X_ISR_UART0))
1604 + do_IRQ(AR531X_MISC_IRQ_UART0);
1605 + else if (ar231x_misc_intrs & AR531X_ISR_WD)
1606 + do_IRQ(AR531X_MISC_IRQ_WATCHDOG);
1607 + else
1608 + do_IRQ(AR531X_MISC_IRQ_NONE);
1609 +}
1610 +
1611 +static asmlinkage void
1612 +ar5312_irq_dispatch(void)
1613 +{
1614 + int pending = read_c0_status() & read_c0_cause();
1615 +
1616 + if (pending & CAUSEF_IP2)
1617 + do_IRQ(AR5312_IRQ_WLAN0_INTRS);
1618 + else if (pending & CAUSEF_IP3)
1619 + do_IRQ(AR5312_IRQ_ENET0_INTRS);
1620 + else if (pending & CAUSEF_IP4)
1621 + do_IRQ(AR5312_IRQ_ENET1_INTRS);
1622 + else if (pending & CAUSEF_IP5)
1623 + do_IRQ(AR5312_IRQ_WLAN1_INTRS);
1624 + else if (pending & CAUSEF_IP6)
1625 + ar5312_misc_irq_dispatch();
1626 + else if (pending & CAUSEF_IP7)
1627 + do_IRQ(AR531X_IRQ_CPU_CLOCK);
1628 +}
1629 +
1630 +
1631 +/* Enable the specified AR531X_MISC_IRQ interrupt */
1632 +static void
1633 +ar5312_misc_intr_enable(struct irq_data *d)
1634 +{
1635 + unsigned int imr;
1636 +
1637 + imr = ar231x_read_reg(AR531X_IMR);
1638 + imr |= (1 << (d->irq - AR531X_MISC_IRQ_BASE - 1));
1639 + ar231x_write_reg(AR531X_IMR, imr);
1640 +}
1641 +
1642 +/* Disable the specified AR531X_MISC_IRQ interrupt */
1643 +static void
1644 +ar5312_misc_intr_disable(struct irq_data *d)
1645 +{
1646 + unsigned int imr;
1647 +
1648 + imr = ar231x_read_reg(AR531X_IMR);
1649 + imr &= ~(1 << (d->irq - AR531X_MISC_IRQ_BASE - 1));
1650 + ar231x_write_reg(AR531X_IMR, imr);
1651 + ar231x_read_reg(AR531X_IMR); /* flush write buffer */
1652 +}
1653 +
1654 +static struct irq_chip ar5312_misc_intr_controller = {
1655 + .irq_mask = ar5312_misc_intr_disable,
1656 + .irq_unmask = ar5312_misc_intr_enable,
1657 +};
1658 +
1659 +
1660 +static irqreturn_t ar5312_ahb_proc_handler(int cpl, void *dev_id)
1661 +{
1662 + u32 proc1 = ar231x_read_reg(AR531X_PROC1);
1663 + u32 proc_addr = ar231x_read_reg(AR531X_PROCADDR); /* clears error */
1664 + u32 dma1 = ar231x_read_reg(AR531X_DMA1);
1665 + u32 dma_addr = ar231x_read_reg(AR531X_DMAADDR); /* clears error */
1666 +
1667 + pr_emerg("AHB interrupt: PROCADDR=0x%8.8x PROC1=0x%8.8x "
1668 + "DMAADDR=0x%8.8x DMA1=0x%8.8x\n", proc_addr, proc1, dma_addr,
1669 + dma1);
1670 +
1671 + machine_restart("AHB error"); /* Catastrophic failure */
1672 + return IRQ_HANDLED;
1673 +}
1674 +
1675 +
1676 +static struct irqaction ar5312_ahb_proc_interrupt = {
1677 + .handler = ar5312_ahb_proc_handler,
1678 + .name = "ar5312_ahb_proc_interrupt",
1679 +};
1680 +
1681 +
1682 +static struct irqaction cascade = {
1683 + .handler = no_action,
1684 + .name = "cascade",
1685 +};
1686 +
1687 +void __init ar5312_irq_init(void)
1688 +{
1689 + int i;
1690 +
1691 + if (!is_5312())
1692 + return;
1693 +
1694 + ar231x_irq_dispatch = ar5312_irq_dispatch;
1695 + for (i = 0; i < AR531X_MISC_IRQ_COUNT; i++) {
1696 + int irq = AR531X_MISC_IRQ_BASE + i;
1697 + irq_set_chip_and_handler(irq, &ar5312_misc_intr_controller,
1698 + handle_level_irq);
1699 + }
1700 + setup_irq(AR531X_MISC_IRQ_AHB_PROC, &ar5312_ahb_proc_interrupt);
1701 + setup_irq(AR5312_IRQ_MISC_INTRS, &cascade);
1702 +}
1703 +
1704 +static u32
1705 +ar5312_gpio_set_output(u32 mask, u32 val)
1706 +{
1707 + u32 reg;
1708 +
1709 + reg = ar231x_read_reg(AR531X_GPIO_CR);
1710 + reg |= mask;
1711 + reg &= ~val;
1712 + ar231x_write_reg(AR531X_GPIO_CR, reg);
1713 + return reg;
1714 +}
1715 +
1716 +static u32
1717 +ar5312_gpio_get(u32 valid_mask)
1718 +{
1719 + u32 reg;
1720 + reg = ar231x_read_reg(AR531X_GPIO_DI);
1721 + reg &= valid_mask;
1722 + return reg;
1723 +}
1724 +
1725 +static u32
1726 +ar5312_gpio_set(u32 mask, u32 value)
1727 +{
1728 + u32 reg;
1729 + reg = ar231x_read_reg(AR531X_GPIO_DO);
1730 + reg &= ~mask;
1731 + reg |= value;
1732 + ar231x_write_reg(AR531X_GPIO_DO, reg);
1733 + return reg;
1734 +}
1735 +
1736 +/*
1737 + * gpiolib implementations. Original mask based methods preserved
1738 + */
1739 +static int
1740 +ar5312_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
1741 +{
1742 + struct ar231x_gpio_chip *gpch =
1743 + container_of(chip, struct ar231x_gpio_chip, chip);
1744 + u32 mask = 1 << gpio;
1745 + u32 rett;
1746 + if (!(gpch->valid_mask & mask))
1747 + return 0;
1748 + rett = ar5312_gpio_get(gpch->valid_mask);
1749 + return !!(rett & mask);
1750 +}
1751 +
1752 +static void
1753 +ar5312_gpio_set_value(struct gpio_chip *chip, unsigned gpio, int value)
1754 +{
1755 + struct ar231x_gpio_chip *gpch =
1756 + container_of(chip, struct ar231x_gpio_chip, chip);
1757 + u32 mask = 1 << gpio;
1758 + if (!(gpch->valid_mask & mask))
1759 + return;
1760 + ar5312_gpio_set(mask, (!!value) * mask);
1761 +}
1762 +
1763 +static int
1764 +ar5312_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
1765 +{
1766 + struct ar231x_gpio_chip *gpch =
1767 + container_of(chip, struct ar231x_gpio_chip, chip);
1768 + u32 mask = 1 << gpio;
1769 + if (!(gpch->valid_mask & mask))
1770 + return -ENXIO;
1771 + ar5312_gpio_set_output(mask, 0);
1772 + return 0;
1773 +}
1774 +static int
1775 +ar5312_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, int value)
1776 +{
1777 + struct ar231x_gpio_chip *gpch =
1778 + container_of(chip, struct ar231x_gpio_chip, chip);
1779 + u32 mask = 1 << gpio;
1780 + if (!(gpch->valid_mask & mask))
1781 + return -ENXIO;
1782 + ar5312_gpio_set_output(mask, mask);
1783 + ar5312_gpio_set(mask, (!!value) * mask);
1784 + return 0;
1785 +}
1786 +
1787 +static struct ar231x_gpio_chip ar5312_gpio_chip = {
1788 + .valid_mask = (1 << 22) - 1,
1789 + .chip = {
1790 + .label = "ar5312-gpio",
1791 + .direction_input = ar5312_gpio_direction_input,
1792 + .direction_output = ar5312_gpio_direction_output,
1793 + .set = ar5312_gpio_set_value,
1794 + .get = ar5312_gpio_get_value,
1795 + .base = 0,
1796 + .ngpio = AR531X_GPIO_IRQ_COUNT, /* 22 */
1797 + }
1798 +};
1799 +
1800 +/* end of gpiolib */
1801 +
1802 +static struct physmap_flash_data ar5312_flash_data = {
1803 + .width = 2,
1804 +};
1805 +
1806 +static struct resource ar5312_flash_resource = {
1807 + .start = AR531X_FLASH,
1808 + .end = AR531X_FLASH + 0x800000 - 1,
1809 + .flags = IORESOURCE_MEM,
1810 +};
1811 +
1812 +static struct ar231x_eth ar5312_eth0_data = {
1813 + .reset_base = AR531X_RESET,
1814 + .reset_mac = AR531X_RESET_ENET0,
1815 + .reset_phy = AR531X_RESET_EPHY0,
1816 + .phy_base = KSEG1ADDR(AR531X_ENET0),
1817 + .config = &ar231x_board,
1818 +};
1819 +
1820 +static struct ar231x_eth ar5312_eth1_data = {
1821 + .reset_base = AR531X_RESET,
1822 + .reset_mac = AR531X_RESET_ENET1,
1823 + .reset_phy = AR531X_RESET_EPHY1,
1824 + .phy_base = KSEG1ADDR(AR531X_ENET1),
1825 + .config = &ar231x_board,
1826 +};
1827 +
1828 +static struct platform_device ar5312_physmap_flash = {
1829 + .name = "physmap-flash",
1830 + .id = 0,
1831 + .dev.platform_data = &ar5312_flash_data,
1832 + .resource = &ar5312_flash_resource,
1833 + .num_resources = 1,
1834 +};
1835 +
1836 +#ifdef CONFIG_LEDS_GPIO
1837 +static struct gpio_led ar5312_leds[] = {
1838 + { .name = "wlan", .gpio = 0, .active_low = 1, },
1839 +};
1840 +
1841 +static const struct gpio_led_platform_data ar5312_led_data = {
1842 + .num_leds = ARRAY_SIZE(ar5312_leds),
1843 + .leds = (void *)ar5312_leds,
1844 +};
1845 +
1846 +static struct platform_device ar5312_gpio_leds = {
1847 + .name = "leds-gpio",
1848 + .id = -1,
1849 + .dev.platform_data = (void *)&ar5312_led_data,
1850 +};
1851 +#endif
1852 +
1853 +/*
1854 + * NB: This mapping size is larger than the actual flash size,
1855 + * but this shouldn't be a problem here, because the flash
1856 + * will simply be mapped multiple times.
1857 + */
1858 +static char __init *ar5312_flash_limit(void)
1859 +{
1860 + u32 ctl;
1861 + /*
1862 + * Configure flash bank 0.
1863 + * Assume 8M window size. Flash will be aliased if it's smaller
1864 + */
1865 + ctl = FLASHCTL_E |
1866 + FLASHCTL_AC_8M |
1867 + FLASHCTL_RBLE |
1868 + (0x01 << FLASHCTL_IDCY_S) |
1869 + (0x07 << FLASHCTL_WST1_S) |
1870 + (0x07 << FLASHCTL_WST2_S) |
1871 + (ar231x_read_reg(AR531X_FLASHCTL0) & FLASHCTL_MW);
1872 +
1873 + ar231x_write_reg(AR531X_FLASHCTL0, ctl);
1874 +
1875 + /* Disable other flash banks */
1876 + ar231x_write_reg(AR531X_FLASHCTL1,
1877 + ar231x_read_reg(AR531X_FLASHCTL1) &
1878 + ~(FLASHCTL_E | FLASHCTL_AC));
1879 +
1880 + ar231x_write_reg(AR531X_FLASHCTL2,
1881 + ar231x_read_reg(AR531X_FLASHCTL2) &
1882 + ~(FLASHCTL_E | FLASHCTL_AC));
1883 +
1884 + return (char *)KSEG1ADDR(AR531X_FLASH + 0x800000);
1885 +}
1886 +
1887 +int __init ar5312_init_devices(void)
1888 +{
1889 + struct ar231x_boarddata *config;
1890 + u32 fctl = 0;
1891 + u8 *c;
1892 +
1893 + if (!is_5312())
1894 + return 0;
1895 +
1896 + /* Locate board/radio config data */
1897 + ar231x_find_config(ar5312_flash_limit());
1898 + config = ar231x_board.config;
1899 +
1900 + /* AR2313 has CPU minor rev. 10 */
1901 + if ((current_cpu_data.processor_id & 0xff) == 0x0a)
1902 + ar231x_devtype = DEV_TYPE_AR2313;
1903 +
1904 + /* AR2312 shares the same Silicon ID as AR5312 */
1905 + else if (config->flags & BD_ISCASPER)
1906 + ar231x_devtype = DEV_TYPE_AR2312;
1907 +
1908 + /* Everything else is probably AR5312 or compatible */
1909 + else
1910 + ar231x_devtype = DEV_TYPE_AR5312;
1911 +
1912 + /* fixup flash width */
1913 + fctl = ar231x_read_reg(AR531X_FLASHCTL) & FLASHCTL_MW;
1914 + switch (fctl) {
1915 + case FLASHCTL_MWx16:
1916 + ar5312_flash_data.width = 2;
1917 + break;
1918 + case FLASHCTL_MWx8:
1919 + default:
1920 + ar5312_flash_data.width = 1;
1921 + break;
1922 + }
1923 +
1924 + platform_device_register(&ar5312_physmap_flash);
1925 +
1926 +#ifdef CONFIG_LEDS_GPIO
1927 + ar5312_leds[0].gpio = config->sys_led_gpio;
1928 + platform_device_register(&ar5312_gpio_leds);
1929 +#endif
1930 +
1931 + /* Fix up MAC addresses if necessary */
1932 + if (!memcmp(config->enet0_mac, "\xff\xff\xff\xff\xff\xff", 6))
1933 + memcpy(config->enet0_mac, config->enet1_mac, 6);
1934 +
1935 + /* If ENET0 and ENET1 have the same mac address,
1936 + * increment the one from ENET1 */
1937 + if (memcmp(config->enet0_mac, config->enet1_mac, 6) == 0) {
1938 + c = config->enet1_mac + 5;
1939 + while ((c >= config->enet1_mac) && !(++(*c)))
1940 + c--;
1941 + }
1942 +
1943 + switch (ar231x_devtype) {
1944 + case DEV_TYPE_AR5312:
1945 + ar5312_eth0_data.macaddr = config->enet0_mac;
1946 + ar231x_add_ethernet(0, KSEG1ADDR(AR531X_ENET0),
1947 + AR5312_IRQ_ENET0_INTRS, &ar5312_eth0_data);
1948 +
1949 + ar5312_eth1_data.macaddr = config->enet1_mac;
1950 + ar231x_add_ethernet(1, KSEG1ADDR(AR531X_ENET1),
1951 + AR5312_IRQ_ENET1_INTRS, &ar5312_eth1_data);
1952 +
1953 + if (!ar231x_board.radio)
1954 + return 0;
1955 +
1956 + if (!(config->flags & BD_WLAN0))
1957 + break;
1958 +
1959 + ar231x_add_wmac(0, AR531X_WLAN0, AR5312_IRQ_WLAN0_INTRS);
1960 + break;
1961 + /*
1962 + * AR2312/3 ethernet uses the PHY of ENET0, but the MAC
1963 + * of ENET1. Atheros calls it 'twisted' for a reason :)
1964 + */
1965 + case DEV_TYPE_AR2312:
1966 + case DEV_TYPE_AR2313:
1967 + ar5312_eth1_data.phy_base = ar5312_eth0_data.phy_base;
1968 + ar5312_eth1_data.reset_phy = ar5312_eth0_data.reset_phy;
1969 + ar5312_eth1_data.macaddr = config->enet0_mac;
1970 + ar231x_add_ethernet(0, KSEG1ADDR(AR531X_ENET1),
1971 + AR5312_IRQ_ENET1_INTRS, &ar5312_eth1_data);
1972 +
1973 + if (!ar231x_board.radio)
1974 + return 0;
1975 + break;
1976 + default:
1977 + break;
1978 + }
1979 +
1980 + if (config->flags & BD_WLAN1)
1981 + ar231x_add_wmac(1, AR531X_WLAN1, AR5312_IRQ_WLAN1_INTRS);
1982 +
1983 + return 0;
1984 +}
1985 +
1986 +
1987 +static void ar5312_restart(char *command)
1988 +{
1989 + /* reset the system */
1990 + local_irq_disable();
1991 + while (1)
1992 + ar231x_write_reg(AR531X_RESET, AR531X_RESET_SYSTEM);
1993 +}
1994 +
1995 +
1996 +/*
1997 + * This table is indexed by bits 5..4 of the CLOCKCTL1 register
1998 + * to determine the predevisor value.
1999 + */
2000 +static int clockctl1_predivide_table[4] __initdata = { 1, 2, 4, 5 };
2001 +
2002 +
2003 +static int __init
2004 +ar5312_cpu_frequency(void)
2005 +{
2006 + unsigned int scratch;
2007 + unsigned int predivide_mask, predivide_shift;
2008 + unsigned int multiplier_mask, multiplier_shift;
2009 + unsigned int clock_ctl1, predivide_select, predivisor, multiplier;
2010 + unsigned int doubler_mask;
2011 + u16 devid;
2012 +
2013 + /* Trust the bootrom's idea of cpu frequency. */
2014 + scratch = ar231x_read_reg(AR5312_SCRATCH);
2015 + if (scratch)
2016 + return scratch;
2017 +
2018 + devid = ar231x_read_reg(AR531X_REV);
2019 + devid &= AR531X_REV_MAJ;
2020 + devid >>= AR531X_REV_MAJ_S;
2021 + if (devid == AR531X_REV_MAJ_AR2313) {
2022 + predivide_mask = AR2313_CLOCKCTL1_PREDIVIDE_MASK;
2023 + predivide_shift = AR2313_CLOCKCTL1_PREDIVIDE_SHIFT;
2024 + multiplier_mask = AR2313_CLOCKCTL1_MULTIPLIER_MASK;
2025 + multiplier_shift = AR2313_CLOCKCTL1_MULTIPLIER_SHIFT;
2026 + doubler_mask = AR2313_CLOCKCTL1_DOUBLER_MASK;
2027 + } else { /* AR5312 and AR2312 */
2028 + predivide_mask = AR5312_CLOCKCTL1_PREDIVIDE_MASK;
2029 + predivide_shift = AR5312_CLOCKCTL1_PREDIVIDE_SHIFT;
2030 + multiplier_mask = AR5312_CLOCKCTL1_MULTIPLIER_MASK;
2031 + multiplier_shift = AR5312_CLOCKCTL1_MULTIPLIER_SHIFT;
2032 + doubler_mask = AR5312_CLOCKCTL1_DOUBLER_MASK;
2033 + }
2034 +
2035 + /*
2036 + * Clocking is derived from a fixed 40MHz input clock.
2037 + *
2038 + * cpu_freq = input_clock * MULT (where MULT is PLL multiplier)
2039 + * sys_freq = cpu_freq / 4 (used for APB clock, serial,
2040 + * flash, Timer, Watchdog Timer)
2041 + *
2042 + * cnt_freq = cpu_freq / 2 (use for CPU count/compare)
2043 + *
2044 + * So, for example, with a PLL multiplier of 5, we have
2045 + *
2046 + * cpu_freq = 200MHz
2047 + * sys_freq = 50MHz
2048 + * cnt_freq = 100MHz
2049 + *
2050 + * We compute the CPU frequency, based on PLL settings.
2051 + */
2052 +
2053 + clock_ctl1 = ar231x_read_reg(AR5312_CLOCKCTL1);
2054 + predivide_select = (clock_ctl1 & predivide_mask) >> predivide_shift;
2055 + predivisor = clockctl1_predivide_table[predivide_select];
2056 + multiplier = (clock_ctl1 & multiplier_mask) >> multiplier_shift;
2057 +
2058 + if (clock_ctl1 & doubler_mask)
2059 + multiplier = multiplier << 1;
2060 +
2061 + return (40000000 / predivisor) * multiplier;
2062 +}
2063 +
2064 +static inline int
2065 +ar5312_sys_frequency(void)
2066 +{
2067 + return ar5312_cpu_frequency() / 4;
2068 +}
2069 +
2070 +void __init
2071 +ar5312_time_init(void)
2072 +{
2073 + if (!is_5312())
2074 + return;
2075 +
2076 + mips_hpt_frequency = ar5312_cpu_frequency() / 2;
2077 +}
2078 +
2079 +int __init
2080 +ar5312_gpio_init(void)
2081 +{
2082 + int ret;
2083 + struct ar231x_gpio_chip *gpch;
2084 + gpch = &ar5312_gpio_chip;
2085 + ret = gpiochip_add(&gpch->chip);
2086 + if (ret) {
2087 + pr_err("%s: failed to add gpiochip\n", gpch->chip.label);
2088 + return ret;
2089 + }
2090 + pr_info("%s: registered %d GPIOs\n", gpch->chip.label,
2091 + gpch->chip.ngpio);
2092 + return ret;
2093 +}
2094 +
2095 +void __init
2096 +ar5312_prom_init(void)
2097 +{
2098 + u32 memsize, memcfg, bank0AC, bank1AC;
2099 + u32 devid;
2100 +
2101 + if (!is_5312())
2102 + return;
2103 +
2104 + /* Detect memory size */
2105 + memcfg = ar231x_read_reg(AR531X_MEM_CFG1);
2106 + bank0AC = (memcfg & MEM_CFG1_AC0) >> MEM_CFG1_AC0_S;
2107 + bank1AC = (memcfg & MEM_CFG1_AC1) >> MEM_CFG1_AC1_S;
2108 + memsize = (bank0AC ? (1 << (bank0AC+1)) : 0) +
2109 + (bank1AC ? (1 << (bank1AC+1)) : 0);
2110 + memsize <<= 20;
2111 + add_memory_region(0, memsize, BOOT_MEM_RAM);
2112 +
2113 + devid = ar231x_read_reg(AR531X_REV);
2114 + devid >>= AR531X_REV_WMAC_MIN_S;
2115 + devid &= AR531X_REV_CHIP;
2116 + ar231x_board.devid = (u16) devid;
2117 + ar5312_gpio_init();
2118 +}
2119 +
2120 +void __init
2121 +ar5312_plat_setup(void)
2122 +{
2123 + if (!is_5312())
2124 + return;
2125 +
2126 + /* Clear any lingering AHB errors */
2127 + ar231x_read_reg(AR531X_PROCADDR);
2128 + ar231x_read_reg(AR531X_DMAADDR);
2129 + ar231x_write_reg(AR531X_WD_CTRL, AR531X_WD_CTRL_IGNORE_EXPIRATION);
2130 +
2131 + _machine_restart = ar5312_restart;
2132 + ar231x_serial_setup(KSEG1ADDR(AR531X_UART0), ar5312_sys_frequency());
2133 +}
2134 +
2135 --- /dev/null
2136 +++ b/arch/mips/ar231x/ar2315.c
2137 @@ -0,0 +1,639 @@
2138 +/*
2139 + * This file is subject to the terms and conditions of the GNU General Public
2140 + * License. See the file "COPYING" in the main directory of this archive
2141 + * for more details.
2142 + *
2143 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
2144 + * Copyright (C) 2006 FON Technology, SL.
2145 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
2146 + * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
2147 + * Copyright (C) 2012 Alexandros C. Couloumbis <alex@ozo.com>
2148 + */
2149 +
2150 +/*
2151 + * Platform devices for Atheros SoCs
2152 + */
2153 +
2154 +#include <generated/autoconf.h>
2155 +#include <linux/init.h>
2156 +#include <linux/module.h>
2157 +#include <linux/types.h>
2158 +#include <linux/string.h>
2159 +#include <linux/platform_device.h>
2160 +#include <linux/kernel.h>
2161 +#include <linux/reboot.h>
2162 +#include <linux/delay.h>
2163 +#include <linux/leds.h>
2164 +#include <linux/gpio.h>
2165 +#include <asm/bootinfo.h>
2166 +#include <asm/reboot.h>
2167 +#include <asm/time.h>
2168 +#include <linux/irq.h>
2169 +#include <linux/io.h>
2170 +
2171 +#include <ar231x_platform.h>
2172 +#include <ar2315_regs.h>
2173 +#include <ar231x.h>
2174 +#include "devices.h"
2175 +#include "ar2315.h"
2176 +
2177 +static u32 gpiointmask, gpiointval;
2178 +
2179 +static inline void ar2315_gpio_irq(void)
2180 +{
2181 + u32 pend;
2182 + int bit = -1;
2183 +
2184 + /* only do one gpio interrupt at a time */
2185 + pend = (ar231x_read_reg(AR2315_GPIO_DI) ^ gpiointval) & gpiointmask;
2186 +
2187 + if (pend) {
2188 + bit = fls(pend) - 1;
2189 + pend &= ~(1 << bit);
2190 + gpiointval ^= (1 << bit);
2191 + }
2192 +
2193 + if (!pend)
2194 + ar231x_write_reg(AR2315_ISR, AR2315_ISR_GPIO);
2195 +
2196 + /* Enable interrupt with edge detection */
2197 + if ((ar231x_read_reg(AR2315_GPIO_CR) & AR2315_GPIO_CR_M(bit)) !=
2198 + AR2315_GPIO_CR_I(bit))
2199 + return;
2200 +
2201 + if (bit >= 0)
2202 + do_IRQ(AR531X_GPIO_IRQ_BASE + bit);
2203 +}
2204 +
2205 +
2206 +/*
2207 + * Called when an interrupt is received, this function
2208 + * determines exactly which interrupt it was, and it
2209 + * invokes the appropriate handler.
2210 + *
2211 + * Implicitly, we also define interrupt priority by
2212 + * choosing which to dispatch first.
2213 + */
2214 +static asmlinkage void
2215 +ar2315_irq_dispatch(void)
2216 +{
2217 + int pending = read_c0_status() & read_c0_cause();
2218 +
2219 + if (pending & CAUSEF_IP3)
2220 + do_IRQ(AR2315_IRQ_WLAN0_INTRS);
2221 + else if (pending & CAUSEF_IP4)
2222 + do_IRQ(AR2315_IRQ_ENET0_INTRS);
2223 + else if (pending & CAUSEF_IP2) {
2224 + unsigned int misc_intr = ar231x_read_reg(AR2315_ISR) &
2225 + ar231x_read_reg(AR2315_IMR);
2226 +
2227 + if (misc_intr & AR2315_ISR_SPI)
2228 + do_IRQ(AR531X_MISC_IRQ_SPI);
2229 + else if (misc_intr & AR2315_ISR_TIMER)
2230 + do_IRQ(AR531X_MISC_IRQ_TIMER);
2231 + else if (misc_intr & AR2315_ISR_AHB)
2232 + do_IRQ(AR531X_MISC_IRQ_AHB_PROC);
2233 + else if (misc_intr & AR2315_ISR_GPIO)
2234 + ar2315_gpio_irq();
2235 + else if (misc_intr & AR2315_ISR_UART0)
2236 + do_IRQ(AR531X_MISC_IRQ_UART0);
2237 + else if (misc_intr & AR2315_ISR_WD) {
2238 + ar231x_write_reg(AR2315_ISR, AR2315_ISR_WD);
2239 + do_IRQ(AR531X_MISC_IRQ_WATCHDOG);
2240 + } else
2241 + do_IRQ(AR531X_MISC_IRQ_NONE);
2242 + } else if (pending & CAUSEF_IP7)
2243 + do_IRQ(AR531X_IRQ_CPU_CLOCK);
2244 +}
2245 +
2246 +static void ar2315_set_gpiointmask(int gpio, int level)
2247 +{
2248 + u32 reg;
2249 +
2250 + reg = ar231x_read_reg(AR2315_GPIO_INT);
2251 + reg &= ~(AR2315_GPIO_INT_M | AR2315_GPIO_INT_LVL_M);
2252 + reg |= gpio | AR2315_GPIO_INT_LVL(level);
2253 + ar231x_write_reg(AR2315_GPIO_INT, reg);
2254 +}
2255 +
2256 +static void ar2315_gpio_intr_enable(struct irq_data *d)
2257 +{
2258 + unsigned int gpio = d->irq - AR531X_GPIO_IRQ_BASE;
2259 +
2260 + /* Enable interrupt with edge detection */
2261 + if ((ar231x_read_reg(AR2315_GPIO_CR) & AR2315_GPIO_CR_M(gpio)) !=
2262 + AR2315_GPIO_CR_I(gpio))
2263 + return;
2264 +
2265 + gpiointmask |= (1 << gpio);
2266 + ar2315_set_gpiointmask(gpio, 3);
2267 +}
2268 +
2269 +static void ar2315_gpio_intr_disable(struct irq_data *d)
2270 +{
2271 + unsigned int gpio = d->irq - AR531X_GPIO_IRQ_BASE;
2272 +
2273 + /* Disable interrupt */
2274 + gpiointmask &= ~(1 << gpio);
2275 + ar2315_set_gpiointmask(gpio, 0);
2276 +}
2277 +
2278 +static struct irq_chip ar2315_gpio_intr_controller = {
2279 + .irq_mask = ar2315_gpio_intr_disable,
2280 + .irq_unmask = ar2315_gpio_intr_enable,
2281 +};
2282 +
2283 +static void
2284 +ar2315_misc_intr_enable(struct irq_data *d)
2285 +{
2286 + unsigned int imr;
2287 +
2288 + imr = ar231x_read_reg(AR2315_IMR);
2289 + switch (d->irq) {
2290 + case AR531X_MISC_IRQ_SPI:
2291 + imr |= AR2315_ISR_SPI;
2292 + break;
2293 + case AR531X_MISC_IRQ_TIMER:
2294 + imr |= AR2315_ISR_TIMER;
2295 + break;
2296 + case AR531X_MISC_IRQ_AHB_PROC:
2297 + imr |= AR2315_ISR_AHB;
2298 + break;
2299 + case AR531X_MISC_IRQ_GPIO:
2300 + imr |= AR2315_ISR_GPIO;
2301 + break;
2302 + case AR531X_MISC_IRQ_UART0:
2303 + imr |= AR2315_ISR_UART0;
2304 + break;
2305 + case AR531X_MISC_IRQ_WATCHDOG:
2306 + imr |= AR2315_ISR_WD;
2307 + break;
2308 + default:
2309 + break;
2310 + }
2311 + ar231x_write_reg(AR2315_IMR, imr);
2312 +}
2313 +
2314 +static void
2315 +ar2315_misc_intr_disable(struct irq_data *d)
2316 +{
2317 + unsigned int imr;
2318 +
2319 + imr = ar231x_read_reg(AR2315_IMR);
2320 + switch (d->irq) {
2321 + case AR531X_MISC_IRQ_SPI:
2322 + imr &= ~AR2315_ISR_SPI;
2323 + break;
2324 + case AR531X_MISC_IRQ_TIMER:
2325 + imr &= ~AR2315_ISR_TIMER;
2326 + break;
2327 + case AR531X_MISC_IRQ_AHB_PROC:
2328 + imr &= ~AR2315_ISR_AHB;
2329 + break;
2330 + case AR531X_MISC_IRQ_GPIO:
2331 + imr &= ~AR2315_ISR_GPIO;
2332 + break;
2333 + case AR531X_MISC_IRQ_UART0:
2334 + imr &= ~AR2315_ISR_UART0;
2335 + break;
2336 + case AR531X_MISC_IRQ_WATCHDOG:
2337 + imr &= ~AR2315_ISR_WD;
2338 + break;
2339 + default:
2340 + break;
2341 + }
2342 + ar231x_write_reg(AR2315_IMR, imr);
2343 +}
2344 +
2345 +static struct irq_chip ar2315_misc_intr_controller = {
2346 + .irq_mask = ar2315_misc_intr_disable,
2347 + .irq_unmask = ar2315_misc_intr_enable,
2348 +};
2349 +
2350 +static irqreturn_t ar2315_ahb_proc_handler(int cpl, void *dev_id)
2351 +{
2352 + ar231x_write_reg(AR2315_AHB_ERR0, AHB_ERROR_DET);
2353 + ar231x_read_reg(AR2315_AHB_ERR1);
2354 +
2355 + pr_emerg("AHB fatal error\n");
2356 + machine_restart("AHB error"); /* Catastrophic failure */
2357 +
2358 + return IRQ_HANDLED;
2359 +}
2360 +
2361 +static struct irqaction ar2315_ahb_proc_interrupt = {
2362 + .handler = ar2315_ahb_proc_handler,
2363 + .name = "ar2315_ahb_proc_interrupt",
2364 +};
2365 +
2366 +static struct irqaction cascade = {
2367 + .handler = no_action,
2368 + .name = "cascade",
2369 +};
2370 +
2371 +void
2372 +ar2315_irq_init(void)
2373 +{
2374 + int i;
2375 +
2376 + if (!is_2315())
2377 + return;
2378 +
2379 + ar231x_irq_dispatch = ar2315_irq_dispatch;
2380 + gpiointval = ar231x_read_reg(AR2315_GPIO_DI);
2381 + for (i = 0; i < AR531X_MISC_IRQ_COUNT; i++) {
2382 + int irq = AR531X_MISC_IRQ_BASE + i;
2383 + irq_set_chip_and_handler(irq, &ar2315_misc_intr_controller,
2384 + handle_level_irq);
2385 + }
2386 + for (i = 0; i < AR531X_GPIO_IRQ_COUNT; i++) {
2387 + int irq = AR531X_GPIO_IRQ_BASE + i;
2388 + irq_set_chip_and_handler(irq, &ar2315_gpio_intr_controller,
2389 + handle_level_irq);
2390 + }
2391 + setup_irq(AR531X_MISC_IRQ_GPIO, &cascade);
2392 + setup_irq(AR531X_MISC_IRQ_AHB_PROC, &ar2315_ahb_proc_interrupt);
2393 + setup_irq(AR2315_IRQ_MISC_INTRS, &cascade);
2394 +}
2395 +
2396 +static u32
2397 +ar2315_gpio_set_output(u32 mask, u32 val)
2398 +{
2399 + u32 reg;
2400 +
2401 + reg = ar231x_read_reg(AR2315_GPIO_CR);
2402 + reg &= ~mask;
2403 + reg |= val;
2404 + ar231x_write_reg(AR2315_GPIO_CR, reg);
2405 + return reg;
2406 +}
2407 +
2408 +static u32
2409 +ar2315_gpio_get(u32 valid_mask)
2410 +{
2411 + u32 reg;
2412 + reg = ar231x_read_reg(AR2315_GPIO_DI);
2413 + reg &= valid_mask;
2414 + return reg;
2415 +}
2416 +
2417 +static u32
2418 +ar2315_gpio_set(u32 mask, u32 value)
2419 +{
2420 + u32 reg;
2421 + reg = ar231x_read_reg(AR2315_GPIO_DO);
2422 + reg &= ~mask;
2423 + reg |= value;
2424 + ar231x_write_reg(AR2315_GPIO_DO, reg);
2425 + return reg;
2426 +}
2427 +
2428 +/*
2429 + * gpiolib implementation. Original legacy mask based methods
2430 + * preserved for now.
2431 + */
2432 +static int
2433 +ar2315_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
2434 +{
2435 + struct ar231x_gpio_chip *gpch =
2436 + container_of(chip, struct ar231x_gpio_chip, chip);
2437 + u32 mask = 1 << gpio;
2438 + u32 rett;
2439 + if (!(gpch->valid_mask & mask))
2440 + return 0;
2441 + rett = ar2315_gpio_get(gpch->valid_mask); /* legacy code */
2442 + return !!(rett & mask);
2443 +}
2444 +
2445 +static void
2446 +ar2315_gpio_set_value(struct gpio_chip *chip, unsigned gpio, int value)
2447 +{
2448 + struct ar231x_gpio_chip *gpch =
2449 + container_of(chip, struct ar231x_gpio_chip, chip);
2450 + u32 mask = 1 << gpio;
2451 + if (!(gpch->valid_mask & mask))
2452 + return;
2453 + ar2315_gpio_set(mask, (!!value) * mask); /* legacy */
2454 +}
2455 +
2456 +static int
2457 +ar2315_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
2458 +{
2459 + struct ar231x_gpio_chip *gpch =
2460 + container_of(chip, struct ar231x_gpio_chip, chip);
2461 + u32 mask = 1 << gpio;
2462 + if (!(gpch->valid_mask & mask))
2463 + return -ENXIO;
2464 + ar2315_gpio_set_output(mask, 0); /* legacy */
2465 + return 0;
2466 +}
2467 +
2468 +static int
2469 +ar2315_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, int value)
2470 +{
2471 + struct ar231x_gpio_chip *gpch =
2472 + container_of(chip, struct ar231x_gpio_chip, chip);
2473 + u32 mask = 1 << gpio;
2474 + if (!(gpch->valid_mask & mask))
2475 + return -ENXIO;
2476 + ar2315_gpio_set_output(mask, mask); /* both legacy */
2477 + ar2315_gpio_set(mask, (!!value) * mask);
2478 + return 0;
2479 +}
2480 +
2481 +static struct ar231x_gpio_chip ar2315_gpio_chip = {
2482 + .valid_mask = (1 << 22) - 1,
2483 + .chip = {
2484 + .label = "ar2315-gpio",
2485 + .direction_input = ar2315_gpio_direction_input,
2486 + .direction_output = ar2315_gpio_direction_output,
2487 + .set = ar2315_gpio_set_value,
2488 + .get = ar2315_gpio_get_value,
2489 + .base = 0,
2490 + .ngpio = AR531X_GPIO_IRQ_COUNT, /* 22 */
2491 + }
2492 +};
2493 +
2494 +/* end of gpiolib */
2495 +
2496 +
2497 +static struct ar231x_eth ar2315_eth_data = {
2498 + .reset_base = AR2315_RESET,
2499 + .reset_mac = AR2315_RESET_ENET0,
2500 + .reset_phy = AR2315_RESET_EPHY0,
2501 + .phy_base = KSEG1ADDR(AR2315_ENET0),
2502 + .config = &ar231x_board,
2503 +};
2504 +
2505 +static struct resource ar2315_spiflash_res[] = {
2506 + {
2507 + .name = "spiflash_read",
2508 + .flags = IORESOURCE_MEM,
2509 + .start = AR2315_SPI_READ,
2510 + .end = AR2315_SPI_READ + 0x1000000 - 1,
2511 + },
2512 + {
2513 + .name = "spiflash_mmr",
2514 + .flags = IORESOURCE_MEM,
2515 + .start = AR2315_SPI_MMR,
2516 + .end = AR2315_SPI_MMR + 12 - 1,
2517 + },
2518 +};
2519 +
2520 +static struct platform_device ar2315_spiflash = {
2521 + .id = 0,
2522 + .name = "ar2315-spiflash",
2523 + .resource = ar2315_spiflash_res,
2524 + .num_resources = ARRAY_SIZE(ar2315_spiflash_res)
2525 +};
2526 +
2527 +static struct resource ar2315_wdt_res[] = {
2528 + {
2529 + .flags = IORESOURCE_MEM,
2530 + .start = AR2315_WD,
2531 + .end = AR2315_WD + 8 - 1,
2532 + },
2533 + {
2534 + .flags = IORESOURCE_IRQ,
2535 + .start = AR531X_MISC_IRQ_WATCHDOG,
2536 + .end = AR531X_MISC_IRQ_WATCHDOG,
2537 + }
2538 +};
2539 +
2540 +static struct platform_device ar2315_wdt = {
2541 + .id = 0,
2542 + .name = "ar2315-wdt",
2543 + .resource = ar2315_wdt_res,
2544 + .num_resources = ARRAY_SIZE(ar2315_wdt_res)
2545 +};
2546 +
2547 +/*
2548 + * NB: We use mapping size that is larger than the actual flash size,
2549 + * but this shouldn't be a problem here, because the flash will simply
2550 + * be mapped multiple times.
2551 + */
2552 +static u8 __init *ar2315_flash_limit(void)
2553 +{
2554 + return (u8 *)KSEG1ADDR(ar2315_spiflash_res[0].end + 1);
2555 +}
2556 +
2557 +#ifdef CONFIG_LEDS_GPIO
2558 +static struct gpio_led ar2315_leds[6];
2559 +static struct gpio_led_platform_data ar2315_led_data = {
2560 + .leds = (void *)ar2315_leds,
2561 +};
2562 +
2563 +static struct platform_device ar2315_gpio_leds = {
2564 + .name = "leds-gpio",
2565 + .id = -1,
2566 + .dev = {
2567 + .platform_data = (void *)&ar2315_led_data,
2568 + }
2569 +};
2570 +
2571 +static void __init
2572 +ar2315_init_gpio_leds(void)
2573 +{
2574 + static char led_names[6][6];
2575 + int i, led = 0;
2576 +
2577 + ar2315_led_data.num_leds = 0;
2578 + for (i = 1; i < 8; i++) {
2579 + if ((i == AR2315_RESET_GPIO) ||
2580 + (i == ar231x_board.config->reset_config_gpio))
2581 + continue;
2582 +
2583 + if (i == ar231x_board.config->sys_led_gpio)
2584 + strcpy(led_names[led], "wlan");
2585 + else
2586 + sprintf(led_names[led], "gpio%d", i);
2587 +
2588 + ar2315_leds[led].name = led_names[led];
2589 + ar2315_leds[led].gpio = i;
2590 + ar2315_leds[led].active_low = 0;
2591 + led++;
2592 + }
2593 + ar2315_led_data.num_leds = led;
2594 + platform_device_register(&ar2315_gpio_leds);
2595 +}
2596 +#else
2597 +static inline void ar2315_init_gpio_leds(void)
2598 +{
2599 +}
2600 +#endif
2601 +
2602 +int __init
2603 +ar2315_init_devices(void)
2604 +{
2605 + if (!is_2315())
2606 + return 0;
2607 +
2608 + /* Find board configuration */
2609 + ar231x_find_config(ar2315_flash_limit());
2610 + ar2315_eth_data.macaddr = ar231x_board.config->enet0_mac;
2611 +
2612 + ar2315_init_gpio_leds();
2613 + platform_device_register(&ar2315_wdt);
2614 + platform_device_register(&ar2315_spiflash);
2615 + ar231x_add_ethernet(0, KSEG1ADDR(AR2315_ENET0), AR2315_IRQ_ENET0_INTRS,
2616 + &ar2315_eth_data);
2617 + ar231x_add_wmac(0, AR2315_WLAN0, AR2315_IRQ_WLAN0_INTRS);
2618 +
2619 + return 0;
2620 +}
2621 +
2622 +static void
2623 +ar2315_restart(char *command)
2624 +{
2625 + void (*mips_reset_vec)(void) = (void *)0xbfc00000;
2626 +
2627 + local_irq_disable();
2628 +
2629 + /* try reset the system via reset control */
2630 + ar231x_write_reg(AR2315_COLD_RESET, AR2317_RESET_SYSTEM);
2631 +
2632 + /* Cold reset does not work on the AR2315/6, use the GPIO reset bits
2633 + * a workaround. Give it some time to attempt a gpio based hardware
2634 + * reset (atheros reference design workaround) */
2635 + gpio_request_one(AR2315_RESET_GPIO, GPIOF_OUT_INIT_LOW, "Reset");
2636 + mdelay(100);
2637 +
2638 + /* Some boards (e.g. Senao EOC-2610) don't implement the reset logic
2639 + * workaround. Attempt to jump to the mips reset location -
2640 + * the boot loader itself might be able to recover the system */
2641 + mips_reset_vec();
2642 +}
2643 +
2644 +
2645 +/*
2646 + * This table is indexed by bits 5..4 of the CLOCKCTL1 register
2647 + * to determine the predevisor value.
2648 + */
2649 +static int clockctl1_predivide_table[4] __initdata = { 1, 2, 4, 5 };
2650 +static int pllc_divide_table[5] __initdata = { 2, 3, 4, 6, 3 };
2651 +
2652 +static unsigned int __init
2653 +ar2315_sys_clk(unsigned int clock_ctl)
2654 +{
2655 + unsigned int pllc_ctrl, cpu_div;
2656 + unsigned int pllc_out, refdiv, fdiv, divby2;
2657 + unsigned int clk_div;
2658 +
2659 + pllc_ctrl = ar231x_read_reg(AR2315_PLLC_CTL);
2660 + refdiv = (pllc_ctrl & PLLC_REF_DIV_M) >> PLLC_REF_DIV_S;
2661 + refdiv = clockctl1_predivide_table[refdiv];
2662 + fdiv = (pllc_ctrl & PLLC_FDBACK_DIV_M) >> PLLC_FDBACK_DIV_S;
2663 + divby2 = (pllc_ctrl & PLLC_ADD_FDBACK_DIV_M) >> PLLC_ADD_FDBACK_DIV_S;
2664 + divby2 += 1;
2665 + pllc_out = (40000000/refdiv)*(2*divby2)*fdiv;
2666 +
2667 + /* clkm input selected */
2668 + switch (clock_ctl & CPUCLK_CLK_SEL_M) {
2669 + case 0:
2670 + case 1:
2671 + clk_div = pllc_divide_table[(pllc_ctrl & PLLC_CLKM_DIV_M) >>
2672 + PLLC_CLKM_DIV_S];
2673 + break;
2674 + case 2:
2675 + clk_div = pllc_divide_table[(pllc_ctrl & PLLC_CLKC_DIV_M) >>
2676 + PLLC_CLKC_DIV_S];
2677 + break;
2678 + default:
2679 + pllc_out = 40000000;
2680 + clk_div = 1;
2681 + break;
2682 + }
2683 +
2684 + cpu_div = (clock_ctl & CPUCLK_CLK_DIV_M) >> CPUCLK_CLK_DIV_S;
2685 + cpu_div = cpu_div * 2 ?: 1;
2686 +
2687 + return pllc_out / (clk_div * cpu_div);
2688 +}
2689 +
2690 +static inline unsigned int
2691 +ar2315_cpu_frequency(void)
2692 +{
2693 + return ar2315_sys_clk(ar231x_read_reg(AR2315_CPUCLK));
2694 +}
2695 +
2696 +static inline unsigned int
2697 +ar2315_apb_frequency(void)
2698 +{
2699 + return ar2315_sys_clk(ar231x_read_reg(AR2315_AMBACLK));
2700 +}
2701 +
2702 +void __init
2703 +ar2315_time_init(void)
2704 +{
2705 + if (!is_2315())
2706 + return;
2707 +
2708 + mips_hpt_frequency = ar2315_cpu_frequency() / 2;
2709 +}
2710 +
2711 +int __init
2712 +ar2315_gpio_init(void)
2713 +{
2714 + int ret;
2715 + struct ar231x_gpio_chip *gpch;
2716 + gpch = &ar2315_gpio_chip;
2717 + ret = gpiochip_add(&gpch->chip);
2718 + if (ret) {
2719 + pr_err("%s: failed to add gpiochip\n", gpch->chip.label);
2720 + return ret;
2721 + }
2722 + pr_info("%s: registered %d GPIOs\n", gpch->chip.label,
2723 + gpch->chip.ngpio);
2724 + return ret;
2725 +}
2726 +
2727 +
2728 +
2729 +void __init
2730 +ar2315_prom_init(void)
2731 +{
2732 + u32 memsize, memcfg, devid;
2733 +
2734 + if (!is_2315())
2735 + return;
2736 +
2737 + memcfg = ar231x_read_reg(AR2315_MEM_CFG);
2738 + memsize = 1 + ((memcfg & SDRAM_DATA_WIDTH_M) >> SDRAM_DATA_WIDTH_S);
2739 + memsize <<= 1 + ((memcfg & SDRAM_COL_WIDTH_M) >> SDRAM_COL_WIDTH_S);
2740 + memsize <<= 1 + ((memcfg & SDRAM_ROW_WIDTH_M) >> SDRAM_ROW_WIDTH_S);
2741 + memsize <<= 3;
2742 + add_memory_region(0, memsize, BOOT_MEM_RAM);
2743 +
2744 + /* Detect the hardware based on the device ID */
2745 + devid = ar231x_read_reg(AR2315_SREV) & AR2315_REV_CHIP;
2746 + switch (devid) {
2747 + case 0x90:
2748 + case 0x91:
2749 + ar231x_devtype = DEV_TYPE_AR2317;
2750 + break;
2751 + default:
2752 + ar231x_devtype = DEV_TYPE_AR2315;
2753 + break;
2754 + }
2755 + ar2315_gpio_init();
2756 + ar231x_board.devid = devid;
2757 +}
2758 +
2759 +void __init
2760 +ar2315_plat_setup(void)
2761 +{
2762 + u32 config;
2763 +
2764 + if (!is_2315())
2765 + return;
2766 +
2767 + /* Clear any lingering AHB errors */
2768 + config = read_c0_config();
2769 + write_c0_config(config & ~0x3);
2770 + ar231x_write_reg(AR2315_AHB_ERR0, AHB_ERROR_DET);
2771 + ar231x_read_reg(AR2315_AHB_ERR1);
2772 + ar231x_write_reg(AR2315_WDC, AR2315_WDC_IGNORE_EXPIRATION);
2773 +
2774 + _machine_restart = ar2315_restart;
2775 + ar231x_serial_setup(KSEG1ADDR(AR2315_UART0), ar2315_apb_frequency());
2776 +}
2777 --- /dev/null
2778 +++ b/arch/mips/ar231x/ar2315.h
2779 @@ -0,0 +1,37 @@
2780 +#ifndef __AR2315_H
2781 +#define __AR2315_H
2782 +
2783 +#ifdef CONFIG_ATHEROS_AR2315
2784 +
2785 +extern void ar2315_irq_init(void);
2786 +extern int ar2315_init_devices(void);
2787 +extern void ar2315_prom_init(void);
2788 +extern void ar2315_plat_setup(void);
2789 +extern void ar2315_time_init(void);
2790 +
2791 +#else
2792 +
2793 +static inline void ar2315_irq_init(void)
2794 +{
2795 +}
2796 +
2797 +static inline int ar2315_init_devices(void)
2798 +{
2799 + return 0;
2800 +}
2801 +
2802 +static inline void ar2315_prom_init(void)
2803 +{
2804 +}
2805 +
2806 +static inline void ar2315_plat_setup(void)
2807 +{
2808 +}
2809 +
2810 +static inline void ar2315_time_init(void)
2811 +{
2812 +}
2813 +
2814 +#endif
2815 +
2816 +#endif
2817 --- /dev/null
2818 +++ b/arch/mips/ar231x/ar5312.h
2819 @@ -0,0 +1,38 @@
2820 +#ifndef __AR5312_H
2821 +#define __AR5312_H
2822 +
2823 +#ifdef CONFIG_ATHEROS_AR5312
2824 +
2825 +extern void ar5312_irq_init(void);
2826 +extern int ar5312_init_devices(void);
2827 +extern void ar5312_prom_init(void);
2828 +extern void ar5312_plat_setup(void);
2829 +extern void ar5312_time_init(void);
2830 +extern void ar5312_time_init(void);
2831 +
2832 +#else
2833 +
2834 +static inline void ar5312_irq_init(void)
2835 +{
2836 +}
2837 +
2838 +static inline int ar5312_init_devices(void)
2839 +{
2840 + return 0;
2841 +}
2842 +
2843 +static inline void ar5312_prom_init(void)
2844 +{
2845 +}
2846 +
2847 +static inline void ar5312_plat_setup(void)
2848 +{
2849 +}
2850 +
2851 +static inline void ar5312_time_init(void)
2852 +{
2853 +}
2854 +
2855 +#endif
2856 +
2857 +#endif
2858 --- /dev/null
2859 +++ b/arch/mips/include/asm/mach-ar231x/ar231x.h
2860 @@ -0,0 +1,57 @@
2861 +#ifndef __AR531X_H
2862 +#define __AR531X_H
2863 +
2864 +#include <linux/types.h>
2865 +#include <linux/io.h>
2866 +
2867 +#define AR531X_MISC_IRQ_BASE 0x20
2868 +#define AR531X_GPIO_IRQ_BASE 0x30
2869 +
2870 +/* Software's idea of interrupts handled by "CPU Interrupt Controller" */
2871 +#define AR531X_IRQ_NONE (MIPS_CPU_IRQ_BASE+0)
2872 +#define AR531X_IRQ_CPU_CLOCK (MIPS_CPU_IRQ_BASE+7) /* C0_CAUSE: 0x8000 */
2873 +
2874 +/* Miscellaneous interrupts, which share IP6 */
2875 +#define AR531X_MISC_IRQ_NONE (AR531X_MISC_IRQ_BASE+0)
2876 +#define AR531X_MISC_IRQ_TIMER (AR531X_MISC_IRQ_BASE+1)
2877 +#define AR531X_MISC_IRQ_AHB_PROC (AR531X_MISC_IRQ_BASE+2)
2878 +#define AR531X_MISC_IRQ_AHB_DMA (AR531X_MISC_IRQ_BASE+3)
2879 +#define AR531X_MISC_IRQ_GPIO (AR531X_MISC_IRQ_BASE+4)
2880 +#define AR531X_MISC_IRQ_UART0 (AR531X_MISC_IRQ_BASE+5)
2881 +#define AR531X_MISC_IRQ_UART0_DMA (AR531X_MISC_IRQ_BASE+6)
2882 +#define AR531X_MISC_IRQ_WATCHDOG (AR531X_MISC_IRQ_BASE+7)
2883 +#define AR531X_MISC_IRQ_LOCAL (AR531X_MISC_IRQ_BASE+8)
2884 +#define AR531X_MISC_IRQ_SPI (AR531X_MISC_IRQ_BASE+9)
2885 +#define AR531X_MISC_IRQ_COUNT 10
2886 +
2887 +/* GPIO Interrupts [0..7], share AR531X_MISC_IRQ_GPIO */
2888 +#define AR531X_GPIO_IRQ_NONE (AR531X_GPIO_IRQ_BASE+0)
2889 +#define AR531X_GPIO_IRQ(n) (AR531X_GPIO_IRQ_BASE+n)
2890 +#define AR531X_GPIO_IRQ_COUNT 22
2891 +
2892 +static inline u32
2893 +ar231x_read_reg(u32 reg)
2894 +{
2895 + return __raw_readl((void __iomem *)KSEG1ADDR(reg));
2896 +}
2897 +
2898 +static inline void
2899 +ar231x_write_reg(u32 reg, u32 val)
2900 +{
2901 + __raw_writel(val, (void __iomem *)KSEG1ADDR(reg));
2902 +}
2903 +
2904 +static inline u32
2905 +ar231x_mask_reg(u32 reg, u32 mask, u32 val)
2906 +{
2907 + u32 ret;
2908 +
2909 + ret = ar231x_read_reg(reg);
2910 + ret &= ~mask;
2911 + ret |= val;
2912 + ar231x_write_reg(reg, ret);
2913 +
2914 + return ret;
2915 +}
2916 +
2917 +#endif
2918 --- /dev/null
2919 +++ b/arch/mips/ar231x/devices.h
2920 @@ -0,0 +1,42 @@
2921 +#ifndef __AR231X_DEVICES_H
2922 +#define __AR231X_DEVICES_H
2923 +#include <linux/gpio.h>
2924 +
2925 +enum {
2926 + /* handled by ar5312.c */
2927 + DEV_TYPE_AR2312,
2928 + DEV_TYPE_AR2313,
2929 + DEV_TYPE_AR5312,
2930 +
2931 + /* handled by ar2315.c */
2932 + DEV_TYPE_AR2315,
2933 + DEV_TYPE_AR2316,
2934 + DEV_TYPE_AR2317,
2935 +
2936 + DEV_TYPE_UNKNOWN
2937 +};
2938 +
2939 +extern int ar231x_devtype;
2940 +extern struct ar231x_board_config ar231x_board;
2941 +extern asmlinkage void (*ar231x_irq_dispatch)(void);
2942 +
2943 +extern int ar231x_find_config(u8 *flash_limit);
2944 +extern void ar231x_serial_setup(u32 mapbase, unsigned int uartclk);
2945 +extern int ar231x_add_wmac(int nr, u32 base, int irq);
2946 +extern int ar231x_add_ethernet(int nr, u32 base, int irq, void *pdata);
2947 +
2948 +static inline bool is_2315(void)
2949 +{
2950 + return (current_cpu_data.cputype == CPU_4KEC);
2951 +}
2952 +
2953 +static inline bool is_5312(void)
2954 +{
2955 + return !is_2315();
2956 +}
2957 +
2958 +struct ar231x_gpio_chip {
2959 + u32 valid_mask;
2960 + struct gpio_chip chip;
2961 +};
2962 +#endif
2963 --- /dev/null
2964 +++ b/arch/mips/ar231x/devices.c
2965 @@ -0,0 +1,168 @@
2966 +#include <linux/kernel.h>
2967 +#include <linux/init.h>
2968 +#include <linux/serial.h>
2969 +#include <linux/serial_core.h>
2970 +#include <linux/serial_8250.h>
2971 +#include <linux/platform_device.h>
2972 +#include <ar231x_platform.h>
2973 +#include <ar231x.h>
2974 +#include "devices.h"
2975 +#include "ar5312.h"
2976 +#include "ar2315.h"
2977 +
2978 +struct ar231x_board_config ar231x_board;
2979 +int ar231x_devtype = DEV_TYPE_UNKNOWN;
2980 +
2981 +static struct resource ar231x_eth0_res[] = {
2982 + {
2983 + .name = "eth0_membase",
2984 + .flags = IORESOURCE_MEM,
2985 + },
2986 + {
2987 + .name = "eth0_irq",
2988 + .flags = IORESOURCE_IRQ,
2989 + }
2990 +};
2991 +
2992 +static struct resource ar231x_eth1_res[] = {
2993 + {
2994 + .name = "eth1_membase",
2995 + .flags = IORESOURCE_MEM,
2996 + },
2997 + {
2998 + .name = "eth1_irq",
2999 + .flags = IORESOURCE_IRQ,
3000 + }
3001 +};
3002 +
3003 +static struct platform_device ar231x_eth[] = {
3004 + {
3005 + .id = 0,
3006 + .name = "ar231x-eth",
3007 + .resource = ar231x_eth0_res,
3008 + .num_resources = ARRAY_SIZE(ar231x_eth0_res)
3009 + },
3010 + {
3011 + .id = 1,
3012 + .name = "ar231x-eth",
3013 + .resource = ar231x_eth1_res,
3014 + .num_resources = ARRAY_SIZE(ar231x_eth1_res)
3015 + }
3016 +};
3017 +
3018 +static struct resource ar231x_wmac0_res[] = {
3019 + {
3020 + .name = "wmac0_membase",
3021 + .flags = IORESOURCE_MEM,
3022 + },
3023 + {
3024 + .name = "wmac0_irq",
3025 + .flags = IORESOURCE_IRQ,
3026 + }
3027 +};
3028 +
3029 +static struct resource ar231x_wmac1_res[] = {
3030 + {
3031 + .name = "wmac1_membase",
3032 + .flags = IORESOURCE_MEM,
3033 + },
3034 + {
3035 + .name = "wmac1_irq",
3036 + .flags = IORESOURCE_IRQ,
3037 + }
3038 +};
3039 +
3040 +
3041 +static struct platform_device ar231x_wmac[] = {
3042 + {
3043 + .id = 0,
3044 + .name = "ar231x-wmac",
3045 + .resource = ar231x_wmac0_res,
3046 + .num_resources = ARRAY_SIZE(ar231x_wmac0_res),
3047 + .dev.platform_data = &ar231x_board,
3048 + },
3049 + {
3050 + .id = 1,
3051 + .name = "ar231x-wmac",
3052 + .resource = ar231x_wmac1_res,
3053 + .num_resources = ARRAY_SIZE(ar231x_wmac1_res),
3054 + .dev.platform_data = &ar231x_board,
3055 + },
3056 +};
3057 +
3058 +static const char * const devtype_strings[] = {
3059 + [DEV_TYPE_AR5312] = "Atheros AR5312",
3060 + [DEV_TYPE_AR2312] = "Atheros AR2312",
3061 + [DEV_TYPE_AR2313] = "Atheros AR2313",
3062 + [DEV_TYPE_AR2315] = "Atheros AR2315",
3063 + [DEV_TYPE_AR2316] = "Atheros AR2316",
3064 + [DEV_TYPE_AR2317] = "Atheros AR2317",
3065 + [DEV_TYPE_UNKNOWN] = "Atheros (unknown)",
3066 +};
3067 +
3068 +const char *get_system_type(void)
3069 +{
3070 + if ((ar231x_devtype >= ARRAY_SIZE(devtype_strings)) ||
3071 + !devtype_strings[ar231x_devtype])
3072 + return devtype_strings[DEV_TYPE_UNKNOWN];
3073 + return devtype_strings[ar231x_devtype];
3074 +}
3075 +
3076 +
3077 +int __init
3078 +ar231x_add_ethernet(int nr, u32 base, int irq, void *pdata)
3079 +{
3080 + struct resource *res;
3081 +
3082 + ar231x_eth[nr].dev.platform_data = pdata;
3083 + res = &ar231x_eth[nr].resource[0];
3084 + res->start = base;
3085 + res->end = base + 0x2000 - 1;
3086 + res++;
3087 + res->start = irq;
3088 + res->end = irq;
3089 + return platform_device_register(&ar231x_eth[nr]);
3090 +}
3091 +
3092 +void __init
3093 +ar231x_serial_setup(u32 mapbase, unsigned int uartclk)
3094 +{
3095 + struct uart_port s;
3096 +
3097 + memset(&s, 0, sizeof(s));
3098 +
3099 + s.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
3100 + s.iotype = UPIO_MEM;
3101 + s.irq = AR531X_MISC_IRQ_UART0;
3102 + s.regshift = 2;
3103 + s.mapbase = mapbase;
3104 + s.uartclk = uartclk;
3105 + s.membase = (void __iomem *)s.mapbase;
3106 +
3107 + early_serial_setup(&s);
3108 +}
3109 +
3110 +int __init
3111 +ar231x_add_wmac(int nr, u32 base, int irq)
3112 +{
3113 + struct resource *res;
3114 +
3115 + ar231x_wmac[nr].dev.platform_data = &ar231x_board;
3116 + res = &ar231x_wmac[nr].resource[0];
3117 + res->start = base;
3118 + res->end = base + 0x10000 - 1;
3119 + res++;
3120 + res->start = irq;
3121 + res->end = irq;
3122 + return platform_device_register(&ar231x_wmac[nr]);
3123 +}
3124 +
3125 +static int __init ar231x_register_devices(void)
3126 +{
3127 + ar5312_init_devices();
3128 + ar2315_init_devices();
3129 +
3130 + return 0;
3131 +}
3132 +
3133 +device_initcall(ar231x_register_devices);
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