atheros[ar2315-spiflash]: print detected flash size
[openwrt/svn-archive/archive.git] / target / linux / atheros / patches-3.10 / 100-board.patch
1 --- a/arch/mips/Kconfig
2 +++ b/arch/mips/Kconfig
3 @@ -138,6 +138,19 @@ config BCM63XX
4 help
5 Support for BCM63XX based boards
6
7 +config ATHEROS_AR231X
8 + bool "Atheros 231x/531x SoC support"
9 + select CEVT_R4K
10 + select CSRC_R4K
11 + select DMA_NONCOHERENT
12 + select IRQ_CPU
13 + select SYS_HAS_CPU_MIPS32_R1
14 + select SYS_SUPPORTS_BIG_ENDIAN
15 + select SYS_SUPPORTS_32BIT_KERNEL
16 + select ARCH_REQUIRE_GPIOLIB
17 + help
18 + Support for AR231x and AR531x based boards
19 +
20 config MIPS_COBALT
21 bool "Cobalt Server"
22 select CEVT_R4K
23 @@ -838,6 +851,7 @@ config NLM_XLP_BOARD
24
25 endchoice
26
27 +source "arch/mips/ar231x/Kconfig"
28 source "arch/mips/alchemy/Kconfig"
29 source "arch/mips/ath79/Kconfig"
30 source "arch/mips/bcm47xx/Kconfig"
31 --- a/arch/mips/Kbuild.platforms
32 +++ b/arch/mips/Kbuild.platforms
33 @@ -6,6 +6,7 @@ platforms += ath79
34 platforms += bcm47xx
35 platforms += bcm63xx
36 platforms += cavium-octeon
37 +platforms += ar231x
38 platforms += cobalt
39 platforms += dec
40 platforms += emma
41 --- /dev/null
42 +++ b/arch/mips/ar231x/Platform
43 @@ -0,0 +1,6 @@
44 +#
45 +# Atheros AR5312/AR2312 WiSoC
46 +#
47 +platform-$(CONFIG_ATHEROS_AR231X) += ar231x/
48 +cflags-$(CONFIG_ATHEROS_AR231X) += -I$(srctree)/arch/mips/include/asm/mach-ar231x
49 +load-$(CONFIG_ATHEROS_AR231X) += 0xffffffff80041000
50 --- /dev/null
51 +++ b/arch/mips/ar231x/Kconfig
52 @@ -0,0 +1,16 @@
53 +config ATHEROS_AR5312
54 + bool "Atheros 5312/2312+ support"
55 + depends on ATHEROS_AR231X
56 + default y
57 +
58 +config ATHEROS_AR2315
59 + bool "Atheros 2315+ support"
60 + depends on ATHEROS_AR231X
61 + select DMA_NONCOHERENT
62 + select CEVT_R4K
63 + select CSRC_R4K
64 + select IRQ_CPU
65 + select SYS_HAS_CPU_MIPS32_R1
66 + select SYS_SUPPORTS_32BIT_KERNEL
67 + select SYS_SUPPORTS_BIG_ENDIAN
68 + default y
69 --- /dev/null
70 +++ b/arch/mips/ar231x/Makefile
71 @@ -0,0 +1,13 @@
72 +#
73 +# This file is subject to the terms and conditions of the GNU General Public
74 +# License. See the file "COPYING" in the main directory of this archive
75 +# for more details.
76 +#
77 +# Copyright (C) 2006 FON Technology, SL.
78 +# Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
79 +# Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
80 +#
81 +
82 +obj-y += board.o prom.o devices.o
83 +obj-$(CONFIG_ATHEROS_AR5312) += ar5312.o
84 +obj-$(CONFIG_ATHEROS_AR2315) += ar2315.o
85 --- /dev/null
86 +++ b/arch/mips/ar231x/board.c
87 @@ -0,0 +1,261 @@
88 +/*
89 + * This file is subject to the terms and conditions of the GNU General Public
90 + * License. See the file "COPYING" in the main directory of this archive
91 + * for more details.
92 + *
93 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
94 + * Copyright (C) 2006 FON Technology, SL.
95 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
96 + * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
97 + */
98 +
99 +#include <generated/autoconf.h>
100 +#include <linux/init.h>
101 +#include <linux/module.h>
102 +#include <linux/types.h>
103 +#include <linux/string.h>
104 +#include <linux/platform_device.h>
105 +#include <linux/kernel.h>
106 +#include <linux/random.h>
107 +#include <linux/etherdevice.h>
108 +#include <linux/irq.h>
109 +#include <linux/io.h>
110 +#include <asm/irq_cpu.h>
111 +#include <asm/reboot.h>
112 +
113 +#include <ar231x_platform.h>
114 +#include "devices.h"
115 +#include "ar5312.h"
116 +#include "ar2315.h"
117 +
118 +void (*ar231x_irq_dispatch)(void);
119 +
120 +static inline bool
121 +check_radio_magic(u8 *addr)
122 +{
123 + addr += 0x7a; /* offset for flash magic */
124 + if ((addr[0] == 0x5a) && (addr[1] == 0xa5))
125 + return 1;
126 +
127 + return 0;
128 +}
129 +
130 +static inline bool
131 +check_board_data(u8 *flash_limit, u8 *addr, bool broken)
132 +{
133 + /* config magic found */
134 + if (*((u32 *)addr) == AR531X_BD_MAGIC)
135 + return 1;
136 +
137 + if (!broken)
138 + return 0;
139 +
140 + if (check_radio_magic(addr + 0xf8))
141 + ar231x_board.radio = addr + 0xf8;
142 + if ((addr < flash_limit + 0x10000) &&
143 + check_radio_magic(addr + 0x10000))
144 + ar231x_board.radio = addr + 0x10000;
145 +
146 + if (ar231x_board.radio) {
147 + /* broken board data detected, use radio data to find the
148 + * offset, user will fix this */
149 + return 1;
150 + }
151 + return 0;
152 +}
153 +
154 +static u8 *
155 +find_board_config(u8 *flash_limit, bool broken)
156 +{
157 + u8 *addr;
158 + int found = 0;
159 +
160 + for (addr = flash_limit - 0x1000;
161 + addr >= flash_limit - 0x30000;
162 + addr -= 0x1000) {
163 +
164 + if (check_board_data(flash_limit, addr, broken)) {
165 + found = 1;
166 + break;
167 + }
168 + }
169 +
170 + if (!found)
171 + addr = NULL;
172 +
173 + return addr;
174 +}
175 +
176 +static u8 *
177 +find_radio_config(u8 *flash_limit, u8 *board_config)
178 +{
179 + int found;
180 + u8 *radio_config;
181 +
182 + /*
183 + * Now find the start of Radio Configuration data, using heuristics:
184 + * Search forward from Board Configuration data by 0x1000 bytes
185 + * at a time until we find non-0xffffffff.
186 + */
187 + found = 0;
188 + for (radio_config = board_config + 0x1000;
189 + (radio_config < flash_limit);
190 + radio_config += 0x1000) {
191 + if ((*(u32 *)radio_config != 0xffffffff) &&
192 + check_radio_magic(radio_config)) {
193 + found = 1;
194 + break;
195 + }
196 + }
197 +
198 + /* AR2316 relocates radio config to new location */
199 + if (!found) {
200 + for (radio_config = board_config + 0xf8;
201 + (radio_config < flash_limit - 0x1000 + 0xf8);
202 + radio_config += 0x1000) {
203 + if ((*(u32 *)radio_config != 0xffffffff) &&
204 + check_radio_magic(radio_config)) {
205 + found = 1;
206 + break;
207 + }
208 + }
209 + }
210 +
211 + if (!found) {
212 + pr_warn("WARNING: Could not find Radio Configuration data\n");
213 + radio_config = 0;
214 + }
215 +
216 + return radio_config;
217 +}
218 +
219 +int __init
220 +ar231x_find_config(u8 *flash_limit)
221 +{
222 + struct ar231x_boarddata *config;
223 + unsigned int rcfg_size;
224 + int broken_boarddata = 0;
225 + u8 *bcfg, *rcfg;
226 + u8 *board_data;
227 + u8 *radio_data;
228 + u8 *mac_addr;
229 + u32 offset;
230 +
231 + ar231x_board.config = NULL;
232 + ar231x_board.radio = NULL;
233 + /* Copy the board and radio data to RAM, because accessing the mapped
234 + * memory of the flash directly after booting is not safe */
235 +
236 + /* Try to find valid board and radio data */
237 + bcfg = find_board_config(flash_limit, false);
238 +
239 + /* If that fails, try to at least find valid radio data */
240 + if (!bcfg) {
241 + bcfg = find_board_config(flash_limit, true);
242 + broken_boarddata = 1;
243 + }
244 +
245 + if (!bcfg) {
246 + pr_warn("WARNING: No board configuration data found!\n");
247 + return -ENODEV;
248 + }
249 +
250 + board_data = kzalloc(BOARD_CONFIG_BUFSZ, GFP_KERNEL);
251 + ar231x_board.config = (struct ar231x_boarddata *)board_data;
252 + memcpy(board_data, bcfg, 0x100);
253 + if (broken_boarddata) {
254 + pr_warn("WARNING: broken board data detected\n");
255 + config = ar231x_board.config;
256 + if (!memcmp(config->enet0_mac, "\x00\x00\x00\x00\x00\x00", 6)) {
257 + pr_info("Fixing up empty mac addresses\n");
258 + config->reset_config_gpio = 0xffff;
259 + config->sys_led_gpio = 0xffff;
260 + random_ether_addr(config->wlan0_mac);
261 + config->wlan0_mac[0] &= ~0x06;
262 + random_ether_addr(config->enet0_mac);
263 + random_ether_addr(config->enet1_mac);
264 + }
265 + }
266 +
267 +
268 + /* Radio config starts 0x100 bytes after board config, regardless
269 + * of what the physical layout on the flash chip looks like */
270 +
271 + if (ar231x_board.radio)
272 + rcfg = (u8 *)ar231x_board.radio;
273 + else
274 + rcfg = find_radio_config(flash_limit, bcfg);
275 +
276 + if (!rcfg)
277 + return -ENODEV;
278 +
279 + radio_data = board_data + 0x100 + ((rcfg - bcfg) & 0xfff);
280 + ar231x_board.radio = radio_data;
281 + offset = radio_data - board_data;
282 + pr_info("Radio config found at offset 0x%x (0x%x)\n", rcfg - bcfg,
283 + offset);
284 + rcfg_size = BOARD_CONFIG_BUFSZ - offset;
285 + memcpy(radio_data, rcfg, rcfg_size);
286 +
287 + mac_addr = &radio_data[0x1d * 2];
288 + if (is_broadcast_ether_addr(mac_addr)) {
289 + pr_info("Radio MAC is blank; using board-data\n");
290 + memcpy(mac_addr, ar231x_board.config->wlan0_mac, ETH_ALEN);
291 + }
292 +
293 + return 0;
294 +}
295 +
296 +static void
297 +ar231x_halt(void)
298 +{
299 + local_irq_disable();
300 + while (1)
301 + ;
302 +}
303 +
304 +void __init
305 +plat_mem_setup(void)
306 +{
307 + _machine_halt = ar231x_halt;
308 + pm_power_off = ar231x_halt;
309 +
310 + ar5312_plat_setup();
311 + ar2315_plat_setup();
312 +
313 + /* Disable data watchpoints */
314 + write_c0_watchlo0(0);
315 +}
316 +
317 +
318 +asmlinkage void
319 +plat_irq_dispatch(void)
320 +{
321 + ar231x_irq_dispatch();
322 +}
323 +
324 +void __init
325 +plat_time_init(void)
326 +{
327 + ar5312_time_init();
328 + ar2315_time_init();
329 +}
330 +
331 +unsigned int __cpuinit
332 +get_c0_compare_int(void)
333 +{
334 + return CP0_LEGACY_COMPARE_IRQ;
335 +}
336 +
337 +void __init
338 +arch_init_irq(void)
339 +{
340 + clear_c0_status(ST0_IM);
341 + mips_cpu_irq_init();
342 +
343 + /* Initialize interrupt controllers */
344 + ar5312_irq_init();
345 + ar2315_irq_init();
346 +}
347 +
348 +
349 --- /dev/null
350 +++ b/arch/mips/ar231x/prom.c
351 @@ -0,0 +1,37 @@
352 +/*
353 + * This file is subject to the terms and conditions of the GNU General Public
354 + * License. See the file "COPYING" in the main directory of this archive
355 + * for more details.
356 + *
357 + * Copyright MontaVista Software Inc
358 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
359 + * Copyright (C) 2006 FON Technology, SL.
360 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
361 + * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
362 + */
363 +
364 +/*
365 + * Prom setup file for ar531x
366 + */
367 +
368 +#include <linux/init.h>
369 +#include <generated/autoconf.h>
370 +#include <linux/kernel.h>
371 +#include <linux/string.h>
372 +#include <linux/mm.h>
373 +#include <linux/bootmem.h>
374 +
375 +#include <asm/bootinfo.h>
376 +#include <asm/addrspace.h>
377 +#include "ar5312.h"
378 +#include "ar2315.h"
379 +
380 +void __init prom_init(void)
381 +{
382 + ar5312_prom_init();
383 + ar2315_prom_init();
384 +}
385 +
386 +void __init prom_free_prom_memory(void)
387 +{
388 +}
389 --- /dev/null
390 +++ b/arch/mips/include/asm/mach-ar231x/ar231x_platform.h
391 @@ -0,0 +1,83 @@
392 +#ifndef __AR531X_PLATFORM_H
393 +#define __AR531X_PLATFORM_H
394 +
395 +/*
396 + * This is board-specific data that is stored in a "fixed" location in flash.
397 + * It is shared across operating systems, so it should not be changed lightly.
398 + * The main reason we need it is in order to extract the ethernet MAC
399 + * address(es).
400 + */
401 +struct ar231x_boarddata {
402 + u32 magic; /* board data is valid */
403 +#define AR531X_BD_MAGIC 0x35333131 /* "5311", for all 531x platforms */
404 + u16 cksum; /* checksum (starting with BD_REV 2) */
405 + u16 rev; /* revision of this struct */
406 +#define BD_REV 4
407 + char board_name[64]; /* Name of board */
408 + u16 major; /* Board major number */
409 + u16 minor; /* Board minor number */
410 + u32 flags; /* Board configuration */
411 +#define BD_ENET0 0x00000001 /* ENET0 is stuffed */
412 +#define BD_ENET1 0x00000002 /* ENET1 is stuffed */
413 +#define BD_UART1 0x00000004 /* UART1 is stuffed */
414 +#define BD_UART0 0x00000008 /* UART0 is stuffed (dma) */
415 +#define BD_RSTFACTORY 0x00000010 /* Reset factory defaults stuffed */
416 +#define BD_SYSLED 0x00000020 /* System LED stuffed */
417 +#define BD_EXTUARTCLK 0x00000040 /* External UART clock */
418 +#define BD_CPUFREQ 0x00000080 /* cpu freq is valid in nvram */
419 +#define BD_SYSFREQ 0x00000100 /* sys freq is set in nvram */
420 +#define BD_WLAN0 0x00000200 /* Enable WLAN0 */
421 +#define BD_MEMCAP 0x00000400 /* CAP SDRAM @ mem_cap for testing */
422 +#define BD_DISWATCHDOG 0x00000800 /* disable system watchdog */
423 +#define BD_WLAN1 0x00001000 /* Enable WLAN1 (ar5212) */
424 +#define BD_ISCASPER 0x00002000 /* FLAG for AR2312 */
425 +#define BD_WLAN0_2G_EN 0x00004000 /* FLAG for radio0_2G */
426 +#define BD_WLAN0_5G_EN 0x00008000 /* FLAG for radio0_2G */
427 +#define BD_WLAN1_2G_EN 0x00020000 /* FLAG for radio0_2G */
428 +#define BD_WLAN1_5G_EN 0x00040000 /* FLAG for radio0_2G */
429 + u16 reset_config_gpio; /* Reset factory GPIO pin */
430 + u16 sys_led_gpio; /* System LED GPIO pin */
431 +
432 + u32 cpu_freq; /* CPU core frequency in Hz */
433 + u32 sys_freq; /* System frequency in Hz */
434 + u32 cnt_freq; /* Calculated C0_COUNT frequency */
435 +
436 + u8 wlan0_mac[6];
437 + u8 enet0_mac[6];
438 + u8 enet1_mac[6];
439 +
440 + u16 pci_id; /* Pseudo PCIID for common code */
441 + u16 mem_cap; /* cap bank1 in MB */
442 +
443 + /* version 3 */
444 + u8 wlan1_mac[6]; /* (ar5212) */
445 +};
446 +
447 +#define BOARD_CONFIG_BUFSZ 0x1000
448 +
449 +/*
450 + * Platform device information for the Wireless MAC
451 + */
452 +struct ar231x_board_config {
453 + u16 devid;
454 +
455 + /* board config data */
456 + struct ar231x_boarddata *config;
457 +
458 + /* radio calibration data */
459 + const char *radio;
460 +};
461 +
462 +/*
463 + * Platform device information for the Ethernet MAC
464 + */
465 +struct ar231x_eth {
466 + u32 reset_base;
467 + u32 reset_mac;
468 + u32 reset_phy;
469 + u32 phy_base;
470 + struct ar231x_board_config *config;
471 + char *macaddr;
472 +};
473 +
474 +#endif /* __AR531X_PLATFORM_H */
475 --- /dev/null
476 +++ b/arch/mips/include/asm/mach-ar231x/cpu-feature-overrides.h
477 @@ -0,0 +1,84 @@
478 +/*
479 + * Atheros SoC specific CPU feature overrides
480 + *
481 + * Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
482 + *
483 + * This file was derived from: include/asm-mips/cpu-features.h
484 + * Copyright (C) 2003, 2004 Ralf Baechle
485 + * Copyright (C) 2004 Maciej W. Rozycki
486 + *
487 + * This program is free software; you can redistribute it and/or modify it
488 + * under the terms of the GNU General Public License version 2 as published
489 + * by the Free Software Foundation.
490 + *
491 + */
492 +#ifndef __ASM_MACH_ATHEROS_CPU_FEATURE_OVERRIDES_H
493 +#define __ASM_MACH_ATHEROS_CPU_FEATURE_OVERRIDES_H
494 +
495 +/*
496 + * The ATHEROS SoCs have MIPS 4Kc/4KEc core.
497 + */
498 +#define cpu_has_tlb 1
499 +#define cpu_has_4kex 1
500 +#define cpu_has_3k_cache 0
501 +#define cpu_has_4k_cache 1
502 +#define cpu_has_tx39_cache 0
503 +#define cpu_has_sb1_cache 0
504 +#define cpu_has_fpu 0
505 +#define cpu_has_32fpr 0
506 +#define cpu_has_counter 1
507 +/* #define cpu_has_watch ? */
508 +/* #define cpu_has_divec ? */
509 +/* #define cpu_has_vce ? */
510 +/* #define cpu_has_cache_cdex_p ? */
511 +/* #define cpu_has_cache_cdex_s ? */
512 +/* #define cpu_has_prefetch ? */
513 +/* #define cpu_has_mcheck ? */
514 +#define cpu_has_ejtag 1
515 +
516 +#if !defined(CONFIG_ATHEROS_AR5312)
517 +# define cpu_has_llsc 1
518 +#else
519 +/*
520 + * The MIPS 4Kc V0.9 core in the AR5312/AR2312 have problems with the
521 + * ll/sc instructions.
522 + */
523 +# define cpu_has_llsc 0
524 +#endif
525 +
526 +#define cpu_has_mips16 0
527 +#define cpu_has_mdmx 0
528 +#define cpu_has_mips3d 0
529 +#define cpu_has_smartmips 0
530 +
531 +/* #define cpu_has_vtag_icache ? */
532 +/* #define cpu_has_dc_aliases ? */
533 +/* #define cpu_has_ic_fills_f_dc ? */
534 +/* #define cpu_has_pindexed_dcache ? */
535 +
536 +/* #define cpu_icache_snoops_remote_store ? */
537 +
538 +#define cpu_has_mips32r1 1
539 +
540 +#if !defined(CONFIG_ATHEROS_AR5312)
541 +# define cpu_has_mips32r2 1
542 +#endif
543 +
544 +#define cpu_has_mips64r1 0
545 +#define cpu_has_mips64r2 0
546 +
547 +#define cpu_has_dsp 0
548 +#define cpu_has_mipsmt 0
549 +
550 +/* #define cpu_has_nofpuex ? */
551 +#define cpu_has_64bits 0
552 +#define cpu_has_64bit_zero_reg 0
553 +#define cpu_has_64bit_gp_regs 0
554 +#define cpu_has_64bit_addresses 0
555 +
556 +/* #define cpu_has_inclusive_pcaches ? */
557 +
558 +/* #define cpu_dcache_line_size() ? */
559 +/* #define cpu_icache_line_size() ? */
560 +
561 +#endif /* __ASM_MACH_ATHEROS_CPU_FEATURE_OVERRIDES_H */
562 --- /dev/null
563 +++ b/arch/mips/include/asm/mach-ar231x/dma-coherence.h
564 @@ -0,0 +1,79 @@
565 +/*
566 + * This file is subject to the terms and conditions of the GNU General Public
567 + * License. See the file "COPYING" in the main directory of this archive
568 + * for more details.
569 + *
570 + * Copyright (C) 2006 Ralf Baechle <ralf@linux-mips.org>
571 + * Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
572 + *
573 + */
574 +#ifndef __ASM_MACH_GENERIC_DMA_COHERENCE_H
575 +#define __ASM_MACH_GENERIC_DMA_COHERENCE_H
576 +
577 +#define PCI_DMA_OFFSET 0x20000000
578 +
579 +#include <linux/device.h>
580 +
581 +static inline dma_addr_t ar231x_dev_offset(struct device *dev)
582 +{
583 +#ifdef CONFIG_PCI
584 + extern struct bus_type pci_bus_type;
585 +
586 + if (dev && dev->bus == &pci_bus_type)
587 + return PCI_DMA_OFFSET;
588 + else
589 +#endif
590 + return 0;
591 +}
592 +
593 +static inline dma_addr_t
594 +plat_map_dma_mem(struct device *dev, void *addr, size_t size)
595 +{
596 + return virt_to_phys(addr) + ar231x_dev_offset(dev);
597 +}
598 +
599 +static inline dma_addr_t
600 +plat_map_dma_mem_page(struct device *dev, struct page *page)
601 +{
602 + return page_to_phys(page) + ar231x_dev_offset(dev);
603 +}
604 +
605 +static inline unsigned long
606 +plat_dma_addr_to_phys(struct device *dev, dma_addr_t dma_addr)
607 +{
608 + return dma_addr - ar231x_dev_offset(dev);
609 +}
610 +
611 +static inline void
612 +plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr, size_t size,
613 + enum dma_data_direction direction)
614 +{
615 +}
616 +
617 +static inline int plat_dma_supported(struct device *dev, u64 mask)
618 +{
619 + return 1;
620 +}
621 +
622 +static inline void plat_extra_sync_for_device(struct device *dev)
623 +{
624 + return;
625 +}
626 +
627 +static inline int plat_dma_mapping_error(struct device *dev,
628 + dma_addr_t dma_addr)
629 +{
630 + return 0;
631 +}
632 +
633 +static inline int plat_device_is_coherent(struct device *dev)
634 +{
635 +#ifdef CONFIG_DMA_COHERENT
636 + return 1;
637 +#endif
638 +#ifdef CONFIG_DMA_NONCOHERENT
639 + return 0;
640 +#endif
641 +}
642 +
643 +#endif /* __ASM_MACH_GENERIC_DMA_COHERENCE_H */
644 --- /dev/null
645 +++ b/arch/mips/include/asm/mach-ar231x/gpio.h
646 @@ -0,0 +1,30 @@
647 +#ifndef _ATHEROS_GPIO_H_
648 +#define _ATHEROS_GPIO_H_
649 +
650 +#include <ar231x.h>
651 +
652 +#define gpio_get_value __gpio_get_value
653 +#define gpio_set_value __gpio_set_value
654 +#define gpio_cansleep __gpio_cansleep
655 +
656 +/*
657 + * Wrappers for the generic GPIO layer
658 + */
659 +
660 +/* not sure if these are used? */
661 +
662 +/* Returns IRQ to attach for gpio. Unchecked function */
663 +static inline int gpio_to_irq(unsigned gpio)
664 +{
665 + return AR531X_GPIO_IRQ(gpio);
666 +}
667 +
668 +/* Returns gpio for IRQ attached. Unchecked function */
669 +static inline int irq_to_gpio(unsigned irq)
670 +{
671 + return irq - AR531X_GPIO_IRQ(0);
672 +}
673 +
674 +#include <asm-generic/gpio.h> /* cansleep wrappers */
675 +
676 +#endif
677 --- /dev/null
678 +++ b/arch/mips/include/asm/mach-ar231x/reset.h
679 @@ -0,0 +1,6 @@
680 +#ifndef __AR531X_RESET_H
681 +#define __AR531X_RESET_H
682 +
683 +void ar531x_disable_reset_button(void);
684 +
685 +#endif /* __AR531X_RESET_H */
686 --- /dev/null
687 +++ b/arch/mips/include/asm/mach-ar231x/war.h
688 @@ -0,0 +1,25 @@
689 +/*
690 + * This file is subject to the terms and conditions of the GNU General Public
691 + * License. See the file "COPYING" in the main directory of this archive
692 + * for more details.
693 + *
694 + * Copyright (C) 2008 Felix Fietkau <nbd@openwrt.org>
695 + */
696 +#ifndef __ASM_MIPS_MACH_ATHEROS_WAR_H
697 +#define __ASM_MIPS_MACH_ATHEROS_WAR_H
698 +
699 +#define R4600_V1_INDEX_ICACHEOP_WAR 0
700 +#define R4600_V1_HIT_CACHEOP_WAR 0
701 +#define R4600_V2_HIT_CACHEOP_WAR 0
702 +#define R5432_CP0_INTERRUPT_WAR 0
703 +#define BCM1250_M3_WAR 0
704 +#define SIBYTE_1956_WAR 0
705 +#define MIPS4K_ICACHE_REFILL_WAR 0
706 +#define MIPS_CACHE_SYNC_WAR 0
707 +#define TX49XX_ICACHE_INDEX_INV_WAR 0
708 +#define RM9000_CDEX_SMP_WAR 0
709 +#define ICACHE_REFILLS_WORKAROUND_WAR 0
710 +#define R10000_LLSC_WAR 0
711 +#define MIPS34K_MISSED_ITLB_WAR 0
712 +
713 +#endif /* __ASM_MIPS_MACH_ATHEROS_WAR_H */
714 --- /dev/null
715 +++ b/arch/mips/include/asm/mach-ar231x/ar2315_regs.h
716 @@ -0,0 +1,615 @@
717 +/*
718 + * Register definitions for AR2315+
719 + *
720 + * This file is subject to the terms and conditions of the GNU General Public
721 + * License. See the file "COPYING" in the main directory of this archive
722 + * for more details.
723 + *
724 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
725 + * Copyright (C) 2006 FON Technology, SL.
726 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
727 + * Copyright (C) 2006-2008 Felix Fietkau <nbd@openwrt.org>
728 + */
729 +
730 +#ifndef __AR2315_REG_H
731 +#define __AR2315_REG_H
732 +
733 +/*
734 + * IRQs
735 + */
736 +#define AR2315_IRQ_MISC_INTRS (MIPS_CPU_IRQ_BASE+2) /* C0_CAUSE: 0x0400 */
737 +#define AR2315_IRQ_WLAN0_INTRS (MIPS_CPU_IRQ_BASE+3) /* C0_CAUSE: 0x0800 */
738 +#define AR2315_IRQ_ENET0_INTRS (MIPS_CPU_IRQ_BASE+4) /* C0_CAUSE: 0x1000 */
739 +#define AR2315_IRQ_LCBUS_PCI (MIPS_CPU_IRQ_BASE+5) /* C0_CAUSE: 0x2000 */
740 +#define AR2315_IRQ_WLAN0_POLL (MIPS_CPU_IRQ_BASE+6) /* C0_CAUSE: 0x4000 */
741 +
742 +/*
743 + * Address map
744 + */
745 +#define AR2315_SPI_READ 0x08000000 /* SPI FLASH */
746 +#define AR2315_WLAN0 0x10000000 /* Wireless MMR */
747 +#define AR2315_PCI 0x10100000 /* PCI MMR */
748 +#define AR2315_SDRAMCTL 0x10300000 /* SDRAM MMR */
749 +#define AR2315_LOCAL 0x10400000 /* LOCAL BUS MMR */
750 +#define AR2315_ENET0 0x10500000 /* ETHERNET MMR */
751 +#define AR2315_DSLBASE 0x11000000 /* RESET CONTROL MMR */
752 +#define AR2315_UART0 0x11100003 /* UART MMR */
753 +#define AR2315_SPI 0x11300000 /* SPI FLASH MMR */
754 +#define AR2315_PCIEXT 0x80000000 /* pci external */
755 +
756 +/*
757 + * Reset Register
758 + */
759 +#define AR2315_COLD_RESET (AR2315_DSLBASE + 0x0000)
760 +
761 +#define AR2315_RESET_COLD_AHB 0x00000001
762 +#define AR2315_RESET_COLD_APB 0x00000002
763 +#define AR2315_RESET_COLD_CPU 0x00000004
764 +#define AR2315_RESET_COLD_CPUWARM 0x00000008
765 +#define AR2315_RESET_SYSTEM \
766 + (RESET_COLD_CPU |\
767 + RESET_COLD_APB |\
768 + RESET_COLD_AHB) /* full system */
769 +#define AR2317_RESET_SYSTEM 0x00000010
770 +
771 +
772 +#define AR2315_RESET (AR2315_DSLBASE + 0x0004)
773 +
774 +/* warm reset WLAN0 MAC */
775 +#define AR2315_RESET_WARM_WLAN0_MAC 0x00000001
776 +/* warm reset WLAN0 BaseBand */
777 +#define AR2315_RESET_WARM_WLAN0_BB 0x00000002
778 +/* warm reset MPEG-TS */
779 +#define AR2315_RESET_MPEGTS_RSVD 0x00000004
780 +/* warm reset PCI ahb/dma */
781 +#define AR2315_RESET_PCIDMA 0x00000008
782 +/* warm reset memory controller */
783 +#define AR2315_RESET_MEMCTL 0x00000010
784 +/* warm reset local bus */
785 +#define AR2315_RESET_LOCAL 0x00000020
786 +/* warm reset I2C bus */
787 +#define AR2315_RESET_I2C_RSVD 0x00000040
788 +/* warm reset SPI interface */
789 +#define AR2315_RESET_SPI 0x00000080
790 +/* warm reset UART0 */
791 +#define AR2315_RESET_UART0 0x00000100
792 +/* warm reset IR interface */
793 +#define AR2315_RESET_IR_RSVD 0x00000200
794 +/* cold reset ENET0 phy */
795 +#define AR2315_RESET_EPHY0 0x00000400
796 +/* cold reset ENET0 mac */
797 +#define AR2315_RESET_ENET0 0x00000800
798 +
799 +/*
800 + * AHB master arbitration control
801 + */
802 +#define AR2315_AHB_ARB_CTL (AR2315_DSLBASE + 0x0008)
803 +
804 +/* CPU, default */
805 +#define AR2315_ARB_CPU 0x00000001
806 +/* WLAN */
807 +#define AR2315_ARB_WLAN 0x00000002
808 +/* MPEG-TS */
809 +#define AR2315_ARB_MPEGTS_RSVD 0x00000004
810 +/* LOCAL */
811 +#define AR2315_ARB_LOCAL 0x00000008
812 +/* PCI */
813 +#define AR2315_ARB_PCI 0x00000010
814 +/* Ethernet */
815 +#define AR2315_ARB_ETHERNET 0x00000020
816 +/* retry policy, debug only */
817 +#define AR2315_ARB_RETRY 0x00000100
818 +
819 +/*
820 + * Config Register
821 + */
822 +#define AR2315_ENDIAN_CTL (AR2315_DSLBASE + 0x000c)
823 +
824 +/* EC - AHB bridge endianess */
825 +#define AR2315_CONFIG_AHB 0x00000001
826 +/* WLAN byteswap */
827 +#define AR2315_CONFIG_WLAN 0x00000002
828 +/* MPEG-TS byteswap */
829 +#define AR2315_CONFIG_MPEGTS_RSVD 0x00000004
830 +/* PCI byteswap */
831 +#define AR2315_CONFIG_PCI 0x00000008
832 +/* Memory controller endianess */
833 +#define AR2315_CONFIG_MEMCTL 0x00000010
834 +/* Local bus byteswap */
835 +#define AR2315_CONFIG_LOCAL 0x00000020
836 +/* Ethernet byteswap */
837 +#define AR2315_CONFIG_ETHERNET 0x00000040
838 +
839 +/* CPU write buffer merge */
840 +#define AR2315_CONFIG_MERGE 0x00000200
841 +/* CPU big endian */
842 +#define AR2315_CONFIG_CPU 0x00000400
843 +#define AR2315_CONFIG_PCIAHB 0x00000800
844 +#define AR2315_CONFIG_PCIAHB_BRIDGE 0x00001000
845 +/* SPI byteswap */
846 +#define AR2315_CONFIG_SPI 0x00008000
847 +#define AR2315_CONFIG_CPU_DRAM 0x00010000
848 +#define AR2315_CONFIG_CPU_PCI 0x00020000
849 +#define AR2315_CONFIG_CPU_MMR 0x00040000
850 +#define AR2315_CONFIG_BIG 0x00000400
851 +
852 +
853 +/*
854 + * NMI control
855 + */
856 +#define AR2315_NMI_CTL (AR2315_DSLBASE + 0x0010)
857 +
858 +#define AR2315_NMI_EN 1
859 +
860 +/*
861 + * Revision Register - Initial value is 0x3010 (WMAC 3.0, AR531X 1.0).
862 + */
863 +#define AR2315_SREV (AR2315_DSLBASE + 0x0014)
864 +
865 +#define AR2315_REV_MAJ 0x00f0
866 +#define AR2315_REV_MAJ_S 4
867 +#define AR2315_REV_MIN 0x000f
868 +#define AR2315_REV_MIN_S 0
869 +#define AR2315_REV_CHIP (AR2315_REV_MAJ|AR2315_REV_MIN)
870 +
871 +/*
872 + * Interface Enable
873 + */
874 +#define AR2315_IF_CTL (AR2315_DSLBASE + 0x0018)
875 +
876 +#define AR2315_IF_MASK 0x00000007
877 +#define AR2315_IF_DISABLED 0
878 +#define AR2315_IF_PCI 1
879 +#define AR2315_IF_TS_LOCAL 2
880 +/* only for emulation with separate pins */
881 +#define AR2315_IF_ALL 3
882 +#define AR2315_IF_LOCAL_HOST 0x00000008
883 +#define AR2315_IF_PCI_HOST 0x00000010
884 +#define AR2315_IF_PCI_INTR 0x00000020
885 +#define AR2315_IF_PCI_CLK_MASK 0x00030000
886 +#define AR2315_IF_PCI_CLK_INPUT 0
887 +#define AR2315_IF_PCI_CLK_OUTPUT_LOW 1
888 +#define AR2315_IF_PCI_CLK_OUTPUT_CLK 2
889 +#define AR2315_IF_PCI_CLK_OUTPUT_HIGH 3
890 +#define AR2315_IF_PCI_CLK_SHIFT 16
891 +
892 +/*
893 + * APB Interrupt control
894 + */
895 +
896 +#define AR2315_ISR (AR2315_DSLBASE + 0x0020)
897 +#define AR2315_IMR (AR2315_DSLBASE + 0x0024)
898 +#define AR2315_GISR (AR2315_DSLBASE + 0x0028)
899 +
900 +#define AR2315_ISR_UART0 0x0001 /* high speed UART */
901 +#define AR2315_ISR_I2C_RSVD 0x0002 /* I2C bus */
902 +#define AR2315_ISR_SPI 0x0004 /* SPI bus */
903 +#define AR2315_ISR_AHB 0x0008 /* AHB error */
904 +#define AR2315_ISR_APB 0x0010 /* APB error */
905 +#define AR2315_ISR_TIMER 0x0020 /* timer */
906 +#define AR2315_ISR_GPIO 0x0040 /* GPIO */
907 +#define AR2315_ISR_WD 0x0080 /* watchdog */
908 +#define AR2315_ISR_IR_RSVD 0x0100 /* IR */
909 +
910 +#define AR2315_GISR_MISC 0x0001
911 +#define AR2315_GISR_WLAN0 0x0002
912 +#define AR2315_GISR_MPEGTS_RSVD 0x0004
913 +#define AR2315_GISR_LOCALPCI 0x0008
914 +#define AR2315_GISR_WMACPOLL 0x0010
915 +#define AR2315_GISR_TIMER 0x0020
916 +#define AR2315_GISR_ETHERNET 0x0040
917 +
918 +/*
919 + * Interrupt routing from IO to the processor IP bits
920 + * Define our inter mask and level
921 + */
922 +#define AR2315_INTR_MISCIO SR_IBIT3
923 +#define AR2315_INTR_WLAN0 SR_IBIT4
924 +#define AR2315_INTR_ENET0 SR_IBIT5
925 +#define AR2315_INTR_LOCALPCI SR_IBIT6
926 +#define AR2315_INTR_WMACPOLL SR_IBIT7
927 +#define AR2315_INTR_COMPARE SR_IBIT8
928 +
929 +/*
930 + * Timers
931 + */
932 +#define AR2315_TIMER (AR2315_DSLBASE + 0x0030)
933 +#define AR2315_RELOAD (AR2315_DSLBASE + 0x0034)
934 +#define AR2315_WD (AR2315_DSLBASE + 0x0038)
935 +#define AR2315_WDC (AR2315_DSLBASE + 0x003c)
936 +
937 +#define AR2315_WDC_IGNORE_EXPIRATION 0x00000000
938 +#define AR2315_WDC_NMI 0x00000001 /* NMI on watchdog */
939 +#define AR2315_WDC_RESET 0x00000002 /* reset on watchdog */
940 +
941 +/*
942 + * CPU Performance Counters
943 + */
944 +#define AR2315_PERFCNT0 (AR2315_DSLBASE + 0x0048)
945 +#define AR2315_PERFCNT1 (AR2315_DSLBASE + 0x004c)
946 +
947 +#define AR2315_PERF0_DATAHIT 0x0001 /* Count Data Cache Hits */
948 +#define AR2315_PERF0_DATAMISS 0x0002 /* Count Data Cache Misses */
949 +#define AR2315_PERF0_INSTHIT 0x0004 /* Count Instruction Cache Hits */
950 +#define AR2315_PERF0_INSTMISS 0x0008 /* Count Instruction Cache Misses */
951 +#define AR2315_PERF0_ACTIVE 0x0010 /* Count Active Processor Cycles */
952 +#define AR2315_PERF0_WBHIT 0x0020 /* Count CPU Write Buffer Hits */
953 +#define AR2315_PERF0_WBMISS 0x0040 /* Count CPU Write Buffer Misses */
954 +
955 +#define AR2315_PERF1_EB_ARDY 0x0001 /* Count EB_ARdy signal */
956 +#define AR2315_PERF1_EB_AVALID 0x0002 /* Count EB_AValid signal */
957 +#define AR2315_PERF1_EB_WDRDY 0x0004 /* Count EB_WDRdy signal */
958 +#define AR2315_PERF1_EB_RDVAL 0x0008 /* Count EB_RdVal signal */
959 +#define AR2315_PERF1_VRADDR 0x0010 /* Count valid read address cycles */
960 +#define AR2315_PERF1_VWADDR 0x0020 /* Count valid write address cycles */
961 +#define AR2315_PERF1_VWDATA 0x0040 /* Count valid write data cycles */
962 +
963 +/*
964 + * AHB Error Reporting.
965 + */
966 +#define AR2315_AHB_ERR0 (AR2315_DSLBASE + 0x0050) /* error */
967 +#define AR2315_AHB_ERR1 (AR2315_DSLBASE + 0x0054) /* haddr */
968 +#define AR2315_AHB_ERR2 (AR2315_DSLBASE + 0x0058) /* hwdata */
969 +#define AR2315_AHB_ERR3 (AR2315_DSLBASE + 0x005c) /* hrdata */
970 +#define AR2315_AHB_ERR4 (AR2315_DSLBASE + 0x0060) /* status */
971 +
972 +#define AHB_ERROR_DET 1 /* AHB Error has been detected, */
973 + /* write 1 to clear all bits in ERR0 */
974 +#define AHB_ERROR_OVR 2 /* AHB Error overflow has been detected */
975 +#define AHB_ERROR_WDT 4 /* AHB Error due to wdt instead of hresp */
976 +
977 +#define AR2315_PROCERR_HMAST 0x0000000f
978 +#define AR2315_PROCERR_HMAST_DFLT 0
979 +#define AR2315_PROCERR_HMAST_WMAC 1
980 +#define AR2315_PROCERR_HMAST_ENET 2
981 +#define AR2315_PROCERR_HMAST_PCIENDPT 3
982 +#define AR2315_PROCERR_HMAST_LOCAL 4
983 +#define AR2315_PROCERR_HMAST_CPU 5
984 +#define AR2315_PROCERR_HMAST_PCITGT 6
985 +
986 +#define AR2315_PROCERR_HMAST_S 0
987 +#define AR2315_PROCERR_HWRITE 0x00000010
988 +#define AR2315_PROCERR_HSIZE 0x00000060
989 +#define AR2315_PROCERR_HSIZE_S 5
990 +#define AR2315_PROCERR_HTRANS 0x00000180
991 +#define AR2315_PROCERR_HTRANS_S 7
992 +#define AR2315_PROCERR_HBURST 0x00000e00
993 +#define AR2315_PROCERR_HBURST_S 9
994 +
995 +/*
996 + * Clock Control
997 + */
998 +#define AR2315_PLLC_CTL (AR2315_DSLBASE + 0x0064)
999 +#define AR2315_PLLV_CTL (AR2315_DSLBASE + 0x0068)
1000 +#define AR2315_CPUCLK (AR2315_DSLBASE + 0x006c)
1001 +#define AR2315_AMBACLK (AR2315_DSLBASE + 0x0070)
1002 +#define AR2315_SYNCCLK (AR2315_DSLBASE + 0x0074)
1003 +#define AR2315_DSL_SLEEP_CTL (AR2315_DSLBASE + 0x0080)
1004 +#define AR2315_DSL_SLEEP_DUR (AR2315_DSLBASE + 0x0084)
1005 +
1006 +/* PLLc Control fields */
1007 +#define PLLC_REF_DIV_M 0x00000003
1008 +#define PLLC_REF_DIV_S 0
1009 +#define PLLC_FDBACK_DIV_M 0x0000007C
1010 +#define PLLC_FDBACK_DIV_S 2
1011 +#define PLLC_ADD_FDBACK_DIV_M 0x00000080
1012 +#define PLLC_ADD_FDBACK_DIV_S 7
1013 +#define PLLC_CLKC_DIV_M 0x0001c000
1014 +#define PLLC_CLKC_DIV_S 14
1015 +#define PLLC_CLKM_DIV_M 0x00700000
1016 +#define PLLC_CLKM_DIV_S 20
1017 +
1018 +/* CPU CLK Control fields */
1019 +#define CPUCLK_CLK_SEL_M 0x00000003
1020 +#define CPUCLK_CLK_SEL_S 0
1021 +#define CPUCLK_CLK_DIV_M 0x0000000c
1022 +#define CPUCLK_CLK_DIV_S 2
1023 +
1024 +/* AMBA CLK Control fields */
1025 +#define AMBACLK_CLK_SEL_M 0x00000003
1026 +#define AMBACLK_CLK_SEL_S 0
1027 +#define AMBACLK_CLK_DIV_M 0x0000000c
1028 +#define AMBACLK_CLK_DIV_S 2
1029 +
1030 +/*
1031 + * GPIO
1032 + */
1033 +#define AR2315_GPIO_DI (AR2315_DSLBASE + 0x0088)
1034 +#define AR2315_GPIO_DO (AR2315_DSLBASE + 0x0090)
1035 +#define AR2315_GPIO_CR (AR2315_DSLBASE + 0x0098)
1036 +#define AR2315_GPIO_INT (AR2315_DSLBASE + 0x00a0)
1037 +
1038 +#define AR2315_GPIO_CR_M(x) (1 << (x)) /* mask for i/o */
1039 +#define AR2315_GPIO_CR_O(x) (1 << (x)) /* output */
1040 +#define AR2315_GPIO_CR_I(x) (0) /* input */
1041 +
1042 +#define AR2315_GPIO_INT_S(x) (x) /* interrupt enable */
1043 +#define AR2315_GPIO_INT_M (0x3F) /* mask for int */
1044 +#define AR2315_GPIO_INT_LVL(x) ((x) << 6) /* interrupt level */
1045 +#define AR2315_GPIO_INT_LVL_M ((0x3) << 6) /* mask for int level */
1046 +
1047 +#define AR2315_GPIO_INT_MAX_Y 1 /* Maximum value of Y for
1048 + * AR5313_GPIO_INT_* macros */
1049 +#define AR2315_GPIO_INT_LVL_OFF 0 /* Triggerring off */
1050 +#define AR2315_GPIO_INT_LVL_LOW 1 /* Low Level Triggered */
1051 +#define AR2315_GPIO_INT_LVL_HIGH 2 /* High Level Triggered */
1052 +#define AR2315_GPIO_INT_LVL_EDGE 3 /* Edge Triggered */
1053 +
1054 +#define AR2315_RESET_GPIO 5
1055 +#define AR2315_NUM_GPIO 22
1056 +
1057 +/*
1058 + * PCI Clock Control
1059 + */
1060 +#define AR2315_PCICLK (AR2315_DSLBASE + 0x00a4)
1061 +
1062 +#define AR2315_PCICLK_INPUT_M 0x3
1063 +#define AR2315_PCICLK_INPUT_S 0
1064 +
1065 +#define AR2315_PCICLK_PLLC_CLKM 0
1066 +#define AR2315_PCICLK_PLLC_CLKM1 1
1067 +#define AR2315_PCICLK_PLLC_CLKC 2
1068 +#define AR2315_PCICLK_REF_CLK 3
1069 +
1070 +#define AR2315_PCICLK_DIV_M 0xc
1071 +#define AR2315_PCICLK_DIV_S 2
1072 +
1073 +#define AR2315_PCICLK_IN_FREQ 0
1074 +#define AR2315_PCICLK_IN_FREQ_DIV_6 1
1075 +#define AR2315_PCICLK_IN_FREQ_DIV_8 2
1076 +#define AR2315_PCICLK_IN_FREQ_DIV_10 3
1077 +
1078 +/*
1079 + * Observation Control Register
1080 + */
1081 +#define AR2315_OCR (AR2315_DSLBASE + 0x00b0)
1082 +#define OCR_GPIO0_IRIN 0x0040
1083 +#define OCR_GPIO1_IROUT 0x0080
1084 +#define OCR_GPIO3_RXCLR 0x0200
1085 +
1086 +/*
1087 + * General Clock Control
1088 + */
1089 +
1090 +#define AR2315_MISCCLK (AR2315_DSLBASE + 0x00b4)
1091 +#define MISCCLK_PLLBYPASS_EN 0x00000001
1092 +#define MISCCLK_PROCREFCLK 0x00000002
1093 +
1094 +/*
1095 + * SDRAM Controller
1096 + * - No read or write buffers are included.
1097 + */
1098 +#define AR2315_MEM_CFG (AR2315_SDRAMCTL + 0x00)
1099 +#define AR2315_MEM_CTRL (AR2315_SDRAMCTL + 0x0c)
1100 +#define AR2315_MEM_REF (AR2315_SDRAMCTL + 0x10)
1101 +
1102 +#define SDRAM_DATA_WIDTH_M 0x00006000
1103 +#define SDRAM_DATA_WIDTH_S 13
1104 +
1105 +#define SDRAM_COL_WIDTH_M 0x00001E00
1106 +#define SDRAM_COL_WIDTH_S 9
1107 +
1108 +#define SDRAM_ROW_WIDTH_M 0x000001E0
1109 +#define SDRAM_ROW_WIDTH_S 5
1110 +
1111 +#define SDRAM_BANKADDR_BITS_M 0x00000018
1112 +#define SDRAM_BANKADDR_BITS_S 3
1113 +
1114 +/*
1115 + * SPI Flash Interface Registers
1116 + */
1117 +
1118 +#define AR2315_SPI_CTL (AR2315_SPI + 0x00)
1119 +#define AR2315_SPI_OPCODE (AR2315_SPI + 0x04)
1120 +#define AR2315_SPI_DATA (AR2315_SPI + 0x08)
1121 +
1122 +#define SPI_CTL_START 0x00000100
1123 +#define SPI_CTL_BUSY 0x00010000
1124 +#define SPI_CTL_TXCNT_MASK 0x0000000f
1125 +#define SPI_CTL_RXCNT_MASK 0x000000f0
1126 +#define SPI_CTL_TX_RX_CNT_MASK 0x000000ff
1127 +#define SPI_CTL_SIZE_MASK 0x00060000
1128 +
1129 +#define SPI_CTL_CLK_SEL_MASK 0x03000000
1130 +#define SPI_OPCODE_MASK 0x000000ff
1131 +
1132 +/*
1133 + * PCI Bus Interface Registers
1134 + */
1135 +#define AR2315_PCI_1MS_REG (AR2315_PCI + 0x0008)
1136 +#define AR2315_PCI_1MS_MASK 0x3FFFF /* # of AHB clk cycles in 1ms */
1137 +
1138 +#define AR2315_PCI_MISC_CONFIG (AR2315_PCI + 0x000c)
1139 +#define AR2315_PCIMISC_TXD_EN 0x00000001 /* Enable TXD for fragments */
1140 +#define AR2315_PCIMISC_CFG_SEL 0x00000002 /* mem or config cycles */
1141 +#define AR2315_PCIMISC_GIG_MASK 0x0000000C /* bits 31-30 for pci req */
1142 +#define AR2315_PCIMISC_RST_MODE 0x00000030
1143 +#define AR2315_PCIRST_INPUT 0x00000000 /* 4:5=0 rst is input */
1144 +#define AR2315_PCIRST_LOW 0x00000010 /* 4:5=1 rst to GND */
1145 +#define AR2315_PCIRST_HIGH 0x00000020 /* 4:5=2 rst to VDD */
1146 +#define AR2315_PCIGRANT_EN 0x00000000 /* 6:7=0 early grant en */
1147 +#define AR2315_PCIGRANT_FRAME 0x00000040 /* 6:7=1 grant waits 4 frame */
1148 +#define AR2315_PCIGRANT_IDLE 0x00000080 /* 6:7=2 grant waits 4 idle */
1149 +#define AR2315_PCIGRANT_GAP 0x00000000 /* 6:7=2 grant waits 4 idle */
1150 +#define AR2315_PCICACHE_DIS 0x00001000 /* PCI external access cache
1151 + * disable */
1152 +
1153 +#define AR2315_PCI_OUT_TSTAMP (AR2315_PCI + 0x0010)
1154 +
1155 +#define AR2315_PCI_UNCACHE_CFG (AR2315_PCI + 0x0014)
1156 +
1157 +#define AR2315_PCI_IN_EN (AR2315_PCI + 0x0100)
1158 +#define AR2315_PCI_IN_EN0 0x01 /* Enable chain 0 */
1159 +#define AR2315_PCI_IN_EN1 0x02 /* Enable chain 1 */
1160 +#define AR2315_PCI_IN_EN2 0x04 /* Enable chain 2 */
1161 +#define AR2315_PCI_IN_EN3 0x08 /* Enable chain 3 */
1162 +
1163 +#define AR2315_PCI_IN_DIS (AR2315_PCI + 0x0104)
1164 +#define AR2315_PCI_IN_DIS0 0x01 /* Disable chain 0 */
1165 +#define AR2315_PCI_IN_DIS1 0x02 /* Disable chain 1 */
1166 +#define AR2315_PCI_IN_DIS2 0x04 /* Disable chain 2 */
1167 +#define AR2315_PCI_IN_DIS3 0x08 /* Disable chain 3 */
1168 +
1169 +#define AR2315_PCI_IN_PTR (AR2315_PCI + 0x0200)
1170 +
1171 +#define AR2315_PCI_OUT_EN (AR2315_PCI + 0x0400)
1172 +#define AR2315_PCI_OUT_EN0 0x01 /* Enable chain 0 */
1173 +
1174 +#define AR2315_PCI_OUT_DIS (AR2315_PCI + 0x0404)
1175 +#define AR2315_PCI_OUT_DIS0 0x01 /* Disable chain 0 */
1176 +
1177 +#define AR2315_PCI_OUT_PTR (AR2315_PCI + 0x0408)
1178 +
1179 +#define AR2315_PCI_INT_STATUS (AR2315_PCI + 0x0500) /* write one to clr */
1180 +#define AR2315_PCI_TXINT 0x00000001 /* Desc In Completed */
1181 +#define AR2315_PCI_TXOK 0x00000002 /* Desc In OK */
1182 +#define AR2315_PCI_TXERR 0x00000004 /* Desc In ERR */
1183 +#define AR2315_PCI_TXEOL 0x00000008 /* Desc In End-of-List */
1184 +#define AR2315_PCI_RXINT 0x00000010 /* Desc Out Completed */
1185 +#define AR2315_PCI_RXOK 0x00000020 /* Desc Out OK */
1186 +#define AR2315_PCI_RXERR 0x00000040 /* Desc Out ERR */
1187 +#define AR2315_PCI_RXEOL 0x00000080 /* Desc Out EOL */
1188 +#define AR2315_PCI_TXOOD 0x00000200 /* Desc In Out-of-Desc */
1189 +#define AR2315_PCI_MASK 0x0000FFFF /* Desc Mask */
1190 +#define AR2315_PCI_EXT_INT 0x02000000
1191 +#define AR2315_PCI_ABORT_INT 0x04000000
1192 +
1193 +#define AR2315_PCI_INT_MASK (AR2315_PCI + 0x0504) /* same as INT_STATUS */
1194 +
1195 +#define AR2315_PCI_INTEN_REG (AR2315_PCI + 0x0508)
1196 +#define AR2315_PCI_INT_DISABLE 0x00 /* disable pci interrupts */
1197 +#define AR2315_PCI_INT_ENABLE 0x01 /* enable pci interrupts */
1198 +
1199 +#define AR2315_PCI_HOST_IN_EN (AR2315_PCI + 0x0800)
1200 +#define AR2315_PCI_HOST_IN_DIS (AR2315_PCI + 0x0804)
1201 +#define AR2315_PCI_HOST_IN_PTR (AR2315_PCI + 0x0810)
1202 +#define AR2315_PCI_HOST_OUT_EN (AR2315_PCI + 0x0900)
1203 +#define AR2315_PCI_HOST_OUT_DIS (AR2315_PCI + 0x0904)
1204 +#define AR2315_PCI_HOST_OUT_PTR (AR2315_PCI + 0x0908)
1205 +
1206 +
1207 +/*
1208 + * Local Bus Interface Registers
1209 + */
1210 +#define AR2315_LB_CONFIG (AR2315_LOCAL + 0x0000)
1211 +#define AR2315_LBCONF_OE 0x00000001 /* =1 OE is low-true */
1212 +#define AR2315_LBCONF_CS0 0x00000002 /* =1 first CS is low-true */
1213 +#define AR2315_LBCONF_CS1 0x00000004 /* =1 2nd CS is low-true */
1214 +#define AR2315_LBCONF_RDY 0x00000008 /* =1 RDY is low-true */
1215 +#define AR2315_LBCONF_WE 0x00000010 /* =1 Write En is low-true */
1216 +#define AR2315_LBCONF_WAIT 0x00000020 /* =1 WAIT is low-true */
1217 +#define AR2315_LBCONF_ADS 0x00000040 /* =1 Adr Strobe is low-true */
1218 +#define AR2315_LBCONF_MOT 0x00000080 /* =0 Intel, =1 Motorola */
1219 +#define AR2315_LBCONF_8CS 0x00000100 /* =1 8 bits CS, 0= 16bits */
1220 +#define AR2315_LBCONF_8DS 0x00000200 /* =1 8 bits Data S, 0=16bits */
1221 +#define AR2315_LBCONF_ADS_EN 0x00000400 /* =1 Enable ADS */
1222 +#define AR2315_LBCONF_ADR_OE 0x00000800 /* =1 Adr cap on OE, WE or DS */
1223 +#define AR2315_LBCONF_ADDT_MUX 0x00001000 /* =1 Adr and Data share bus */
1224 +#define AR2315_LBCONF_DATA_OE 0x00002000 /* =1 Data cap on OE, WE, DS */
1225 +#define AR2315_LBCONF_16DATA 0x00004000 /* =1 Data is 16 bits wide */
1226 +#define AR2315_LBCONF_SWAPDT 0x00008000 /* =1 Byte swap data */
1227 +#define AR2315_LBCONF_SYNC 0x00010000 /* =1 Bus synchronous to clk */
1228 +#define AR2315_LBCONF_INT 0x00020000 /* =1 Intr is low true */
1229 +#define AR2315_LBCONF_INT_CTR0 0x00000000 /* GND high-Z, Vdd is high-Z */
1230 +#define AR2315_LBCONF_INT_CTR1 0x00040000 /* GND drive, Vdd is high-Z */
1231 +#define AR2315_LBCONF_INT_CTR2 0x00080000 /* GND high-Z, Vdd drive */
1232 +#define AR2315_LBCONF_INT_CTR3 0x000C0000 /* GND drive, Vdd drive */
1233 +#define AR2315_LBCONF_RDY_WAIT 0x00100000 /* =1 RDY is negative of WAIT */
1234 +#define AR2315_LBCONF_INT_PULSE 0x00200000 /* =1 Interrupt is a pulse */
1235 +#define AR2315_LBCONF_ENABLE 0x00400000 /* =1 Falcon respond to LB */
1236 +
1237 +#define AR2315_LB_CLKSEL (AR2315_LOCAL + 0x0004)
1238 +#define AR2315_LBCLK_EXT 0x0001 /* use external clk for lb */
1239 +
1240 +#define AR2315_LB_1MS (AR2315_LOCAL + 0x0008)
1241 +#define AR2315_LB1MS_MASK 0x3FFFF /* # of AHB clk cycles in 1ms */
1242 +
1243 +#define AR2315_LB_MISCCFG (AR2315_LOCAL + 0x000C)
1244 +#define AR2315_LBM_TXD_EN 0x00000001 /* Enable TXD for fragments */
1245 +#define AR2315_LBM_RX_INTEN 0x00000002 /* Enable LB ints on RX ready */
1246 +#define AR2315_LBM_MBOXWR_INTEN 0x00000004 /* Enable LB ints on mbox wr */
1247 +#define AR2315_LBM_MBOXRD_INTEN 0x00000008 /* Enable LB ints on mbox rd */
1248 +#define AR2315_LMB_DESCSWAP_EN 0x00000010 /* Byte swap desc enable */
1249 +#define AR2315_LBM_TIMEOUT_MASK 0x00FFFF80
1250 +#define AR2315_LBM_TIMEOUT_SHFT 7
1251 +#define AR2315_LBM_PORTMUX 0x07000000
1252 +
1253 +
1254 +#define AR2315_LB_RXTSOFF (AR2315_LOCAL + 0x0010)
1255 +
1256 +#define AR2315_LB_TX_CHAIN_EN (AR2315_LOCAL + 0x0100)
1257 +#define AR2315_LB_TXEN_0 0x01
1258 +#define AR2315_LB_TXEN_1 0x02
1259 +#define AR2315_LB_TXEN_2 0x04
1260 +#define AR2315_LB_TXEN_3 0x08
1261 +
1262 +#define AR2315_LB_TX_CHAIN_DIS (AR2315_LOCAL + 0x0104)
1263 +#define AR2315_LB_TX_DESC_PTR (AR2315_LOCAL + 0x0200)
1264 +
1265 +#define AR2315_LB_RX_CHAIN_EN (AR2315_LOCAL + 0x0400)
1266 +#define AR2315_LB_RXEN 0x01
1267 +
1268 +#define AR2315_LB_RX_CHAIN_DIS (AR2315_LOCAL + 0x0404)
1269 +#define AR2315_LB_RX_DESC_PTR (AR2315_LOCAL + 0x0408)
1270 +
1271 +#define AR2315_LB_INT_STATUS (AR2315_LOCAL + 0x0500)
1272 +#define AR2315_INT_TX_DESC 0x0001
1273 +#define AR2315_INT_TX_OK 0x0002
1274 +#define AR2315_INT_TX_ERR 0x0004
1275 +#define AR2315_INT_TX_EOF 0x0008
1276 +#define AR2315_INT_RX_DESC 0x0010
1277 +#define AR2315_INT_RX_OK 0x0020
1278 +#define AR2315_INT_RX_ERR 0x0040
1279 +#define AR2315_INT_RX_EOF 0x0080
1280 +#define AR2315_INT_TX_TRUNC 0x0100
1281 +#define AR2315_INT_TX_STARVE 0x0200
1282 +#define AR2315_INT_LB_TIMEOUT 0x0400
1283 +#define AR2315_INT_LB_ERR 0x0800
1284 +#define AR2315_INT_MBOX_WR 0x1000
1285 +#define AR2315_INT_MBOX_RD 0x2000
1286 +
1287 +/* Bit definitions for INT MASK are the same as INT_STATUS */
1288 +#define AR2315_LB_INT_MASK (AR2315_LOCAL + 0x0504)
1289 +
1290 +#define AR2315_LB_INT_EN (AR2315_LOCAL + 0x0508)
1291 +#define AR2315_LB_MBOX (AR2315_LOCAL + 0x0600)
1292 +
1293 +/*
1294 + * IR Interface Registers
1295 + */
1296 +#define AR2315_IR_PKTDATA (AR2315_IR + 0x0000)
1297 +
1298 +#define AR2315_IR_PKTLEN (AR2315_IR + 0x07fc) /* 0 - 63 */
1299 +
1300 +#define AR2315_IR_CONTROL (AR2315_IR + 0x0800)
1301 +#define AR2315_IRCTL_TX 0x00000000 /* use as tranmitter */
1302 +#define AR2315_IRCTL_RX 0x00000001 /* use as receiver */
1303 +#define AR2315_IRCTL_SAMPLECLK_MASK 0x00003ffe /* Sample clk divisor */
1304 +#define AR2315_IRCTL_SAMPLECLK_SHFT 1
1305 +#define AR2315_IRCTL_OUTPUTCLK_MASK 0x03ffc000 /* Output clk div */
1306 +#define AR2315_IRCTL_OUTPUTCLK_SHFT 14
1307 +
1308 +#define AR2315_IR_STATUS (AR2315_IR + 0x0804)
1309 +#define AR2315_IRSTS_RX 0x00000001 /* receive in progress */
1310 +#define AR2315_IRSTS_TX 0x00000002 /* transmit in progress */
1311 +
1312 +#define AR2315_IR_CONFIG (AR2315_IR + 0x0808)
1313 +#define AR2315_IRCFG_INVIN 0x00000001 /* invert in polarity */
1314 +#define AR2315_IRCFG_INVOUT 0x00000002 /* invert out polarity */
1315 +#define AR2315_IRCFG_SEQ_START_WIN_SEL 0x00000004 /* 1 => 28, 0 => 7 */
1316 +#define AR2315_IRCFG_SEQ_START_THRESH 0x000000f0
1317 +#define AR2315_IRCFG_SEQ_END_UNIT_SEL 0x00000100
1318 +#define AR2315_IRCFG_SEQ_END_UNIT_THRESH 0x00007e00
1319 +#define AR2315_IRCFG_SEQ_END_WIN_SEL 0x00008000
1320 +#define AR2315_IRCFG_SEQ_END_WIN_THRESH 0x001f0000
1321 +#define AR2315_IRCFG_NUM_BACKOFF_WORDS 0x01e00000
1322 +
1323 +#define HOST_PCI_DEV_ID 3
1324 +#define HOST_PCI_MBAR0 0x10000000
1325 +#define HOST_PCI_MBAR1 0x20000000
1326 +#define HOST_PCI_MBAR2 0x30000000
1327 +
1328 +#define HOST_PCI_SDRAM_BASEADDR HOST_PCI_MBAR1
1329 +#define PCI_DEVICE_MEM_SPACE 0x800000
1330 +
1331 +#endif /* __AR2315_REG_H */
1332 --- /dev/null
1333 +++ b/arch/mips/include/asm/mach-ar231x/ar5312_regs.h
1334 @@ -0,0 +1,233 @@
1335 +/*
1336 + * This file is subject to the terms and conditions of the GNU General Public
1337 + * License. See the file "COPYING" in the main directory of this archive
1338 + * for more details.
1339 + *
1340 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
1341 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
1342 + * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
1343 + */
1344 +
1345 +#ifndef AR5312_H
1346 +#define AR5312_H
1347 +
1348 +#include <asm/addrspace.h>
1349 +
1350 +/*
1351 + * IRQs
1352 + */
1353 +
1354 +#define AR5312_IRQ_WLAN0_INTRS (MIPS_CPU_IRQ_BASE+2) /* C0_CAUSE: 0x0400 */
1355 +#define AR5312_IRQ_ENET0_INTRS (MIPS_CPU_IRQ_BASE+3) /* C0_CAUSE: 0x0800 */
1356 +#define AR5312_IRQ_ENET1_INTRS (MIPS_CPU_IRQ_BASE+4) /* C0_CAUSE: 0x1000 */
1357 +#define AR5312_IRQ_WLAN1_INTRS (MIPS_CPU_IRQ_BASE+5) /* C0_CAUSE: 0x2000 */
1358 +#define AR5312_IRQ_MISC_INTRS (MIPS_CPU_IRQ_BASE+6) /* C0_CAUSE: 0x4000 */
1359 +
1360 +
1361 +/* Address Map */
1362 +#define AR531X_WLAN0 0x18000000
1363 +#define AR531X_WLAN1 0x18500000
1364 +#define AR531X_ENET0 0x18100000
1365 +#define AR531X_ENET1 0x18200000
1366 +#define AR531X_SDRAMCTL 0x18300000
1367 +#define AR531X_FLASHCTL 0x18400000
1368 +#define AR531X_APBBASE 0x1c000000
1369 +#define AR531X_FLASH 0x1e000000
1370 +#define AR531X_UART0 0xbc000003 /* UART MMR */
1371 +
1372 +/*
1373 + * AR531X_NUM_ENET_MAC defines the number of ethernet MACs that
1374 + * should be considered available. The AR5312 supports 2 enet MACS,
1375 + * even though many reference boards only actually use 1 of them
1376 + * (i.e. Only MAC 0 is actually connected to an enet PHY or PHY switch.
1377 + * The AR2312 supports 1 enet MAC.
1378 + */
1379 +#define AR531X_NUM_ENET_MAC 2
1380 +
1381 +/*
1382 + * Need these defines to determine true number of ethernet MACs
1383 + */
1384 +#define AR5212_AR5312_REV2 0x0052 /* AR5312 WMAC (AP31) */
1385 +#define AR5212_AR5312_REV7 0x0057 /* AR5312 WMAC (AP30-040) */
1386 +#define AR5212_AR2313_REV8 0x0058 /* AR2313 WMAC (AP43-030) */
1387 +
1388 +/*
1389 + * AR531X_NUM_WMAC defines the number of Wireless MACs that\
1390 + * should be considered available.
1391 + */
1392 +#define AR531X_NUM_WMAC 2
1393 +
1394 +/* Reset/Timer Block Address Map */
1395 +#define AR531X_RESETTMR (AR531X_APBBASE + 0x3000)
1396 +#define AR531X_TIMER (AR531X_RESETTMR + 0x0000) /* countdown timer */
1397 +#define AR531X_WD_CTRL (AR531X_RESETTMR + 0x0008) /* watchdog cntrl */
1398 +#define AR531X_WD_TIMER (AR531X_RESETTMR + 0x000c) /* watchdog timer */
1399 +#define AR531X_ISR (AR531X_RESETTMR + 0x0010) /* Intr Status Reg */
1400 +#define AR531X_IMR (AR531X_RESETTMR + 0x0014) /* Intr Mask Reg */
1401 +#define AR531X_RESET (AR531X_RESETTMR + 0x0020)
1402 +#define AR5312_CLOCKCTL1 (AR531X_RESETTMR + 0x0064)
1403 +#define AR5312_SCRATCH (AR531X_RESETTMR + 0x006c)
1404 +#define AR531X_PROCADDR (AR531X_RESETTMR + 0x0070)
1405 +#define AR531X_PROC1 (AR531X_RESETTMR + 0x0074)
1406 +#define AR531X_DMAADDR (AR531X_RESETTMR + 0x0078)
1407 +#define AR531X_DMA1 (AR531X_RESETTMR + 0x007c)
1408 +#define AR531X_ENABLE (AR531X_RESETTMR + 0x0080) /* interface enb */
1409 +#define AR531X_REV (AR531X_RESETTMR + 0x0090) /* revision */
1410 +
1411 +/* AR531X_WD_CTRL register bit field definitions */
1412 +#define AR531X_WD_CTRL_IGNORE_EXPIRATION 0x0000
1413 +#define AR531X_WD_CTRL_NMI 0x0001
1414 +#define AR531X_WD_CTRL_RESET 0x0002
1415 +
1416 +/* AR531X_ISR register bit field definitions */
1417 +#define AR531X_ISR_NONE 0x0000
1418 +#define AR531X_ISR_TIMER 0x0001
1419 +#define AR531X_ISR_AHBPROC 0x0002
1420 +#define AR531X_ISR_AHBDMA 0x0004
1421 +#define AR531X_ISR_GPIO 0x0008
1422 +#define AR531X_ISR_UART0 0x0010
1423 +#define AR531X_ISR_UART0DMA 0x0020
1424 +#define AR531X_ISR_WD 0x0040
1425 +#define AR531X_ISR_LOCAL 0x0080
1426 +
1427 +/* AR531X_RESET register bit field definitions */
1428 +#define AR531X_RESET_SYSTEM 0x00000001 /* cold reset full system */
1429 +#define AR531X_RESET_PROC 0x00000002 /* cold reset MIPS core */
1430 +#define AR531X_RESET_WLAN0 0x00000004 /* cold reset WLAN MAC and BB */
1431 +#define AR531X_RESET_EPHY0 0x00000008 /* cold reset ENET0 phy */
1432 +#define AR531X_RESET_EPHY1 0x00000010 /* cold reset ENET1 phy */
1433 +#define AR531X_RESET_ENET0 0x00000020 /* cold reset ENET0 mac */
1434 +#define AR531X_RESET_ENET1 0x00000040 /* cold reset ENET1 mac */
1435 +#define AR531X_RESET_UART0 0x00000100 /* cold reset UART0 (high speed) */
1436 +#define AR531X_RESET_WLAN1 0x00000200 /* cold reset WLAN MAC/BB */
1437 +#define AR531X_RESET_APB 0x00000400 /* cold reset APB (ar5312) */
1438 +#define AR531X_RESET_WARM_PROC 0x00001000 /* warm reset MIPS core */
1439 +#define AR531X_RESET_WARM_WLAN0_MAC 0x00002000 /* warm reset WLAN0 MAC */
1440 +#define AR531X_RESET_WARM_WLAN0_BB 0x00004000 /* warm reset WLAN0 BaseBand */
1441 +#define AR531X_RESET_NMI 0x00010000 /* send an NMI to the processor */
1442 +#define AR531X_RESET_WARM_WLAN1_MAC 0x00020000 /* warm reset WLAN1 mac */
1443 +#define AR531X_RESET_WARM_WLAN1_BB 0x00040000 /* warm reset WLAN1 baseband */
1444 +#define AR531X_RESET_LOCAL_BUS 0x00080000 /* reset local bus */
1445 +#define AR531X_RESET_WDOG 0x00100000 /* last reset was a watchdog */
1446 +
1447 +#define AR531X_RESET_WMAC0_BITS \
1448 + (AR531X_RESET_WLAN0 |\
1449 + AR531X_RESET_WARM_WLAN0_MAC |\
1450 + AR531X_RESET_WARM_WLAN0_BB)
1451 +
1452 +#define AR531X_RESERT_WMAC1_BITS \
1453 + (AR531X_RESET_WLAN1 |\
1454 + AR531X_RESET_WARM_WLAN1_MAC |\
1455 + AR531X_RESET_WARM_WLAN1_BB)
1456 +
1457 +/* AR5312_CLOCKCTL1 register bit field definitions */
1458 +#define AR5312_CLOCKCTL1_PREDIVIDE_MASK 0x00000030
1459 +#define AR5312_CLOCKCTL1_PREDIVIDE_SHIFT 4
1460 +#define AR5312_CLOCKCTL1_MULTIPLIER_MASK 0x00001f00
1461 +#define AR5312_CLOCKCTL1_MULTIPLIER_SHIFT 8
1462 +#define AR5312_CLOCKCTL1_DOUBLER_MASK 0x00010000
1463 +
1464 +/* Valid for AR5312 and AR2312 */
1465 +#define AR5312_CLOCKCTL1_PREDIVIDE_MASK 0x00000030
1466 +#define AR5312_CLOCKCTL1_PREDIVIDE_SHIFT 4
1467 +#define AR5312_CLOCKCTL1_MULTIPLIER_MASK 0x00001f00
1468 +#define AR5312_CLOCKCTL1_MULTIPLIER_SHIFT 8
1469 +#define AR5312_CLOCKCTL1_DOUBLER_MASK 0x00010000
1470 +
1471 +/* Valid for AR2313 */
1472 +#define AR2313_CLOCKCTL1_PREDIVIDE_MASK 0x00003000
1473 +#define AR2313_CLOCKCTL1_PREDIVIDE_SHIFT 12
1474 +#define AR2313_CLOCKCTL1_MULTIPLIER_MASK 0x001f0000
1475 +#define AR2313_CLOCKCTL1_MULTIPLIER_SHIFT 16
1476 +#define AR2313_CLOCKCTL1_DOUBLER_MASK 0x00000000
1477 +
1478 +
1479 +/* AR531X_ENABLE register bit field definitions */
1480 +#define AR531X_ENABLE_WLAN0 0x0001
1481 +#define AR531X_ENABLE_ENET0 0x0002
1482 +#define AR531X_ENABLE_ENET1 0x0004
1483 +#define AR531X_ENABLE_UART_AND_WLAN1_PIO 0x0008 /* UART, and WLAN1 PIOs */
1484 +#define AR531X_ENABLE_WLAN1_DMA 0x0010 /* WLAN1 DMAs */
1485 +#define AR531X_ENABLE_WLAN1 \
1486 + (AR531X_ENABLE_UART_AND_WLAN1_PIO |\
1487 + AR531X_ENABLE_WLAN1_DMA)
1488 +
1489 +/* AR531X_REV register bit field definitions */
1490 +#define AR531X_REV_WMAC_MAJ 0xf000
1491 +#define AR531X_REV_WMAC_MAJ_S 12
1492 +#define AR531X_REV_WMAC_MIN 0x0f00
1493 +#define AR531X_REV_WMAC_MIN_S 8
1494 +#define AR531X_REV_MAJ 0x00f0
1495 +#define AR531X_REV_MAJ_S 4
1496 +#define AR531X_REV_MIN 0x000f
1497 +#define AR531X_REV_MIN_S 0
1498 +#define AR531X_REV_CHIP (AR531X_REV_MAJ|AR531X_REV_MIN)
1499 +
1500 +/* Major revision numbers, bits 7..4 of Revision ID register */
1501 +#define AR531X_REV_MAJ_AR5312 0x4
1502 +#define AR531X_REV_MAJ_AR2313 0x5
1503 +
1504 +/* Minor revision numbers, bits 3..0 of Revision ID register */
1505 +#define AR5312_REV_MIN_DUAL 0x0 /* Dual WLAN version */
1506 +#define AR5312_REV_MIN_SINGLE 0x1 /* Single WLAN version */
1507 +
1508 +/* AR531X_FLASHCTL register bit field definitions */
1509 +#define FLASHCTL_IDCY 0x0000000f /* Idle cycle turn around time */
1510 +#define FLASHCTL_IDCY_S 0
1511 +#define FLASHCTL_WST1 0x000003e0 /* Wait state 1 */
1512 +#define FLASHCTL_WST1_S 5
1513 +#define FLASHCTL_RBLE 0x00000400 /* Read byte lane enable */
1514 +#define FLASHCTL_WST2 0x0000f800 /* Wait state 2 */
1515 +#define FLASHCTL_WST2_S 11
1516 +#define FLASHCTL_AC 0x00070000 /* Flash address check (added) */
1517 +#define FLASHCTL_AC_S 16
1518 +#define FLASHCTL_AC_128K 0x00000000
1519 +#define FLASHCTL_AC_256K 0x00010000
1520 +#define FLASHCTL_AC_512K 0x00020000
1521 +#define FLASHCTL_AC_1M 0x00030000
1522 +#define FLASHCTL_AC_2M 0x00040000
1523 +#define FLASHCTL_AC_4M 0x00050000
1524 +#define FLASHCTL_AC_8M 0x00060000
1525 +#define FLASHCTL_AC_RES 0x00070000 /* 16MB is not supported */
1526 +#define FLASHCTL_E 0x00080000 /* Flash bank enable (added) */
1527 +#define FLASHCTL_BUSERR 0x01000000 /* Bus transfer error status flag */
1528 +#define FLASHCTL_WPERR 0x02000000 /* Write protect error status flag */
1529 +#define FLASHCTL_WP 0x04000000 /* Write protect */
1530 +#define FLASHCTL_BM 0x08000000 /* Burst mode */
1531 +#define FLASHCTL_MW 0x30000000 /* Memory width */
1532 +#define FLASHCTL_MWx8 0x00000000 /* Memory width x8 */
1533 +#define FLASHCTL_MWx16 0x10000000 /* Memory width x16 */
1534 +#define FLASHCTL_MWx32 0x20000000 /* Memory width x32 (not supported) */
1535 +#define FLASHCTL_ATNR 0x00000000 /* Access type == no retry */
1536 +#define FLASHCTL_ATR 0x80000000 /* Access type == retry every */
1537 +#define FLASHCTL_ATR4 0xc0000000 /* Access type == retry every 4 */
1538 +
1539 +/* ARM Flash Controller -- 3 flash banks with either x8 or x16 devices. */
1540 +#define AR531X_FLASHCTL0 (AR531X_FLASHCTL + 0x00)
1541 +#define AR531X_FLASHCTL1 (AR531X_FLASHCTL + 0x04)
1542 +#define AR531X_FLASHCTL2 (AR531X_FLASHCTL + 0x08)
1543 +
1544 +/* ARM SDRAM Controller -- just enough to determine memory size */
1545 +#define AR531X_MEM_CFG1 (AR531X_SDRAMCTL + 0x04)
1546 +#define MEM_CFG1_AC0 0x00000700 /* bank 0: SDRAM addr check (added) */
1547 +#define MEM_CFG1_AC0_S 8
1548 +#define MEM_CFG1_AC1 0x00007000 /* bank 1: SDRAM addr check (added) */
1549 +#define MEM_CFG1_AC1_S 12
1550 +
1551 +/* GPIO Address Map */
1552 +#define AR531X_GPIO (AR531X_APBBASE + 0x2000)
1553 +#define AR531X_GPIO_DO (AR531X_GPIO + 0x00) /* output register */
1554 +#define AR531X_GPIO_DI (AR531X_GPIO + 0x04) /* intput register */
1555 +#define AR531X_GPIO_CR (AR531X_GPIO + 0x08) /* control register */
1556 +
1557 +/* GPIO Control Register bit field definitions */
1558 +#define AR531X_GPIO_CR_M(x) (1 << (x)) /* mask for i/o */
1559 +#define AR531X_GPIO_CR_O(x) (0 << (x)) /* mask for output */
1560 +#define AR531X_GPIO_CR_I(x) (1 << (x)) /* mask for input */
1561 +#define AR531X_GPIO_CR_INT(x) (1 << ((x)+8)) /* mask for interrupt*/
1562 +#define AR531X_GPIO_CR_UART(x) (1 << ((x)+16)) /* uart multiplex */
1563 +#define AR531X_NUM_GPIO 8
1564 +
1565 +
1566 +#endif
1567 +
1568 --- /dev/null
1569 +++ b/arch/mips/ar231x/ar5312.c
1570 @@ -0,0 +1,582 @@
1571 +/*
1572 + * This file is subject to the terms and conditions of the GNU General Public
1573 + * License. See the file "COPYING" in the main directory of this archive
1574 + * for more details.
1575 + *
1576 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
1577 + * Copyright (C) 2006 FON Technology, SL.
1578 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
1579 + * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
1580 + * Copyright (C) 2012 Alexandros C. Couloumbis <alex@ozo.com>
1581 + */
1582 +
1583 +/*
1584 + * Platform devices for Atheros SoCs
1585 + */
1586 +
1587 +#include <generated/autoconf.h>
1588 +#include <linux/init.h>
1589 +#include <linux/module.h>
1590 +#include <linux/types.h>
1591 +#include <linux/string.h>
1592 +#include <linux/mtd/physmap.h>
1593 +#include <linux/platform_device.h>
1594 +#include <linux/kernel.h>
1595 +#include <linux/reboot.h>
1596 +#include <linux/leds.h>
1597 +#include <linux/gpio.h>
1598 +#include <asm/bootinfo.h>
1599 +#include <asm/reboot.h>
1600 +#include <asm/time.h>
1601 +#include <linux/irq.h>
1602 +#include <linux/io.h>
1603 +
1604 +#include <ar231x_platform.h>
1605 +#include <ar5312_regs.h>
1606 +#include <ar231x.h>
1607 +#include "devices.h"
1608 +#include "ar5312.h"
1609 +
1610 +static void
1611 +ar5312_misc_irq_dispatch(void)
1612 +{
1613 + unsigned int ar231x_misc_intrs = ar231x_read_reg(AR531X_ISR) &
1614 + ar231x_read_reg(AR531X_IMR);
1615 +
1616 + if (ar231x_misc_intrs & AR531X_ISR_TIMER) {
1617 + do_IRQ(AR531X_MISC_IRQ_TIMER);
1618 + (void)ar231x_read_reg(AR531X_TIMER);
1619 + } else if (ar231x_misc_intrs & AR531X_ISR_AHBPROC)
1620 + do_IRQ(AR531X_MISC_IRQ_AHB_PROC);
1621 + else if ((ar231x_misc_intrs & AR531X_ISR_UART0))
1622 + do_IRQ(AR531X_MISC_IRQ_UART0);
1623 + else if (ar231x_misc_intrs & AR531X_ISR_WD)
1624 + do_IRQ(AR531X_MISC_IRQ_WATCHDOG);
1625 + else
1626 + do_IRQ(AR531X_MISC_IRQ_NONE);
1627 +}
1628 +
1629 +static asmlinkage void
1630 +ar5312_irq_dispatch(void)
1631 +{
1632 + int pending = read_c0_status() & read_c0_cause();
1633 +
1634 + if (pending & CAUSEF_IP2)
1635 + do_IRQ(AR5312_IRQ_WLAN0_INTRS);
1636 + else if (pending & CAUSEF_IP3)
1637 + do_IRQ(AR5312_IRQ_ENET0_INTRS);
1638 + else if (pending & CAUSEF_IP4)
1639 + do_IRQ(AR5312_IRQ_ENET1_INTRS);
1640 + else if (pending & CAUSEF_IP5)
1641 + do_IRQ(AR5312_IRQ_WLAN1_INTRS);
1642 + else if (pending & CAUSEF_IP6)
1643 + ar5312_misc_irq_dispatch();
1644 + else if (pending & CAUSEF_IP7)
1645 + do_IRQ(AR531X_IRQ_CPU_CLOCK);
1646 +}
1647 +
1648 +
1649 +/* Enable the specified AR531X_MISC_IRQ interrupt */
1650 +static void
1651 +ar5312_misc_intr_enable(struct irq_data *d)
1652 +{
1653 + unsigned int imr;
1654 +
1655 + imr = ar231x_read_reg(AR531X_IMR);
1656 + imr |= (1 << (d->irq - AR531X_MISC_IRQ_BASE - 1));
1657 + ar231x_write_reg(AR531X_IMR, imr);
1658 +}
1659 +
1660 +/* Disable the specified AR531X_MISC_IRQ interrupt */
1661 +static void
1662 +ar5312_misc_intr_disable(struct irq_data *d)
1663 +{
1664 + unsigned int imr;
1665 +
1666 + imr = ar231x_read_reg(AR531X_IMR);
1667 + imr &= ~(1 << (d->irq - AR531X_MISC_IRQ_BASE - 1));
1668 + ar231x_write_reg(AR531X_IMR, imr);
1669 + ar231x_read_reg(AR531X_IMR); /* flush write buffer */
1670 +}
1671 +
1672 +static struct irq_chip ar5312_misc_intr_controller = {
1673 + .irq_mask = ar5312_misc_intr_disable,
1674 + .irq_unmask = ar5312_misc_intr_enable,
1675 +};
1676 +
1677 +
1678 +static irqreturn_t ar5312_ahb_proc_handler(int cpl, void *dev_id)
1679 +{
1680 + u32 proc1 = ar231x_read_reg(AR531X_PROC1);
1681 + u32 proc_addr = ar231x_read_reg(AR531X_PROCADDR); /* clears error */
1682 + u32 dma1 = ar231x_read_reg(AR531X_DMA1);
1683 + u32 dma_addr = ar231x_read_reg(AR531X_DMAADDR); /* clears error */
1684 +
1685 + pr_emerg("AHB interrupt: PROCADDR=0x%8.8x PROC1=0x%8.8x "
1686 + "DMAADDR=0x%8.8x DMA1=0x%8.8x\n", proc_addr, proc1, dma_addr,
1687 + dma1);
1688 +
1689 + machine_restart("AHB error"); /* Catastrophic failure */
1690 + return IRQ_HANDLED;
1691 +}
1692 +
1693 +
1694 +static struct irqaction ar5312_ahb_proc_interrupt = {
1695 + .handler = ar5312_ahb_proc_handler,
1696 + .name = "ar5312_ahb_proc_interrupt",
1697 +};
1698 +
1699 +
1700 +static struct irqaction cascade = {
1701 + .handler = no_action,
1702 + .name = "cascade",
1703 +};
1704 +
1705 +void __init ar5312_irq_init(void)
1706 +{
1707 + int i;
1708 +
1709 + if (!is_5312())
1710 + return;
1711 +
1712 + ar231x_irq_dispatch = ar5312_irq_dispatch;
1713 + for (i = 0; i < AR531X_MISC_IRQ_COUNT; i++) {
1714 + int irq = AR531X_MISC_IRQ_BASE + i;
1715 + irq_set_chip_and_handler(irq, &ar5312_misc_intr_controller,
1716 + handle_level_irq);
1717 + }
1718 + setup_irq(AR531X_MISC_IRQ_AHB_PROC, &ar5312_ahb_proc_interrupt);
1719 + setup_irq(AR5312_IRQ_MISC_INTRS, &cascade);
1720 +}
1721 +
1722 +static u32
1723 +ar5312_gpio_set_output(u32 mask, u32 val)
1724 +{
1725 + u32 reg;
1726 +
1727 + reg = ar231x_read_reg(AR531X_GPIO_CR);
1728 + reg |= mask;
1729 + reg &= ~val;
1730 + ar231x_write_reg(AR531X_GPIO_CR, reg);
1731 + return reg;
1732 +}
1733 +
1734 +static u32
1735 +ar5312_gpio_get(u32 valid_mask)
1736 +{
1737 + u32 reg;
1738 + reg = ar231x_read_reg(AR531X_GPIO_DI);
1739 + reg &= valid_mask;
1740 + return reg;
1741 +}
1742 +
1743 +static u32
1744 +ar5312_gpio_set(u32 mask, u32 value)
1745 +{
1746 + u32 reg;
1747 + reg = ar231x_read_reg(AR531X_GPIO_DO);
1748 + reg &= ~mask;
1749 + reg |= value;
1750 + ar231x_write_reg(AR531X_GPIO_DO, reg);
1751 + return reg;
1752 +}
1753 +
1754 +/*
1755 + * gpiolib implementations. Original mask based methods preserved
1756 + */
1757 +static int
1758 +ar5312_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
1759 +{
1760 + struct ar231x_gpio_chip *gpch =
1761 + container_of(chip, struct ar231x_gpio_chip, chip);
1762 + u32 mask = 1 << gpio;
1763 + u32 rett;
1764 + if (!(gpch->valid_mask & mask))
1765 + return 0;
1766 + rett = ar5312_gpio_get(gpch->valid_mask);
1767 + return !!(rett & mask);
1768 +}
1769 +
1770 +static void
1771 +ar5312_gpio_set_value(struct gpio_chip *chip, unsigned gpio, int value)
1772 +{
1773 + struct ar231x_gpio_chip *gpch =
1774 + container_of(chip, struct ar231x_gpio_chip, chip);
1775 + u32 mask = 1 << gpio;
1776 + if (!(gpch->valid_mask & mask))
1777 + return;
1778 + ar5312_gpio_set(mask, (!!value) * mask);
1779 +}
1780 +
1781 +static int
1782 +ar5312_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
1783 +{
1784 + struct ar231x_gpio_chip *gpch =
1785 + container_of(chip, struct ar231x_gpio_chip, chip);
1786 + u32 mask = 1 << gpio;
1787 + if (!(gpch->valid_mask & mask))
1788 + return -ENXIO;
1789 + ar5312_gpio_set_output(mask, 0);
1790 + return 0;
1791 +}
1792 +static int
1793 +ar5312_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, int value)
1794 +{
1795 + struct ar231x_gpio_chip *gpch =
1796 + container_of(chip, struct ar231x_gpio_chip, chip);
1797 + u32 mask = 1 << gpio;
1798 + if (!(gpch->valid_mask & mask))
1799 + return -ENXIO;
1800 + ar5312_gpio_set_output(mask, mask);
1801 + ar5312_gpio_set(mask, (!!value) * mask);
1802 + return 0;
1803 +}
1804 +
1805 +static struct ar231x_gpio_chip ar5312_gpio_chip = {
1806 + .valid_mask = (1 << 22) - 1,
1807 + .chip = {
1808 + .label = "ar5312-gpio",
1809 + .direction_input = ar5312_gpio_direction_input,
1810 + .direction_output = ar5312_gpio_direction_output,
1811 + .set = ar5312_gpio_set_value,
1812 + .get = ar5312_gpio_get_value,
1813 + .base = 0,
1814 + .ngpio = AR531X_GPIO_IRQ_COUNT, /* 22 */
1815 + }
1816 +};
1817 +
1818 +/* end of gpiolib */
1819 +
1820 +static struct physmap_flash_data ar5312_flash_data = {
1821 + .width = 2,
1822 +};
1823 +
1824 +static struct resource ar5312_flash_resource = {
1825 + .start = AR531X_FLASH,
1826 + .end = AR531X_FLASH + 0x800000 - 1,
1827 + .flags = IORESOURCE_MEM,
1828 +};
1829 +
1830 +static struct ar231x_eth ar5312_eth0_data = {
1831 + .reset_base = AR531X_RESET,
1832 + .reset_mac = AR531X_RESET_ENET0,
1833 + .reset_phy = AR531X_RESET_EPHY0,
1834 + .phy_base = KSEG1ADDR(AR531X_ENET0),
1835 + .config = &ar231x_board,
1836 +};
1837 +
1838 +static struct ar231x_eth ar5312_eth1_data = {
1839 + .reset_base = AR531X_RESET,
1840 + .reset_mac = AR531X_RESET_ENET1,
1841 + .reset_phy = AR531X_RESET_EPHY1,
1842 + .phy_base = KSEG1ADDR(AR531X_ENET1),
1843 + .config = &ar231x_board,
1844 +};
1845 +
1846 +static struct platform_device ar5312_physmap_flash = {
1847 + .name = "physmap-flash",
1848 + .id = 0,
1849 + .dev.platform_data = &ar5312_flash_data,
1850 + .resource = &ar5312_flash_resource,
1851 + .num_resources = 1,
1852 +};
1853 +
1854 +#ifdef CONFIG_LEDS_GPIO
1855 +static struct gpio_led ar5312_leds[] = {
1856 + { .name = "wlan", .gpio = 0, .active_low = 1, },
1857 +};
1858 +
1859 +static const struct gpio_led_platform_data ar5312_led_data = {
1860 + .num_leds = ARRAY_SIZE(ar5312_leds),
1861 + .leds = (void *)ar5312_leds,
1862 +};
1863 +
1864 +static struct platform_device ar5312_gpio_leds = {
1865 + .name = "leds-gpio",
1866 + .id = -1,
1867 + .dev.platform_data = (void *)&ar5312_led_data,
1868 +};
1869 +#endif
1870 +
1871 +/*
1872 + * NB: This mapping size is larger than the actual flash size,
1873 + * but this shouldn't be a problem here, because the flash
1874 + * will simply be mapped multiple times.
1875 + */
1876 +static char __init *ar5312_flash_limit(void)
1877 +{
1878 + u32 ctl;
1879 + /*
1880 + * Configure flash bank 0.
1881 + * Assume 8M window size. Flash will be aliased if it's smaller
1882 + */
1883 + ctl = FLASHCTL_E |
1884 + FLASHCTL_AC_8M |
1885 + FLASHCTL_RBLE |
1886 + (0x01 << FLASHCTL_IDCY_S) |
1887 + (0x07 << FLASHCTL_WST1_S) |
1888 + (0x07 << FLASHCTL_WST2_S) |
1889 + (ar231x_read_reg(AR531X_FLASHCTL0) & FLASHCTL_MW);
1890 +
1891 + ar231x_write_reg(AR531X_FLASHCTL0, ctl);
1892 +
1893 + /* Disable other flash banks */
1894 + ar231x_write_reg(AR531X_FLASHCTL1,
1895 + ar231x_read_reg(AR531X_FLASHCTL1) &
1896 + ~(FLASHCTL_E | FLASHCTL_AC));
1897 +
1898 + ar231x_write_reg(AR531X_FLASHCTL2,
1899 + ar231x_read_reg(AR531X_FLASHCTL2) &
1900 + ~(FLASHCTL_E | FLASHCTL_AC));
1901 +
1902 + return (char *)KSEG1ADDR(AR531X_FLASH + 0x800000);
1903 +}
1904 +
1905 +int __init ar5312_init_devices(void)
1906 +{
1907 + struct ar231x_boarddata *config;
1908 + u32 fctl = 0;
1909 + u8 *c;
1910 +
1911 + if (!is_5312())
1912 + return 0;
1913 +
1914 + /* Locate board/radio config data */
1915 + ar231x_find_config(ar5312_flash_limit());
1916 + config = ar231x_board.config;
1917 +
1918 + /* AR2313 has CPU minor rev. 10 */
1919 + if ((current_cpu_data.processor_id & 0xff) == 0x0a)
1920 + ar231x_devtype = DEV_TYPE_AR2313;
1921 +
1922 + /* AR2312 shares the same Silicon ID as AR5312 */
1923 + else if (config->flags & BD_ISCASPER)
1924 + ar231x_devtype = DEV_TYPE_AR2312;
1925 +
1926 + /* Everything else is probably AR5312 or compatible */
1927 + else
1928 + ar231x_devtype = DEV_TYPE_AR5312;
1929 +
1930 + /* fixup flash width */
1931 + fctl = ar231x_read_reg(AR531X_FLASHCTL) & FLASHCTL_MW;
1932 + switch (fctl) {
1933 + case FLASHCTL_MWx16:
1934 + ar5312_flash_data.width = 2;
1935 + break;
1936 + case FLASHCTL_MWx8:
1937 + default:
1938 + ar5312_flash_data.width = 1;
1939 + break;
1940 + }
1941 +
1942 + platform_device_register(&ar5312_physmap_flash);
1943 +
1944 +#ifdef CONFIG_LEDS_GPIO
1945 + ar5312_leds[0].gpio = config->sys_led_gpio;
1946 + platform_device_register(&ar5312_gpio_leds);
1947 +#endif
1948 +
1949 + /* Fix up MAC addresses if necessary */
1950 + if (!memcmp(config->enet0_mac, "\xff\xff\xff\xff\xff\xff", 6))
1951 + memcpy(config->enet0_mac, config->enet1_mac, 6);
1952 +
1953 + /* If ENET0 and ENET1 have the same mac address,
1954 + * increment the one from ENET1 */
1955 + if (memcmp(config->enet0_mac, config->enet1_mac, 6) == 0) {
1956 + c = config->enet1_mac + 5;
1957 + while ((c >= config->enet1_mac) && !(++(*c)))
1958 + c--;
1959 + }
1960 +
1961 + switch (ar231x_devtype) {
1962 + case DEV_TYPE_AR5312:
1963 + ar5312_eth0_data.macaddr = config->enet0_mac;
1964 + ar231x_add_ethernet(0, KSEG1ADDR(AR531X_ENET0),
1965 + AR5312_IRQ_ENET0_INTRS, &ar5312_eth0_data);
1966 +
1967 + ar5312_eth1_data.macaddr = config->enet1_mac;
1968 + ar231x_add_ethernet(1, KSEG1ADDR(AR531X_ENET1),
1969 + AR5312_IRQ_ENET1_INTRS, &ar5312_eth1_data);
1970 +
1971 + if (!ar231x_board.radio)
1972 + return 0;
1973 +
1974 + if (!(config->flags & BD_WLAN0))
1975 + break;
1976 +
1977 + ar231x_add_wmac(0, AR531X_WLAN0, AR5312_IRQ_WLAN0_INTRS);
1978 + break;
1979 + /*
1980 + * AR2312/3 ethernet uses the PHY of ENET0, but the MAC
1981 + * of ENET1. Atheros calls it 'twisted' for a reason :)
1982 + */
1983 + case DEV_TYPE_AR2312:
1984 + case DEV_TYPE_AR2313:
1985 + ar5312_eth1_data.phy_base = ar5312_eth0_data.phy_base;
1986 + ar5312_eth1_data.reset_phy = ar5312_eth0_data.reset_phy;
1987 + ar5312_eth1_data.macaddr = config->enet0_mac;
1988 + ar231x_add_ethernet(0, KSEG1ADDR(AR531X_ENET1),
1989 + AR5312_IRQ_ENET1_INTRS, &ar5312_eth1_data);
1990 +
1991 + if (!ar231x_board.radio)
1992 + return 0;
1993 + break;
1994 + default:
1995 + break;
1996 + }
1997 +
1998 + if (config->flags & BD_WLAN1)
1999 + ar231x_add_wmac(1, AR531X_WLAN1, AR5312_IRQ_WLAN1_INTRS);
2000 +
2001 + return 0;
2002 +}
2003 +
2004 +
2005 +static void ar5312_restart(char *command)
2006 +{
2007 + /* reset the system */
2008 + local_irq_disable();
2009 + while (1)
2010 + ar231x_write_reg(AR531X_RESET, AR531X_RESET_SYSTEM);
2011 +}
2012 +
2013 +
2014 +/*
2015 + * This table is indexed by bits 5..4 of the CLOCKCTL1 register
2016 + * to determine the predevisor value.
2017 + */
2018 +static int clockctl1_predivide_table[4] __initdata = { 1, 2, 4, 5 };
2019 +
2020 +
2021 +static int __init
2022 +ar5312_cpu_frequency(void)
2023 +{
2024 + unsigned int scratch;
2025 + unsigned int predivide_mask, predivide_shift;
2026 + unsigned int multiplier_mask, multiplier_shift;
2027 + unsigned int clock_ctl1, predivide_select, predivisor, multiplier;
2028 + unsigned int doubler_mask;
2029 + u16 devid;
2030 +
2031 + /* Trust the bootrom's idea of cpu frequency. */
2032 + scratch = ar231x_read_reg(AR5312_SCRATCH);
2033 + if (scratch)
2034 + return scratch;
2035 +
2036 + devid = ar231x_read_reg(AR531X_REV);
2037 + devid &= AR531X_REV_MAJ;
2038 + devid >>= AR531X_REV_MAJ_S;
2039 + if (devid == AR531X_REV_MAJ_AR2313) {
2040 + predivide_mask = AR2313_CLOCKCTL1_PREDIVIDE_MASK;
2041 + predivide_shift = AR2313_CLOCKCTL1_PREDIVIDE_SHIFT;
2042 + multiplier_mask = AR2313_CLOCKCTL1_MULTIPLIER_MASK;
2043 + multiplier_shift = AR2313_CLOCKCTL1_MULTIPLIER_SHIFT;
2044 + doubler_mask = AR2313_CLOCKCTL1_DOUBLER_MASK;
2045 + } else { /* AR5312 and AR2312 */
2046 + predivide_mask = AR5312_CLOCKCTL1_PREDIVIDE_MASK;
2047 + predivide_shift = AR5312_CLOCKCTL1_PREDIVIDE_SHIFT;
2048 + multiplier_mask = AR5312_CLOCKCTL1_MULTIPLIER_MASK;
2049 + multiplier_shift = AR5312_CLOCKCTL1_MULTIPLIER_SHIFT;
2050 + doubler_mask = AR5312_CLOCKCTL1_DOUBLER_MASK;
2051 + }
2052 +
2053 + /*
2054 + * Clocking is derived from a fixed 40MHz input clock.
2055 + *
2056 + * cpu_freq = input_clock * MULT (where MULT is PLL multiplier)
2057 + * sys_freq = cpu_freq / 4 (used for APB clock, serial,
2058 + * flash, Timer, Watchdog Timer)
2059 + *
2060 + * cnt_freq = cpu_freq / 2 (use for CPU count/compare)
2061 + *
2062 + * So, for example, with a PLL multiplier of 5, we have
2063 + *
2064 + * cpu_freq = 200MHz
2065 + * sys_freq = 50MHz
2066 + * cnt_freq = 100MHz
2067 + *
2068 + * We compute the CPU frequency, based on PLL settings.
2069 + */
2070 +
2071 + clock_ctl1 = ar231x_read_reg(AR5312_CLOCKCTL1);
2072 + predivide_select = (clock_ctl1 & predivide_mask) >> predivide_shift;
2073 + predivisor = clockctl1_predivide_table[predivide_select];
2074 + multiplier = (clock_ctl1 & multiplier_mask) >> multiplier_shift;
2075 +
2076 + if (clock_ctl1 & doubler_mask)
2077 + multiplier = multiplier << 1;
2078 +
2079 + return (40000000 / predivisor) * multiplier;
2080 +}
2081 +
2082 +static inline int
2083 +ar5312_sys_frequency(void)
2084 +{
2085 + return ar5312_cpu_frequency() / 4;
2086 +}
2087 +
2088 +void __init
2089 +ar5312_time_init(void)
2090 +{
2091 + if (!is_5312())
2092 + return;
2093 +
2094 + mips_hpt_frequency = ar5312_cpu_frequency() / 2;
2095 +}
2096 +
2097 +int __init
2098 +ar5312_gpio_init(void)
2099 +{
2100 + int ret;
2101 + struct ar231x_gpio_chip *gpch;
2102 + gpch = &ar5312_gpio_chip;
2103 + ret = gpiochip_add(&gpch->chip);
2104 + if (ret) {
2105 + pr_err("%s: failed to add gpiochip\n", gpch->chip.label);
2106 + return ret;
2107 + }
2108 + pr_info("%s: registered %d GPIOs\n", gpch->chip.label,
2109 + gpch->chip.ngpio);
2110 + return ret;
2111 +}
2112 +
2113 +void __init
2114 +ar5312_prom_init(void)
2115 +{
2116 + u32 memsize, memcfg, bank0AC, bank1AC;
2117 + u32 devid;
2118 +
2119 + if (!is_5312())
2120 + return;
2121 +
2122 + /* Detect memory size */
2123 + memcfg = ar231x_read_reg(AR531X_MEM_CFG1);
2124 + bank0AC = (memcfg & MEM_CFG1_AC0) >> MEM_CFG1_AC0_S;
2125 + bank1AC = (memcfg & MEM_CFG1_AC1) >> MEM_CFG1_AC1_S;
2126 + memsize = (bank0AC ? (1 << (bank0AC+1)) : 0) +
2127 + (bank1AC ? (1 << (bank1AC+1)) : 0);
2128 + memsize <<= 20;
2129 + add_memory_region(0, memsize, BOOT_MEM_RAM);
2130 +
2131 + devid = ar231x_read_reg(AR531X_REV);
2132 + devid >>= AR531X_REV_WMAC_MIN_S;
2133 + devid &= AR531X_REV_CHIP;
2134 + ar231x_board.devid = (u16) devid;
2135 + ar5312_gpio_init();
2136 +}
2137 +
2138 +void __init
2139 +ar5312_plat_setup(void)
2140 +{
2141 + if (!is_5312())
2142 + return;
2143 +
2144 + /* Clear any lingering AHB errors */
2145 + ar231x_read_reg(AR531X_PROCADDR);
2146 + ar231x_read_reg(AR531X_DMAADDR);
2147 + ar231x_write_reg(AR531X_WD_CTRL, AR531X_WD_CTRL_IGNORE_EXPIRATION);
2148 +
2149 + _machine_restart = ar5312_restart;
2150 + ar231x_serial_setup(KSEG1ADDR(AR531X_UART0), ar5312_sys_frequency());
2151 +}
2152 +
2153 --- /dev/null
2154 +++ b/arch/mips/ar231x/ar2315.c
2155 @@ -0,0 +1,623 @@
2156 +/*
2157 + * This file is subject to the terms and conditions of the GNU General Public
2158 + * License. See the file "COPYING" in the main directory of this archive
2159 + * for more details.
2160 + *
2161 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
2162 + * Copyright (C) 2006 FON Technology, SL.
2163 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
2164 + * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
2165 + * Copyright (C) 2012 Alexandros C. Couloumbis <alex@ozo.com>
2166 + */
2167 +
2168 +/*
2169 + * Platform devices for Atheros SoCs
2170 + */
2171 +
2172 +#include <generated/autoconf.h>
2173 +#include <linux/init.h>
2174 +#include <linux/module.h>
2175 +#include <linux/types.h>
2176 +#include <linux/string.h>
2177 +#include <linux/platform_device.h>
2178 +#include <linux/kernel.h>
2179 +#include <linux/reboot.h>
2180 +#include <linux/delay.h>
2181 +#include <linux/leds.h>
2182 +#include <linux/gpio.h>
2183 +#include <asm/bootinfo.h>
2184 +#include <asm/reboot.h>
2185 +#include <asm/time.h>
2186 +#include <linux/irq.h>
2187 +#include <linux/io.h>
2188 +
2189 +#include <ar231x_platform.h>
2190 +#include <ar2315_regs.h>
2191 +#include <ar231x.h>
2192 +#include "devices.h"
2193 +#include "ar2315.h"
2194 +
2195 +static u32 gpiointmask, gpiointval;
2196 +
2197 +static inline void ar2315_gpio_irq(void)
2198 +{
2199 + u32 pend;
2200 + int bit = -1;
2201 +
2202 + /* only do one gpio interrupt at a time */
2203 + pend = (ar231x_read_reg(AR2315_GPIO_DI) ^ gpiointval) & gpiointmask;
2204 +
2205 + if (pend) {
2206 + bit = fls(pend) - 1;
2207 + pend &= ~(1 << bit);
2208 + gpiointval ^= (1 << bit);
2209 + }
2210 +
2211 + if (!pend)
2212 + ar231x_write_reg(AR2315_ISR, AR2315_ISR_GPIO);
2213 +
2214 + /* Enable interrupt with edge detection */
2215 + if ((ar231x_read_reg(AR2315_GPIO_CR) & AR2315_GPIO_CR_M(bit)) !=
2216 + AR2315_GPIO_CR_I(bit))
2217 + return;
2218 +
2219 + if (bit >= 0)
2220 + do_IRQ(AR531X_GPIO_IRQ_BASE + bit);
2221 +}
2222 +
2223 +
2224 +/*
2225 + * Called when an interrupt is received, this function
2226 + * determines exactly which interrupt it was, and it
2227 + * invokes the appropriate handler.
2228 + *
2229 + * Implicitly, we also define interrupt priority by
2230 + * choosing which to dispatch first.
2231 + */
2232 +static asmlinkage void
2233 +ar2315_irq_dispatch(void)
2234 +{
2235 + int pending = read_c0_status() & read_c0_cause();
2236 +
2237 + if (pending & CAUSEF_IP3)
2238 + do_IRQ(AR2315_IRQ_WLAN0_INTRS);
2239 + else if (pending & CAUSEF_IP4)
2240 + do_IRQ(AR2315_IRQ_ENET0_INTRS);
2241 + else if (pending & CAUSEF_IP2) {
2242 + unsigned int misc_intr = ar231x_read_reg(AR2315_ISR) &
2243 + ar231x_read_reg(AR2315_IMR);
2244 +
2245 + if (misc_intr & AR2315_ISR_SPI)
2246 + do_IRQ(AR531X_MISC_IRQ_SPI);
2247 + else if (misc_intr & AR2315_ISR_TIMER)
2248 + do_IRQ(AR531X_MISC_IRQ_TIMER);
2249 + else if (misc_intr & AR2315_ISR_AHB)
2250 + do_IRQ(AR531X_MISC_IRQ_AHB_PROC);
2251 + else if (misc_intr & AR2315_ISR_GPIO)
2252 + ar2315_gpio_irq();
2253 + else if (misc_intr & AR2315_ISR_UART0)
2254 + do_IRQ(AR531X_MISC_IRQ_UART0);
2255 + else if (misc_intr & AR2315_ISR_WD)
2256 + do_IRQ(AR531X_MISC_IRQ_WATCHDOG);
2257 + else
2258 + do_IRQ(AR531X_MISC_IRQ_NONE);
2259 + } else if (pending & CAUSEF_IP7)
2260 + do_IRQ(AR531X_IRQ_CPU_CLOCK);
2261 +}
2262 +
2263 +static void ar2315_set_gpiointmask(int gpio, int level)
2264 +{
2265 + u32 reg;
2266 +
2267 + reg = ar231x_read_reg(AR2315_GPIO_INT);
2268 + reg &= ~(AR2315_GPIO_INT_M | AR2315_GPIO_INT_LVL_M);
2269 + reg |= gpio | AR2315_GPIO_INT_LVL(level);
2270 + ar231x_write_reg(AR2315_GPIO_INT, reg);
2271 +}
2272 +
2273 +static void ar2315_gpio_intr_enable(struct irq_data *d)
2274 +{
2275 + unsigned int gpio = d->irq - AR531X_GPIO_IRQ_BASE;
2276 +
2277 + /* Enable interrupt with edge detection */
2278 + if ((ar231x_read_reg(AR2315_GPIO_CR) & AR2315_GPIO_CR_M(gpio)) !=
2279 + AR2315_GPIO_CR_I(gpio))
2280 + return;
2281 +
2282 + gpiointmask |= (1 << gpio);
2283 + ar2315_set_gpiointmask(gpio, 3);
2284 +}
2285 +
2286 +static void ar2315_gpio_intr_disable(struct irq_data *d)
2287 +{
2288 + unsigned int gpio = d->irq - AR531X_GPIO_IRQ_BASE;
2289 +
2290 + /* Disable interrupt */
2291 + gpiointmask &= ~(1 << gpio);
2292 + ar2315_set_gpiointmask(gpio, 0);
2293 +}
2294 +
2295 +static struct irq_chip ar2315_gpio_intr_controller = {
2296 + .irq_mask = ar2315_gpio_intr_disable,
2297 + .irq_unmask = ar2315_gpio_intr_enable,
2298 +};
2299 +
2300 +static void
2301 +ar2315_misc_intr_enable(struct irq_data *d)
2302 +{
2303 + unsigned int imr;
2304 +
2305 + imr = ar231x_read_reg(AR2315_IMR);
2306 + switch (d->irq) {
2307 + case AR531X_MISC_IRQ_SPI:
2308 + imr |= AR2315_ISR_SPI;
2309 + break;
2310 + case AR531X_MISC_IRQ_TIMER:
2311 + imr |= AR2315_ISR_TIMER;
2312 + break;
2313 + case AR531X_MISC_IRQ_AHB_PROC:
2314 + imr |= AR2315_ISR_AHB;
2315 + break;
2316 + case AR531X_MISC_IRQ_GPIO:
2317 + imr |= AR2315_ISR_GPIO;
2318 + break;
2319 + case AR531X_MISC_IRQ_UART0:
2320 + imr |= AR2315_ISR_UART0;
2321 + break;
2322 + case AR531X_MISC_IRQ_WATCHDOG:
2323 + imr |= AR2315_ISR_WD;
2324 + break;
2325 + default:
2326 + break;
2327 + }
2328 + ar231x_write_reg(AR2315_IMR, imr);
2329 +}
2330 +
2331 +static void
2332 +ar2315_misc_intr_disable(struct irq_data *d)
2333 +{
2334 + unsigned int imr;
2335 +
2336 + imr = ar231x_read_reg(AR2315_IMR);
2337 + switch (d->irq) {
2338 + case AR531X_MISC_IRQ_SPI:
2339 + imr &= ~AR2315_ISR_SPI;
2340 + break;
2341 + case AR531X_MISC_IRQ_TIMER:
2342 + imr &= ~AR2315_ISR_TIMER;
2343 + break;
2344 + case AR531X_MISC_IRQ_AHB_PROC:
2345 + imr &= ~AR2315_ISR_AHB;
2346 + break;
2347 + case AR531X_MISC_IRQ_GPIO:
2348 + imr &= ~AR2315_ISR_GPIO;
2349 + break;
2350 + case AR531X_MISC_IRQ_UART0:
2351 + imr &= ~AR2315_ISR_UART0;
2352 + break;
2353 + case AR531X_MISC_IRQ_WATCHDOG:
2354 + imr &= ~AR2315_ISR_WD;
2355 + break;
2356 + default:
2357 + break;
2358 + }
2359 + ar231x_write_reg(AR2315_IMR, imr);
2360 +}
2361 +
2362 +static struct irq_chip ar2315_misc_intr_controller = {
2363 + .irq_mask = ar2315_misc_intr_disable,
2364 + .irq_unmask = ar2315_misc_intr_enable,
2365 +};
2366 +
2367 +static irqreturn_t ar2315_ahb_proc_handler(int cpl, void *dev_id)
2368 +{
2369 + ar231x_write_reg(AR2315_AHB_ERR0, AHB_ERROR_DET);
2370 + ar231x_read_reg(AR2315_AHB_ERR1);
2371 +
2372 + pr_emerg("AHB fatal error\n");
2373 + machine_restart("AHB error"); /* Catastrophic failure */
2374 +
2375 + return IRQ_HANDLED;
2376 +}
2377 +
2378 +static struct irqaction ar2315_ahb_proc_interrupt = {
2379 + .handler = ar2315_ahb_proc_handler,
2380 + .name = "ar2315_ahb_proc_interrupt",
2381 +};
2382 +
2383 +static struct irqaction cascade = {
2384 + .handler = no_action,
2385 + .name = "cascade",
2386 +};
2387 +
2388 +void
2389 +ar2315_irq_init(void)
2390 +{
2391 + int i;
2392 +
2393 + if (!is_2315())
2394 + return;
2395 +
2396 + ar231x_irq_dispatch = ar2315_irq_dispatch;
2397 + gpiointval = ar231x_read_reg(AR2315_GPIO_DI);
2398 + for (i = 0; i < AR531X_MISC_IRQ_COUNT; i++) {
2399 + int irq = AR531X_MISC_IRQ_BASE + i;
2400 + irq_set_chip_and_handler(irq, &ar2315_misc_intr_controller,
2401 + handle_level_irq);
2402 + }
2403 + for (i = 0; i < AR531X_GPIO_IRQ_COUNT; i++) {
2404 + int irq = AR531X_GPIO_IRQ_BASE + i;
2405 + irq_set_chip_and_handler(irq, &ar2315_gpio_intr_controller,
2406 + handle_level_irq);
2407 + }
2408 + setup_irq(AR531X_MISC_IRQ_GPIO, &cascade);
2409 + setup_irq(AR531X_MISC_IRQ_AHB_PROC, &ar2315_ahb_proc_interrupt);
2410 + setup_irq(AR2315_IRQ_MISC_INTRS, &cascade);
2411 +}
2412 +
2413 +static u32
2414 +ar2315_gpio_set_output(u32 mask, u32 val)
2415 +{
2416 + u32 reg;
2417 +
2418 + reg = ar231x_read_reg(AR2315_GPIO_CR);
2419 + reg &= ~mask;
2420 + reg |= val;
2421 + ar231x_write_reg(AR2315_GPIO_CR, reg);
2422 + return reg;
2423 +}
2424 +
2425 +static u32
2426 +ar2315_gpio_get(u32 valid_mask)
2427 +{
2428 + u32 reg;
2429 + reg = ar231x_read_reg(AR2315_GPIO_DI);
2430 + reg &= valid_mask;
2431 + return reg;
2432 +}
2433 +
2434 +static u32
2435 +ar2315_gpio_set(u32 mask, u32 value)
2436 +{
2437 + u32 reg;
2438 + reg = ar231x_read_reg(AR2315_GPIO_DO);
2439 + reg &= ~mask;
2440 + reg |= value;
2441 + ar231x_write_reg(AR2315_GPIO_DO, reg);
2442 + return reg;
2443 +}
2444 +
2445 +/*
2446 + * gpiolib implementation. Original legacy mask based methods
2447 + * preserved for now.
2448 + */
2449 +static int
2450 +ar2315_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
2451 +{
2452 + struct ar231x_gpio_chip *gpch =
2453 + container_of(chip, struct ar231x_gpio_chip, chip);
2454 + u32 mask = 1 << gpio;
2455 + u32 rett;
2456 + if (!(gpch->valid_mask & mask))
2457 + return 0;
2458 + rett = ar2315_gpio_get(gpch->valid_mask); /* legacy code */
2459 + return !!(rett & mask);
2460 +}
2461 +
2462 +static void
2463 +ar2315_gpio_set_value(struct gpio_chip *chip, unsigned gpio, int value)
2464 +{
2465 + struct ar231x_gpio_chip *gpch =
2466 + container_of(chip, struct ar231x_gpio_chip, chip);
2467 + u32 mask = 1 << gpio;
2468 + if (!(gpch->valid_mask & mask))
2469 + return;
2470 + ar2315_gpio_set(mask, (!!value) * mask); /* legacy */
2471 +}
2472 +
2473 +static int
2474 +ar2315_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
2475 +{
2476 + struct ar231x_gpio_chip *gpch =
2477 + container_of(chip, struct ar231x_gpio_chip, chip);
2478 + u32 mask = 1 << gpio;
2479 + if (!(gpch->valid_mask & mask))
2480 + return -ENXIO;
2481 + ar2315_gpio_set_output(mask, 0); /* legacy */
2482 + return 0;
2483 +}
2484 +
2485 +static int
2486 +ar2315_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, int value)
2487 +{
2488 + struct ar231x_gpio_chip *gpch =
2489 + container_of(chip, struct ar231x_gpio_chip, chip);
2490 + u32 mask = 1 << gpio;
2491 + if (!(gpch->valid_mask & mask))
2492 + return -ENXIO;
2493 + ar2315_gpio_set_output(mask, mask); /* both legacy */
2494 + ar2315_gpio_set(mask, (!!value) * mask);
2495 + return 0;
2496 +}
2497 +
2498 +static struct ar231x_gpio_chip ar2315_gpio_chip = {
2499 + .valid_mask = (1 << 22) - 1,
2500 + .chip = {
2501 + .label = "ar2315-gpio",
2502 + .direction_input = ar2315_gpio_direction_input,
2503 + .direction_output = ar2315_gpio_direction_output,
2504 + .set = ar2315_gpio_set_value,
2505 + .get = ar2315_gpio_get_value,
2506 + .base = 0,
2507 + .ngpio = AR531X_GPIO_IRQ_COUNT, /* 22 */
2508 + }
2509 +};
2510 +
2511 +/* end of gpiolib */
2512 +
2513 +
2514 +static struct ar231x_eth ar2315_eth_data = {
2515 + .reset_base = AR2315_RESET,
2516 + .reset_mac = AR2315_RESET_ENET0,
2517 + .reset_phy = AR2315_RESET_EPHY0,
2518 + .phy_base = KSEG1ADDR(AR2315_ENET0),
2519 + .config = &ar231x_board,
2520 +};
2521 +
2522 +static struct resource ar2315_spiflash_res[] = {
2523 + {
2524 + .name = "flash_base",
2525 + .flags = IORESOURCE_MEM,
2526 + .start = KSEG1ADDR(AR2315_SPI_READ),
2527 + .end = KSEG1ADDR(AR2315_SPI_READ) + 0x1000000 - 1,
2528 + },
2529 + {
2530 + .name = "flash_regs",
2531 + .flags = IORESOURCE_MEM,
2532 + .start = 0x11300000,
2533 + .end = 0x11300012,
2534 + },
2535 +};
2536 +
2537 +static struct platform_device ar2315_spiflash = {
2538 + .id = 0,
2539 + .name = "spiflash",
2540 + .resource = ar2315_spiflash_res,
2541 + .num_resources = ARRAY_SIZE(ar2315_spiflash_res)
2542 +};
2543 +
2544 +static struct platform_device ar2315_wdt = {
2545 + .id = 0,
2546 + .name = "ar2315_wdt",
2547 +};
2548 +
2549 +/*
2550 + * NB: We use mapping size that is larger than the actual flash size,
2551 + * but this shouldn't be a problem here, because the flash will simply
2552 + * be mapped multiple times.
2553 + */
2554 +static u8 __init *ar2315_flash_limit(void)
2555 +{
2556 + return (u8 *)ar2315_spiflash_res[0].end + 1;
2557 +}
2558 +
2559 +#ifdef CONFIG_LEDS_GPIO
2560 +static struct gpio_led ar2315_leds[6];
2561 +static struct gpio_led_platform_data ar2315_led_data = {
2562 + .leds = (void *)ar2315_leds,
2563 +};
2564 +
2565 +static struct platform_device ar2315_gpio_leds = {
2566 + .name = "leds-gpio",
2567 + .id = -1,
2568 + .dev = {
2569 + .platform_data = (void *)&ar2315_led_data,
2570 + }
2571 +};
2572 +
2573 +static void __init
2574 +ar2315_init_gpio_leds(void)
2575 +{
2576 + static char led_names[6][6];
2577 + int i, led = 0;
2578 +
2579 + ar2315_led_data.num_leds = 0;
2580 + for (i = 1; i < 8; i++) {
2581 + if ((i == AR2315_RESET_GPIO) ||
2582 + (i == ar231x_board.config->reset_config_gpio))
2583 + continue;
2584 +
2585 + if (i == ar231x_board.config->sys_led_gpio)
2586 + strcpy(led_names[led], "wlan");
2587 + else
2588 + sprintf(led_names[led], "gpio%d", i);
2589 +
2590 + ar2315_leds[led].name = led_names[led];
2591 + ar2315_leds[led].gpio = i;
2592 + ar2315_leds[led].active_low = 0;
2593 + led++;
2594 + }
2595 + ar2315_led_data.num_leds = led;
2596 + platform_device_register(&ar2315_gpio_leds);
2597 +}
2598 +#else
2599 +static inline void ar2315_init_gpio_leds(void)
2600 +{
2601 +}
2602 +#endif
2603 +
2604 +int __init
2605 +ar2315_init_devices(void)
2606 +{
2607 + if (!is_2315())
2608 + return 0;
2609 +
2610 + /* Find board configuration */
2611 + ar231x_find_config(ar2315_flash_limit());
2612 + ar2315_eth_data.macaddr = ar231x_board.config->enet0_mac;
2613 +
2614 + ar2315_init_gpio_leds();
2615 + platform_device_register(&ar2315_wdt);
2616 + platform_device_register(&ar2315_spiflash);
2617 + ar231x_add_ethernet(0, KSEG1ADDR(AR2315_ENET0), AR2315_IRQ_ENET0_INTRS,
2618 + &ar2315_eth_data);
2619 + ar231x_add_wmac(0, AR2315_WLAN0, AR2315_IRQ_WLAN0_INTRS);
2620 +
2621 + return 0;
2622 +}
2623 +
2624 +static void
2625 +ar2315_restart(char *command)
2626 +{
2627 + void (*mips_reset_vec)(void) = (void *)0xbfc00000;
2628 +
2629 + local_irq_disable();
2630 +
2631 + /* try reset the system via reset control */
2632 + ar231x_write_reg(AR2315_COLD_RESET, AR2317_RESET_SYSTEM);
2633 +
2634 + /* Cold reset does not work on the AR2315/6, use the GPIO reset bits
2635 + * a workaround. Give it some time to attempt a gpio based hardware
2636 + * reset (atheros reference design workaround) */
2637 + gpio_request_one(AR2315_RESET_GPIO, GPIOF_OUT_INIT_LOW, "Reset");
2638 + mdelay(100);
2639 +
2640 + /* Some boards (e.g. Senao EOC-2610) don't implement the reset logic
2641 + * workaround. Attempt to jump to the mips reset location -
2642 + * the boot loader itself might be able to recover the system */
2643 + mips_reset_vec();
2644 +}
2645 +
2646 +
2647 +/*
2648 + * This table is indexed by bits 5..4 of the CLOCKCTL1 register
2649 + * to determine the predevisor value.
2650 + */
2651 +static int clockctl1_predivide_table[4] __initdata = { 1, 2, 4, 5 };
2652 +static int pllc_divide_table[5] __initdata = { 2, 3, 4, 6, 3 };
2653 +
2654 +static unsigned int __init
2655 +ar2315_sys_clk(unsigned int clock_ctl)
2656 +{
2657 + unsigned int pllc_ctrl, cpu_div;
2658 + unsigned int pllc_out, refdiv, fdiv, divby2;
2659 + unsigned int clk_div;
2660 +
2661 + pllc_ctrl = ar231x_read_reg(AR2315_PLLC_CTL);
2662 + refdiv = (pllc_ctrl & PLLC_REF_DIV_M) >> PLLC_REF_DIV_S;
2663 + refdiv = clockctl1_predivide_table[refdiv];
2664 + fdiv = (pllc_ctrl & PLLC_FDBACK_DIV_M) >> PLLC_FDBACK_DIV_S;
2665 + divby2 = (pllc_ctrl & PLLC_ADD_FDBACK_DIV_M) >> PLLC_ADD_FDBACK_DIV_S;
2666 + divby2 += 1;
2667 + pllc_out = (40000000/refdiv)*(2*divby2)*fdiv;
2668 +
2669 + /* clkm input selected */
2670 + switch (clock_ctl & CPUCLK_CLK_SEL_M) {
2671 + case 0:
2672 + case 1:
2673 + clk_div = pllc_divide_table[(pllc_ctrl & PLLC_CLKM_DIV_M) >>
2674 + PLLC_CLKM_DIV_S];
2675 + break;
2676 + case 2:
2677 + clk_div = pllc_divide_table[(pllc_ctrl & PLLC_CLKC_DIV_M) >>
2678 + PLLC_CLKC_DIV_S];
2679 + break;
2680 + default:
2681 + pllc_out = 40000000;
2682 + clk_div = 1;
2683 + break;
2684 + }
2685 +
2686 + cpu_div = (clock_ctl & CPUCLK_CLK_DIV_M) >> CPUCLK_CLK_DIV_S;
2687 + cpu_div = cpu_div * 2 ?: 1;
2688 +
2689 + return pllc_out / (clk_div * cpu_div);
2690 +}
2691 +
2692 +static inline unsigned int
2693 +ar2315_cpu_frequency(void)
2694 +{
2695 + return ar2315_sys_clk(ar231x_read_reg(AR2315_CPUCLK));
2696 +}
2697 +
2698 +static inline unsigned int
2699 +ar2315_apb_frequency(void)
2700 +{
2701 + return ar2315_sys_clk(ar231x_read_reg(AR2315_AMBACLK));
2702 +}
2703 +
2704 +void __init
2705 +ar2315_time_init(void)
2706 +{
2707 + if (!is_2315())
2708 + return;
2709 +
2710 + mips_hpt_frequency = ar2315_cpu_frequency() / 2;
2711 +}
2712 +
2713 +int __init
2714 +ar2315_gpio_init(void)
2715 +{
2716 + int ret;
2717 + struct ar231x_gpio_chip *gpch;
2718 + gpch = &ar2315_gpio_chip;
2719 + ret = gpiochip_add(&gpch->chip);
2720 + if (ret) {
2721 + pr_err("%s: failed to add gpiochip\n", gpch->chip.label);
2722 + return ret;
2723 + }
2724 + pr_info("%s: registered %d GPIOs\n", gpch->chip.label,
2725 + gpch->chip.ngpio);
2726 + return ret;
2727 +}
2728 +
2729 +
2730 +
2731 +void __init
2732 +ar2315_prom_init(void)
2733 +{
2734 + u32 memsize, memcfg, devid;
2735 +
2736 + if (!is_2315())
2737 + return;
2738 +
2739 + memcfg = ar231x_read_reg(AR2315_MEM_CFG);
2740 + memsize = 1 + ((memcfg & SDRAM_DATA_WIDTH_M) >> SDRAM_DATA_WIDTH_S);
2741 + memsize <<= 1 + ((memcfg & SDRAM_COL_WIDTH_M) >> SDRAM_COL_WIDTH_S);
2742 + memsize <<= 1 + ((memcfg & SDRAM_ROW_WIDTH_M) >> SDRAM_ROW_WIDTH_S);
2743 + memsize <<= 3;
2744 + add_memory_region(0, memsize, BOOT_MEM_RAM);
2745 +
2746 + /* Detect the hardware based on the device ID */
2747 + devid = ar231x_read_reg(AR2315_SREV) & AR2315_REV_CHIP;
2748 + switch (devid) {
2749 + case 0x90:
2750 + case 0x91:
2751 + ar231x_devtype = DEV_TYPE_AR2317;
2752 + break;
2753 + default:
2754 + ar231x_devtype = DEV_TYPE_AR2315;
2755 + break;
2756 + }
2757 + ar2315_gpio_init();
2758 + ar231x_board.devid = devid;
2759 +}
2760 +
2761 +void __init
2762 +ar2315_plat_setup(void)
2763 +{
2764 + u32 config;
2765 +
2766 + if (!is_2315())
2767 + return;
2768 +
2769 + /* Clear any lingering AHB errors */
2770 + config = read_c0_config();
2771 + write_c0_config(config & ~0x3);
2772 + ar231x_write_reg(AR2315_AHB_ERR0, AHB_ERROR_DET);
2773 + ar231x_read_reg(AR2315_AHB_ERR1);
2774 + ar231x_write_reg(AR2315_WDC, AR2315_WDC_IGNORE_EXPIRATION);
2775 +
2776 + _machine_restart = ar2315_restart;
2777 + ar231x_serial_setup(KSEG1ADDR(AR2315_UART0), ar2315_apb_frequency());
2778 +}
2779 --- /dev/null
2780 +++ b/arch/mips/ar231x/ar2315.h
2781 @@ -0,0 +1,37 @@
2782 +#ifndef __AR2315_H
2783 +#define __AR2315_H
2784 +
2785 +#ifdef CONFIG_ATHEROS_AR2315
2786 +
2787 +extern void ar2315_irq_init(void);
2788 +extern int ar2315_init_devices(void);
2789 +extern void ar2315_prom_init(void);
2790 +extern void ar2315_plat_setup(void);
2791 +extern void ar2315_time_init(void);
2792 +
2793 +#else
2794 +
2795 +static inline void ar2315_irq_init(void)
2796 +{
2797 +}
2798 +
2799 +static inline int ar2315_init_devices(void)
2800 +{
2801 + return 0;
2802 +}
2803 +
2804 +static inline void ar2315_prom_init(void)
2805 +{
2806 +}
2807 +
2808 +static inline void ar2315_plat_setup(void)
2809 +{
2810 +}
2811 +
2812 +static inline void ar2315_time_init(void)
2813 +{
2814 +}
2815 +
2816 +#endif
2817 +
2818 +#endif
2819 --- /dev/null
2820 +++ b/arch/mips/ar231x/ar5312.h
2821 @@ -0,0 +1,38 @@
2822 +#ifndef __AR5312_H
2823 +#define __AR5312_H
2824 +
2825 +#ifdef CONFIG_ATHEROS_AR5312
2826 +
2827 +extern void ar5312_irq_init(void);
2828 +extern int ar5312_init_devices(void);
2829 +extern void ar5312_prom_init(void);
2830 +extern void ar5312_plat_setup(void);
2831 +extern void ar5312_time_init(void);
2832 +extern void ar5312_time_init(void);
2833 +
2834 +#else
2835 +
2836 +static inline void ar5312_irq_init(void)
2837 +{
2838 +}
2839 +
2840 +static inline int ar5312_init_devices(void)
2841 +{
2842 + return 0;
2843 +}
2844 +
2845 +static inline void ar5312_prom_init(void)
2846 +{
2847 +}
2848 +
2849 +static inline void ar5312_plat_setup(void)
2850 +{
2851 +}
2852 +
2853 +static inline void ar5312_time_init(void)
2854 +{
2855 +}
2856 +
2857 +#endif
2858 +
2859 +#endif
2860 --- /dev/null
2861 +++ b/arch/mips/include/asm/mach-ar231x/ar231x.h
2862 @@ -0,0 +1,57 @@
2863 +#ifndef __AR531X_H
2864 +#define __AR531X_H
2865 +
2866 +#include <linux/types.h>
2867 +#include <linux/io.h>
2868 +
2869 +#define AR531X_MISC_IRQ_BASE 0x20
2870 +#define AR531X_GPIO_IRQ_BASE 0x30
2871 +
2872 +/* Software's idea of interrupts handled by "CPU Interrupt Controller" */
2873 +#define AR531X_IRQ_NONE (MIPS_CPU_IRQ_BASE+0)
2874 +#define AR531X_IRQ_CPU_CLOCK (MIPS_CPU_IRQ_BASE+7) /* C0_CAUSE: 0x8000 */
2875 +
2876 +/* Miscellaneous interrupts, which share IP6 */
2877 +#define AR531X_MISC_IRQ_NONE (AR531X_MISC_IRQ_BASE+0)
2878 +#define AR531X_MISC_IRQ_TIMER (AR531X_MISC_IRQ_BASE+1)
2879 +#define AR531X_MISC_IRQ_AHB_PROC (AR531X_MISC_IRQ_BASE+2)
2880 +#define AR531X_MISC_IRQ_AHB_DMA (AR531X_MISC_IRQ_BASE+3)
2881 +#define AR531X_MISC_IRQ_GPIO (AR531X_MISC_IRQ_BASE+4)
2882 +#define AR531X_MISC_IRQ_UART0 (AR531X_MISC_IRQ_BASE+5)
2883 +#define AR531X_MISC_IRQ_UART0_DMA (AR531X_MISC_IRQ_BASE+6)
2884 +#define AR531X_MISC_IRQ_WATCHDOG (AR531X_MISC_IRQ_BASE+7)
2885 +#define AR531X_MISC_IRQ_LOCAL (AR531X_MISC_IRQ_BASE+8)
2886 +#define AR531X_MISC_IRQ_SPI (AR531X_MISC_IRQ_BASE+9)
2887 +#define AR531X_MISC_IRQ_COUNT 10
2888 +
2889 +/* GPIO Interrupts [0..7], share AR531X_MISC_IRQ_GPIO */
2890 +#define AR531X_GPIO_IRQ_NONE (AR531X_GPIO_IRQ_BASE+0)
2891 +#define AR531X_GPIO_IRQ(n) (AR531X_GPIO_IRQ_BASE+n)
2892 +#define AR531X_GPIO_IRQ_COUNT 22
2893 +
2894 +static inline u32
2895 +ar231x_read_reg(u32 reg)
2896 +{
2897 + return __raw_readl((u32 *)KSEG1ADDR(reg));
2898 +}
2899 +
2900 +static inline void
2901 +ar231x_write_reg(u32 reg, u32 val)
2902 +{
2903 + __raw_writel(val, (u32 *)KSEG1ADDR(reg));
2904 +}
2905 +
2906 +static inline u32
2907 +ar231x_mask_reg(u32 reg, u32 mask, u32 val)
2908 +{
2909 + u32 ret;
2910 +
2911 + ret = ar231x_read_reg(reg);
2912 + ret &= ~mask;
2913 + ret |= val;
2914 + ar231x_write_reg(reg, ret);
2915 +
2916 + return ret;
2917 +}
2918 +
2919 +#endif
2920 --- /dev/null
2921 +++ b/arch/mips/ar231x/devices.h
2922 @@ -0,0 +1,42 @@
2923 +#ifndef __AR231X_DEVICES_H
2924 +#define __AR231X_DEVICES_H
2925 +#include <linux/gpio.h>
2926 +
2927 +enum {
2928 + /* handled by ar5312.c */
2929 + DEV_TYPE_AR2312,
2930 + DEV_TYPE_AR2313,
2931 + DEV_TYPE_AR5312,
2932 +
2933 + /* handled by ar2315.c */
2934 + DEV_TYPE_AR2315,
2935 + DEV_TYPE_AR2316,
2936 + DEV_TYPE_AR2317,
2937 +
2938 + DEV_TYPE_UNKNOWN
2939 +};
2940 +
2941 +extern int ar231x_devtype;
2942 +extern struct ar231x_board_config ar231x_board;
2943 +extern asmlinkage void (*ar231x_irq_dispatch)(void);
2944 +
2945 +extern int ar231x_find_config(u8 *flash_limit);
2946 +extern void ar231x_serial_setup(u32 mapbase, unsigned int uartclk);
2947 +extern int ar231x_add_wmac(int nr, u32 base, int irq);
2948 +extern int ar231x_add_ethernet(int nr, u32 base, int irq, void *pdata);
2949 +
2950 +static inline bool is_2315(void)
2951 +{
2952 + return (current_cpu_data.cputype == CPU_4KEC);
2953 +}
2954 +
2955 +static inline bool is_5312(void)
2956 +{
2957 + return !is_2315();
2958 +}
2959 +
2960 +struct ar231x_gpio_chip {
2961 + u32 valid_mask;
2962 + struct gpio_chip chip;
2963 +};
2964 +#endif
2965 --- /dev/null
2966 +++ b/arch/mips/ar231x/devices.c
2967 @@ -0,0 +1,168 @@
2968 +#include <linux/kernel.h>
2969 +#include <linux/init.h>
2970 +#include <linux/serial.h>
2971 +#include <linux/serial_core.h>
2972 +#include <linux/serial_8250.h>
2973 +#include <linux/platform_device.h>
2974 +#include <ar231x_platform.h>
2975 +#include <ar231x.h>
2976 +#include "devices.h"
2977 +#include "ar5312.h"
2978 +#include "ar2315.h"
2979 +
2980 +struct ar231x_board_config ar231x_board;
2981 +int ar231x_devtype = DEV_TYPE_UNKNOWN;
2982 +
2983 +static struct resource ar231x_eth0_res[] = {
2984 + {
2985 + .name = "eth0_membase",
2986 + .flags = IORESOURCE_MEM,
2987 + },
2988 + {
2989 + .name = "eth0_irq",
2990 + .flags = IORESOURCE_IRQ,
2991 + }
2992 +};
2993 +
2994 +static struct resource ar231x_eth1_res[] = {
2995 + {
2996 + .name = "eth1_membase",
2997 + .flags = IORESOURCE_MEM,
2998 + },
2999 + {
3000 + .name = "eth1_irq",
3001 + .flags = IORESOURCE_IRQ,
3002 + }
3003 +};
3004 +
3005 +static struct platform_device ar231x_eth[] = {
3006 + {
3007 + .id = 0,
3008 + .name = "ar231x-eth",
3009 + .resource = ar231x_eth0_res,
3010 + .num_resources = ARRAY_SIZE(ar231x_eth0_res)
3011 + },
3012 + {
3013 + .id = 1,
3014 + .name = "ar231x-eth",
3015 + .resource = ar231x_eth1_res,
3016 + .num_resources = ARRAY_SIZE(ar231x_eth1_res)
3017 + }
3018 +};
3019 +
3020 +static struct resource ar231x_wmac0_res[] = {
3021 + {
3022 + .name = "wmac0_membase",
3023 + .flags = IORESOURCE_MEM,
3024 + },
3025 + {
3026 + .name = "wmac0_irq",
3027 + .flags = IORESOURCE_IRQ,
3028 + }
3029 +};
3030 +
3031 +static struct resource ar231x_wmac1_res[] = {
3032 + {
3033 + .name = "wmac1_membase",
3034 + .flags = IORESOURCE_MEM,
3035 + },
3036 + {
3037 + .name = "wmac1_irq",
3038 + .flags = IORESOURCE_IRQ,
3039 + }
3040 +};
3041 +
3042 +
3043 +static struct platform_device ar231x_wmac[] = {
3044 + {
3045 + .id = 0,
3046 + .name = "ar231x-wmac",
3047 + .resource = ar231x_wmac0_res,
3048 + .num_resources = ARRAY_SIZE(ar231x_wmac0_res),
3049 + .dev.platform_data = &ar231x_board,
3050 + },
3051 + {
3052 + .id = 1,
3053 + .name = "ar231x-wmac",
3054 + .resource = ar231x_wmac1_res,
3055 + .num_resources = ARRAY_SIZE(ar231x_wmac1_res),
3056 + .dev.platform_data = &ar231x_board,
3057 + },
3058 +};
3059 +
3060 +static const char * const devtype_strings[] = {
3061 + [DEV_TYPE_AR5312] = "Atheros AR5312",
3062 + [DEV_TYPE_AR2312] = "Atheros AR2312",
3063 + [DEV_TYPE_AR2313] = "Atheros AR2313",
3064 + [DEV_TYPE_AR2315] = "Atheros AR2315",
3065 + [DEV_TYPE_AR2316] = "Atheros AR2316",
3066 + [DEV_TYPE_AR2317] = "Atheros AR2317",
3067 + [DEV_TYPE_UNKNOWN] = "Atheros (unknown)",
3068 +};
3069 +
3070 +const char *get_system_type(void)
3071 +{
3072 + if ((ar231x_devtype >= ARRAY_SIZE(devtype_strings)) ||
3073 + !devtype_strings[ar231x_devtype])
3074 + return devtype_strings[DEV_TYPE_UNKNOWN];
3075 + return devtype_strings[ar231x_devtype];
3076 +}
3077 +
3078 +
3079 +int __init
3080 +ar231x_add_ethernet(int nr, u32 base, int irq, void *pdata)
3081 +{
3082 + struct resource *res;
3083 +
3084 + ar231x_eth[nr].dev.platform_data = pdata;
3085 + res = &ar231x_eth[nr].resource[0];
3086 + res->start = base;
3087 + res->end = base + 0x2000 - 1;
3088 + res++;
3089 + res->start = irq;
3090 + res->end = irq;
3091 + return platform_device_register(&ar231x_eth[nr]);
3092 +}
3093 +
3094 +void __init
3095 +ar231x_serial_setup(u32 mapbase, unsigned int uartclk)
3096 +{
3097 + struct uart_port s;
3098 +
3099 + memset(&s, 0, sizeof(s));
3100 +
3101 + s.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
3102 + s.iotype = UPIO_MEM;
3103 + s.irq = AR531X_MISC_IRQ_UART0;
3104 + s.regshift = 2;
3105 + s.mapbase = mapbase;
3106 + s.uartclk = uartclk;
3107 + s.membase = (void __iomem *)s.mapbase;
3108 +
3109 + early_serial_setup(&s);
3110 +}
3111 +
3112 +int __init
3113 +ar231x_add_wmac(int nr, u32 base, int irq)
3114 +{
3115 + struct resource *res;
3116 +
3117 + ar231x_wmac[nr].dev.platform_data = &ar231x_board;
3118 + res = &ar231x_wmac[nr].resource[0];
3119 + res->start = base;
3120 + res->end = base + 0x10000 - 1;
3121 + res++;
3122 + res->start = irq;
3123 + res->end = irq;
3124 + return platform_device_register(&ar231x_wmac[nr]);
3125 +}
3126 +
3127 +static int __init ar231x_register_devices(void)
3128 +{
3129 + ar5312_init_devices();
3130 + ar2315_init_devices();
3131 +
3132 + return 0;
3133 +}
3134 +
3135 +device_initcall(ar231x_register_devices);