atheros: various printk(...) fixes
[openwrt/svn-archive/archive.git] / target / linux / atheros / patches-3.10 / 110-ar2313_ethernet.patch
1 --- a/drivers/net/ethernet/Kconfig
2 +++ b/drivers/net/ethernet/Kconfig
3 @@ -22,6 +22,7 @@ source "drivers/net/ethernet/adaptec/Kco
4 source "drivers/net/ethernet/aeroflex/Kconfig"
5 source "drivers/net/ethernet/alteon/Kconfig"
6 source "drivers/net/ethernet/amd/Kconfig"
7 +source "drivers/net/ethernet/ar231x/Kconfig"
8 source "drivers/net/ethernet/apple/Kconfig"
9 source "drivers/net/ethernet/atheros/Kconfig"
10 source "drivers/net/ethernet/cadence/Kconfig"
11 --- a/drivers/net/ethernet/Makefile
12 +++ b/drivers/net/ethernet/Makefile
13 @@ -9,6 +9,7 @@ obj-$(CONFIG_GRETH) += aeroflex/
14 obj-$(CONFIG_NET_VENDOR_ALTEON) += alteon/
15 obj-$(CONFIG_NET_VENDOR_AMD) += amd/
16 obj-$(CONFIG_NET_VENDOR_APPLE) += apple/
17 +obj-$(CONFIG_NET_VENDOR_AR231X) += ar231x/
18 obj-$(CONFIG_NET_VENDOR_ATHEROS) += atheros/
19 obj-$(CONFIG_NET_CADENCE) += cadence/
20 obj-$(CONFIG_NET_BFIN) += adi/
21 --- /dev/null
22 +++ b/drivers/net/ethernet/ar231x/Kconfig
23 @@ -0,0 +1,5 @@
24 +config NET_VENDOR_AR231X
25 + tristate "AR231X Ethernet support"
26 + depends on ATHEROS_AR231X
27 + help
28 + Support for the AR231x/531x ethernet controller
29 --- /dev/null
30 +++ b/drivers/net/ethernet/ar231x/Makefile
31 @@ -0,0 +1 @@
32 +obj-$(CONFIG_NET_VENDOR_AR231X) += ar231x.o
33 --- /dev/null
34 +++ b/drivers/net/ethernet/ar231x/ar231x.c
35 @@ -0,0 +1,1260 @@
36 +/*
37 + * ar231x.c: Linux driver for the Atheros AR231x Ethernet device.
38 + *
39 + * Copyright (C) 2004 by Sameer Dekate <sdekate@arubanetworks.com>
40 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
41 + * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
42 + *
43 + * Thanks to Atheros for providing hardware and documentation
44 + * enabling me to write this driver.
45 + *
46 + * This program is free software; you can redistribute it and/or modify
47 + * it under the terms of the GNU General Public License as published by
48 + * the Free Software Foundation; either version 2 of the License, or
49 + * (at your option) any later version.
50 + *
51 + * Additional credits:
52 + * This code is taken from John Taylor's Sibyte driver and then
53 + * modified for the AR2313.
54 + */
55 +
56 +#include <linux/module.h>
57 +#include <linux/version.h>
58 +#include <linux/types.h>
59 +#include <linux/errno.h>
60 +#include <linux/ioport.h>
61 +#include <linux/pci.h>
62 +#include <linux/netdevice.h>
63 +#include <linux/etherdevice.h>
64 +#include <linux/interrupt.h>
65 +#include <linux/hardirq.h>
66 +#include <linux/skbuff.h>
67 +#include <linux/init.h>
68 +#include <linux/delay.h>
69 +#include <linux/mm.h>
70 +#include <linux/highmem.h>
71 +#include <linux/sockios.h>
72 +#include <linux/pkt_sched.h>
73 +#include <linux/mii.h>
74 +#include <linux/phy.h>
75 +#include <linux/ethtool.h>
76 +#include <linux/ctype.h>
77 +#include <linux/platform_device.h>
78 +
79 +#include <net/sock.h>
80 +#include <net/ip.h>
81 +
82 +#include <asm/io.h>
83 +#include <asm/irq.h>
84 +#include <asm/byteorder.h>
85 +#include <asm/uaccess.h>
86 +#include <asm/bootinfo.h>
87 +
88 +#define AR2313_MTU 1692
89 +#define AR2313_PRIOS 1
90 +#define AR2313_QUEUES (2*AR2313_PRIOS)
91 +#define AR2313_DESCR_ENTRIES 64
92 +
93 +
94 +#ifndef min
95 +#define min(a,b) (((a)<(b))?(a):(b))
96 +#endif
97 +
98 +#ifndef SMP_CACHE_BYTES
99 +#define SMP_CACHE_BYTES L1_CACHE_BYTES
100 +#endif
101 +
102 +#define AR2313_MBOX_SET_BIT 0x8
103 +
104 +#include "ar231x.h"
105 +
106 +/**
107 + * New interrupt handler strategy:
108 + *
109 + * An old interrupt handler worked using the traditional method of
110 + * replacing an skbuff with a new one when a packet arrives. However
111 + * the rx rings do not need to contain a static number of buffer
112 + * descriptors, thus it makes sense to move the memory allocation out
113 + * of the main interrupt handler and do it in a bottom half handler
114 + * and only allocate new buffers when the number of buffers in the
115 + * ring is below a certain threshold. In order to avoid starving the
116 + * NIC under heavy load it is however necessary to force allocation
117 + * when hitting a minimum threshold. The strategy for alloction is as
118 + * follows:
119 + *
120 + * RX_LOW_BUF_THRES - allocate buffers in the bottom half
121 + * RX_PANIC_LOW_THRES - we are very low on buffers, allocate
122 + * the buffers in the interrupt handler
123 + * RX_RING_THRES - maximum number of buffers in the rx ring
124 + *
125 + * One advantagous side effect of this allocation approach is that the
126 + * entire rx processing can be done without holding any spin lock
127 + * since the rx rings and registers are totally independent of the tx
128 + * ring and its registers. This of course includes the kmalloc's of
129 + * new skb's. Thus start_xmit can run in parallel with rx processing
130 + * and the memory allocation on SMP systems.
131 + *
132 + * Note that running the skb reallocation in a bottom half opens up
133 + * another can of races which needs to be handled properly. In
134 + * particular it can happen that the interrupt handler tries to run
135 + * the reallocation while the bottom half is either running on another
136 + * CPU or was interrupted on the same CPU. To get around this the
137 + * driver uses bitops to prevent the reallocation routines from being
138 + * reentered.
139 + *
140 + * TX handling can also be done without holding any spin lock, wheee
141 + * this is fun! since tx_csm is only written to by the interrupt
142 + * handler.
143 + */
144 +
145 +/**
146 + * Threshold values for RX buffer allocation - the low water marks for
147 + * when to start refilling the rings are set to 75% of the ring
148 + * sizes. It seems to make sense to refill the rings entirely from the
149 + * intrrupt handler once it gets below the panic threshold, that way
150 + * we don't risk that the refilling is moved to another CPU when the
151 + * one running the interrupt handler just got the slab code hot in its
152 + * cache.
153 + */
154 +#define RX_RING_SIZE AR2313_DESCR_ENTRIES
155 +#define RX_PANIC_THRES (RX_RING_SIZE/4)
156 +#define RX_LOW_THRES ((3*RX_RING_SIZE)/4)
157 +#define CRC_LEN 4
158 +#define RX_OFFSET 2
159 +
160 +#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
161 +#define VLAN_HDR 4
162 +#else
163 +#define VLAN_HDR 0
164 +#endif
165 +
166 +#define AR2313_BUFSIZE (AR2313_MTU + VLAN_HDR + ETH_HLEN + CRC_LEN + RX_OFFSET)
167 +
168 +#ifdef MODULE
169 +MODULE_LICENSE("GPL");
170 +MODULE_AUTHOR("Sameer Dekate <sdekate@arubanetworks.com>, Imre Kaloz <kaloz@openwrt.org>, Felix Fietkau <nbd@openwrt.org>");
171 +MODULE_DESCRIPTION("AR231x Ethernet driver");
172 +#endif
173 +
174 +#define virt_to_phys(x) ((u32)(x) & 0x1fffffff)
175 +
176 +/* prototypes */
177 +static void ar231x_halt(struct net_device *dev);
178 +static void rx_tasklet_func(unsigned long data);
179 +static void rx_tasklet_cleanup(struct net_device *dev);
180 +static void ar231x_multicast_list(struct net_device *dev);
181 +static void ar231x_tx_timeout(struct net_device *dev);
182 +
183 +static int ar231x_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum);
184 +static int ar231x_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum, u16 value);
185 +static int ar231x_mdiobus_reset(struct mii_bus *bus);
186 +static int ar231x_mdiobus_probe (struct net_device *dev);
187 +static void ar231x_adjust_link(struct net_device *dev);
188 +
189 +#ifndef ERR
190 +#define ERR(fmt, args...) printk("%s: " fmt, __func__, ##args)
191 +#endif
192 +
193 +#ifdef CONFIG_NET_POLL_CONTROLLER
194 +static void
195 +ar231x_netpoll(struct net_device *dev)
196 +{
197 + unsigned long flags;
198 +
199 + local_irq_save(flags);
200 + ar231x_interrupt(dev->irq, dev);
201 + local_irq_restore(flags);
202 +}
203 +#endif
204 +
205 +static const struct net_device_ops ar231x_ops = {
206 + .ndo_open = ar231x_open,
207 + .ndo_stop = ar231x_close,
208 + .ndo_start_xmit = ar231x_start_xmit,
209 + .ndo_set_rx_mode = ar231x_multicast_list,
210 + .ndo_do_ioctl = ar231x_ioctl,
211 + .ndo_change_mtu = eth_change_mtu,
212 + .ndo_validate_addr = eth_validate_addr,
213 + .ndo_set_mac_address = eth_mac_addr,
214 + .ndo_tx_timeout = ar231x_tx_timeout,
215 +#ifdef CONFIG_NET_POLL_CONTROLLER
216 + .ndo_poll_controller = ar231x_netpoll,
217 +#endif
218 +};
219 +
220 +int ar231x_probe(struct platform_device *pdev)
221 +{
222 + struct net_device *dev;
223 + struct ar231x_private *sp;
224 + struct resource *res;
225 + unsigned long ar_eth_base;
226 + char buf[64];
227 +
228 + dev = alloc_etherdev(sizeof(struct ar231x_private));
229 +
230 + if (dev == NULL) {
231 + printk(KERN_ERR
232 + "ar231x: Unable to allocate net_device structure!\n");
233 + return -ENOMEM;
234 + }
235 +
236 + platform_set_drvdata(pdev, dev);
237 +
238 + sp = netdev_priv(dev);
239 + sp->dev = dev;
240 + sp->cfg = pdev->dev.platform_data;
241 +
242 + sprintf(buf, "eth%d_membase", pdev->id);
243 + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, buf);
244 + if (!res)
245 + return -ENODEV;
246 +
247 + sp->link = 0;
248 + ar_eth_base = res->start;
249 +
250 + sprintf(buf, "eth%d_irq", pdev->id);
251 + dev->irq = platform_get_irq_byname(pdev, buf);
252 +
253 + spin_lock_init(&sp->lock);
254 +
255 + dev->features |= NETIF_F_HIGHDMA;
256 + dev->netdev_ops = &ar231x_ops;
257 +
258 + tasklet_init(&sp->rx_tasklet, rx_tasklet_func, (unsigned long) dev);
259 + tasklet_disable(&sp->rx_tasklet);
260 +
261 + sp->eth_regs =
262 + ioremap_nocache(virt_to_phys(ar_eth_base), sizeof(*sp->eth_regs));
263 + if (!sp->eth_regs) {
264 + printk("Can't remap eth registers\n");
265 + return -ENXIO;
266 + }
267 +
268 + /**
269 + * When there's only one MAC, PHY regs are typically on ENET0,
270 + * even though the MAC might be on ENET1.
271 + * Needto remap PHY regs separately in this case
272 + */
273 + if (virt_to_phys(ar_eth_base) == virt_to_phys(sp->phy_regs))
274 + sp->phy_regs = sp->eth_regs;
275 + else {
276 + sp->phy_regs =
277 + ioremap_nocache(virt_to_phys(sp->cfg->phy_base),
278 + sizeof(*sp->phy_regs));
279 + if (!sp->phy_regs) {
280 + printk("Can't remap phy registers\n");
281 + return -ENXIO;
282 + }
283 + }
284 +
285 + sp->dma_regs =
286 + ioremap_nocache(virt_to_phys(ar_eth_base + 0x1000),
287 + sizeof(*sp->dma_regs));
288 + dev->base_addr = (unsigned int) sp->dma_regs;
289 + if (!sp->dma_regs) {
290 + printk("Can't remap DMA registers\n");
291 + return -ENXIO;
292 + }
293 +
294 + sp->int_regs = ioremap_nocache(virt_to_phys(sp->cfg->reset_base), 4);
295 + if (!sp->int_regs) {
296 + printk("Can't remap INTERRUPT registers\n");
297 + return -ENXIO;
298 + }
299 +
300 + strncpy(sp->name, "Atheros AR231x", sizeof(sp->name) - 1);
301 + sp->name[sizeof(sp->name) - 1] = '\0';
302 + memcpy(dev->dev_addr, sp->cfg->macaddr, 6);
303 +
304 + if (ar231x_init(dev)) {
305 + /* ar231x_init() calls ar231x_init_cleanup() on error */
306 + kfree(dev);
307 + return -ENODEV;
308 + }
309 +
310 + if (register_netdev(dev)) {
311 + printk("%s: register_netdev failed\n", __func__);
312 + return -1;
313 + }
314 +
315 + printk("%s: %s: %02x:%02x:%02x:%02x:%02x:%02x, irq %d\n",
316 + dev->name, sp->name,
317 + dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
318 + dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5], dev->irq);
319 +
320 + sp->mii_bus = mdiobus_alloc();
321 + if (sp->mii_bus == NULL)
322 + return -1;
323 +
324 + sp->mii_bus->priv = dev;
325 + sp->mii_bus->read = ar231x_mdiobus_read;
326 + sp->mii_bus->write = ar231x_mdiobus_write;
327 + sp->mii_bus->reset = ar231x_mdiobus_reset;
328 + sp->mii_bus->name = "ar231x_eth_mii";
329 + snprintf(sp->mii_bus->id, MII_BUS_ID_SIZE, "%d", pdev->id);
330 + sp->mii_bus->irq = kmalloc(sizeof(int), GFP_KERNEL);
331 + *sp->mii_bus->irq = PHY_POLL;
332 +
333 + mdiobus_register(sp->mii_bus);
334 +
335 + if (ar231x_mdiobus_probe(dev) != 0) {
336 + printk(KERN_ERR "%s: mdiobus_probe failed\n", dev->name);
337 + rx_tasklet_cleanup(dev);
338 + ar231x_init_cleanup(dev);
339 + unregister_netdev(dev);
340 + kfree(dev);
341 + return -ENODEV;
342 + }
343 +
344 + /* start link poll timer */
345 + ar231x_setup_timer(dev);
346 +
347 + return 0;
348 +}
349 +
350 +
351 +static void ar231x_multicast_list(struct net_device *dev)
352 +{
353 + struct ar231x_private *sp = netdev_priv(dev);
354 + unsigned int filter;
355 +
356 + filter = sp->eth_regs->mac_control;
357 +
358 + if (dev->flags & IFF_PROMISC)
359 + filter |= MAC_CONTROL_PR;
360 + else
361 + filter &= ~MAC_CONTROL_PR;
362 + if ((dev->flags & IFF_ALLMULTI) || (netdev_mc_count(dev) > 0))
363 + filter |= MAC_CONTROL_PM;
364 + else
365 + filter &= ~MAC_CONTROL_PM;
366 +
367 + sp->eth_regs->mac_control = filter;
368 +}
369 +
370 +static void rx_tasklet_cleanup(struct net_device *dev)
371 +{
372 + struct ar231x_private *sp = netdev_priv(dev);
373 +
374 + /**
375 + * Tasklet may be scheduled. Need to get it removed from the list
376 + * since we're about to free the struct.
377 + */
378 +
379 + sp->unloading = 1;
380 + tasklet_enable(&sp->rx_tasklet);
381 + tasklet_kill(&sp->rx_tasklet);
382 +}
383 +
384 +static int ar231x_remove(struct platform_device *pdev)
385 +{
386 + struct net_device *dev = platform_get_drvdata(pdev);
387 + struct ar231x_private *sp = netdev_priv(dev);
388 + rx_tasklet_cleanup(dev);
389 + ar231x_init_cleanup(dev);
390 + unregister_netdev(dev);
391 + mdiobus_unregister(sp->mii_bus);
392 + mdiobus_free(sp->mii_bus);
393 + kfree(dev);
394 + return 0;
395 +}
396 +
397 +
398 +/**
399 + * Restart the AR2313 ethernet controller.
400 + */
401 +static int ar231x_restart(struct net_device *dev)
402 +{
403 + /* disable interrupts */
404 + disable_irq(dev->irq);
405 +
406 + /* stop mac */
407 + ar231x_halt(dev);
408 +
409 + /* initialize */
410 + ar231x_init(dev);
411 +
412 + /* enable interrupts */
413 + enable_irq(dev->irq);
414 +
415 + return 0;
416 +}
417 +
418 +static struct platform_driver ar231x_driver = {
419 + .driver.name = "ar231x-eth",
420 + .probe = ar231x_probe,
421 + .remove = ar231x_remove,
422 +};
423 +
424 +module_platform_driver(ar231x_driver);
425 +
426 +static void ar231x_free_descriptors(struct net_device *dev)
427 +{
428 + struct ar231x_private *sp = netdev_priv(dev);
429 + if (sp->rx_ring != NULL) {
430 + kfree((void *) KSEG0ADDR(sp->rx_ring));
431 + sp->rx_ring = NULL;
432 + sp->tx_ring = NULL;
433 + }
434 +}
435 +
436 +
437 +static int ar231x_allocate_descriptors(struct net_device *dev)
438 +{
439 + struct ar231x_private *sp = netdev_priv(dev);
440 + int size;
441 + int j;
442 + ar231x_descr_t *space;
443 +
444 + if (sp->rx_ring != NULL) {
445 + printk("%s: already done.\n", __FUNCTION__);
446 + return 0;
447 + }
448 +
449 + size =
450 + (sizeof(ar231x_descr_t) * (AR2313_DESCR_ENTRIES * AR2313_QUEUES));
451 + space = kmalloc(size, GFP_KERNEL);
452 + if (space == NULL)
453 + return 1;
454 +
455 + /* invalidate caches */
456 + dma_cache_inv((unsigned int) space, size);
457 +
458 + /* now convert pointer to KSEG1 */
459 + space = (ar231x_descr_t *) KSEG1ADDR(space);
460 +
461 + memset((void *) space, 0, size);
462 +
463 + sp->rx_ring = space;
464 + space += AR2313_DESCR_ENTRIES;
465 +
466 + sp->tx_ring = space;
467 + space += AR2313_DESCR_ENTRIES;
468 +
469 + /* Initialize the transmit Descriptors */
470 + for (j = 0; j < AR2313_DESCR_ENTRIES; j++) {
471 + ar231x_descr_t *td = &sp->tx_ring[j];
472 + td->status = 0;
473 + td->devcs = DMA_TX1_CHAINED;
474 + td->addr = 0;
475 + td->descr =
476 + virt_to_phys(&sp->
477 + tx_ring[(j + 1) & (AR2313_DESCR_ENTRIES - 1)]);
478 + }
479 +
480 + return 0;
481 +}
482 +
483 +
484 +/**
485 + * Generic cleanup handling data allocated during init. Used when the
486 + * module is unloaded or if an error occurs during initialization
487 + */
488 +static void ar231x_init_cleanup(struct net_device *dev)
489 +{
490 + struct ar231x_private *sp = netdev_priv(dev);
491 + struct sk_buff *skb;
492 + int j;
493 +
494 + ar231x_free_descriptors(dev);
495 +
496 + if (sp->eth_regs)
497 + iounmap((void *) sp->eth_regs);
498 + if (sp->dma_regs)
499 + iounmap((void *) sp->dma_regs);
500 +
501 + if (sp->rx_skb) {
502 + for (j = 0; j < AR2313_DESCR_ENTRIES; j++) {
503 + skb = sp->rx_skb[j];
504 + if (skb) {
505 + sp->rx_skb[j] = NULL;
506 + dev_kfree_skb(skb);
507 + }
508 + }
509 + kfree(sp->rx_skb);
510 + sp->rx_skb = NULL;
511 + }
512 +
513 + if (sp->tx_skb) {
514 + for (j = 0; j < AR2313_DESCR_ENTRIES; j++) {
515 + skb = sp->tx_skb[j];
516 + if (skb) {
517 + sp->tx_skb[j] = NULL;
518 + dev_kfree_skb(skb);
519 + }
520 + }
521 + kfree(sp->tx_skb);
522 + sp->tx_skb = NULL;
523 + }
524 +}
525 +
526 +static int ar231x_setup_timer(struct net_device *dev)
527 +{
528 + struct ar231x_private *sp = netdev_priv(dev);
529 +
530 + init_timer(&sp->link_timer);
531 +
532 + sp->link_timer.function = ar231x_link_timer_fn;
533 + sp->link_timer.data = (int) dev;
534 + sp->link_timer.expires = jiffies + HZ;
535 +
536 + add_timer(&sp->link_timer);
537 + return 0;
538 +}
539 +
540 +static void ar231x_link_timer_fn(unsigned long data)
541 +{
542 + struct net_device *dev = (struct net_device *) data;
543 + struct ar231x_private *sp = netdev_priv(dev);
544 +
545 + /**
546 + * See if the link status changed.
547 + * This was needed to make sure we set the PHY to the
548 + * autonegotiated value of half or full duplex.
549 + */
550 + ar231x_check_link(dev);
551 +
552 + /**
553 + * Loop faster when we don't have link.
554 + * This was needed to speed up the AP bootstrap time.
555 + */
556 + if (sp->link == 0)
557 + mod_timer(&sp->link_timer, jiffies + HZ / 2);
558 + else
559 + mod_timer(&sp->link_timer, jiffies + LINK_TIMER);
560 +}
561 +
562 +static void ar231x_check_link(struct net_device *dev)
563 +{
564 + struct ar231x_private *sp = netdev_priv(dev);
565 + u16 phy_data;
566 +
567 + phy_data = ar231x_mdiobus_read(sp->mii_bus, sp->phy, MII_BMSR);
568 + if (sp->phy_data != phy_data) {
569 + if (phy_data & BMSR_LSTATUS) {
570 + /**
571 + * Link is present, ready link partner ability to
572 + * deterine duplexity.
573 + */
574 + int duplex = 0;
575 + u16 reg;
576 +
577 + sp->link = 1;
578 + reg = ar231x_mdiobus_read(sp->mii_bus, sp->phy, MII_BMCR);
579 + if (reg & BMCR_ANENABLE) {
580 + /* auto neg enabled */
581 + reg = ar231x_mdiobus_read(sp->mii_bus, sp->phy, MII_LPA);
582 + duplex = (reg & (LPA_100FULL | LPA_10FULL)) ? 1 : 0;
583 + } else {
584 + /* no auto neg, just read duplex config */
585 + duplex = (reg & BMCR_FULLDPLX) ? 1 : 0;
586 + }
587 +
588 + printk(KERN_INFO "%s: Configuring MAC for %s duplex\n",
589 + dev->name, (duplex) ? "full" : "half");
590 +
591 + if (duplex) {
592 + /* full duplex */
593 + sp->eth_regs->mac_control =
594 + ((sp->eth_regs->
595 + mac_control | MAC_CONTROL_F) & ~MAC_CONTROL_DRO);
596 + } else {
597 + /* half duplex */
598 + sp->eth_regs->mac_control =
599 + ((sp->eth_regs->
600 + mac_control | MAC_CONTROL_DRO) & ~MAC_CONTROL_F);
601 + }
602 + } else {
603 + /* no link */
604 + sp->link = 0;
605 + }
606 + sp->phy_data = phy_data;
607 + }
608 +}
609 +
610 +static int ar231x_reset_reg(struct net_device *dev)
611 +{
612 + struct ar231x_private *sp = netdev_priv(dev);
613 + unsigned int ethsal, ethsah;
614 + unsigned int flags;
615 +
616 + *sp->int_regs |= sp->cfg->reset_mac;
617 + mdelay(10);
618 + *sp->int_regs &= ~sp->cfg->reset_mac;
619 + mdelay(10);
620 + *sp->int_regs |= sp->cfg->reset_phy;
621 + mdelay(10);
622 + *sp->int_regs &= ~sp->cfg->reset_phy;
623 + mdelay(10);
624 +
625 + sp->dma_regs->bus_mode = (DMA_BUS_MODE_SWR);
626 + mdelay(10);
627 + sp->dma_regs->bus_mode =
628 + ((32 << DMA_BUS_MODE_PBL_SHIFT) | DMA_BUS_MODE_BLE);
629 +
630 + /* enable interrupts */
631 + sp->dma_regs->intr_ena = (DMA_STATUS_AIS |
632 + DMA_STATUS_NIS |
633 + DMA_STATUS_RI |
634 + DMA_STATUS_TI | DMA_STATUS_FBE);
635 + sp->dma_regs->xmt_base = virt_to_phys(sp->tx_ring);
636 + sp->dma_regs->rcv_base = virt_to_phys(sp->rx_ring);
637 + sp->dma_regs->control =
638 + (DMA_CONTROL_SR | DMA_CONTROL_ST | DMA_CONTROL_SF);
639 +
640 + sp->eth_regs->flow_control = (FLOW_CONTROL_FCE);
641 + sp->eth_regs->vlan_tag = (0x8100);
642 +
643 + /* Enable Ethernet Interface */
644 + flags = (MAC_CONTROL_TE | /* transmit enable */
645 + MAC_CONTROL_PM | /* pass mcast */
646 + MAC_CONTROL_F | /* full duplex */
647 + MAC_CONTROL_HBD); /* heart beat disabled */
648 +
649 + if (dev->flags & IFF_PROMISC) { /* set promiscuous mode */
650 + flags |= MAC_CONTROL_PR;
651 + }
652 + sp->eth_regs->mac_control = flags;
653 +
654 + /* Set all Ethernet station address registers to their initial values */
655 + ethsah = ((((u_int) (dev->dev_addr[5]) << 8) & (u_int) 0x0000FF00) |
656 + (((u_int) (dev->dev_addr[4]) << 0) & (u_int) 0x000000FF));
657 +
658 + ethsal = ((((u_int) (dev->dev_addr[3]) << 24) & (u_int) 0xFF000000) |
659 + (((u_int) (dev->dev_addr[2]) << 16) & (u_int) 0x00FF0000) |
660 + (((u_int) (dev->dev_addr[1]) << 8) & (u_int) 0x0000FF00) |
661 + (((u_int) (dev->dev_addr[0]) << 0) & (u_int) 0x000000FF));
662 +
663 + sp->eth_regs->mac_addr[0] = ethsah;
664 + sp->eth_regs->mac_addr[1] = ethsal;
665 +
666 + mdelay(10);
667 +
668 + return 0;
669 +}
670 +
671 +
672 +static int ar231x_init(struct net_device *dev)
673 +{
674 + struct ar231x_private *sp = netdev_priv(dev);
675 + int ecode = 0;
676 +
677 + /* Allocate descriptors */
678 + if (ar231x_allocate_descriptors(dev)) {
679 + printk("%s: %s: ar231x_allocate_descriptors failed\n",
680 + dev->name, __FUNCTION__);
681 + ecode = -EAGAIN;
682 + goto init_error;
683 + }
684 +
685 + /* Get the memory for the skb rings */
686 + if (sp->rx_skb == NULL) {
687 + sp->rx_skb =
688 + kmalloc(sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES,
689 + GFP_KERNEL);
690 + if (!(sp->rx_skb)) {
691 + printk("%s: %s: rx_skb kmalloc failed\n",
692 + dev->name, __FUNCTION__);
693 + ecode = -EAGAIN;
694 + goto init_error;
695 + }
696 + }
697 + memset(sp->rx_skb, 0, sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES);
698 +
699 + if (sp->tx_skb == NULL) {
700 + sp->tx_skb =
701 + kmalloc(sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES,
702 + GFP_KERNEL);
703 + if (!(sp->tx_skb)) {
704 + printk("%s: %s: tx_skb kmalloc failed\n",
705 + dev->name, __FUNCTION__);
706 + ecode = -EAGAIN;
707 + goto init_error;
708 + }
709 + }
710 + memset(sp->tx_skb, 0, sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES);
711 +
712 + /**
713 + * Set tx_csm before we start receiving interrupts, otherwise
714 + * the interrupt handler might think it is supposed to process
715 + * tx ints before we are up and running, which may cause a null
716 + * pointer access in the int handler.
717 + */
718 + sp->rx_skbprd = 0;
719 + sp->cur_rx = 0;
720 + sp->tx_prd = 0;
721 + sp->tx_csm = 0;
722 +
723 + /* Zero the stats before starting the interface */
724 + memset(&dev->stats, 0, sizeof(dev->stats));
725 +
726 + /**
727 + * We load the ring here as there seem to be no way to tell the
728 + * firmware to wipe the ring without re-initializing it.
729 + */
730 + ar231x_load_rx_ring(dev, RX_RING_SIZE);
731 +
732 + /* Init hardware */
733 + ar231x_reset_reg(dev);
734 +
735 + /* Get the IRQ */
736 + ecode =
737 + request_irq(dev->irq, &ar231x_interrupt,
738 + IRQF_DISABLED,
739 + dev->name, dev);
740 + if (ecode) {
741 + printk(KERN_WARNING "%s: %s: Requested IRQ %d is busy\n",
742 + dev->name, __FUNCTION__, dev->irq);
743 + goto init_error;
744 + }
745 +
746 +
747 + tasklet_enable(&sp->rx_tasklet);
748 +
749 + return 0;
750 +
751 + init_error:
752 + ar231x_init_cleanup(dev);
753 + return ecode;
754 +}
755 +
756 +/**
757 + * Load the rx ring.
758 + *
759 + * Loading rings is safe without holding the spin lock since this is
760 + * done only before the device is enabled, thus no interrupts are
761 + * generated and by the interrupt handler/tasklet handler.
762 + */
763 +static void ar231x_load_rx_ring(struct net_device *dev, int nr_bufs)
764 +{
765 + struct ar231x_private *sp = netdev_priv(dev);
766 + short i, idx;
767 +
768 + idx = sp->rx_skbprd;
769 +
770 + for (i = 0; i < nr_bufs; i++) {
771 + struct sk_buff *skb;
772 + ar231x_descr_t *rd;
773 +
774 + if (sp->rx_skb[idx])
775 + break;
776 +
777 + skb = netdev_alloc_skb_ip_align(dev, AR2313_BUFSIZE);
778 + if (!skb) {
779 + printk("\n\n\n\n %s: No memory in system\n\n\n\n",
780 + __FUNCTION__);
781 + break;
782 + }
783 +
784 + /* Make sure IP header starts on a fresh cache line */
785 + skb->dev = dev;
786 + sp->rx_skb[idx] = skb;
787 +
788 + rd = (ar231x_descr_t *) & sp->rx_ring[idx];
789 +
790 + /* initialize dma descriptor */
791 + rd->devcs = ((AR2313_BUFSIZE << DMA_RX1_BSIZE_SHIFT) |
792 + DMA_RX1_CHAINED);
793 + rd->addr = virt_to_phys(skb->data);
794 + rd->descr =
795 + virt_to_phys(&sp->
796 + rx_ring[(idx + 1) & (AR2313_DESCR_ENTRIES - 1)]);
797 + rd->status = DMA_RX_OWN;
798 +
799 + idx = DSC_NEXT(idx);
800 + }
801 +
802 + if (i)
803 + sp->rx_skbprd = idx;
804 +
805 + return;
806 +}
807 +
808 +#define AR2313_MAX_PKTS_PER_CALL 64
809 +
810 +static int ar231x_rx_int(struct net_device *dev)
811 +{
812 + struct ar231x_private *sp = netdev_priv(dev);
813 + struct sk_buff *skb, *skb_new;
814 + ar231x_descr_t *rxdesc;
815 + unsigned int status;
816 + u32 idx;
817 + int pkts = 0;
818 + int rval;
819 +
820 + idx = sp->cur_rx;
821 +
822 + /* process at most the entire ring and then wait for another int */
823 + while (1) {
824 + rxdesc = &sp->rx_ring[idx];
825 + status = rxdesc->status;
826 +
827 + if (status & DMA_RX_OWN) {
828 + /* SiByte owns descriptor or descr not yet filled in */
829 + rval = 0;
830 + break;
831 + }
832 +
833 + if (++pkts > AR2313_MAX_PKTS_PER_CALL) {
834 + rval = 1;
835 + break;
836 + }
837 +
838 + if ((status & DMA_RX_ERROR) && !(status & DMA_RX_LONG)) {
839 + dev->stats.rx_errors++;
840 + dev->stats.rx_dropped++;
841 +
842 + /* add statistics counters */
843 + if (status & DMA_RX_ERR_CRC)
844 + dev->stats.rx_crc_errors++;
845 + if (status & DMA_RX_ERR_COL)
846 + dev->stats.rx_over_errors++;
847 + if (status & DMA_RX_ERR_LENGTH)
848 + dev->stats.rx_length_errors++;
849 + if (status & DMA_RX_ERR_RUNT)
850 + dev->stats.rx_over_errors++;
851 + if (status & DMA_RX_ERR_DESC)
852 + dev->stats.rx_over_errors++;
853 +
854 + } else {
855 + /* alloc new buffer. */
856 + skb_new = netdev_alloc_skb_ip_align(dev, AR2313_BUFSIZE);
857 + if (skb_new != NULL) {
858 + skb = sp->rx_skb[idx];
859 + /* set skb */
860 + skb_put(skb,
861 + ((status >> DMA_RX_LEN_SHIFT) & 0x3fff) - CRC_LEN);
862 +
863 + dev->stats.rx_bytes += skb->len;
864 + skb->protocol = eth_type_trans(skb, dev);
865 + /* pass the packet to upper layers */
866 + netif_rx(skb);
867 +
868 + skb_new->dev = dev;
869 + /* reset descriptor's curr_addr */
870 + rxdesc->addr = virt_to_phys(skb_new->data);
871 +
872 + dev->stats.rx_packets++;
873 + sp->rx_skb[idx] = skb_new;
874 + } else {
875 + dev->stats.rx_dropped++;
876 + }
877 + }
878 +
879 + rxdesc->devcs = ((AR2313_BUFSIZE << DMA_RX1_BSIZE_SHIFT) |
880 + DMA_RX1_CHAINED);
881 + rxdesc->status = DMA_RX_OWN;
882 +
883 + idx = DSC_NEXT(idx);
884 + }
885 +
886 + sp->cur_rx = idx;
887 +
888 + return rval;
889 +}
890 +
891 +
892 +static void ar231x_tx_int(struct net_device *dev)
893 +{
894 + struct ar231x_private *sp = netdev_priv(dev);
895 + u32 idx;
896 + struct sk_buff *skb;
897 + ar231x_descr_t *txdesc;
898 + unsigned int status = 0;
899 +
900 + idx = sp->tx_csm;
901 +
902 + while (idx != sp->tx_prd) {
903 + txdesc = &sp->tx_ring[idx];
904 + status = txdesc->status;
905 +
906 + if (status & DMA_TX_OWN) {
907 + /* ar231x dma still owns descr */
908 + break;
909 + }
910 + /* done with this descriptor */
911 + dma_unmap_single(NULL, txdesc->addr,
912 + txdesc->devcs & DMA_TX1_BSIZE_MASK,
913 + DMA_TO_DEVICE);
914 + txdesc->status = 0;
915 +
916 + if (status & DMA_TX_ERROR) {
917 + dev->stats.tx_errors++;
918 + dev->stats.tx_dropped++;
919 + if (status & DMA_TX_ERR_UNDER)
920 + dev->stats.tx_fifo_errors++;
921 + if (status & DMA_TX_ERR_HB)
922 + dev->stats.tx_heartbeat_errors++;
923 + if (status & (DMA_TX_ERR_LOSS | DMA_TX_ERR_LINK))
924 + dev->stats.tx_carrier_errors++;
925 + if (status & (DMA_TX_ERR_LATE |
926 + DMA_TX_ERR_COL |
927 + DMA_TX_ERR_JABBER | DMA_TX_ERR_DEFER))
928 + dev->stats.tx_aborted_errors++;
929 + } else {
930 + /* transmit OK */
931 + dev->stats.tx_packets++;
932 + }
933 +
934 + skb = sp->tx_skb[idx];
935 + sp->tx_skb[idx] = NULL;
936 + idx = DSC_NEXT(idx);
937 + dev->stats.tx_bytes += skb->len;
938 + dev_kfree_skb_irq(skb);
939 + }
940 +
941 + sp->tx_csm = idx;
942 +
943 + return;
944 +}
945 +
946 +
947 +static void rx_tasklet_func(unsigned long data)
948 +{
949 + struct net_device *dev = (struct net_device *) data;
950 + struct ar231x_private *sp = netdev_priv(dev);
951 +
952 + if (sp->unloading)
953 + return;
954 +
955 + if (ar231x_rx_int(dev)) {
956 + tasklet_hi_schedule(&sp->rx_tasklet);
957 + } else {
958 + unsigned long flags;
959 + spin_lock_irqsave(&sp->lock, flags);
960 + sp->dma_regs->intr_ena |= DMA_STATUS_RI;
961 + spin_unlock_irqrestore(&sp->lock, flags);
962 + }
963 +}
964 +
965 +static void rx_schedule(struct net_device *dev)
966 +{
967 + struct ar231x_private *sp = netdev_priv(dev);
968 +
969 + sp->dma_regs->intr_ena &= ~DMA_STATUS_RI;
970 +
971 + tasklet_hi_schedule(&sp->rx_tasklet);
972 +}
973 +
974 +static irqreturn_t ar231x_interrupt(int irq, void *dev_id)
975 +{
976 + struct net_device *dev = (struct net_device *) dev_id;
977 + struct ar231x_private *sp = netdev_priv(dev);
978 + unsigned int status, enabled;
979 +
980 + /* clear interrupt */
981 + /* Don't clear RI bit if currently disabled */
982 + status = sp->dma_regs->status;
983 + enabled = sp->dma_regs->intr_ena;
984 + sp->dma_regs->status = status & enabled;
985 +
986 + if (status & DMA_STATUS_NIS) {
987 + /* normal status */
988 + /**
989 + * Don't schedule rx processing if interrupt
990 + * is already disabled.
991 + */
992 + if (status & enabled & DMA_STATUS_RI) {
993 + /* receive interrupt */
994 + rx_schedule(dev);
995 + }
996 + if (status & DMA_STATUS_TI) {
997 + /* transmit interrupt */
998 + ar231x_tx_int(dev);
999 + }
1000 + }
1001 +
1002 + /* abnormal status */
1003 + if (status & (DMA_STATUS_FBE | DMA_STATUS_TPS))
1004 + ar231x_restart(dev);
1005 +
1006 + return IRQ_HANDLED;
1007 +}
1008 +
1009 +
1010 +static int ar231x_open(struct net_device *dev)
1011 +{
1012 + struct ar231x_private *sp = netdev_priv(dev);
1013 + unsigned int ethsal, ethsah;
1014 +
1015 + /* reset the hardware, in case the MAC address changed */
1016 + ethsah = ((((u_int) (dev->dev_addr[5]) << 8) & (u_int) 0x0000FF00) |
1017 + (((u_int) (dev->dev_addr[4]) << 0) & (u_int) 0x000000FF));
1018 +
1019 + ethsal = ((((u_int) (dev->dev_addr[3]) << 24) & (u_int) 0xFF000000) |
1020 + (((u_int) (dev->dev_addr[2]) << 16) & (u_int) 0x00FF0000) |
1021 + (((u_int) (dev->dev_addr[1]) << 8) & (u_int) 0x0000FF00) |
1022 + (((u_int) (dev->dev_addr[0]) << 0) & (u_int) 0x000000FF));
1023 +
1024 + sp->eth_regs->mac_addr[0] = ethsah;
1025 + sp->eth_regs->mac_addr[1] = ethsal;
1026 +
1027 + mdelay(10);
1028 +
1029 + dev->mtu = 1500;
1030 + netif_start_queue(dev);
1031 +
1032 + sp->eth_regs->mac_control |= MAC_CONTROL_RE;
1033 +
1034 + return 0;
1035 +}
1036 +
1037 +static void ar231x_tx_timeout(struct net_device *dev)
1038 +{
1039 + struct ar231x_private *sp = netdev_priv(dev);
1040 + unsigned long flags;
1041 +
1042 + spin_lock_irqsave(&sp->lock, flags);
1043 + ar231x_restart(dev);
1044 + spin_unlock_irqrestore(&sp->lock, flags);
1045 +}
1046 +
1047 +static void ar231x_halt(struct net_device *dev)
1048 +{
1049 + struct ar231x_private *sp = netdev_priv(dev);
1050 + int j;
1051 +
1052 + tasklet_disable(&sp->rx_tasklet);
1053 +
1054 + /* kill the MAC */
1055 + sp->eth_regs->mac_control &= ~(MAC_CONTROL_RE | /* disable Receives */
1056 + MAC_CONTROL_TE); /* disable Transmits */
1057 + /* stop dma */
1058 + sp->dma_regs->control = 0;
1059 + sp->dma_regs->bus_mode = DMA_BUS_MODE_SWR;
1060 +
1061 + /* place phy and MAC in reset */
1062 + *sp->int_regs |= (sp->cfg->reset_mac | sp->cfg->reset_phy);
1063 +
1064 + /* free buffers on tx ring */
1065 + for (j = 0; j < AR2313_DESCR_ENTRIES; j++) {
1066 + struct sk_buff *skb;
1067 + ar231x_descr_t *txdesc;
1068 +
1069 + txdesc = &sp->tx_ring[j];
1070 + txdesc->descr = 0;
1071 +
1072 + skb = sp->tx_skb[j];
1073 + if (skb) {
1074 + dev_kfree_skb(skb);
1075 + sp->tx_skb[j] = NULL;
1076 + }
1077 + }
1078 +}
1079 +
1080 +/**
1081 + * close should do nothing. Here's why. It's called when
1082 + * 'ifconfig bond0 down' is run. If it calls free_irq then
1083 + * the irq is gone forever ! When bond0 is made 'up' again,
1084 + * the ar231x_open () does not call request_irq (). Worse,
1085 + * the call to ar231x_halt() generates a WDOG reset due to
1086 + * the write to 'sp->int_regs' and the box reboots.
1087 + * Commenting this out is good since it allows the
1088 + * system to resume when bond0 is made up again.
1089 + */
1090 +static int ar231x_close(struct net_device *dev)
1091 +{
1092 +#if 0
1093 + /* Disable interrupts */
1094 + disable_irq(dev->irq);
1095 +
1096 + /**
1097 + * Without (or before) releasing irq and stopping hardware, this
1098 + * is an absolute non-sense, by the way. It will be reset instantly
1099 + * by the first irq.
1100 + */
1101 + netif_stop_queue(dev);
1102 +
1103 + /* stop the MAC and DMA engines */
1104 + ar231x_halt(dev);
1105 +
1106 + /* release the interrupt */
1107 + free_irq(dev->irq, dev);
1108 +
1109 +#endif
1110 + return 0;
1111 +}
1112 +
1113 +static int ar231x_start_xmit(struct sk_buff *skb, struct net_device *dev)
1114 +{
1115 + struct ar231x_private *sp = netdev_priv(dev);
1116 + ar231x_descr_t *td;
1117 + u32 idx;
1118 +
1119 + idx = sp->tx_prd;
1120 + td = &sp->tx_ring[idx];
1121 +
1122 + if (td->status & DMA_TX_OWN) {
1123 + /* free skbuf and lie to the caller that we sent it out */
1124 + dev->stats.tx_dropped++;
1125 + dev_kfree_skb(skb);
1126 +
1127 + /* restart transmitter in case locked */
1128 + sp->dma_regs->xmt_poll = 0;
1129 + return 0;
1130 + }
1131 +
1132 + /* Setup the transmit descriptor. */
1133 + td->devcs = ((skb->len << DMA_TX1_BSIZE_SHIFT) |
1134 + (DMA_TX1_LS | DMA_TX1_IC | DMA_TX1_CHAINED));
1135 + td->addr = dma_map_single(NULL, skb->data, skb->len, DMA_TO_DEVICE);
1136 + td->status = DMA_TX_OWN;
1137 +
1138 + /* kick transmitter last */
1139 + sp->dma_regs->xmt_poll = 0;
1140 +
1141 + sp->tx_skb[idx] = skb;
1142 + idx = DSC_NEXT(idx);
1143 + sp->tx_prd = idx;
1144 +
1145 + return 0;
1146 +}
1147 +
1148 +static int ar231x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1149 +{
1150 + struct ar231x_private *sp = netdev_priv(dev);
1151 + int ret;
1152 +
1153 + switch (cmd) {
1154 + case SIOCETHTOOL:
1155 + spin_lock_irq(&sp->lock);
1156 + ret = phy_ethtool_ioctl(sp->phy_dev, (void *) ifr->ifr_data);
1157 + spin_unlock_irq(&sp->lock);
1158 + return ret;
1159 +
1160 + case SIOCSIFHWADDR:
1161 + if (copy_from_user
1162 + (dev->dev_addr, ifr->ifr_data, sizeof(dev->dev_addr)))
1163 + return -EFAULT;
1164 + return 0;
1165 +
1166 + case SIOCGIFHWADDR:
1167 + if (copy_to_user
1168 + (ifr->ifr_data, dev->dev_addr, sizeof(dev->dev_addr)))
1169 + return -EFAULT;
1170 + return 0;
1171 +
1172 + case SIOCGMIIPHY:
1173 + case SIOCGMIIREG:
1174 + case SIOCSMIIREG:
1175 + return phy_mii_ioctl(sp->phy_dev, ifr, cmd);
1176 +
1177 + default:
1178 + break;
1179 + }
1180 +
1181 + return -EOPNOTSUPP;
1182 +}
1183 +
1184 +static void ar231x_adjust_link(struct net_device *dev)
1185 +{
1186 + struct ar231x_private *sp = netdev_priv(dev);
1187 + unsigned int mc;
1188 +
1189 + if (!sp->phy_dev->link)
1190 + return;
1191 +
1192 + if (sp->phy_dev->duplex != sp->oldduplex) {
1193 + mc = readl(&sp->eth_regs->mac_control);
1194 + mc &= ~(MAC_CONTROL_F | MAC_CONTROL_DRO);
1195 + if (sp->phy_dev->duplex)
1196 + mc |= MAC_CONTROL_F;
1197 + else
1198 + mc |= MAC_CONTROL_DRO;
1199 + writel(mc, &sp->eth_regs->mac_control);
1200 + sp->oldduplex = sp->phy_dev->duplex;
1201 + }
1202 +}
1203 +
1204 +#define MII_ADDR(phy, reg) \
1205 + ((reg << MII_ADDR_REG_SHIFT) | (phy << MII_ADDR_PHY_SHIFT))
1206 +
1207 +static int
1208 +ar231x_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum)
1209 +{
1210 + struct net_device *const dev = bus->priv;
1211 + struct ar231x_private *sp = netdev_priv(dev);
1212 + volatile ETHERNET_STRUCT *ethernet = sp->phy_regs;
1213 +
1214 + ethernet->mii_addr = MII_ADDR(phy_addr, regnum);
1215 + while (ethernet->mii_addr & MII_ADDR_BUSY);
1216 + return ethernet->mii_data >> MII_DATA_SHIFT;
1217 +}
1218 +
1219 +static int
1220 +ar231x_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum,
1221 + u16 value)
1222 +{
1223 + struct net_device *const dev = bus->priv;
1224 + struct ar231x_private *sp = netdev_priv(dev);
1225 + volatile ETHERNET_STRUCT *ethernet = sp->phy_regs;
1226 +
1227 + while (ethernet->mii_addr & MII_ADDR_BUSY);
1228 + ethernet->mii_data = value << MII_DATA_SHIFT;
1229 + ethernet->mii_addr = MII_ADDR(phy_addr, regnum) | MII_ADDR_WRITE;
1230 +
1231 + return 0;
1232 +}
1233 +
1234 +static int ar231x_mdiobus_reset(struct mii_bus *bus)
1235 +{
1236 + struct net_device *const dev = bus->priv;
1237 +
1238 + ar231x_reset_reg(dev);
1239 +
1240 + return 0;
1241 +}
1242 +
1243 +static int ar231x_mdiobus_probe (struct net_device *dev)
1244 +{
1245 + struct ar231x_private *const sp = netdev_priv(dev);
1246 + struct phy_device *phydev = NULL;
1247 + int phy_addr;
1248 +
1249 + /* find the first (lowest address) PHY on the current MAC's MII bus */
1250 + for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++)
1251 + if (sp->mii_bus->phy_map[phy_addr]) {
1252 + phydev = sp->mii_bus->phy_map[phy_addr];
1253 + sp->phy = phy_addr;
1254 + break; /* break out with first one found */
1255 + }
1256 +
1257 + if (!phydev) {
1258 + printk (KERN_ERR "ar231x: %s: no PHY found\n", dev->name);
1259 + return -1;
1260 + }
1261 +
1262 + /* now we are supposed to have a proper phydev, to attach to... */
1263 + BUG_ON(!phydev);
1264 + BUG_ON(phydev->attached_dev);
1265 +
1266 + phydev = phy_connect(dev, dev_name(&phydev->dev), &ar231x_adjust_link, 0,
1267 + PHY_INTERFACE_MODE_MII);
1268 +
1269 + if (IS_ERR(phydev)) {
1270 + printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
1271 + return PTR_ERR(phydev);
1272 + }
1273 +
1274 + /* mask with MAC supported features */
1275 + phydev->supported &= (SUPPORTED_10baseT_Half
1276 + | SUPPORTED_10baseT_Full
1277 + | SUPPORTED_100baseT_Half
1278 + | SUPPORTED_100baseT_Full
1279 + | SUPPORTED_Autoneg
1280 + /* | SUPPORTED_Pause | SUPPORTED_Asym_Pause */
1281 + | SUPPORTED_MII
1282 + | SUPPORTED_TP);
1283 +
1284 + phydev->advertising = phydev->supported;
1285 +
1286 + sp->oldduplex = -1;
1287 + sp->phy_dev = phydev;
1288 +
1289 + printk(KERN_INFO "%s: attached PHY driver [%s] "
1290 + "(mii_bus:phy_addr=%s)\n",
1291 + dev->name, phydev->drv->name, dev_name(&phydev->dev));
1292 +
1293 + return 0;
1294 +}
1295 +
1296 --- /dev/null
1297 +++ b/drivers/net/ethernet/ar231x/ar231x.h
1298 @@ -0,0 +1,289 @@
1299 +/*
1300 + * ar231x.h: Linux driver for the Atheros AR231x Ethernet device.
1301 + *
1302 + * Copyright (C) 2004 by Sameer Dekate <sdekate@arubanetworks.com>
1303 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
1304 + * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
1305 + *
1306 + * Thanks to Atheros for providing hardware and documentation
1307 + * enabling me to write this driver.
1308 + *
1309 + * This program is free software; you can redistribute it and/or modify
1310 + * it under the terms of the GNU General Public License as published by
1311 + * the Free Software Foundation; either version 2 of the License, or
1312 + * (at your option) any later version.
1313 + */
1314 +
1315 +#ifndef _AR2313_H_
1316 +#define _AR2313_H_
1317 +
1318 +#include <linux/interrupt.h>
1319 +#include <generated/autoconf.h>
1320 +#include <linux/bitops.h>
1321 +#include <asm/bootinfo.h>
1322 +#include <ar231x_platform.h>
1323 +
1324 +/* probe link timer - 5 secs */
1325 +#define LINK_TIMER (5*HZ)
1326 +
1327 +#define IS_DMA_TX_INT(X) (((X) & (DMA_STATUS_TI)) != 0)
1328 +#define IS_DMA_RX_INT(X) (((X) & (DMA_STATUS_RI)) != 0)
1329 +#define IS_DRIVER_OWNED(X) (((X) & (DMA_TX_OWN)) == 0)
1330 +
1331 +#define AR2313_TX_TIMEOUT (HZ/4)
1332 +
1333 +/* Rings */
1334 +#define DSC_RING_ENTRIES_SIZE (AR2313_DESCR_ENTRIES * sizeof(struct desc))
1335 +#define DSC_NEXT(idx) ((idx + 1) & (AR2313_DESCR_ENTRIES - 1))
1336 +
1337 +#define AR2313_MBGET 2
1338 +#define AR2313_MBSET 3
1339 +#define AR2313_PCI_RECONFIG 4
1340 +#define AR2313_PCI_DUMP 5
1341 +#define AR2313_TEST_PANIC 6
1342 +#define AR2313_TEST_NULLPTR 7
1343 +#define AR2313_READ_DATA 8
1344 +#define AR2313_WRITE_DATA 9
1345 +#define AR2313_GET_VERSION 10
1346 +#define AR2313_TEST_HANG 11
1347 +#define AR2313_SYNC 12
1348 +
1349 +#define DMA_RX_ERR_CRC BIT(1)
1350 +#define DMA_RX_ERR_DRIB BIT(2)
1351 +#define DMA_RX_ERR_MII BIT(3)
1352 +#define DMA_RX_EV2 BIT(5)
1353 +#define DMA_RX_ERR_COL BIT(6)
1354 +#define DMA_RX_LONG BIT(7)
1355 +#define DMA_RX_LS BIT(8) /* last descriptor */
1356 +#define DMA_RX_FS BIT(9) /* first descriptor */
1357 +#define DMA_RX_MF BIT(10) /* multicast frame */
1358 +#define DMA_RX_ERR_RUNT BIT(11) /* runt frame */
1359 +#define DMA_RX_ERR_LENGTH BIT(12) /* length error */
1360 +#define DMA_RX_ERR_DESC BIT(14) /* descriptor error */
1361 +#define DMA_RX_ERROR BIT(15) /* error summary */
1362 +#define DMA_RX_LEN_MASK 0x3fff0000
1363 +#define DMA_RX_LEN_SHIFT 16
1364 +#define DMA_RX_FILT BIT(30)
1365 +#define DMA_RX_OWN BIT(31) /* desc owned by DMA controller */
1366 +
1367 +#define DMA_RX1_BSIZE_MASK 0x000007ff
1368 +#define DMA_RX1_BSIZE_SHIFT 0
1369 +#define DMA_RX1_CHAINED BIT(24)
1370 +#define DMA_RX1_RER BIT(25)
1371 +
1372 +#define DMA_TX_ERR_UNDER BIT(1) /* underflow error */
1373 +#define DMA_TX_ERR_DEFER BIT(2) /* excessive deferral */
1374 +#define DMA_TX_COL_MASK 0x78
1375 +#define DMA_TX_COL_SHIFT 3
1376 +#define DMA_TX_ERR_HB BIT(7) /* hearbeat failure */
1377 +#define DMA_TX_ERR_COL BIT(8) /* excessive collisions */
1378 +#define DMA_TX_ERR_LATE BIT(9) /* late collision */
1379 +#define DMA_TX_ERR_LINK BIT(10) /* no carrier */
1380 +#define DMA_TX_ERR_LOSS BIT(11) /* loss of carrier */
1381 +#define DMA_TX_ERR_JABBER BIT(14) /* transmit jabber timeout */
1382 +#define DMA_TX_ERROR BIT(15) /* frame aborted */
1383 +#define DMA_TX_OWN BIT(31) /* descr owned by DMA controller */
1384 +
1385 +#define DMA_TX1_BSIZE_MASK 0x000007ff
1386 +#define DMA_TX1_BSIZE_SHIFT 0
1387 +#define DMA_TX1_CHAINED BIT(24) /* chained descriptors */
1388 +#define DMA_TX1_TER BIT(25) /* transmit end of ring */
1389 +#define DMA_TX1_FS BIT(29) /* first segment */
1390 +#define DMA_TX1_LS BIT(30) /* last segment */
1391 +#define DMA_TX1_IC BIT(31) /* interrupt on completion */
1392 +
1393 +#define RCVPKT_LENGTH(X) (X >> 16) /* Received pkt Length */
1394 +
1395 +#define MAC_CONTROL_RE BIT(2) /* receive enable */
1396 +#define MAC_CONTROL_TE BIT(3) /* transmit enable */
1397 +#define MAC_CONTROL_DC BIT(5) /* Deferral check */
1398 +#define MAC_CONTROL_ASTP BIT(8) /* Auto pad strip */
1399 +#define MAC_CONTROL_DRTY BIT(10) /* Disable retry */
1400 +#define MAC_CONTROL_DBF BIT(11) /* Disable bcast frames */
1401 +#define MAC_CONTROL_LCC BIT(12) /* late collision ctrl */
1402 +#define MAC_CONTROL_HP BIT(13) /* Hash Perfect filtering */
1403 +#define MAC_CONTROL_HASH BIT(14) /* Unicast hash filtering */
1404 +#define MAC_CONTROL_HO BIT(15) /* Hash only filtering */
1405 +#define MAC_CONTROL_PB BIT(16) /* Pass Bad frames */
1406 +#define MAC_CONTROL_IF BIT(17) /* Inverse filtering */
1407 +#define MAC_CONTROL_PR BIT(18) /* promiscuous mode (valid frames only) */
1408 +#define MAC_CONTROL_PM BIT(19) /* pass multicast */
1409 +#define MAC_CONTROL_F BIT(20) /* full-duplex */
1410 +#define MAC_CONTROL_DRO BIT(23) /* Disable Receive Own */
1411 +#define MAC_CONTROL_HBD BIT(28) /* heart-beat disabled (MUST BE SET) */
1412 +#define MAC_CONTROL_BLE BIT(30) /* big endian mode */
1413 +#define MAC_CONTROL_RA BIT(31) /* receive all (valid and invalid frames) */
1414 +
1415 +#define MII_ADDR_BUSY BIT(0)
1416 +#define MII_ADDR_WRITE BIT(1)
1417 +#define MII_ADDR_REG_SHIFT 6
1418 +#define MII_ADDR_PHY_SHIFT 11
1419 +#define MII_DATA_SHIFT 0
1420 +
1421 +#define FLOW_CONTROL_FCE BIT(1)
1422 +
1423 +#define DMA_BUS_MODE_SWR BIT(0) /* software reset */
1424 +#define DMA_BUS_MODE_BLE BIT(7) /* big endian mode */
1425 +#define DMA_BUS_MODE_PBL_SHIFT 8 /* programmable burst length 32 */
1426 +#define DMA_BUS_MODE_DBO BIT(20) /* big-endian descriptors */
1427 +
1428 +#define DMA_STATUS_TI BIT(0) /* transmit interrupt */
1429 +#define DMA_STATUS_TPS BIT(1) /* transmit process stopped */
1430 +#define DMA_STATUS_TU BIT(2) /* transmit buffer unavailable */
1431 +#define DMA_STATUS_TJT BIT(3) /* transmit buffer timeout */
1432 +#define DMA_STATUS_UNF BIT(5) /* transmit underflow */
1433 +#define DMA_STATUS_RI BIT(6) /* receive interrupt */
1434 +#define DMA_STATUS_RU BIT(7) /* receive buffer unavailable */
1435 +#define DMA_STATUS_RPS BIT(8) /* receive process stopped */
1436 +#define DMA_STATUS_ETI BIT(10) /* early transmit interrupt */
1437 +#define DMA_STATUS_FBE BIT(13) /* fatal bus interrupt */
1438 +#define DMA_STATUS_ERI BIT(14) /* early receive interrupt */
1439 +#define DMA_STATUS_AIS BIT(15) /* abnormal interrupt summary */
1440 +#define DMA_STATUS_NIS BIT(16) /* normal interrupt summary */
1441 +#define DMA_STATUS_RS_SHIFT 17 /* receive process state */
1442 +#define DMA_STATUS_TS_SHIFT 20 /* transmit process state */
1443 +#define DMA_STATUS_EB_SHIFT 23 /* error bits */
1444 +
1445 +#define DMA_CONTROL_SR BIT(1) /* start receive */
1446 +#define DMA_CONTROL_ST BIT(13) /* start transmit */
1447 +#define DMA_CONTROL_SF BIT(21) /* store and forward */
1448 +
1449 +
1450 +typedef struct {
1451 + volatile unsigned int status; /* OWN, Device control and status. */
1452 + volatile unsigned int devcs; /* pkt Control bits + Length */
1453 + volatile unsigned int addr; /* Current Address. */
1454 + volatile unsigned int descr; /* Next descriptor in chain. */
1455 +} ar231x_descr_t;
1456 +
1457 +
1458 +
1459 +/**
1460 + * New Combo structure for Both Eth0 AND eth1
1461 + */
1462 +typedef struct {
1463 + volatile unsigned int mac_control; /* 0x00 */
1464 + volatile unsigned int mac_addr[2]; /* 0x04 - 0x08 */
1465 + volatile unsigned int mcast_table[2]; /* 0x0c - 0x10 */
1466 + volatile unsigned int mii_addr; /* 0x14 */
1467 + volatile unsigned int mii_data; /* 0x18 */
1468 + volatile unsigned int flow_control; /* 0x1c */
1469 + volatile unsigned int vlan_tag; /* 0x20 */
1470 + volatile unsigned int pad[7]; /* 0x24 - 0x3c */
1471 + volatile unsigned int ucast_table[8]; /* 0x40-0x5c */
1472 +
1473 +} ETHERNET_STRUCT;
1474 +
1475 +/********************************************************************
1476 + * Interrupt controller
1477 + ********************************************************************/
1478 +
1479 +typedef struct {
1480 + volatile unsigned int wdog_control; /* 0x08 */
1481 + volatile unsigned int wdog_timer; /* 0x0c */
1482 + volatile unsigned int misc_status; /* 0x10 */
1483 + volatile unsigned int misc_mask; /* 0x14 */
1484 + volatile unsigned int global_status; /* 0x18 */
1485 + volatile unsigned int reserved; /* 0x1c */
1486 + volatile unsigned int reset_control; /* 0x20 */
1487 +} INTERRUPT;
1488 +
1489 +/********************************************************************
1490 + * DMA controller
1491 + ********************************************************************/
1492 +typedef struct {
1493 + volatile unsigned int bus_mode; /* 0x00 (CSR0) */
1494 + volatile unsigned int xmt_poll; /* 0x04 (CSR1) */
1495 + volatile unsigned int rcv_poll; /* 0x08 (CSR2) */
1496 + volatile unsigned int rcv_base; /* 0x0c (CSR3) */
1497 + volatile unsigned int xmt_base; /* 0x10 (CSR4) */
1498 + volatile unsigned int status; /* 0x14 (CSR5) */
1499 + volatile unsigned int control; /* 0x18 (CSR6) */
1500 + volatile unsigned int intr_ena; /* 0x1c (CSR7) */
1501 + volatile unsigned int rcv_missed; /* 0x20 (CSR8) */
1502 + volatile unsigned int reserved[11]; /* 0x24-0x4c (CSR9-19) */
1503 + volatile unsigned int cur_tx_buf_addr; /* 0x50 (CSR20) */
1504 + volatile unsigned int cur_rx_buf_addr; /* 0x50 (CSR21) */
1505 +} DMA;
1506 +
1507 +/**
1508 + * Struct private for the Sibyte.
1509 + *
1510 + * Elements are grouped so variables used by the tx handling goes
1511 + * together, and will go into the same cache lines etc. in order to
1512 + * avoid cache line contention between the rx and tx handling on SMP.
1513 + *
1514 + * Frequently accessed variables are put at the beginning of the
1515 + * struct to help the compiler generate better/shorter code.
1516 + */
1517 +struct ar231x_private {
1518 + struct net_device *dev;
1519 + int version;
1520 + u32 mb[2];
1521 +
1522 + volatile ETHERNET_STRUCT *phy_regs;
1523 + volatile ETHERNET_STRUCT *eth_regs;
1524 + volatile DMA *dma_regs;
1525 + volatile u32 *int_regs;
1526 + struct ar231x_eth *cfg;
1527 +
1528 + spinlock_t lock; /* Serialise access to device */
1529 +
1530 + /* RX and TX descriptors, must be adjacent */
1531 + ar231x_descr_t *rx_ring;
1532 + ar231x_descr_t *tx_ring;
1533 +
1534 +
1535 + struct sk_buff **rx_skb;
1536 + struct sk_buff **tx_skb;
1537 +
1538 + /* RX elements */
1539 + u32 rx_skbprd;
1540 + u32 cur_rx;
1541 +
1542 + /* TX elements */
1543 + u32 tx_prd;
1544 + u32 tx_csm;
1545 +
1546 + /* Misc elements */
1547 + char name[48];
1548 + struct {
1549 + u32 address;
1550 + u32 length;
1551 + char *mapping;
1552 + } desc;
1553 +
1554 +
1555 + struct timer_list link_timer;
1556 + unsigned short phy; /* merlot phy = 1, samsung phy = 0x1f */
1557 + unsigned short mac;
1558 + unsigned short link; /* 0 - link down, 1 - link up */
1559 + u16 phy_data;
1560 +
1561 + struct tasklet_struct rx_tasklet;
1562 + int unloading;
1563 +
1564 + struct phy_device *phy_dev;
1565 + struct mii_bus *mii_bus;
1566 + int oldduplex;
1567 +};
1568 +
1569 +
1570 +/* Prototypes */
1571 +static int ar231x_init(struct net_device *dev);
1572 +#ifdef TX_TIMEOUT
1573 +static void ar231x_tx_timeout(struct net_device *dev);
1574 +#endif
1575 +static int ar231x_restart(struct net_device *dev);
1576 +static void ar231x_load_rx_ring(struct net_device *dev, int bufs);
1577 +static irqreturn_t ar231x_interrupt(int irq, void *dev_id);
1578 +static int ar231x_open(struct net_device *dev);
1579 +static int ar231x_start_xmit(struct sk_buff *skb, struct net_device *dev);
1580 +static int ar231x_close(struct net_device *dev);
1581 +static int ar231x_ioctl(struct net_device *dev, struct ifreq *ifr,
1582 + int cmd);
1583 +static void ar231x_init_cleanup(struct net_device *dev);
1584 +static int ar231x_setup_timer(struct net_device *dev);
1585 +static void ar231x_link_timer_fn(unsigned long data);
1586 +static void ar231x_check_link(struct net_device *dev);
1587 +#endif /* _AR2313_H_ */