atheros: avoid CamelCase
[openwrt/svn-archive/archive.git] / target / linux / atheros / patches-3.10 / 110-ar2313_ethernet.patch
1 --- a/drivers/net/ethernet/Kconfig
2 +++ b/drivers/net/ethernet/Kconfig
3 @@ -22,6 +22,7 @@ source "drivers/net/ethernet/adaptec/Kco
4 source "drivers/net/ethernet/aeroflex/Kconfig"
5 source "drivers/net/ethernet/alteon/Kconfig"
6 source "drivers/net/ethernet/amd/Kconfig"
7 +source "drivers/net/ethernet/ar231x/Kconfig"
8 source "drivers/net/ethernet/apple/Kconfig"
9 source "drivers/net/ethernet/atheros/Kconfig"
10 source "drivers/net/ethernet/cadence/Kconfig"
11 --- a/drivers/net/ethernet/Makefile
12 +++ b/drivers/net/ethernet/Makefile
13 @@ -9,6 +9,7 @@ obj-$(CONFIG_GRETH) += aeroflex/
14 obj-$(CONFIG_NET_VENDOR_ALTEON) += alteon/
15 obj-$(CONFIG_NET_VENDOR_AMD) += amd/
16 obj-$(CONFIG_NET_VENDOR_APPLE) += apple/
17 +obj-$(CONFIG_NET_VENDOR_AR231X) += ar231x/
18 obj-$(CONFIG_NET_VENDOR_ATHEROS) += atheros/
19 obj-$(CONFIG_NET_CADENCE) += cadence/
20 obj-$(CONFIG_NET_BFIN) += adi/
21 --- /dev/null
22 +++ b/drivers/net/ethernet/ar231x/Kconfig
23 @@ -0,0 +1,5 @@
24 +config NET_VENDOR_AR231X
25 + tristate "AR231X Ethernet support"
26 + depends on ATHEROS_AR231X
27 + help
28 + Support for the AR231x/531x ethernet controller
29 --- /dev/null
30 +++ b/drivers/net/ethernet/ar231x/Makefile
31 @@ -0,0 +1 @@
32 +obj-$(CONFIG_NET_VENDOR_AR231X) += ar231x.o
33 --- /dev/null
34 +++ b/drivers/net/ethernet/ar231x/ar231x.c
35 @@ -0,0 +1,1278 @@
36 +/*
37 + * ar231x.c: Linux driver for the Atheros AR231x Ethernet device.
38 + *
39 + * Copyright (C) 2004 by Sameer Dekate <sdekate@arubanetworks.com>
40 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
41 + * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
42 + *
43 + * Thanks to Atheros for providing hardware and documentation
44 + * enabling me to write this driver.
45 + *
46 + * This program is free software; you can redistribute it and/or modify
47 + * it under the terms of the GNU General Public License as published by
48 + * the Free Software Foundation; either version 2 of the License, or
49 + * (at your option) any later version.
50 + *
51 + * Additional credits:
52 + * This code is taken from John Taylor's Sibyte driver and then
53 + * modified for the AR2313.
54 + */
55 +
56 +#include <linux/module.h>
57 +#include <linux/version.h>
58 +#include <linux/types.h>
59 +#include <linux/errno.h>
60 +#include <linux/ioport.h>
61 +#include <linux/pci.h>
62 +#include <linux/netdevice.h>
63 +#include <linux/etherdevice.h>
64 +#include <linux/interrupt.h>
65 +#include <linux/hardirq.h>
66 +#include <linux/skbuff.h>
67 +#include <linux/init.h>
68 +#include <linux/delay.h>
69 +#include <linux/mm.h>
70 +#include <linux/highmem.h>
71 +#include <linux/sockios.h>
72 +#include <linux/pkt_sched.h>
73 +#include <linux/mii.h>
74 +#include <linux/phy.h>
75 +#include <linux/ethtool.h>
76 +#include <linux/ctype.h>
77 +#include <linux/platform_device.h>
78 +
79 +#include <net/sock.h>
80 +#include <net/ip.h>
81 +
82 +#include <asm/io.h>
83 +#include <asm/irq.h>
84 +#include <asm/byteorder.h>
85 +#include <asm/uaccess.h>
86 +#include <asm/bootinfo.h>
87 +
88 +#define AR2313_MTU 1692
89 +#define AR2313_PRIOS 1
90 +#define AR2313_QUEUES (2*AR2313_PRIOS)
91 +#define AR2313_DESCR_ENTRIES 64
92 +
93 +
94 +#ifndef min
95 +#define min(a,b) (((a)<(b))?(a):(b))
96 +#endif
97 +
98 +#ifndef SMP_CACHE_BYTES
99 +#define SMP_CACHE_BYTES L1_CACHE_BYTES
100 +#endif
101 +
102 +#define AR2313_MBOX_SET_BIT 0x8
103 +
104 +#include "ar231x.h"
105 +
106 +/*
107 + * New interrupt handler strategy:
108 + *
109 + * An old interrupt handler worked using the traditional method of
110 + * replacing an skbuff with a new one when a packet arrives. However
111 + * the rx rings do not need to contain a static number of buffer
112 + * descriptors, thus it makes sense to move the memory allocation out
113 + * of the main interrupt handler and do it in a bottom half handler
114 + * and only allocate new buffers when the number of buffers in the
115 + * ring is below a certain threshold. In order to avoid starving the
116 + * NIC under heavy load it is however necessary to force allocation
117 + * when hitting a minimum threshold. The strategy for alloction is as
118 + * follows:
119 + *
120 + * RX_LOW_BUF_THRES - allocate buffers in the bottom half
121 + * RX_PANIC_LOW_THRES - we are very low on buffers, allocate
122 + * the buffers in the interrupt handler
123 + * RX_RING_THRES - maximum number of buffers in the rx ring
124 + *
125 + * One advantagous side effect of this allocation approach is that the
126 + * entire rx processing can be done without holding any spin lock
127 + * since the rx rings and registers are totally independent of the tx
128 + * ring and its registers. This of course includes the kmalloc's of
129 + * new skb's. Thus start_xmit can run in parallel with rx processing
130 + * and the memory allocation on SMP systems.
131 + *
132 + * Note that running the skb reallocation in a bottom half opens up
133 + * another can of races which needs to be handled properly. In
134 + * particular it can happen that the interrupt handler tries to run
135 + * the reallocation while the bottom half is either running on another
136 + * CPU or was interrupted on the same CPU. To get around this the
137 + * driver uses bitops to prevent the reallocation routines from being
138 + * reentered.
139 + *
140 + * TX handling can also be done without holding any spin lock, wheee
141 + * this is fun! since tx_csm is only written to by the interrupt
142 + * handler.
143 + */
144 +
145 +/*
146 + * Threshold values for RX buffer allocation - the low water marks for
147 + * when to start refilling the rings are set to 75% of the ring
148 + * sizes. It seems to make sense to refill the rings entirely from the
149 + * intrrupt handler once it gets below the panic threshold, that way
150 + * we don't risk that the refilling is moved to another CPU when the
151 + * one running the interrupt handler just got the slab code hot in its
152 + * cache.
153 + */
154 +#define RX_RING_SIZE AR2313_DESCR_ENTRIES
155 +#define RX_PANIC_THRES (RX_RING_SIZE/4)
156 +#define RX_LOW_THRES ((3*RX_RING_SIZE)/4)
157 +#define CRC_LEN 4
158 +#define RX_OFFSET 2
159 +
160 +#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
161 +#define VLAN_HDR 4
162 +#else
163 +#define VLAN_HDR 0
164 +#endif
165 +
166 +#define AR2313_BUFSIZE (AR2313_MTU + VLAN_HDR + ETH_HLEN + CRC_LEN + RX_OFFSET)
167 +
168 +#ifdef MODULE
169 +MODULE_LICENSE("GPL");
170 +MODULE_AUTHOR("Sameer Dekate <sdekate@arubanetworks.com>, Imre Kaloz <kaloz@openwrt.org>, Felix Fietkau <nbd@openwrt.org>");
171 +MODULE_DESCRIPTION("AR231x Ethernet driver");
172 +#endif
173 +
174 +#define virt_to_phys(x) ((u32)(x) & 0x1fffffff)
175 +
176 +// prototypes
177 +static void ar231x_halt(struct net_device *dev);
178 +static void rx_tasklet_func(unsigned long data);
179 +static void rx_tasklet_cleanup(struct net_device *dev);
180 +static void ar231x_multicast_list(struct net_device *dev);
181 +static void ar231x_tx_timeout(struct net_device *dev);
182 +
183 +static int ar231x_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum);
184 +static int ar231x_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum, u16 value);
185 +static int ar231x_mdiobus_reset(struct mii_bus *bus);
186 +static int ar231x_mdiobus_probe (struct net_device *dev);
187 +static void ar231x_adjust_link(struct net_device *dev);
188 +
189 +#ifndef ERR
190 +#define ERR(fmt, args...) printk("%s: " fmt, __func__, ##args)
191 +#endif
192 +
193 +#ifdef CONFIG_NET_POLL_CONTROLLER
194 +static void
195 +ar231x_netpoll(struct net_device *dev)
196 +{
197 + unsigned long flags;
198 +
199 + local_irq_save(flags);
200 + ar231x_interrupt(dev->irq, dev);
201 + local_irq_restore(flags);
202 +}
203 +#endif
204 +
205 +static const struct net_device_ops ar231x_ops = {
206 + .ndo_open = ar231x_open,
207 + .ndo_stop = ar231x_close,
208 + .ndo_start_xmit = ar231x_start_xmit,
209 + .ndo_set_rx_mode = ar231x_multicast_list,
210 + .ndo_do_ioctl = ar231x_ioctl,
211 + .ndo_change_mtu = eth_change_mtu,
212 + .ndo_validate_addr = eth_validate_addr,
213 + .ndo_set_mac_address = eth_mac_addr,
214 + .ndo_tx_timeout = ar231x_tx_timeout,
215 +#ifdef CONFIG_NET_POLL_CONTROLLER
216 + .ndo_poll_controller = ar231x_netpoll,
217 +#endif
218 +};
219 +
220 +int ar231x_probe(struct platform_device *pdev)
221 +{
222 + struct net_device *dev;
223 + struct ar231x_private *sp;
224 + struct resource *res;
225 + unsigned long ar_eth_base;
226 + char buf[64];
227 +
228 + dev = alloc_etherdev(sizeof(struct ar231x_private));
229 +
230 + if (dev == NULL) {
231 + printk(KERN_ERR
232 + "ar231x: Unable to allocate net_device structure!\n");
233 + return -ENOMEM;
234 + }
235 +
236 + platform_set_drvdata(pdev, dev);
237 +
238 + sp = netdev_priv(dev);
239 + sp->dev = dev;
240 + sp->cfg = pdev->dev.platform_data;
241 +
242 + sprintf(buf, "eth%d_membase", pdev->id);
243 + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, buf);
244 + if (!res)
245 + return -ENODEV;
246 +
247 + sp->link = 0;
248 + ar_eth_base = res->start;
249 +
250 + sprintf(buf, "eth%d_irq", pdev->id);
251 + dev->irq = platform_get_irq_byname(pdev, buf);
252 +
253 + spin_lock_init(&sp->lock);
254 +
255 + dev->features |= NETIF_F_HIGHDMA;
256 + dev->netdev_ops = &ar231x_ops;
257 +
258 + tasklet_init(&sp->rx_tasklet, rx_tasklet_func, (unsigned long) dev);
259 + tasklet_disable(&sp->rx_tasklet);
260 +
261 + sp->eth_regs =
262 + ioremap_nocache(virt_to_phys(ar_eth_base), sizeof(*sp->eth_regs));
263 + if (!sp->eth_regs) {
264 + printk("Can't remap eth registers\n");
265 + return (-ENXIO);
266 + }
267 +
268 + /*
269 + * When there's only one MAC, PHY regs are typically on ENET0,
270 + * even though the MAC might be on ENET1.
271 + * Needto remap PHY regs separately in this case
272 + */
273 + if (virt_to_phys(ar_eth_base) == virt_to_phys(sp->phy_regs))
274 + sp->phy_regs = sp->eth_regs;
275 + else {
276 + sp->phy_regs =
277 + ioremap_nocache(virt_to_phys(sp->cfg->phy_base),
278 + sizeof(*sp->phy_regs));
279 + if (!sp->phy_regs) {
280 + printk("Can't remap phy registers\n");
281 + return (-ENXIO);
282 + }
283 + }
284 +
285 + sp->dma_regs =
286 + ioremap_nocache(virt_to_phys(ar_eth_base + 0x1000),
287 + sizeof(*sp->dma_regs));
288 + dev->base_addr = (unsigned int) sp->dma_regs;
289 + if (!sp->dma_regs) {
290 + printk("Can't remap DMA registers\n");
291 + return (-ENXIO);
292 + }
293 +
294 + sp->int_regs = ioremap_nocache(virt_to_phys(sp->cfg->reset_base), 4);
295 + if (!sp->int_regs) {
296 + printk("Can't remap INTERRUPT registers\n");
297 + return (-ENXIO);
298 + }
299 +
300 + strncpy(sp->name, "Atheros AR231x", sizeof(sp->name) - 1);
301 + sp->name[sizeof(sp->name) - 1] = '\0';
302 + memcpy(dev->dev_addr, sp->cfg->macaddr, 6);
303 +
304 + if (ar231x_init(dev)) {
305 + /*
306 + * ar231x_init() calls ar231x_init_cleanup() on error.
307 + */
308 + kfree(dev);
309 + return -ENODEV;
310 + }
311 +
312 + if (register_netdev(dev)) {
313 + printk("%s: register_netdev failed\n", __func__);
314 + return -1;
315 + }
316 +
317 + printk("%s: %s: %02x:%02x:%02x:%02x:%02x:%02x, irq %d\n",
318 + dev->name, sp->name,
319 + dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
320 + dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5], dev->irq);
321 +
322 + sp->mii_bus = mdiobus_alloc();
323 + if (sp->mii_bus == NULL)
324 + return -1;
325 +
326 + sp->mii_bus->priv = dev;
327 + sp->mii_bus->read = ar231x_mdiobus_read;
328 + sp->mii_bus->write = ar231x_mdiobus_write;
329 + sp->mii_bus->reset = ar231x_mdiobus_reset;
330 + sp->mii_bus->name = "ar231x_eth_mii";
331 + snprintf(sp->mii_bus->id, MII_BUS_ID_SIZE, "%d", pdev->id);
332 + sp->mii_bus->irq = kmalloc(sizeof(int), GFP_KERNEL);
333 + *sp->mii_bus->irq = PHY_POLL;
334 +
335 + mdiobus_register(sp->mii_bus);
336 +
337 + if (ar231x_mdiobus_probe(dev) != 0) {
338 + printk(KERN_ERR "%s: mdiobus_probe failed\n", dev->name);
339 + rx_tasklet_cleanup(dev);
340 + ar231x_init_cleanup(dev);
341 + unregister_netdev(dev);
342 + kfree(dev);
343 + return -ENODEV;
344 + }
345 +
346 + /* start link poll timer */
347 + ar231x_setup_timer(dev);
348 +
349 + return 0;
350 +}
351 +
352 +
353 +static void ar231x_multicast_list(struct net_device *dev)
354 +{
355 + struct ar231x_private *sp = netdev_priv(dev);
356 + unsigned int filter;
357 +
358 + filter = sp->eth_regs->mac_control;
359 +
360 + if (dev->flags & IFF_PROMISC)
361 + filter |= MAC_CONTROL_PR;
362 + else
363 + filter &= ~MAC_CONTROL_PR;
364 + if ((dev->flags & IFF_ALLMULTI) || (netdev_mc_count(dev) > 0))
365 + filter |= MAC_CONTROL_PM;
366 + else
367 + filter &= ~MAC_CONTROL_PM;
368 +
369 + sp->eth_regs->mac_control = filter;
370 +}
371 +
372 +static void rx_tasklet_cleanup(struct net_device *dev)
373 +{
374 + struct ar231x_private *sp = netdev_priv(dev);
375 +
376 + /*
377 + * Tasklet may be scheduled. Need to get it removed from the list
378 + * since we're about to free the struct.
379 + */
380 +
381 + sp->unloading = 1;
382 + tasklet_enable(&sp->rx_tasklet);
383 + tasklet_kill(&sp->rx_tasklet);
384 +}
385 +
386 +static int ar231x_remove(struct platform_device *pdev)
387 +{
388 + struct net_device *dev = platform_get_drvdata(pdev);
389 + struct ar231x_private *sp = netdev_priv(dev);
390 + rx_tasklet_cleanup(dev);
391 + ar231x_init_cleanup(dev);
392 + unregister_netdev(dev);
393 + mdiobus_unregister(sp->mii_bus);
394 + mdiobus_free(sp->mii_bus);
395 + kfree(dev);
396 + return 0;
397 +}
398 +
399 +
400 +/*
401 + * Restart the AR2313 ethernet controller.
402 + */
403 +static int ar231x_restart(struct net_device *dev)
404 +{
405 + /* disable interrupts */
406 + disable_irq(dev->irq);
407 +
408 + /* stop mac */
409 + ar231x_halt(dev);
410 +
411 + /* initialize */
412 + ar231x_init(dev);
413 +
414 + /* enable interrupts */
415 + enable_irq(dev->irq);
416 +
417 + return 0;
418 +}
419 +
420 +static struct platform_driver ar231x_driver = {
421 + .driver.name = "ar231x-eth",
422 + .probe = ar231x_probe,
423 + .remove = ar231x_remove,
424 +};
425 +
426 +module_platform_driver(ar231x_driver);
427 +
428 +static void ar231x_free_descriptors(struct net_device *dev)
429 +{
430 + struct ar231x_private *sp = netdev_priv(dev);
431 + if (sp->rx_ring != NULL) {
432 + kfree((void *) KSEG0ADDR(sp->rx_ring));
433 + sp->rx_ring = NULL;
434 + sp->tx_ring = NULL;
435 + }
436 +}
437 +
438 +
439 +static int ar231x_allocate_descriptors(struct net_device *dev)
440 +{
441 + struct ar231x_private *sp = netdev_priv(dev);
442 + int size;
443 + int j;
444 + ar231x_descr_t *space;
445 +
446 + if (sp->rx_ring != NULL) {
447 + printk("%s: already done.\n", __FUNCTION__);
448 + return 0;
449 + }
450 +
451 + size =
452 + (sizeof(ar231x_descr_t) * (AR2313_DESCR_ENTRIES * AR2313_QUEUES));
453 + space = kmalloc(size, GFP_KERNEL);
454 + if (space == NULL)
455 + return 1;
456 +
457 + /* invalidate caches */
458 + dma_cache_inv((unsigned int) space, size);
459 +
460 + /* now convert pointer to KSEG1 */
461 + space = (ar231x_descr_t *) KSEG1ADDR(space);
462 +
463 + memset((void *) space, 0, size);
464 +
465 + sp->rx_ring = space;
466 + space += AR2313_DESCR_ENTRIES;
467 +
468 + sp->tx_ring = space;
469 + space += AR2313_DESCR_ENTRIES;
470 +
471 + /* Initialize the transmit Descriptors */
472 + for (j = 0; j < AR2313_DESCR_ENTRIES; j++) {
473 + ar231x_descr_t *td = &sp->tx_ring[j];
474 + td->status = 0;
475 + td->devcs = DMA_TX1_CHAINED;
476 + td->addr = 0;
477 + td->descr =
478 + virt_to_phys(&sp->
479 + tx_ring[(j + 1) & (AR2313_DESCR_ENTRIES - 1)]);
480 + }
481 +
482 + return 0;
483 +}
484 +
485 +
486 +/*
487 + * Generic cleanup handling data allocated during init. Used when the
488 + * module is unloaded or if an error occurs during initialization
489 + */
490 +static void ar231x_init_cleanup(struct net_device *dev)
491 +{
492 + struct ar231x_private *sp = netdev_priv(dev);
493 + struct sk_buff *skb;
494 + int j;
495 +
496 + ar231x_free_descriptors(dev);
497 +
498 + if (sp->eth_regs)
499 + iounmap((void *) sp->eth_regs);
500 + if (sp->dma_regs)
501 + iounmap((void *) sp->dma_regs);
502 +
503 + if (sp->rx_skb) {
504 + for (j = 0; j < AR2313_DESCR_ENTRIES; j++) {
505 + skb = sp->rx_skb[j];
506 + if (skb) {
507 + sp->rx_skb[j] = NULL;
508 + dev_kfree_skb(skb);
509 + }
510 + }
511 + kfree(sp->rx_skb);
512 + sp->rx_skb = NULL;
513 + }
514 +
515 + if (sp->tx_skb) {
516 + for (j = 0; j < AR2313_DESCR_ENTRIES; j++) {
517 + skb = sp->tx_skb[j];
518 + if (skb) {
519 + sp->tx_skb[j] = NULL;
520 + dev_kfree_skb(skb);
521 + }
522 + }
523 + kfree(sp->tx_skb);
524 + sp->tx_skb = NULL;
525 + }
526 +}
527 +
528 +static int ar231x_setup_timer(struct net_device *dev)
529 +{
530 + struct ar231x_private *sp = netdev_priv(dev);
531 +
532 + init_timer(&sp->link_timer);
533 +
534 + sp->link_timer.function = ar231x_link_timer_fn;
535 + sp->link_timer.data = (int) dev;
536 + sp->link_timer.expires = jiffies + HZ;
537 +
538 + add_timer(&sp->link_timer);
539 + return 0;
540 +
541 +}
542 +
543 +static void ar231x_link_timer_fn(unsigned long data)
544 +{
545 + struct net_device *dev = (struct net_device *) data;
546 + struct ar231x_private *sp = netdev_priv(dev);
547 +
548 + // see if the link status changed
549 + // This was needed to make sure we set the PHY to the
550 + // autonegotiated value of half or full duplex.
551 + ar231x_check_link(dev);
552 +
553 + // Loop faster when we don't have link.
554 + // This was needed to speed up the AP bootstrap time.
555 + if (sp->link == 0) {
556 + mod_timer(&sp->link_timer, jiffies + HZ / 2);
557 + } else {
558 + mod_timer(&sp->link_timer, jiffies + LINK_TIMER);
559 + }
560 +}
561 +
562 +static void ar231x_check_link(struct net_device *dev)
563 +{
564 + struct ar231x_private *sp = netdev_priv(dev);
565 + u16 phy_data;
566 +
567 + phy_data = ar231x_mdiobus_read(sp->mii_bus, sp->phy, MII_BMSR);
568 + if (sp->phy_data != phy_data) {
569 + if (phy_data & BMSR_LSTATUS) {
570 + /* link is present, ready link partner ability to deterine
571 + duplexity */
572 + int duplex = 0;
573 + u16 reg;
574 +
575 + sp->link = 1;
576 + reg = ar231x_mdiobus_read(sp->mii_bus, sp->phy, MII_BMCR);
577 + if (reg & BMCR_ANENABLE) {
578 + /* auto neg enabled */
579 + reg = ar231x_mdiobus_read(sp->mii_bus, sp->phy, MII_LPA);
580 + duplex = (reg & (LPA_100FULL | LPA_10FULL)) ? 1 : 0;
581 + } else {
582 + /* no auto neg, just read duplex config */
583 + duplex = (reg & BMCR_FULLDPLX) ? 1 : 0;
584 + }
585 +
586 + printk(KERN_INFO "%s: Configuring MAC for %s duplex\n",
587 + dev->name, (duplex) ? "full" : "half");
588 +
589 + if (duplex) {
590 + /* full duplex */
591 + sp->eth_regs->mac_control =
592 + ((sp->eth_regs->
593 + mac_control | MAC_CONTROL_F) & ~MAC_CONTROL_DRO);
594 + } else {
595 + /* half duplex */
596 + sp->eth_regs->mac_control =
597 + ((sp->eth_regs->
598 + mac_control | MAC_CONTROL_DRO) & ~MAC_CONTROL_F);
599 + }
600 + } else {
601 + /* no link */
602 + sp->link = 0;
603 + }
604 + sp->phy_data = phy_data;
605 + }
606 +}
607 +
608 +static int ar231x_reset_reg(struct net_device *dev)
609 +{
610 + struct ar231x_private *sp = netdev_priv(dev);
611 + unsigned int ethsal, ethsah;
612 + unsigned int flags;
613 +
614 + *sp->int_regs |= sp->cfg->reset_mac;
615 + mdelay(10);
616 + *sp->int_regs &= ~sp->cfg->reset_mac;
617 + mdelay(10);
618 + *sp->int_regs |= sp->cfg->reset_phy;
619 + mdelay(10);
620 + *sp->int_regs &= ~sp->cfg->reset_phy;
621 + mdelay(10);
622 +
623 + sp->dma_regs->bus_mode = (DMA_BUS_MODE_SWR);
624 + mdelay(10);
625 + sp->dma_regs->bus_mode =
626 + ((32 << DMA_BUS_MODE_PBL_SHIFT) | DMA_BUS_MODE_BLE);
627 +
628 + /* enable interrupts */
629 + sp->dma_regs->intr_ena = (DMA_STATUS_AIS |
630 + DMA_STATUS_NIS |
631 + DMA_STATUS_RI |
632 + DMA_STATUS_TI | DMA_STATUS_FBE);
633 + sp->dma_regs->xmt_base = virt_to_phys(sp->tx_ring);
634 + sp->dma_regs->rcv_base = virt_to_phys(sp->rx_ring);
635 + sp->dma_regs->control =
636 + (DMA_CONTROL_SR | DMA_CONTROL_ST | DMA_CONTROL_SF);
637 +
638 + sp->eth_regs->flow_control = (FLOW_CONTROL_FCE);
639 + sp->eth_regs->vlan_tag = (0x8100);
640 +
641 + /* Enable Ethernet Interface */
642 + flags = (MAC_CONTROL_TE | /* transmit enable */
643 + MAC_CONTROL_PM | /* pass mcast */
644 + MAC_CONTROL_F | /* full duplex */
645 + MAC_CONTROL_HBD); /* heart beat disabled */
646 +
647 + if (dev->flags & IFF_PROMISC) { /* set promiscuous mode */
648 + flags |= MAC_CONTROL_PR;
649 + }
650 + sp->eth_regs->mac_control = flags;
651 +
652 + /* Set all Ethernet station address registers to their initial values */
653 + ethsah = ((((u_int) (dev->dev_addr[5]) << 8) & (u_int) 0x0000FF00) |
654 + (((u_int) (dev->dev_addr[4]) << 0) & (u_int) 0x000000FF));
655 +
656 + ethsal = ((((u_int) (dev->dev_addr[3]) << 24) & (u_int) 0xFF000000) |
657 + (((u_int) (dev->dev_addr[2]) << 16) & (u_int) 0x00FF0000) |
658 + (((u_int) (dev->dev_addr[1]) << 8) & (u_int) 0x0000FF00) |
659 + (((u_int) (dev->dev_addr[0]) << 0) & (u_int) 0x000000FF));
660 +
661 + sp->eth_regs->mac_addr[0] = ethsah;
662 + sp->eth_regs->mac_addr[1] = ethsal;
663 +
664 + mdelay(10);
665 +
666 + return (0);
667 +}
668 +
669 +
670 +static int ar231x_init(struct net_device *dev)
671 +{
672 + struct ar231x_private *sp = netdev_priv(dev);
673 + int ecode = 0;
674 +
675 + /*
676 + * Allocate descriptors
677 + */
678 + if (ar231x_allocate_descriptors(dev)) {
679 + printk("%s: %s: ar231x_allocate_descriptors failed\n",
680 + dev->name, __FUNCTION__);
681 + ecode = -EAGAIN;
682 + goto init_error;
683 + }
684 +
685 + /*
686 + * Get the memory for the skb rings.
687 + */
688 + if (sp->rx_skb == NULL) {
689 + sp->rx_skb =
690 + kmalloc(sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES,
691 + GFP_KERNEL);
692 + if (!(sp->rx_skb)) {
693 + printk("%s: %s: rx_skb kmalloc failed\n",
694 + dev->name, __FUNCTION__);
695 + ecode = -EAGAIN;
696 + goto init_error;
697 + }
698 + }
699 + memset(sp->rx_skb, 0, sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES);
700 +
701 + if (sp->tx_skb == NULL) {
702 + sp->tx_skb =
703 + kmalloc(sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES,
704 + GFP_KERNEL);
705 + if (!(sp->tx_skb)) {
706 + printk("%s: %s: tx_skb kmalloc failed\n",
707 + dev->name, __FUNCTION__);
708 + ecode = -EAGAIN;
709 + goto init_error;
710 + }
711 + }
712 + memset(sp->tx_skb, 0, sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES);
713 +
714 + /*
715 + * Set tx_csm before we start receiving interrupts, otherwise
716 + * the interrupt handler might think it is supposed to process
717 + * tx ints before we are up and running, which may cause a null
718 + * pointer access in the int handler.
719 + */
720 + sp->rx_skbprd = 0;
721 + sp->cur_rx = 0;
722 + sp->tx_prd = 0;
723 + sp->tx_csm = 0;
724 +
725 + /*
726 + * Zero the stats before starting the interface
727 + */
728 + memset(&dev->stats, 0, sizeof(dev->stats));
729 +
730 + /*
731 + * We load the ring here as there seem to be no way to tell the
732 + * firmware to wipe the ring without re-initializing it.
733 + */
734 + ar231x_load_rx_ring(dev, RX_RING_SIZE);
735 +
736 + /*
737 + * Init hardware
738 + */
739 + ar231x_reset_reg(dev);
740 +
741 + /*
742 + * Get the IRQ
743 + */
744 + ecode =
745 + request_irq(dev->irq, &ar231x_interrupt,
746 + IRQF_DISABLED,
747 + dev->name, dev);
748 + if (ecode) {
749 + printk(KERN_WARNING "%s: %s: Requested IRQ %d is busy\n",
750 + dev->name, __FUNCTION__, dev->irq);
751 + goto init_error;
752 + }
753 +
754 +
755 + tasklet_enable(&sp->rx_tasklet);
756 +
757 + return 0;
758 +
759 + init_error:
760 + ar231x_init_cleanup(dev);
761 + return ecode;
762 +}
763 +
764 +/*
765 + * Load the rx ring.
766 + *
767 + * Loading rings is safe without holding the spin lock since this is
768 + * done only before the device is enabled, thus no interrupts are
769 + * generated and by the interrupt handler/tasklet handler.
770 + */
771 +static void ar231x_load_rx_ring(struct net_device *dev, int nr_bufs)
772 +{
773 +
774 + struct ar231x_private *sp = netdev_priv(dev);
775 + short i, idx;
776 +
777 + idx = sp->rx_skbprd;
778 +
779 + for (i = 0; i < nr_bufs; i++) {
780 + struct sk_buff *skb;
781 + ar231x_descr_t *rd;
782 +
783 + if (sp->rx_skb[idx])
784 + break;
785 +
786 + skb = netdev_alloc_skb_ip_align(dev, AR2313_BUFSIZE);
787 + if (!skb) {
788 + printk("\n\n\n\n %s: No memory in system\n\n\n\n",
789 + __FUNCTION__);
790 + break;
791 + }
792 +
793 + /*
794 + * Make sure IP header starts on a fresh cache line.
795 + */
796 + skb->dev = dev;
797 + sp->rx_skb[idx] = skb;
798 +
799 + rd = (ar231x_descr_t *) & sp->rx_ring[idx];
800 +
801 + /* initialize dma descriptor */
802 + rd->devcs = ((AR2313_BUFSIZE << DMA_RX1_BSIZE_SHIFT) |
803 + DMA_RX1_CHAINED);
804 + rd->addr = virt_to_phys(skb->data);
805 + rd->descr =
806 + virt_to_phys(&sp->
807 + rx_ring[(idx + 1) & (AR2313_DESCR_ENTRIES - 1)]);
808 + rd->status = DMA_RX_OWN;
809 +
810 + idx = DSC_NEXT(idx);
811 + }
812 +
813 + if (i)
814 + sp->rx_skbprd = idx;
815 +
816 + return;
817 +}
818 +
819 +#define AR2313_MAX_PKTS_PER_CALL 64
820 +
821 +static int ar231x_rx_int(struct net_device *dev)
822 +{
823 + struct ar231x_private *sp = netdev_priv(dev);
824 + struct sk_buff *skb, *skb_new;
825 + ar231x_descr_t *rxdesc;
826 + unsigned int status;
827 + u32 idx;
828 + int pkts = 0;
829 + int rval;
830 +
831 + idx = sp->cur_rx;
832 +
833 + /* process at most the entire ring and then wait for another interrupt
834 + */
835 + while (1) {
836 +
837 + rxdesc = &sp->rx_ring[idx];
838 + status = rxdesc->status;
839 + if (status & DMA_RX_OWN) {
840 + /* SiByte owns descriptor or descr not yet filled in */
841 + rval = 0;
842 + break;
843 + }
844 +
845 + if (++pkts > AR2313_MAX_PKTS_PER_CALL) {
846 + rval = 1;
847 + break;
848 + }
849 +
850 + if ((status & DMA_RX_ERROR) && !(status & DMA_RX_LONG)) {
851 + dev->stats.rx_errors++;
852 + dev->stats.rx_dropped++;
853 +
854 + /* add statistics counters */
855 + if (status & DMA_RX_ERR_CRC)
856 + dev->stats.rx_crc_errors++;
857 + if (status & DMA_RX_ERR_COL)
858 + dev->stats.rx_over_errors++;
859 + if (status & DMA_RX_ERR_LENGTH)
860 + dev->stats.rx_length_errors++;
861 + if (status & DMA_RX_ERR_RUNT)
862 + dev->stats.rx_over_errors++;
863 + if (status & DMA_RX_ERR_DESC)
864 + dev->stats.rx_over_errors++;
865 +
866 + } else {
867 + /* alloc new buffer. */
868 + skb_new = netdev_alloc_skb_ip_align(dev, AR2313_BUFSIZE);
869 + if (skb_new != NULL) {
870 +
871 + skb = sp->rx_skb[idx];
872 + /* set skb */
873 + skb_put(skb,
874 + ((status >> DMA_RX_LEN_SHIFT) & 0x3fff) - CRC_LEN);
875 +
876 + dev->stats.rx_bytes += skb->len;
877 + skb->protocol = eth_type_trans(skb, dev);
878 + /* pass the packet to upper layers */
879 + netif_rx(skb);
880 +
881 + skb_new->dev = dev;
882 + /* reset descriptor's curr_addr */
883 + rxdesc->addr = virt_to_phys(skb_new->data);
884 +
885 + dev->stats.rx_packets++;
886 + sp->rx_skb[idx] = skb_new;
887 + } else {
888 + dev->stats.rx_dropped++;
889 + }
890 + }
891 +
892 + rxdesc->devcs = ((AR2313_BUFSIZE << DMA_RX1_BSIZE_SHIFT) |
893 + DMA_RX1_CHAINED);
894 + rxdesc->status = DMA_RX_OWN;
895 +
896 + idx = DSC_NEXT(idx);
897 + }
898 +
899 + sp->cur_rx = idx;
900 +
901 + return rval;
902 +}
903 +
904 +
905 +static void ar231x_tx_int(struct net_device *dev)
906 +{
907 + struct ar231x_private *sp = netdev_priv(dev);
908 + u32 idx;
909 + struct sk_buff *skb;
910 + ar231x_descr_t *txdesc;
911 + unsigned int status = 0;
912 +
913 + idx = sp->tx_csm;
914 +
915 + while (idx != sp->tx_prd) {
916 + txdesc = &sp->tx_ring[idx];
917 +
918 + if ((status = txdesc->status) & DMA_TX_OWN) {
919 + /* ar231x dma still owns descr */
920 + break;
921 + }
922 + /* done with this descriptor */
923 + dma_unmap_single(NULL, txdesc->addr,
924 + txdesc->devcs & DMA_TX1_BSIZE_MASK,
925 + DMA_TO_DEVICE);
926 + txdesc->status = 0;
927 +
928 + if (status & DMA_TX_ERROR) {
929 + dev->stats.tx_errors++;
930 + dev->stats.tx_dropped++;
931 + if (status & DMA_TX_ERR_UNDER)
932 + dev->stats.tx_fifo_errors++;
933 + if (status & DMA_TX_ERR_HB)
934 + dev->stats.tx_heartbeat_errors++;
935 + if (status & (DMA_TX_ERR_LOSS | DMA_TX_ERR_LINK))
936 + dev->stats.tx_carrier_errors++;
937 + if (status & (DMA_TX_ERR_LATE |
938 + DMA_TX_ERR_COL |
939 + DMA_TX_ERR_JABBER | DMA_TX_ERR_DEFER))
940 + dev->stats.tx_aborted_errors++;
941 + } else {
942 + /* transmit OK */
943 + dev->stats.tx_packets++;
944 + }
945 +
946 + skb = sp->tx_skb[idx];
947 + sp->tx_skb[idx] = NULL;
948 + idx = DSC_NEXT(idx);
949 + dev->stats.tx_bytes += skb->len;
950 + dev_kfree_skb_irq(skb);
951 + }
952 +
953 + sp->tx_csm = idx;
954 +
955 + return;
956 +}
957 +
958 +
959 +static void rx_tasklet_func(unsigned long data)
960 +{
961 + struct net_device *dev = (struct net_device *) data;
962 + struct ar231x_private *sp = netdev_priv(dev);
963 +
964 + if (sp->unloading) {
965 + return;
966 + }
967 +
968 + if (ar231x_rx_int(dev)) {
969 + tasklet_hi_schedule(&sp->rx_tasklet);
970 + } else {
971 + unsigned long flags;
972 + spin_lock_irqsave(&sp->lock, flags);
973 + sp->dma_regs->intr_ena |= DMA_STATUS_RI;
974 + spin_unlock_irqrestore(&sp->lock, flags);
975 + }
976 +}
977 +
978 +static void rx_schedule(struct net_device *dev)
979 +{
980 + struct ar231x_private *sp = netdev_priv(dev);
981 +
982 + sp->dma_regs->intr_ena &= ~DMA_STATUS_RI;
983 +
984 + tasklet_hi_schedule(&sp->rx_tasklet);
985 +}
986 +
987 +static irqreturn_t ar231x_interrupt(int irq, void *dev_id)
988 +{
989 + struct net_device *dev = (struct net_device *) dev_id;
990 + struct ar231x_private *sp = netdev_priv(dev);
991 + unsigned int status, enabled;
992 +
993 + /* clear interrupt */
994 + /*
995 + * Don't clear RI bit if currently disabled.
996 + */
997 + status = sp->dma_regs->status;
998 + enabled = sp->dma_regs->intr_ena;
999 + sp->dma_regs->status = status & enabled;
1000 +
1001 + if (status & DMA_STATUS_NIS) {
1002 + /* normal status */
1003 + /*
1004 + * Don't schedule rx processing if interrupt
1005 + * is already disabled.
1006 + */
1007 + if (status & enabled & DMA_STATUS_RI) {
1008 + /* receive interrupt */
1009 + rx_schedule(dev);
1010 + }
1011 + if (status & DMA_STATUS_TI) {
1012 + /* transmit interrupt */
1013 + ar231x_tx_int(dev);
1014 + }
1015 + }
1016 +
1017 + /* abnormal status */
1018 + if (status & (DMA_STATUS_FBE | DMA_STATUS_TPS)) {
1019 + ar231x_restart(dev);
1020 + }
1021 + return IRQ_HANDLED;
1022 +}
1023 +
1024 +
1025 +static int ar231x_open(struct net_device *dev)
1026 +{
1027 + struct ar231x_private *sp = netdev_priv(dev);
1028 + unsigned int ethsal, ethsah;
1029 +
1030 + /* reset the hardware, in case the MAC address changed */
1031 + ethsah = ((((u_int) (dev->dev_addr[5]) << 8) & (u_int) 0x0000FF00) |
1032 + (((u_int) (dev->dev_addr[4]) << 0) & (u_int) 0x000000FF));
1033 +
1034 + ethsal = ((((u_int) (dev->dev_addr[3]) << 24) & (u_int) 0xFF000000) |
1035 + (((u_int) (dev->dev_addr[2]) << 16) & (u_int) 0x00FF0000) |
1036 + (((u_int) (dev->dev_addr[1]) << 8) & (u_int) 0x0000FF00) |
1037 + (((u_int) (dev->dev_addr[0]) << 0) & (u_int) 0x000000FF));
1038 +
1039 + sp->eth_regs->mac_addr[0] = ethsah;
1040 + sp->eth_regs->mac_addr[1] = ethsal;
1041 +
1042 + mdelay(10);
1043 +
1044 + dev->mtu = 1500;
1045 + netif_start_queue(dev);
1046 +
1047 + sp->eth_regs->mac_control |= MAC_CONTROL_RE;
1048 +
1049 + return 0;
1050 +}
1051 +
1052 +static void ar231x_tx_timeout(struct net_device *dev)
1053 +{
1054 + struct ar231x_private *sp = netdev_priv(dev);
1055 + unsigned long flags;
1056 +
1057 + spin_lock_irqsave(&sp->lock, flags);
1058 + ar231x_restart(dev);
1059 + spin_unlock_irqrestore(&sp->lock, flags);
1060 +}
1061 +
1062 +static void ar231x_halt(struct net_device *dev)
1063 +{
1064 + struct ar231x_private *sp = netdev_priv(dev);
1065 + int j;
1066 +
1067 + tasklet_disable(&sp->rx_tasklet);
1068 +
1069 + /* kill the MAC */
1070 + sp->eth_regs->mac_control &= ~(MAC_CONTROL_RE | /* disable Receives */
1071 + MAC_CONTROL_TE); /* disable Transmits */
1072 + /* stop dma */
1073 + sp->dma_regs->control = 0;
1074 + sp->dma_regs->bus_mode = DMA_BUS_MODE_SWR;
1075 +
1076 + /* place phy and MAC in reset */
1077 + *sp->int_regs |= (sp->cfg->reset_mac | sp->cfg->reset_phy);
1078 +
1079 + /* free buffers on tx ring */
1080 + for (j = 0; j < AR2313_DESCR_ENTRIES; j++) {
1081 + struct sk_buff *skb;
1082 + ar231x_descr_t *txdesc;
1083 +
1084 + txdesc = &sp->tx_ring[j];
1085 + txdesc->descr = 0;
1086 +
1087 + skb = sp->tx_skb[j];
1088 + if (skb) {
1089 + dev_kfree_skb(skb);
1090 + sp->tx_skb[j] = NULL;
1091 + }
1092 + }
1093 +}
1094 +
1095 +/*
1096 + * close should do nothing. Here's why. It's called when
1097 + * 'ifconfig bond0 down' is run. If it calls free_irq then
1098 + * the irq is gone forever ! When bond0 is made 'up' again,
1099 + * the ar231x_open () does not call request_irq (). Worse,
1100 + * the call to ar231x_halt() generates a WDOG reset due to
1101 + * the write to 'sp->int_regs' and the box reboots.
1102 + * Commenting this out is good since it allows the
1103 + * system to resume when bond0 is made up again.
1104 + */
1105 +static int ar231x_close(struct net_device *dev)
1106 +{
1107 +#if 0
1108 + /*
1109 + * Disable interrupts
1110 + */
1111 + disable_irq(dev->irq);
1112 +
1113 + /*
1114 + * Without (or before) releasing irq and stopping hardware, this
1115 + * is an absolute non-sense, by the way. It will be reset instantly
1116 + * by the first irq.
1117 + */
1118 + netif_stop_queue(dev);
1119 +
1120 + /* stop the MAC and DMA engines */
1121 + ar231x_halt(dev);
1122 +
1123 + /* release the interrupt */
1124 + free_irq(dev->irq, dev);
1125 +
1126 +#endif
1127 + return 0;
1128 +}
1129 +
1130 +static int ar231x_start_xmit(struct sk_buff *skb, struct net_device *dev)
1131 +{
1132 + struct ar231x_private *sp = netdev_priv(dev);
1133 + ar231x_descr_t *td;
1134 + u32 idx;
1135 +
1136 + idx = sp->tx_prd;
1137 + td = &sp->tx_ring[idx];
1138 +
1139 + if (td->status & DMA_TX_OWN) {
1140 + /* free skbuf and lie to the caller that we sent it out */
1141 + dev->stats.tx_dropped++;
1142 + dev_kfree_skb(skb);
1143 +
1144 + /* restart transmitter in case locked */
1145 + sp->dma_regs->xmt_poll = 0;
1146 + return 0;
1147 + }
1148 +
1149 + /* Setup the transmit descriptor. */
1150 + td->devcs = ((skb->len << DMA_TX1_BSIZE_SHIFT) |
1151 + (DMA_TX1_LS | DMA_TX1_IC | DMA_TX1_CHAINED));
1152 + td->addr = dma_map_single(NULL, skb->data, skb->len, DMA_TO_DEVICE);
1153 + td->status = DMA_TX_OWN;
1154 +
1155 + /* kick transmitter last */
1156 + sp->dma_regs->xmt_poll = 0;
1157 +
1158 + sp->tx_skb[idx] = skb;
1159 + idx = DSC_NEXT(idx);
1160 + sp->tx_prd = idx;
1161 +
1162 + return 0;
1163 +}
1164 +
1165 +static int ar231x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1166 +{
1167 + struct ar231x_private *sp = netdev_priv(dev);
1168 + int ret;
1169 +
1170 + switch (cmd) {
1171 +
1172 + case SIOCETHTOOL:
1173 + spin_lock_irq(&sp->lock);
1174 + ret = phy_ethtool_ioctl(sp->phy_dev, (void *) ifr->ifr_data);
1175 + spin_unlock_irq(&sp->lock);
1176 + return ret;
1177 +
1178 + case SIOCSIFHWADDR:
1179 + if (copy_from_user
1180 + (dev->dev_addr, ifr->ifr_data, sizeof(dev->dev_addr)))
1181 + return -EFAULT;
1182 + return 0;
1183 +
1184 + case SIOCGIFHWADDR:
1185 + if (copy_to_user
1186 + (ifr->ifr_data, dev->dev_addr, sizeof(dev->dev_addr)))
1187 + return -EFAULT;
1188 + return 0;
1189 +
1190 + case SIOCGMIIPHY:
1191 + case SIOCGMIIREG:
1192 + case SIOCSMIIREG:
1193 + return phy_mii_ioctl(sp->phy_dev, ifr, cmd);
1194 +
1195 + default:
1196 + break;
1197 + }
1198 +
1199 + return -EOPNOTSUPP;
1200 +}
1201 +
1202 +static void ar231x_adjust_link(struct net_device *dev)
1203 +{
1204 + struct ar231x_private *sp = netdev_priv(dev);
1205 + unsigned int mc;
1206 +
1207 + if (!sp->phy_dev->link)
1208 + return;
1209 +
1210 + if (sp->phy_dev->duplex != sp->oldduplex) {
1211 + mc = readl(&sp->eth_regs->mac_control);
1212 + mc &= ~(MAC_CONTROL_F | MAC_CONTROL_DRO);
1213 + if (sp->phy_dev->duplex)
1214 + mc |= MAC_CONTROL_F;
1215 + else
1216 + mc |= MAC_CONTROL_DRO;
1217 + writel(mc, &sp->eth_regs->mac_control);
1218 + sp->oldduplex = sp->phy_dev->duplex;
1219 + }
1220 +}
1221 +
1222 +#define MII_ADDR(phy, reg) \
1223 + ((reg << MII_ADDR_REG_SHIFT) | (phy << MII_ADDR_PHY_SHIFT))
1224 +
1225 +static int
1226 +ar231x_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum)
1227 +{
1228 + struct net_device *const dev = bus->priv;
1229 + struct ar231x_private *sp = netdev_priv(dev);
1230 + volatile ETHERNET_STRUCT *ethernet = sp->phy_regs;
1231 +
1232 + ethernet->mii_addr = MII_ADDR(phy_addr, regnum);
1233 + while (ethernet->mii_addr & MII_ADDR_BUSY);
1234 + return (ethernet->mii_data >> MII_DATA_SHIFT);
1235 +}
1236 +
1237 +static int
1238 +ar231x_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum,
1239 + u16 value)
1240 +{
1241 + struct net_device *const dev = bus->priv;
1242 + struct ar231x_private *sp = netdev_priv(dev);
1243 + volatile ETHERNET_STRUCT *ethernet = sp->phy_regs;
1244 +
1245 + while (ethernet->mii_addr & MII_ADDR_BUSY);
1246 + ethernet->mii_data = value << MII_DATA_SHIFT;
1247 + ethernet->mii_addr = MII_ADDR(phy_addr, regnum) | MII_ADDR_WRITE;
1248 +
1249 + return 0;
1250 +}
1251 +
1252 +static int ar231x_mdiobus_reset(struct mii_bus *bus)
1253 +{
1254 + struct net_device *const dev = bus->priv;
1255 +
1256 + ar231x_reset_reg(dev);
1257 +
1258 + return 0;
1259 +}
1260 +
1261 +static int ar231x_mdiobus_probe (struct net_device *dev)
1262 +{
1263 + struct ar231x_private *const sp = netdev_priv(dev);
1264 + struct phy_device *phydev = NULL;
1265 + int phy_addr;
1266 +
1267 + /* find the first (lowest address) PHY on the current MAC's MII bus */
1268 + for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++)
1269 + if (sp->mii_bus->phy_map[phy_addr]) {
1270 + phydev = sp->mii_bus->phy_map[phy_addr];
1271 + sp->phy = phy_addr;
1272 + break; /* break out with first one found */
1273 + }
1274 +
1275 + if (!phydev) {
1276 + printk (KERN_ERR "ar231x: %s: no PHY found\n", dev->name);
1277 + return -1;
1278 + }
1279 +
1280 + /* now we are supposed to have a proper phydev, to attach to... */
1281 + BUG_ON(!phydev);
1282 + BUG_ON(phydev->attached_dev);
1283 +
1284 + phydev = phy_connect(dev, dev_name(&phydev->dev), &ar231x_adjust_link, 0,
1285 + PHY_INTERFACE_MODE_MII);
1286 +
1287 + if (IS_ERR(phydev)) {
1288 + printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
1289 + return PTR_ERR(phydev);
1290 + }
1291 +
1292 + /* mask with MAC supported features */
1293 + phydev->supported &= (SUPPORTED_10baseT_Half
1294 + | SUPPORTED_10baseT_Full
1295 + | SUPPORTED_100baseT_Half
1296 + | SUPPORTED_100baseT_Full
1297 + | SUPPORTED_Autoneg
1298 + /* | SUPPORTED_Pause | SUPPORTED_Asym_Pause */
1299 + | SUPPORTED_MII
1300 + | SUPPORTED_TP);
1301 +
1302 + phydev->advertising = phydev->supported;
1303 +
1304 + sp->oldduplex = -1;
1305 + sp->phy_dev = phydev;
1306 +
1307 + printk(KERN_INFO "%s: attached PHY driver [%s] "
1308 + "(mii_bus:phy_addr=%s)\n",
1309 + dev->name, phydev->drv->name, dev_name(&phydev->dev));
1310 +
1311 + return 0;
1312 +}
1313 +
1314 --- /dev/null
1315 +++ b/drivers/net/ethernet/ar231x/ar231x.h
1316 @@ -0,0 +1,303 @@
1317 +/*
1318 + * ar231x.h: Linux driver for the Atheros AR231x Ethernet device.
1319 + *
1320 + * Copyright (C) 2004 by Sameer Dekate <sdekate@arubanetworks.com>
1321 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
1322 + * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
1323 + *
1324 + * Thanks to Atheros for providing hardware and documentation
1325 + * enabling me to write this driver.
1326 + *
1327 + * This program is free software; you can redistribute it and/or modify
1328 + * it under the terms of the GNU General Public License as published by
1329 + * the Free Software Foundation; either version 2 of the License, or
1330 + * (at your option) any later version.
1331 + */
1332 +
1333 +#ifndef _AR2313_H_
1334 +#define _AR2313_H_
1335 +
1336 +#include <linux/interrupt.h>
1337 +#include <generated/autoconf.h>
1338 +#include <linux/bitops.h>
1339 +#include <asm/bootinfo.h>
1340 +#include <ar231x_platform.h>
1341 +
1342 +/*
1343 + * probe link timer - 5 secs
1344 + */
1345 +#define LINK_TIMER (5*HZ)
1346 +
1347 +#define IS_DMA_TX_INT(X) (((X) & (DMA_STATUS_TI)) != 0)
1348 +#define IS_DMA_RX_INT(X) (((X) & (DMA_STATUS_RI)) != 0)
1349 +#define IS_DRIVER_OWNED(X) (((X) & (DMA_TX_OWN)) == 0)
1350 +
1351 +#define AR2313_TX_TIMEOUT (HZ/4)
1352 +
1353 +/*
1354 + * Rings
1355 + */
1356 +#define DSC_RING_ENTRIES_SIZE (AR2313_DESCR_ENTRIES * sizeof(struct desc))
1357 +#define DSC_NEXT(idx) ((idx + 1) & (AR2313_DESCR_ENTRIES - 1))
1358 +
1359 +#define AR2313_MBGET 2
1360 +#define AR2313_MBSET 3
1361 +#define AR2313_PCI_RECONFIG 4
1362 +#define AR2313_PCI_DUMP 5
1363 +#define AR2313_TEST_PANIC 6
1364 +#define AR2313_TEST_NULLPTR 7
1365 +#define AR2313_READ_DATA 8
1366 +#define AR2313_WRITE_DATA 9
1367 +#define AR2313_GET_VERSION 10
1368 +#define AR2313_TEST_HANG 11
1369 +#define AR2313_SYNC 12
1370 +
1371 +#define DMA_RX_ERR_CRC BIT(1)
1372 +#define DMA_RX_ERR_DRIB BIT(2)
1373 +#define DMA_RX_ERR_MII BIT(3)
1374 +#define DMA_RX_EV2 BIT(5)
1375 +#define DMA_RX_ERR_COL BIT(6)
1376 +#define DMA_RX_LONG BIT(7)
1377 +#define DMA_RX_LS BIT(8) /* last descriptor */
1378 +#define DMA_RX_FS BIT(9) /* first descriptor */
1379 +#define DMA_RX_MF BIT(10) /* multicast frame */
1380 +#define DMA_RX_ERR_RUNT BIT(11) /* runt frame */
1381 +#define DMA_RX_ERR_LENGTH BIT(12) /* length error */
1382 +#define DMA_RX_ERR_DESC BIT(14) /* descriptor error */
1383 +#define DMA_RX_ERROR BIT(15) /* error summary */
1384 +#define DMA_RX_LEN_MASK 0x3fff0000
1385 +#define DMA_RX_LEN_SHIFT 16
1386 +#define DMA_RX_FILT BIT(30)
1387 +#define DMA_RX_OWN BIT(31) /* desc owned by DMA controller */
1388 +
1389 +#define DMA_RX1_BSIZE_MASK 0x000007ff
1390 +#define DMA_RX1_BSIZE_SHIFT 0
1391 +#define DMA_RX1_CHAINED BIT(24)
1392 +#define DMA_RX1_RER BIT(25)
1393 +
1394 +#define DMA_TX_ERR_UNDER BIT(1) /* underflow error */
1395 +#define DMA_TX_ERR_DEFER BIT(2) /* excessive deferral */
1396 +#define DMA_TX_COL_MASK 0x78
1397 +#define DMA_TX_COL_SHIFT 3
1398 +#define DMA_TX_ERR_HB BIT(7) /* hearbeat failure */
1399 +#define DMA_TX_ERR_COL BIT(8) /* excessive collisions */
1400 +#define DMA_TX_ERR_LATE BIT(9) /* late collision */
1401 +#define DMA_TX_ERR_LINK BIT(10) /* no carrier */
1402 +#define DMA_TX_ERR_LOSS BIT(11) /* loss of carrier */
1403 +#define DMA_TX_ERR_JABBER BIT(14) /* transmit jabber timeout */
1404 +#define DMA_TX_ERROR BIT(15) /* frame aborted */
1405 +#define DMA_TX_OWN BIT(31) /* descr owned by DMA controller */
1406 +
1407 +#define DMA_TX1_BSIZE_MASK 0x000007ff
1408 +#define DMA_TX1_BSIZE_SHIFT 0
1409 +#define DMA_TX1_CHAINED BIT(24) /* chained descriptors */
1410 +#define DMA_TX1_TER BIT(25) /* transmit end of ring */
1411 +#define DMA_TX1_FS BIT(29) /* first segment */
1412 +#define DMA_TX1_LS BIT(30) /* last segment */
1413 +#define DMA_TX1_IC BIT(31) /* interrupt on completion */
1414 +
1415 +#define RCVPKT_LENGTH(X) (X >> 16) /* Received pkt Length */
1416 +
1417 +#define MAC_CONTROL_RE BIT(2) /* receive enable */
1418 +#define MAC_CONTROL_TE BIT(3) /* transmit enable */
1419 +#define MAC_CONTROL_DC BIT(5) /* Deferral check */
1420 +#define MAC_CONTROL_ASTP BIT(8) /* Auto pad strip */
1421 +#define MAC_CONTROL_DRTY BIT(10) /* Disable retry */
1422 +#define MAC_CONTROL_DBF BIT(11) /* Disable bcast frames */
1423 +#define MAC_CONTROL_LCC BIT(12) /* late collision ctrl */
1424 +#define MAC_CONTROL_HP BIT(13) /* Hash Perfect filtering */
1425 +#define MAC_CONTROL_HASH BIT(14) /* Unicast hash filtering */
1426 +#define MAC_CONTROL_HO BIT(15) /* Hash only filtering */
1427 +#define MAC_CONTROL_PB BIT(16) /* Pass Bad frames */
1428 +#define MAC_CONTROL_IF BIT(17) /* Inverse filtering */
1429 +#define MAC_CONTROL_PR BIT(18) /* promiscuous mode (valid frames only) */
1430 +#define MAC_CONTROL_PM BIT(19) /* pass multicast */
1431 +#define MAC_CONTROL_F BIT(20) /* full-duplex */
1432 +#define MAC_CONTROL_DRO BIT(23) /* Disable Receive Own */
1433 +#define MAC_CONTROL_HBD BIT(28) /* heart-beat disabled (MUST BE SET) */
1434 +#define MAC_CONTROL_BLE BIT(30) /* big endian mode */
1435 +#define MAC_CONTROL_RA BIT(31) /* receive all (valid and invalid frames) */
1436 +
1437 +#define MII_ADDR_BUSY BIT(0)
1438 +#define MII_ADDR_WRITE BIT(1)
1439 +#define MII_ADDR_REG_SHIFT 6
1440 +#define MII_ADDR_PHY_SHIFT 11
1441 +#define MII_DATA_SHIFT 0
1442 +
1443 +#define FLOW_CONTROL_FCE BIT(1)
1444 +
1445 +#define DMA_BUS_MODE_SWR BIT(0) /* software reset */
1446 +#define DMA_BUS_MODE_BLE BIT(7) /* big endian mode */
1447 +#define DMA_BUS_MODE_PBL_SHIFT 8 /* programmable burst length 32 */
1448 +#define DMA_BUS_MODE_DBO BIT(20) /* big-endian descriptors */
1449 +
1450 +#define DMA_STATUS_TI BIT(0) /* transmit interrupt */
1451 +#define DMA_STATUS_TPS BIT(1) /* transmit process stopped */
1452 +#define DMA_STATUS_TU BIT(2) /* transmit buffer unavailable */
1453 +#define DMA_STATUS_TJT BIT(3) /* transmit buffer timeout */
1454 +#define DMA_STATUS_UNF BIT(5) /* transmit underflow */
1455 +#define DMA_STATUS_RI BIT(6) /* receive interrupt */
1456 +#define DMA_STATUS_RU BIT(7) /* receive buffer unavailable */
1457 +#define DMA_STATUS_RPS BIT(8) /* receive process stopped */
1458 +#define DMA_STATUS_ETI BIT(10) /* early transmit interrupt */
1459 +#define DMA_STATUS_FBE BIT(13) /* fatal bus interrupt */
1460 +#define DMA_STATUS_ERI BIT(14) /* early receive interrupt */
1461 +#define DMA_STATUS_AIS BIT(15) /* abnormal interrupt summary */
1462 +#define DMA_STATUS_NIS BIT(16) /* normal interrupt summary */
1463 +#define DMA_STATUS_RS_SHIFT 17 /* receive process state */
1464 +#define DMA_STATUS_TS_SHIFT 20 /* transmit process state */
1465 +#define DMA_STATUS_EB_SHIFT 23 /* error bits */
1466 +
1467 +#define DMA_CONTROL_SR BIT(1) /* start receive */
1468 +#define DMA_CONTROL_ST BIT(13) /* start transmit */
1469 +#define DMA_CONTROL_SF BIT(21) /* store and forward */
1470 +
1471 +
1472 +typedef struct {
1473 + volatile unsigned int status; // OWN, Device control and status.
1474 + volatile unsigned int devcs; // pkt Control bits + Length
1475 + volatile unsigned int addr; // Current Address.
1476 + volatile unsigned int descr; // Next descriptor in chain.
1477 +} ar231x_descr_t;
1478 +
1479 +
1480 +
1481 +//
1482 +// New Combo structure for Both Eth0 AND eth1
1483 +//
1484 +typedef struct {
1485 + volatile unsigned int mac_control; /* 0x00 */
1486 + volatile unsigned int mac_addr[2]; /* 0x04 - 0x08 */
1487 + volatile unsigned int mcast_table[2]; /* 0x0c - 0x10 */
1488 + volatile unsigned int mii_addr; /* 0x14 */
1489 + volatile unsigned int mii_data; /* 0x18 */
1490 + volatile unsigned int flow_control; /* 0x1c */
1491 + volatile unsigned int vlan_tag; /* 0x20 */
1492 + volatile unsigned int pad[7]; /* 0x24 - 0x3c */
1493 + volatile unsigned int ucast_table[8]; /* 0x40-0x5c */
1494 +
1495 +} ETHERNET_STRUCT;
1496 +
1497 +/********************************************************************
1498 + * Interrupt controller
1499 + ********************************************************************/
1500 +
1501 +typedef struct {
1502 + volatile unsigned int wdog_control; /* 0x08 */
1503 + volatile unsigned int wdog_timer; /* 0x0c */
1504 + volatile unsigned int misc_status; /* 0x10 */
1505 + volatile unsigned int misc_mask; /* 0x14 */
1506 + volatile unsigned int global_status; /* 0x18 */
1507 + volatile unsigned int reserved; /* 0x1c */
1508 + volatile unsigned int reset_control; /* 0x20 */
1509 +} INTERRUPT;
1510 +
1511 +/********************************************************************
1512 + * DMA controller
1513 + ********************************************************************/
1514 +typedef struct {
1515 + volatile unsigned int bus_mode; /* 0x00 (CSR0) */
1516 + volatile unsigned int xmt_poll; /* 0x04 (CSR1) */
1517 + volatile unsigned int rcv_poll; /* 0x08 (CSR2) */
1518 + volatile unsigned int rcv_base; /* 0x0c (CSR3) */
1519 + volatile unsigned int xmt_base; /* 0x10 (CSR4) */
1520 + volatile unsigned int status; /* 0x14 (CSR5) */
1521 + volatile unsigned int control; /* 0x18 (CSR6) */
1522 + volatile unsigned int intr_ena; /* 0x1c (CSR7) */
1523 + volatile unsigned int rcv_missed; /* 0x20 (CSR8) */
1524 + volatile unsigned int reserved[11]; /* 0x24-0x4c (CSR9-19) */
1525 + volatile unsigned int cur_tx_buf_addr; /* 0x50 (CSR20) */
1526 + volatile unsigned int cur_rx_buf_addr; /* 0x50 (CSR21) */
1527 +} DMA;
1528 +
1529 +/*
1530 + * Struct private for the Sibyte.
1531 + *
1532 + * Elements are grouped so variables used by the tx handling goes
1533 + * together, and will go into the same cache lines etc. in order to
1534 + * avoid cache line contention between the rx and tx handling on SMP.
1535 + *
1536 + * Frequently accessed variables are put at the beginning of the
1537 + * struct to help the compiler generate better/shorter code.
1538 + */
1539 +struct ar231x_private {
1540 + struct net_device *dev;
1541 + int version;
1542 + u32 mb[2];
1543 +
1544 + volatile ETHERNET_STRUCT *phy_regs;
1545 + volatile ETHERNET_STRUCT *eth_regs;
1546 + volatile DMA *dma_regs;
1547 + volatile u32 *int_regs;
1548 + struct ar231x_eth *cfg;
1549 +
1550 + spinlock_t lock; /* Serialise access to device */
1551 +
1552 + /*
1553 + * RX and TX descriptors, must be adjacent
1554 + */
1555 + ar231x_descr_t *rx_ring;
1556 + ar231x_descr_t *tx_ring;
1557 +
1558 +
1559 + struct sk_buff **rx_skb;
1560 + struct sk_buff **tx_skb;
1561 +
1562 + /*
1563 + * RX elements
1564 + */
1565 + u32 rx_skbprd;
1566 + u32 cur_rx;
1567 +
1568 + /*
1569 + * TX elements
1570 + */
1571 + u32 tx_prd;
1572 + u32 tx_csm;
1573 +
1574 + /*
1575 + * Misc elements
1576 + */
1577 + char name[48];
1578 + struct {
1579 + u32 address;
1580 + u32 length;
1581 + char *mapping;
1582 + } desc;
1583 +
1584 +
1585 + struct timer_list link_timer;
1586 + unsigned short phy; /* merlot phy = 1, samsung phy = 0x1f */
1587 + unsigned short mac;
1588 + unsigned short link; /* 0 - link down, 1 - link up */
1589 + u16 phy_data;
1590 +
1591 + struct tasklet_struct rx_tasklet;
1592 + int unloading;
1593 +
1594 + struct phy_device *phy_dev;
1595 + struct mii_bus *mii_bus;
1596 + int oldduplex;
1597 +};
1598 +
1599 +
1600 +/*
1601 + * Prototypes
1602 + */
1603 +static int ar231x_init(struct net_device *dev);
1604 +#ifdef TX_TIMEOUT
1605 +static void ar231x_tx_timeout(struct net_device *dev);
1606 +#endif
1607 +static int ar231x_restart(struct net_device *dev);
1608 +static void ar231x_load_rx_ring(struct net_device *dev, int bufs);
1609 +static irqreturn_t ar231x_interrupt(int irq, void *dev_id);
1610 +static int ar231x_open(struct net_device *dev);
1611 +static int ar231x_start_xmit(struct sk_buff *skb, struct net_device *dev);
1612 +static int ar231x_close(struct net_device *dev);
1613 +static int ar231x_ioctl(struct net_device *dev, struct ifreq *ifr,
1614 + int cmd);
1615 +static void ar231x_init_cleanup(struct net_device *dev);
1616 +static int ar231x_setup_timer(struct net_device *dev);
1617 +static void ar231x_link_timer_fn(unsigned long data);
1618 +static void ar231x_check_link(struct net_device *dev);
1619 +#endif /* _AR2313_H_ */