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atheros[ar231x-eth]: merge patch
[openwrt/svn-archive/archive.git] / target / linux / atheros / patches-3.10 / 110-ar2313_ethernet.patch
1 --- a/drivers/net/ethernet/Kconfig
2 +++ b/drivers/net/ethernet/Kconfig
3 @@ -22,6 +22,7 @@ source "drivers/net/ethernet/adaptec/Kco
4 source "drivers/net/ethernet/aeroflex/Kconfig"
5 source "drivers/net/ethernet/alteon/Kconfig"
6 source "drivers/net/ethernet/amd/Kconfig"
7 +source "drivers/net/ethernet/ar231x/Kconfig"
8 source "drivers/net/ethernet/apple/Kconfig"
9 source "drivers/net/ethernet/atheros/Kconfig"
10 source "drivers/net/ethernet/cadence/Kconfig"
11 --- a/drivers/net/ethernet/Makefile
12 +++ b/drivers/net/ethernet/Makefile
13 @@ -9,6 +9,7 @@ obj-$(CONFIG_GRETH) += aeroflex/
14 obj-$(CONFIG_NET_VENDOR_ALTEON) += alteon/
15 obj-$(CONFIG_NET_VENDOR_AMD) += amd/
16 obj-$(CONFIG_NET_VENDOR_APPLE) += apple/
17 +obj-$(CONFIG_NET_VENDOR_AR231X) += ar231x/
18 obj-$(CONFIG_NET_VENDOR_ATHEROS) += atheros/
19 obj-$(CONFIG_NET_CADENCE) += cadence/
20 obj-$(CONFIG_NET_BFIN) += adi/
21 --- /dev/null
22 +++ b/drivers/net/ethernet/ar231x/Kconfig
23 @@ -0,0 +1,5 @@
24 +config NET_VENDOR_AR231X
25 + tristate "AR231X Ethernet support"
26 + depends on ATHEROS_AR231X
27 + help
28 + Support for the AR231x/531x ethernet controller
29 --- /dev/null
30 +++ b/drivers/net/ethernet/ar231x/Makefile
31 @@ -0,0 +1 @@
32 +obj-$(CONFIG_NET_VENDOR_AR231X) += ar231x.o
33 --- /dev/null
34 +++ b/drivers/net/ethernet/ar231x/ar231x.c
35 @@ -0,0 +1,1254 @@
36 +/*
37 + * ar231x.c: Linux driver for the Atheros AR231x Ethernet device.
38 + *
39 + * Copyright (C) 2004 by Sameer Dekate <sdekate@arubanetworks.com>
40 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
41 + * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
42 + *
43 + * Thanks to Atheros for providing hardware and documentation
44 + * enabling me to write this driver.
45 + *
46 + * This program is free software; you can redistribute it and/or modify
47 + * it under the terms of the GNU General Public License as published by
48 + * the Free Software Foundation; either version 2 of the License, or
49 + * (at your option) any later version.
50 + *
51 + * Additional credits:
52 + * This code is taken from John Taylor's Sibyte driver and then
53 + * modified for the AR2313.
54 + */
55 +
56 +#include <linux/module.h>
57 +#include <linux/version.h>
58 +#include <linux/types.h>
59 +#include <linux/errno.h>
60 +#include <linux/ioport.h>
61 +#include <linux/pci.h>
62 +#include <linux/netdevice.h>
63 +#include <linux/etherdevice.h>
64 +#include <linux/interrupt.h>
65 +#include <linux/hardirq.h>
66 +#include <linux/skbuff.h>
67 +#include <linux/init.h>
68 +#include <linux/delay.h>
69 +#include <linux/mm.h>
70 +#include <linux/highmem.h>
71 +#include <linux/sockios.h>
72 +#include <linux/pkt_sched.h>
73 +#include <linux/mii.h>
74 +#include <linux/phy.h>
75 +#include <linux/ethtool.h>
76 +#include <linux/ctype.h>
77 +#include <linux/platform_device.h>
78 +#include <linux/io.h>
79 +#include <linux/uaccess.h>
80 +
81 +#include <net/sock.h>
82 +#include <net/ip.h>
83 +
84 +#define AR2313_MTU 1692
85 +#define AR2313_PRIOS 1
86 +#define AR2313_QUEUES (2*AR2313_PRIOS)
87 +#define AR2313_DESCR_ENTRIES 64
88 +
89 +
90 +#ifndef min
91 +#define min(a, b) (((a) < (b)) ? (a) : (b))
92 +#endif
93 +
94 +#ifndef SMP_CACHE_BYTES
95 +#define SMP_CACHE_BYTES L1_CACHE_BYTES
96 +#endif
97 +
98 +#define AR2313_MBOX_SET_BIT 0x8
99 +
100 +#include "ar231x.h"
101 +
102 +/**
103 + * New interrupt handler strategy:
104 + *
105 + * An old interrupt handler worked using the traditional method of
106 + * replacing an skbuff with a new one when a packet arrives. However
107 + * the rx rings do not need to contain a static number of buffer
108 + * descriptors, thus it makes sense to move the memory allocation out
109 + * of the main interrupt handler and do it in a bottom half handler
110 + * and only allocate new buffers when the number of buffers in the
111 + * ring is below a certain threshold. In order to avoid starving the
112 + * NIC under heavy load it is however necessary to force allocation
113 + * when hitting a minimum threshold. The strategy for alloction is as
114 + * follows:
115 + *
116 + * RX_LOW_BUF_THRES - allocate buffers in the bottom half
117 + * RX_PANIC_LOW_THRES - we are very low on buffers, allocate
118 + * the buffers in the interrupt handler
119 + * RX_RING_THRES - maximum number of buffers in the rx ring
120 + *
121 + * One advantagous side effect of this allocation approach is that the
122 + * entire rx processing can be done without holding any spin lock
123 + * since the rx rings and registers are totally independent of the tx
124 + * ring and its registers. This of course includes the kmalloc's of
125 + * new skb's. Thus start_xmit can run in parallel with rx processing
126 + * and the memory allocation on SMP systems.
127 + *
128 + * Note that running the skb reallocation in a bottom half opens up
129 + * another can of races which needs to be handled properly. In
130 + * particular it can happen that the interrupt handler tries to run
131 + * the reallocation while the bottom half is either running on another
132 + * CPU or was interrupted on the same CPU. To get around this the
133 + * driver uses bitops to prevent the reallocation routines from being
134 + * reentered.
135 + *
136 + * TX handling can also be done without holding any spin lock, wheee
137 + * this is fun! since tx_csm is only written to by the interrupt
138 + * handler.
139 + */
140 +
141 +/**
142 + * Threshold values for RX buffer allocation - the low water marks for
143 + * when to start refilling the rings are set to 75% of the ring
144 + * sizes. It seems to make sense to refill the rings entirely from the
145 + * intrrupt handler once it gets below the panic threshold, that way
146 + * we don't risk that the refilling is moved to another CPU when the
147 + * one running the interrupt handler just got the slab code hot in its
148 + * cache.
149 + */
150 +#define RX_RING_SIZE AR2313_DESCR_ENTRIES
151 +#define RX_PANIC_THRES (RX_RING_SIZE/4)
152 +#define RX_LOW_THRES ((3*RX_RING_SIZE)/4)
153 +#define CRC_LEN 4
154 +#define RX_OFFSET 2
155 +
156 +#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
157 +#define VLAN_HDR 4
158 +#else
159 +#define VLAN_HDR 0
160 +#endif
161 +
162 +#define AR2313_BUFSIZE (AR2313_MTU + VLAN_HDR + ETH_HLEN + CRC_LEN + \
163 + RX_OFFSET)
164 +
165 +#ifdef MODULE
166 +MODULE_LICENSE("GPL");
167 +MODULE_AUTHOR("Sameer Dekate <sdekate@arubanetworks.com>, Imre Kaloz <kaloz@openwrt.org>, Felix Fietkau <nbd@openwrt.org>");
168 +MODULE_DESCRIPTION("AR231x Ethernet driver");
169 +#endif
170 +
171 +#define virt_to_phys(x) ((u32)(x) & 0x1fffffff)
172 +
173 +/* prototypes */
174 +static void ar231x_halt(struct net_device *dev);
175 +static void rx_tasklet_func(unsigned long data);
176 +static void rx_tasklet_cleanup(struct net_device *dev);
177 +static void ar231x_multicast_list(struct net_device *dev);
178 +static void ar231x_tx_timeout(struct net_device *dev);
179 +
180 +static int ar231x_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum);
181 +static int ar231x_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum,
182 + u16 value);
183 +static int ar231x_mdiobus_reset(struct mii_bus *bus);
184 +static int ar231x_mdiobus_probe(struct net_device *dev);
185 +static void ar231x_adjust_link(struct net_device *dev);
186 +
187 +#ifndef ERR
188 +#define ERR(fmt, args...) printk("%s: " fmt, __func__, ##args)
189 +#endif
190 +
191 +#ifdef CONFIG_NET_POLL_CONTROLLER
192 +static void
193 +ar231x_netpoll(struct net_device *dev)
194 +{
195 + unsigned long flags;
196 +
197 + local_irq_save(flags);
198 + ar231x_interrupt(dev->irq, dev);
199 + local_irq_restore(flags);
200 +}
201 +#endif
202 +
203 +static const struct net_device_ops ar231x_ops = {
204 + .ndo_open = ar231x_open,
205 + .ndo_stop = ar231x_close,
206 + .ndo_start_xmit = ar231x_start_xmit,
207 + .ndo_set_rx_mode = ar231x_multicast_list,
208 + .ndo_do_ioctl = ar231x_ioctl,
209 + .ndo_change_mtu = eth_change_mtu,
210 + .ndo_validate_addr = eth_validate_addr,
211 + .ndo_set_mac_address = eth_mac_addr,
212 + .ndo_tx_timeout = ar231x_tx_timeout,
213 +#ifdef CONFIG_NET_POLL_CONTROLLER
214 + .ndo_poll_controller = ar231x_netpoll,
215 +#endif
216 +};
217 +
218 +int ar231x_probe(struct platform_device *pdev)
219 +{
220 + struct net_device *dev;
221 + struct ar231x_private *sp;
222 + struct resource *res;
223 + unsigned long ar_eth_base;
224 + char buf[64];
225 +
226 + dev = alloc_etherdev(sizeof(struct ar231x_private));
227 +
228 + if (dev == NULL) {
229 + printk(KERN_ERR
230 + "ar231x: Unable to allocate net_device structure!\n");
231 + return -ENOMEM;
232 + }
233 +
234 + platform_set_drvdata(pdev, dev);
235 +
236 + sp = netdev_priv(dev);
237 + sp->dev = dev;
238 + sp->cfg = pdev->dev.platform_data;
239 +
240 + sprintf(buf, "eth%d_membase", pdev->id);
241 + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, buf);
242 + if (!res)
243 + return -ENODEV;
244 +
245 + sp->link = 0;
246 + ar_eth_base = res->start;
247 +
248 + sprintf(buf, "eth%d_irq", pdev->id);
249 + dev->irq = platform_get_irq_byname(pdev, buf);
250 +
251 + spin_lock_init(&sp->lock);
252 +
253 + dev->features |= NETIF_F_HIGHDMA;
254 + dev->netdev_ops = &ar231x_ops;
255 +
256 + tasklet_init(&sp->rx_tasklet, rx_tasklet_func, (unsigned long) dev);
257 + tasklet_disable(&sp->rx_tasklet);
258 +
259 + sp->eth_regs = ioremap_nocache(virt_to_phys(ar_eth_base),
260 + sizeof(*sp->eth_regs));
261 + if (!sp->eth_regs) {
262 + printk("Can't remap eth registers\n");
263 + return -ENXIO;
264 + }
265 +
266 + /**
267 + * When there's only one MAC, PHY regs are typically on ENET0,
268 + * even though the MAC might be on ENET1.
269 + * Needto remap PHY regs separately in this case
270 + */
271 + if (virt_to_phys(ar_eth_base) == virt_to_phys(sp->phy_regs))
272 + sp->phy_regs = sp->eth_regs;
273 + else {
274 + sp->phy_regs =
275 + ioremap_nocache(virt_to_phys(sp->cfg->phy_base),
276 + sizeof(*sp->phy_regs));
277 + if (!sp->phy_regs) {
278 + printk("Can't remap phy registers\n");
279 + return -ENXIO;
280 + }
281 + }
282 +
283 + sp->dma_regs =
284 + ioremap_nocache(virt_to_phys(ar_eth_base + 0x1000),
285 + sizeof(*sp->dma_regs));
286 + dev->base_addr = (unsigned int) sp->dma_regs;
287 + if (!sp->dma_regs) {
288 + printk("Can't remap DMA registers\n");
289 + return -ENXIO;
290 + }
291 +
292 + sp->int_regs = ioremap_nocache(virt_to_phys(sp->cfg->reset_base), 4);
293 + if (!sp->int_regs) {
294 + printk("Can't remap INTERRUPT registers\n");
295 + return -ENXIO;
296 + }
297 +
298 + strncpy(sp->name, "Atheros AR231x", sizeof(sp->name) - 1);
299 + sp->name[sizeof(sp->name) - 1] = '\0';
300 + memcpy(dev->dev_addr, sp->cfg->macaddr, 6);
301 +
302 + if (ar231x_init(dev)) {
303 + /* ar231x_init() calls ar231x_init_cleanup() on error */
304 + kfree(dev);
305 + return -ENODEV;
306 + }
307 +
308 + if (register_netdev(dev)) {
309 + printk("%s: register_netdev failed\n", __func__);
310 + return -1;
311 + }
312 +
313 + printk("%s: %s: %pM, irq %d\n", dev->name, sp->name, dev->dev_addr,
314 + dev->irq);
315 +
316 + sp->mii_bus = mdiobus_alloc();
317 + if (sp->mii_bus == NULL)
318 + return -1;
319 +
320 + sp->mii_bus->priv = dev;
321 + sp->mii_bus->read = ar231x_mdiobus_read;
322 + sp->mii_bus->write = ar231x_mdiobus_write;
323 + sp->mii_bus->reset = ar231x_mdiobus_reset;
324 + sp->mii_bus->name = "ar231x_eth_mii";
325 + snprintf(sp->mii_bus->id, MII_BUS_ID_SIZE, "%d", pdev->id);
326 + sp->mii_bus->irq = kmalloc(sizeof(int), GFP_KERNEL);
327 + *sp->mii_bus->irq = PHY_POLL;
328 +
329 + mdiobus_register(sp->mii_bus);
330 +
331 + if (ar231x_mdiobus_probe(dev) != 0) {
332 + printk(KERN_ERR "%s: mdiobus_probe failed\n", dev->name);
333 + rx_tasklet_cleanup(dev);
334 + ar231x_init_cleanup(dev);
335 + unregister_netdev(dev);
336 + kfree(dev);
337 + return -ENODEV;
338 + }
339 +
340 + /* start link poll timer */
341 + ar231x_setup_timer(dev);
342 +
343 + return 0;
344 +}
345 +
346 +
347 +static void ar231x_multicast_list(struct net_device *dev)
348 +{
349 + struct ar231x_private *sp = netdev_priv(dev);
350 + unsigned int filter;
351 +
352 + filter = sp->eth_regs->mac_control;
353 +
354 + if (dev->flags & IFF_PROMISC)
355 + filter |= MAC_CONTROL_PR;
356 + else
357 + filter &= ~MAC_CONTROL_PR;
358 + if ((dev->flags & IFF_ALLMULTI) || (netdev_mc_count(dev) > 0))
359 + filter |= MAC_CONTROL_PM;
360 + else
361 + filter &= ~MAC_CONTROL_PM;
362 +
363 + sp->eth_regs->mac_control = filter;
364 +}
365 +
366 +static void rx_tasklet_cleanup(struct net_device *dev)
367 +{
368 + struct ar231x_private *sp = netdev_priv(dev);
369 +
370 + /**
371 + * Tasklet may be scheduled. Need to get it removed from the list
372 + * since we're about to free the struct.
373 + */
374 +
375 + sp->unloading = 1;
376 + tasklet_enable(&sp->rx_tasklet);
377 + tasklet_kill(&sp->rx_tasklet);
378 +}
379 +
380 +static int ar231x_remove(struct platform_device *pdev)
381 +{
382 + struct net_device *dev = platform_get_drvdata(pdev);
383 + struct ar231x_private *sp = netdev_priv(dev);
384 + rx_tasklet_cleanup(dev);
385 + ar231x_init_cleanup(dev);
386 + unregister_netdev(dev);
387 + mdiobus_unregister(sp->mii_bus);
388 + mdiobus_free(sp->mii_bus);
389 + kfree(dev);
390 + return 0;
391 +}
392 +
393 +
394 +/**
395 + * Restart the AR2313 ethernet controller.
396 + */
397 +static int ar231x_restart(struct net_device *dev)
398 +{
399 + /* disable interrupts */
400 + disable_irq(dev->irq);
401 +
402 + /* stop mac */
403 + ar231x_halt(dev);
404 +
405 + /* initialize */
406 + ar231x_init(dev);
407 +
408 + /* enable interrupts */
409 + enable_irq(dev->irq);
410 +
411 + return 0;
412 +}
413 +
414 +static struct platform_driver ar231x_driver = {
415 + .driver.name = "ar231x-eth",
416 + .probe = ar231x_probe,
417 + .remove = ar231x_remove,
418 +};
419 +
420 +module_platform_driver(ar231x_driver);
421 +
422 +static void ar231x_free_descriptors(struct net_device *dev)
423 +{
424 + struct ar231x_private *sp = netdev_priv(dev);
425 + if (sp->rx_ring != NULL) {
426 + kfree((void *)KSEG0ADDR(sp->rx_ring));
427 + sp->rx_ring = NULL;
428 + sp->tx_ring = NULL;
429 + }
430 +}
431 +
432 +
433 +static int ar231x_allocate_descriptors(struct net_device *dev)
434 +{
435 + struct ar231x_private *sp = netdev_priv(dev);
436 + int size;
437 + int j;
438 + ar231x_descr_t *space;
439 +
440 + if (sp->rx_ring != NULL) {
441 + printk("%s: already done.\n", __func__);
442 + return 0;
443 + }
444 +
445 + size = sizeof(ar231x_descr_t) * (AR2313_DESCR_ENTRIES * AR2313_QUEUES);
446 + space = kmalloc(size, GFP_KERNEL);
447 + if (space == NULL)
448 + return 1;
449 +
450 + /* invalidate caches */
451 + dma_cache_inv((unsigned int) space, size);
452 +
453 + /* now convert pointer to KSEG1 */
454 + space = (ar231x_descr_t *)KSEG1ADDR(space);
455 +
456 + memset((void *)space, 0, size);
457 +
458 + sp->rx_ring = space;
459 + space += AR2313_DESCR_ENTRIES;
460 +
461 + sp->tx_ring = space;
462 + space += AR2313_DESCR_ENTRIES;
463 +
464 + /* Initialize the transmit Descriptors */
465 + for (j = 0; j < AR2313_DESCR_ENTRIES; j++) {
466 + ar231x_descr_t *td = &sp->tx_ring[j];
467 + td->status = 0;
468 + td->devcs = DMA_TX1_CHAINED;
469 + td->addr = 0;
470 + td->descr = virt_to_phys(&sp->tx_ring[DSC_NEXT(j)]);
471 + }
472 +
473 + return 0;
474 +}
475 +
476 +
477 +/**
478 + * Generic cleanup handling data allocated during init. Used when the
479 + * module is unloaded or if an error occurs during initialization
480 + */
481 +static void ar231x_init_cleanup(struct net_device *dev)
482 +{
483 + struct ar231x_private *sp = netdev_priv(dev);
484 + struct sk_buff *skb;
485 + int j;
486 +
487 + ar231x_free_descriptors(dev);
488 +
489 + if (sp->eth_regs)
490 + iounmap((void *)sp->eth_regs);
491 + if (sp->dma_regs)
492 + iounmap((void *)sp->dma_regs);
493 +
494 + if (sp->rx_skb) {
495 + for (j = 0; j < AR2313_DESCR_ENTRIES; j++) {
496 + skb = sp->rx_skb[j];
497 + if (skb) {
498 + sp->rx_skb[j] = NULL;
499 + dev_kfree_skb(skb);
500 + }
501 + }
502 + kfree(sp->rx_skb);
503 + sp->rx_skb = NULL;
504 + }
505 +
506 + if (sp->tx_skb) {
507 + for (j = 0; j < AR2313_DESCR_ENTRIES; j++) {
508 + skb = sp->tx_skb[j];
509 + if (skb) {
510 + sp->tx_skb[j] = NULL;
511 + dev_kfree_skb(skb);
512 + }
513 + }
514 + kfree(sp->tx_skb);
515 + sp->tx_skb = NULL;
516 + }
517 +}
518 +
519 +static int ar231x_setup_timer(struct net_device *dev)
520 +{
521 + struct ar231x_private *sp = netdev_priv(dev);
522 +
523 + init_timer(&sp->link_timer);
524 +
525 + sp->link_timer.function = ar231x_link_timer_fn;
526 + sp->link_timer.data = (int) dev;
527 + sp->link_timer.expires = jiffies + HZ;
528 +
529 + add_timer(&sp->link_timer);
530 + return 0;
531 +}
532 +
533 +static void ar231x_link_timer_fn(unsigned long data)
534 +{
535 + struct net_device *dev = (struct net_device *)data;
536 + struct ar231x_private *sp = netdev_priv(dev);
537 +
538 + /**
539 + * See if the link status changed.
540 + * This was needed to make sure we set the PHY to the
541 + * autonegotiated value of half or full duplex.
542 + */
543 + ar231x_check_link(dev);
544 +
545 + /**
546 + * Loop faster when we don't have link.
547 + * This was needed to speed up the AP bootstrap time.
548 + */
549 + if (sp->link == 0)
550 + mod_timer(&sp->link_timer, jiffies + HZ / 2);
551 + else
552 + mod_timer(&sp->link_timer, jiffies + LINK_TIMER);
553 +}
554 +
555 +static void ar231x_check_link(struct net_device *dev)
556 +{
557 + struct ar231x_private *sp = netdev_priv(dev);
558 + u16 phy_data;
559 +
560 + phy_data = ar231x_mdiobus_read(sp->mii_bus, sp->phy, MII_BMSR);
561 + if (sp->phy_data != phy_data) {
562 + if (phy_data & BMSR_LSTATUS) {
563 + /**
564 + * Link is present, ready link partner ability to
565 + * deterine duplexity.
566 + */
567 + int duplex = 0;
568 + u16 reg;
569 +
570 + sp->link = 1;
571 + reg = ar231x_mdiobus_read(sp->mii_bus, sp->phy,
572 + MII_BMCR);
573 + if (reg & BMCR_ANENABLE) {
574 + /* auto neg enabled */
575 + reg = ar231x_mdiobus_read(sp->mii_bus, sp->phy,
576 + MII_LPA);
577 + duplex = reg & (LPA_100FULL | LPA_10FULL) ?
578 + 1 : 0;
579 + } else {
580 + /* no auto neg, just read duplex config */
581 + duplex = (reg & BMCR_FULLDPLX) ? 1 : 0;
582 + }
583 +
584 + printk(KERN_INFO "%s: Configuring MAC for %s duplex\n",
585 + dev->name, (duplex) ? "full" : "half");
586 +
587 + if (duplex) {
588 + /* full duplex */
589 + sp->eth_regs->mac_control =
590 + (sp->eth_regs->mac_control |
591 + MAC_CONTROL_F) & ~MAC_CONTROL_DRO;
592 + } else {
593 + /* half duplex */
594 + sp->eth_regs->mac_control =
595 + (sp->eth_regs->mac_control |
596 + MAC_CONTROL_DRO) & ~MAC_CONTROL_F;
597 + }
598 + } else {
599 + /* no link */
600 + sp->link = 0;
601 + }
602 + sp->phy_data = phy_data;
603 + }
604 +}
605 +
606 +static int ar231x_reset_reg(struct net_device *dev)
607 +{
608 + struct ar231x_private *sp = netdev_priv(dev);
609 + unsigned int ethsal, ethsah;
610 + unsigned int flags;
611 +
612 + *sp->int_regs |= sp->cfg->reset_mac;
613 + mdelay(10);
614 + *sp->int_regs &= ~sp->cfg->reset_mac;
615 + mdelay(10);
616 + *sp->int_regs |= sp->cfg->reset_phy;
617 + mdelay(10);
618 + *sp->int_regs &= ~sp->cfg->reset_phy;
619 + mdelay(10);
620 +
621 + sp->dma_regs->bus_mode = (DMA_BUS_MODE_SWR);
622 + mdelay(10);
623 + sp->dma_regs->bus_mode =
624 + ((32 << DMA_BUS_MODE_PBL_SHIFT) | DMA_BUS_MODE_BLE);
625 +
626 + /* enable interrupts */
627 + sp->dma_regs->intr_ena = DMA_STATUS_AIS | DMA_STATUS_NIS |
628 + DMA_STATUS_RI | DMA_STATUS_TI |
629 + DMA_STATUS_FBE;
630 + sp->dma_regs->xmt_base = virt_to_phys(sp->tx_ring);
631 + sp->dma_regs->rcv_base = virt_to_phys(sp->rx_ring);
632 + sp->dma_regs->control =
633 + (DMA_CONTROL_SR | DMA_CONTROL_ST | DMA_CONTROL_SF);
634 +
635 + sp->eth_regs->flow_control = (FLOW_CONTROL_FCE);
636 + sp->eth_regs->vlan_tag = (0x8100);
637 +
638 + /* Enable Ethernet Interface */
639 + flags = (MAC_CONTROL_TE | /* transmit enable */
640 + MAC_CONTROL_PM | /* pass mcast */
641 + MAC_CONTROL_F | /* full duplex */
642 + MAC_CONTROL_HBD); /* heart beat disabled */
643 +
644 + if (dev->flags & IFF_PROMISC) { /* set promiscuous mode */
645 + flags |= MAC_CONTROL_PR;
646 + }
647 + sp->eth_regs->mac_control = flags;
648 +
649 + /* Set all Ethernet station address registers to their initial values */
650 + ethsah = (((u_int) (dev->dev_addr[5]) << 8) & (u_int) 0x0000FF00) |
651 + (((u_int) (dev->dev_addr[4]) << 0) & (u_int) 0x000000FF);
652 +
653 + ethsal = (((u_int) (dev->dev_addr[3]) << 24) & (u_int) 0xFF000000) |
654 + (((u_int) (dev->dev_addr[2]) << 16) & (u_int) 0x00FF0000) |
655 + (((u_int) (dev->dev_addr[1]) << 8) & (u_int) 0x0000FF00) |
656 + (((u_int) (dev->dev_addr[0]) << 0) & (u_int) 0x000000FF);
657 +
658 + sp->eth_regs->mac_addr[0] = ethsah;
659 + sp->eth_regs->mac_addr[1] = ethsal;
660 +
661 + mdelay(10);
662 +
663 + return 0;
664 +}
665 +
666 +
667 +static int ar231x_init(struct net_device *dev)
668 +{
669 + struct ar231x_private *sp = netdev_priv(dev);
670 + int ecode = 0;
671 +
672 + /* Allocate descriptors */
673 + if (ar231x_allocate_descriptors(dev)) {
674 + printk("%s: %s: ar231x_allocate_descriptors failed\n",
675 + dev->name, __func__);
676 + ecode = -EAGAIN;
677 + goto init_error;
678 + }
679 +
680 + /* Get the memory for the skb rings */
681 + if (sp->rx_skb == NULL) {
682 + sp->rx_skb =
683 + kmalloc(sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES,
684 + GFP_KERNEL);
685 + if (!(sp->rx_skb)) {
686 + printk("%s: %s: rx_skb kmalloc failed\n",
687 + dev->name, __func__);
688 + ecode = -EAGAIN;
689 + goto init_error;
690 + }
691 + }
692 + memset(sp->rx_skb, 0, sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES);
693 +
694 + if (sp->tx_skb == NULL) {
695 + sp->tx_skb =
696 + kmalloc(sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES,
697 + GFP_KERNEL);
698 + if (!(sp->tx_skb)) {
699 + printk("%s: %s: tx_skb kmalloc failed\n",
700 + dev->name, __func__);
701 + ecode = -EAGAIN;
702 + goto init_error;
703 + }
704 + }
705 + memset(sp->tx_skb, 0, sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES);
706 +
707 + /**
708 + * Set tx_csm before we start receiving interrupts, otherwise
709 + * the interrupt handler might think it is supposed to process
710 + * tx ints before we are up and running, which may cause a null
711 + * pointer access in the int handler.
712 + */
713 + sp->rx_skbprd = 0;
714 + sp->cur_rx = 0;
715 + sp->tx_prd = 0;
716 + sp->tx_csm = 0;
717 +
718 + /* Zero the stats before starting the interface */
719 + memset(&dev->stats, 0, sizeof(dev->stats));
720 +
721 + /**
722 + * We load the ring here as there seem to be no way to tell the
723 + * firmware to wipe the ring without re-initializing it.
724 + */
725 + ar231x_load_rx_ring(dev, RX_RING_SIZE);
726 +
727 + /* Init hardware */
728 + ar231x_reset_reg(dev);
729 +
730 + /* Get the IRQ */
731 + ecode =
732 + request_irq(dev->irq, &ar231x_interrupt,
733 + IRQF_DISABLED,
734 + dev->name, dev);
735 + if (ecode) {
736 + printk(KERN_WARNING "%s: %s: Requested IRQ %d is busy\n",
737 + dev->name, __func__, dev->irq);
738 + goto init_error;
739 + }
740 +
741 +
742 + tasklet_enable(&sp->rx_tasklet);
743 +
744 + return 0;
745 +
746 +init_error:
747 + ar231x_init_cleanup(dev);
748 + return ecode;
749 +}
750 +
751 +/**
752 + * Load the rx ring.
753 + *
754 + * Loading rings is safe without holding the spin lock since this is
755 + * done only before the device is enabled, thus no interrupts are
756 + * generated and by the interrupt handler/tasklet handler.
757 + */
758 +static void ar231x_load_rx_ring(struct net_device *dev, int nr_bufs)
759 +{
760 + struct ar231x_private *sp = netdev_priv(dev);
761 + short i, idx;
762 +
763 + idx = sp->rx_skbprd;
764 +
765 + for (i = 0; i < nr_bufs; i++) {
766 + struct sk_buff *skb;
767 + ar231x_descr_t *rd;
768 +
769 + if (sp->rx_skb[idx])
770 + break;
771 +
772 + skb = netdev_alloc_skb_ip_align(dev, AR2313_BUFSIZE);
773 + if (!skb) {
774 + printk("\n\n\n\n %s: No memory in system\n\n\n\n",
775 + __func__);
776 + break;
777 + }
778 +
779 + /* Make sure IP header starts on a fresh cache line */
780 + skb->dev = dev;
781 + sp->rx_skb[idx] = skb;
782 +
783 + rd = (ar231x_descr_t *)&sp->rx_ring[idx];
784 +
785 + /* initialize dma descriptor */
786 + rd->devcs = ((AR2313_BUFSIZE << DMA_RX1_BSIZE_SHIFT) |
787 + DMA_RX1_CHAINED);
788 + rd->addr = virt_to_phys(skb->data);
789 + rd->descr = virt_to_phys(&sp->rx_ring[DSC_NEXT(idx)]);
790 + rd->status = DMA_RX_OWN;
791 +
792 + idx = DSC_NEXT(idx);
793 + }
794 +
795 + if (i)
796 + sp->rx_skbprd = idx;
797 +
798 + return;
799 +}
800 +
801 +#define AR2313_MAX_PKTS_PER_CALL 64
802 +
803 +static int ar231x_rx_int(struct net_device *dev)
804 +{
805 + struct ar231x_private *sp = netdev_priv(dev);
806 + struct sk_buff *skb, *skb_new;
807 + ar231x_descr_t *rxdesc;
808 + unsigned int status;
809 + u32 idx;
810 + int pkts = 0;
811 + int rval;
812 +
813 + idx = sp->cur_rx;
814 +
815 + /* process at most the entire ring and then wait for another int */
816 + while (1) {
817 + rxdesc = &sp->rx_ring[idx];
818 + status = rxdesc->status;
819 +
820 + if (status & DMA_RX_OWN) {
821 + /* SiByte owns descriptor or descr not yet filled in */
822 + rval = 0;
823 + break;
824 + }
825 +
826 + if (++pkts > AR2313_MAX_PKTS_PER_CALL) {
827 + rval = 1;
828 + break;
829 + }
830 +
831 + if ((status & DMA_RX_ERROR) && !(status & DMA_RX_LONG)) {
832 + dev->stats.rx_errors++;
833 + dev->stats.rx_dropped++;
834 +
835 + /* add statistics counters */
836 + if (status & DMA_RX_ERR_CRC)
837 + dev->stats.rx_crc_errors++;
838 + if (status & DMA_RX_ERR_COL)
839 + dev->stats.rx_over_errors++;
840 + if (status & DMA_RX_ERR_LENGTH)
841 + dev->stats.rx_length_errors++;
842 + if (status & DMA_RX_ERR_RUNT)
843 + dev->stats.rx_over_errors++;
844 + if (status & DMA_RX_ERR_DESC)
845 + dev->stats.rx_over_errors++;
846 +
847 + } else {
848 + /* alloc new buffer. */
849 + skb_new = netdev_alloc_skb_ip_align(dev,
850 + AR2313_BUFSIZE);
851 + if (skb_new != NULL) {
852 + skb = sp->rx_skb[idx];
853 + /* set skb */
854 + skb_put(skb, ((status >> DMA_RX_LEN_SHIFT) &
855 + 0x3fff) - CRC_LEN);
856 +
857 + dev->stats.rx_bytes += skb->len;
858 + skb->protocol = eth_type_trans(skb, dev);
859 + /* pass the packet to upper layers */
860 + netif_rx(skb);
861 +
862 + skb_new->dev = dev;
863 + /* reset descriptor's curr_addr */
864 + rxdesc->addr = virt_to_phys(skb_new->data);
865 +
866 + dev->stats.rx_packets++;
867 + sp->rx_skb[idx] = skb_new;
868 + } else {
869 + dev->stats.rx_dropped++;
870 + }
871 + }
872 +
873 + rxdesc->devcs = ((AR2313_BUFSIZE << DMA_RX1_BSIZE_SHIFT) |
874 + DMA_RX1_CHAINED);
875 + rxdesc->status = DMA_RX_OWN;
876 +
877 + idx = DSC_NEXT(idx);
878 + }
879 +
880 + sp->cur_rx = idx;
881 +
882 + return rval;
883 +}
884 +
885 +
886 +static void ar231x_tx_int(struct net_device *dev)
887 +{
888 + struct ar231x_private *sp = netdev_priv(dev);
889 + u32 idx;
890 + struct sk_buff *skb;
891 + ar231x_descr_t *txdesc;
892 + unsigned int status = 0;
893 +
894 + idx = sp->tx_csm;
895 +
896 + while (idx != sp->tx_prd) {
897 + txdesc = &sp->tx_ring[idx];
898 + status = txdesc->status;
899 +
900 + if (status & DMA_TX_OWN) {
901 + /* ar231x dma still owns descr */
902 + break;
903 + }
904 + /* done with this descriptor */
905 + dma_unmap_single(NULL, txdesc->addr,
906 + txdesc->devcs & DMA_TX1_BSIZE_MASK,
907 + DMA_TO_DEVICE);
908 + txdesc->status = 0;
909 +
910 + if (status & DMA_TX_ERROR) {
911 + dev->stats.tx_errors++;
912 + dev->stats.tx_dropped++;
913 + if (status & DMA_TX_ERR_UNDER)
914 + dev->stats.tx_fifo_errors++;
915 + if (status & DMA_TX_ERR_HB)
916 + dev->stats.tx_heartbeat_errors++;
917 + if (status & (DMA_TX_ERR_LOSS | DMA_TX_ERR_LINK))
918 + dev->stats.tx_carrier_errors++;
919 + if (status & (DMA_TX_ERR_LATE | DMA_TX_ERR_COL |
920 + DMA_TX_ERR_JABBER | DMA_TX_ERR_DEFER))
921 + dev->stats.tx_aborted_errors++;
922 + } else {
923 + /* transmit OK */
924 + dev->stats.tx_packets++;
925 + }
926 +
927 + skb = sp->tx_skb[idx];
928 + sp->tx_skb[idx] = NULL;
929 + idx = DSC_NEXT(idx);
930 + dev->stats.tx_bytes += skb->len;
931 + dev_kfree_skb_irq(skb);
932 + }
933 +
934 + sp->tx_csm = idx;
935 +
936 + return;
937 +}
938 +
939 +
940 +static void rx_tasklet_func(unsigned long data)
941 +{
942 + struct net_device *dev = (struct net_device *)data;
943 + struct ar231x_private *sp = netdev_priv(dev);
944 +
945 + if (sp->unloading)
946 + return;
947 +
948 + if (ar231x_rx_int(dev)) {
949 + tasklet_hi_schedule(&sp->rx_tasklet);
950 + } else {
951 + unsigned long flags;
952 + spin_lock_irqsave(&sp->lock, flags);
953 + sp->dma_regs->intr_ena |= DMA_STATUS_RI;
954 + spin_unlock_irqrestore(&sp->lock, flags);
955 + }
956 +}
957 +
958 +static void rx_schedule(struct net_device *dev)
959 +{
960 + struct ar231x_private *sp = netdev_priv(dev);
961 +
962 + sp->dma_regs->intr_ena &= ~DMA_STATUS_RI;
963 +
964 + tasklet_hi_schedule(&sp->rx_tasklet);
965 +}
966 +
967 +static irqreturn_t ar231x_interrupt(int irq, void *dev_id)
968 +{
969 + struct net_device *dev = (struct net_device *)dev_id;
970 + struct ar231x_private *sp = netdev_priv(dev);
971 + unsigned int status, enabled;
972 +
973 + /* clear interrupt */
974 + /* Don't clear RI bit if currently disabled */
975 + status = sp->dma_regs->status;
976 + enabled = sp->dma_regs->intr_ena;
977 + sp->dma_regs->status = status & enabled;
978 +
979 + if (status & DMA_STATUS_NIS) {
980 + /* normal status */
981 + /**
982 + * Don't schedule rx processing if interrupt
983 + * is already disabled.
984 + */
985 + if (status & enabled & DMA_STATUS_RI) {
986 + /* receive interrupt */
987 + rx_schedule(dev);
988 + }
989 + if (status & DMA_STATUS_TI) {
990 + /* transmit interrupt */
991 + ar231x_tx_int(dev);
992 + }
993 + }
994 +
995 + /* abnormal status */
996 + if (status & (DMA_STATUS_FBE | DMA_STATUS_TPS))
997 + ar231x_restart(dev);
998 +
999 + return IRQ_HANDLED;
1000 +}
1001 +
1002 +
1003 +static int ar231x_open(struct net_device *dev)
1004 +{
1005 + struct ar231x_private *sp = netdev_priv(dev);
1006 + unsigned int ethsal, ethsah;
1007 +
1008 + /* reset the hardware, in case the MAC address changed */
1009 + ethsah = (((u_int) (dev->dev_addr[5]) << 8) & (u_int) 0x0000FF00) |
1010 + (((u_int) (dev->dev_addr[4]) << 0) & (u_int) 0x000000FF);
1011 +
1012 + ethsal = (((u_int) (dev->dev_addr[3]) << 24) & (u_int) 0xFF000000) |
1013 + (((u_int) (dev->dev_addr[2]) << 16) & (u_int) 0x00FF0000) |
1014 + (((u_int) (dev->dev_addr[1]) << 8) & (u_int) 0x0000FF00) |
1015 + (((u_int) (dev->dev_addr[0]) << 0) & (u_int) 0x000000FF);
1016 +
1017 + sp->eth_regs->mac_addr[0] = ethsah;
1018 + sp->eth_regs->mac_addr[1] = ethsal;
1019 +
1020 + mdelay(10);
1021 +
1022 + dev->mtu = 1500;
1023 + netif_start_queue(dev);
1024 +
1025 + sp->eth_regs->mac_control |= MAC_CONTROL_RE;
1026 +
1027 + return 0;
1028 +}
1029 +
1030 +static void ar231x_tx_timeout(struct net_device *dev)
1031 +{
1032 + struct ar231x_private *sp = netdev_priv(dev);
1033 + unsigned long flags;
1034 +
1035 + spin_lock_irqsave(&sp->lock, flags);
1036 + ar231x_restart(dev);
1037 + spin_unlock_irqrestore(&sp->lock, flags);
1038 +}
1039 +
1040 +static void ar231x_halt(struct net_device *dev)
1041 +{
1042 + struct ar231x_private *sp = netdev_priv(dev);
1043 + int j;
1044 +
1045 + tasklet_disable(&sp->rx_tasklet);
1046 +
1047 + /* kill the MAC */
1048 + sp->eth_regs->mac_control &= ~(MAC_CONTROL_RE | /* disable Receives */
1049 + MAC_CONTROL_TE); /* disable Transmits */
1050 + /* stop dma */
1051 + sp->dma_regs->control = 0;
1052 + sp->dma_regs->bus_mode = DMA_BUS_MODE_SWR;
1053 +
1054 + /* place phy and MAC in reset */
1055 + *sp->int_regs |= (sp->cfg->reset_mac | sp->cfg->reset_phy);
1056 +
1057 + /* free buffers on tx ring */
1058 + for (j = 0; j < AR2313_DESCR_ENTRIES; j++) {
1059 + struct sk_buff *skb;
1060 + ar231x_descr_t *txdesc;
1061 +
1062 + txdesc = &sp->tx_ring[j];
1063 + txdesc->descr = 0;
1064 +
1065 + skb = sp->tx_skb[j];
1066 + if (skb) {
1067 + dev_kfree_skb(skb);
1068 + sp->tx_skb[j] = NULL;
1069 + }
1070 + }
1071 +}
1072 +
1073 +/**
1074 + * close should do nothing. Here's why. It's called when
1075 + * 'ifconfig bond0 down' is run. If it calls free_irq then
1076 + * the irq is gone forever ! When bond0 is made 'up' again,
1077 + * the ar231x_open () does not call request_irq (). Worse,
1078 + * the call to ar231x_halt() generates a WDOG reset due to
1079 + * the write to 'sp->int_regs' and the box reboots.
1080 + * Commenting this out is good since it allows the
1081 + * system to resume when bond0 is made up again.
1082 + */
1083 +static int ar231x_close(struct net_device *dev)
1084 +{
1085 +#if 0
1086 + /* Disable interrupts */
1087 + disable_irq(dev->irq);
1088 +
1089 + /**
1090 + * Without (or before) releasing irq and stopping hardware, this
1091 + * is an absolute non-sense, by the way. It will be reset instantly
1092 + * by the first irq.
1093 + */
1094 + netif_stop_queue(dev);
1095 +
1096 + /* stop the MAC and DMA engines */
1097 + ar231x_halt(dev);
1098 +
1099 + /* release the interrupt */
1100 + free_irq(dev->irq, dev);
1101 +
1102 +#endif
1103 + return 0;
1104 +}
1105 +
1106 +static int ar231x_start_xmit(struct sk_buff *skb, struct net_device *dev)
1107 +{
1108 + struct ar231x_private *sp = netdev_priv(dev);
1109 + ar231x_descr_t *td;
1110 + u32 idx;
1111 +
1112 + idx = sp->tx_prd;
1113 + td = &sp->tx_ring[idx];
1114 +
1115 + if (td->status & DMA_TX_OWN) {
1116 + /* free skbuf and lie to the caller that we sent it out */
1117 + dev->stats.tx_dropped++;
1118 + dev_kfree_skb(skb);
1119 +
1120 + /* restart transmitter in case locked */
1121 + sp->dma_regs->xmt_poll = 0;
1122 + return 0;
1123 + }
1124 +
1125 + /* Setup the transmit descriptor. */
1126 + td->devcs = ((skb->len << DMA_TX1_BSIZE_SHIFT) |
1127 + (DMA_TX1_LS | DMA_TX1_IC | DMA_TX1_CHAINED));
1128 + td->addr = dma_map_single(NULL, skb->data, skb->len, DMA_TO_DEVICE);
1129 + td->status = DMA_TX_OWN;
1130 +
1131 + /* kick transmitter last */
1132 + sp->dma_regs->xmt_poll = 0;
1133 +
1134 + sp->tx_skb[idx] = skb;
1135 + idx = DSC_NEXT(idx);
1136 + sp->tx_prd = idx;
1137 +
1138 + return 0;
1139 +}
1140 +
1141 +static int ar231x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1142 +{
1143 + struct ar231x_private *sp = netdev_priv(dev);
1144 + int ret;
1145 +
1146 + switch (cmd) {
1147 + case SIOCETHTOOL:
1148 + spin_lock_irq(&sp->lock);
1149 + ret = phy_ethtool_ioctl(sp->phy_dev, (void *)ifr->ifr_data);
1150 + spin_unlock_irq(&sp->lock);
1151 + return ret;
1152 +
1153 + case SIOCSIFHWADDR:
1154 + if (copy_from_user
1155 + (dev->dev_addr, ifr->ifr_data, sizeof(dev->dev_addr)))
1156 + return -EFAULT;
1157 + return 0;
1158 +
1159 + case SIOCGIFHWADDR:
1160 + if (copy_to_user
1161 + (ifr->ifr_data, dev->dev_addr, sizeof(dev->dev_addr)))
1162 + return -EFAULT;
1163 + return 0;
1164 +
1165 + case SIOCGMIIPHY:
1166 + case SIOCGMIIREG:
1167 + case SIOCSMIIREG:
1168 + return phy_mii_ioctl(sp->phy_dev, ifr, cmd);
1169 +
1170 + default:
1171 + break;
1172 + }
1173 +
1174 + return -EOPNOTSUPP;
1175 +}
1176 +
1177 +static void ar231x_adjust_link(struct net_device *dev)
1178 +{
1179 + struct ar231x_private *sp = netdev_priv(dev);
1180 + unsigned int mc;
1181 +
1182 + if (!sp->phy_dev->link)
1183 + return;
1184 +
1185 + if (sp->phy_dev->duplex != sp->oldduplex) {
1186 + mc = readl(&sp->eth_regs->mac_control);
1187 + mc &= ~(MAC_CONTROL_F | MAC_CONTROL_DRO);
1188 + if (sp->phy_dev->duplex)
1189 + mc |= MAC_CONTROL_F;
1190 + else
1191 + mc |= MAC_CONTROL_DRO;
1192 + writel(mc, &sp->eth_regs->mac_control);
1193 + sp->oldduplex = sp->phy_dev->duplex;
1194 + }
1195 +}
1196 +
1197 +#define MII_ADDR(phy, reg) \
1198 + ((reg << MII_ADDR_REG_SHIFT) | (phy << MII_ADDR_PHY_SHIFT))
1199 +
1200 +static int
1201 +ar231x_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum)
1202 +{
1203 + struct net_device *const dev = bus->priv;
1204 + struct ar231x_private *sp = netdev_priv(dev);
1205 + volatile ETHERNET_STRUCT *ethernet = sp->phy_regs;
1206 +
1207 + ethernet->mii_addr = MII_ADDR(phy_addr, regnum);
1208 + while (ethernet->mii_addr & MII_ADDR_BUSY)
1209 + ;
1210 + return ethernet->mii_data >> MII_DATA_SHIFT;
1211 +}
1212 +
1213 +static int
1214 +ar231x_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum, u16 value)
1215 +{
1216 + struct net_device *const dev = bus->priv;
1217 + struct ar231x_private *sp = netdev_priv(dev);
1218 + volatile ETHERNET_STRUCT *ethernet = sp->phy_regs;
1219 +
1220 + while (ethernet->mii_addr & MII_ADDR_BUSY)
1221 + ;
1222 + ethernet->mii_data = value << MII_DATA_SHIFT;
1223 + ethernet->mii_addr = MII_ADDR(phy_addr, regnum) | MII_ADDR_WRITE;
1224 +
1225 + return 0;
1226 +}
1227 +
1228 +static int ar231x_mdiobus_reset(struct mii_bus *bus)
1229 +{
1230 + struct net_device *const dev = bus->priv;
1231 +
1232 + ar231x_reset_reg(dev);
1233 +
1234 + return 0;
1235 +}
1236 +
1237 +static int ar231x_mdiobus_probe(struct net_device *dev)
1238 +{
1239 + struct ar231x_private *const sp = netdev_priv(dev);
1240 + struct phy_device *phydev = NULL;
1241 + int phy_addr;
1242 +
1243 + /* find the first (lowest address) PHY on the current MAC's MII bus */
1244 + for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++)
1245 + if (sp->mii_bus->phy_map[phy_addr]) {
1246 + phydev = sp->mii_bus->phy_map[phy_addr];
1247 + sp->phy = phy_addr;
1248 + break; /* break out with first one found */
1249 + }
1250 +
1251 + if (!phydev) {
1252 + printk(KERN_ERR "ar231x: %s: no PHY found\n", dev->name);
1253 + return -1;
1254 + }
1255 +
1256 + /* now we are supposed to have a proper phydev, to attach to... */
1257 + BUG_ON(!phydev);
1258 + BUG_ON(phydev->attached_dev);
1259 +
1260 + phydev = phy_connect(dev, dev_name(&phydev->dev), &ar231x_adjust_link,
1261 + PHY_INTERFACE_MODE_MII);
1262 +
1263 + if (IS_ERR(phydev)) {
1264 + printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
1265 + return PTR_ERR(phydev);
1266 + }
1267 +
1268 + /* mask with MAC supported features */
1269 + phydev->supported &= (SUPPORTED_10baseT_Half
1270 + | SUPPORTED_10baseT_Full
1271 + | SUPPORTED_100baseT_Half
1272 + | SUPPORTED_100baseT_Full
1273 + | SUPPORTED_Autoneg
1274 + /* | SUPPORTED_Pause | SUPPORTED_Asym_Pause */
1275 + | SUPPORTED_MII
1276 + | SUPPORTED_TP);
1277 +
1278 + phydev->advertising = phydev->supported;
1279 +
1280 + sp->oldduplex = -1;
1281 + sp->phy_dev = phydev;
1282 +
1283 + printk(KERN_INFO "%s: attached PHY driver [%s] "
1284 + "(mii_bus:phy_addr=%s)\n",
1285 + dev->name, phydev->drv->name, dev_name(&phydev->dev));
1286 +
1287 + return 0;
1288 +}
1289 +
1290 --- /dev/null
1291 +++ b/drivers/net/ethernet/ar231x/ar231x.h
1292 @@ -0,0 +1,288 @@
1293 +/*
1294 + * ar231x.h: Linux driver for the Atheros AR231x Ethernet device.
1295 + *
1296 + * Copyright (C) 2004 by Sameer Dekate <sdekate@arubanetworks.com>
1297 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
1298 + * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
1299 + *
1300 + * Thanks to Atheros for providing hardware and documentation
1301 + * enabling me to write this driver.
1302 + *
1303 + * This program is free software; you can redistribute it and/or modify
1304 + * it under the terms of the GNU General Public License as published by
1305 + * the Free Software Foundation; either version 2 of the License, or
1306 + * (at your option) any later version.
1307 + */
1308 +
1309 +#ifndef _AR2313_H_
1310 +#define _AR2313_H_
1311 +
1312 +#include <linux/interrupt.h>
1313 +#include <generated/autoconf.h>
1314 +#include <linux/bitops.h>
1315 +#include <ar231x_platform.h>
1316 +
1317 +/* probe link timer - 5 secs */
1318 +#define LINK_TIMER (5*HZ)
1319 +
1320 +#define IS_DMA_TX_INT(X) (((X) & (DMA_STATUS_TI)) != 0)
1321 +#define IS_DMA_RX_INT(X) (((X) & (DMA_STATUS_RI)) != 0)
1322 +#define IS_DRIVER_OWNED(X) (((X) & (DMA_TX_OWN)) == 0)
1323 +
1324 +#define AR2313_TX_TIMEOUT (HZ/4)
1325 +
1326 +/* Rings */
1327 +#define DSC_RING_ENTRIES_SIZE (AR2313_DESCR_ENTRIES * sizeof(struct desc))
1328 +#define DSC_NEXT(idx) ((idx + 1) & (AR2313_DESCR_ENTRIES - 1))
1329 +
1330 +#define AR2313_MBGET 2
1331 +#define AR2313_MBSET 3
1332 +#define AR2313_PCI_RECONFIG 4
1333 +#define AR2313_PCI_DUMP 5
1334 +#define AR2313_TEST_PANIC 6
1335 +#define AR2313_TEST_NULLPTR 7
1336 +#define AR2313_READ_DATA 8
1337 +#define AR2313_WRITE_DATA 9
1338 +#define AR2313_GET_VERSION 10
1339 +#define AR2313_TEST_HANG 11
1340 +#define AR2313_SYNC 12
1341 +
1342 +#define DMA_RX_ERR_CRC BIT(1)
1343 +#define DMA_RX_ERR_DRIB BIT(2)
1344 +#define DMA_RX_ERR_MII BIT(3)
1345 +#define DMA_RX_EV2 BIT(5)
1346 +#define DMA_RX_ERR_COL BIT(6)
1347 +#define DMA_RX_LONG BIT(7)
1348 +#define DMA_RX_LS BIT(8) /* last descriptor */
1349 +#define DMA_RX_FS BIT(9) /* first descriptor */
1350 +#define DMA_RX_MF BIT(10) /* multicast frame */
1351 +#define DMA_RX_ERR_RUNT BIT(11) /* runt frame */
1352 +#define DMA_RX_ERR_LENGTH BIT(12) /* length error */
1353 +#define DMA_RX_ERR_DESC BIT(14) /* descriptor error */
1354 +#define DMA_RX_ERROR BIT(15) /* error summary */
1355 +#define DMA_RX_LEN_MASK 0x3fff0000
1356 +#define DMA_RX_LEN_SHIFT 16
1357 +#define DMA_RX_FILT BIT(30)
1358 +#define DMA_RX_OWN BIT(31) /* desc owned by DMA controller */
1359 +
1360 +#define DMA_RX1_BSIZE_MASK 0x000007ff
1361 +#define DMA_RX1_BSIZE_SHIFT 0
1362 +#define DMA_RX1_CHAINED BIT(24)
1363 +#define DMA_RX1_RER BIT(25)
1364 +
1365 +#define DMA_TX_ERR_UNDER BIT(1) /* underflow error */
1366 +#define DMA_TX_ERR_DEFER BIT(2) /* excessive deferral */
1367 +#define DMA_TX_COL_MASK 0x78
1368 +#define DMA_TX_COL_SHIFT 3
1369 +#define DMA_TX_ERR_HB BIT(7) /* hearbeat failure */
1370 +#define DMA_TX_ERR_COL BIT(8) /* excessive collisions */
1371 +#define DMA_TX_ERR_LATE BIT(9) /* late collision */
1372 +#define DMA_TX_ERR_LINK BIT(10) /* no carrier */
1373 +#define DMA_TX_ERR_LOSS BIT(11) /* loss of carrier */
1374 +#define DMA_TX_ERR_JABBER BIT(14) /* transmit jabber timeout */
1375 +#define DMA_TX_ERROR BIT(15) /* frame aborted */
1376 +#define DMA_TX_OWN BIT(31) /* descr owned by DMA controller */
1377 +
1378 +#define DMA_TX1_BSIZE_MASK 0x000007ff
1379 +#define DMA_TX1_BSIZE_SHIFT 0
1380 +#define DMA_TX1_CHAINED BIT(24) /* chained descriptors */
1381 +#define DMA_TX1_TER BIT(25) /* transmit end of ring */
1382 +#define DMA_TX1_FS BIT(29) /* first segment */
1383 +#define DMA_TX1_LS BIT(30) /* last segment */
1384 +#define DMA_TX1_IC BIT(31) /* interrupt on completion */
1385 +
1386 +#define RCVPKT_LENGTH(X) (X >> 16) /* Received pkt Length */
1387 +
1388 +#define MAC_CONTROL_RE BIT(2) /* receive enable */
1389 +#define MAC_CONTROL_TE BIT(3) /* transmit enable */
1390 +#define MAC_CONTROL_DC BIT(5) /* Deferral check */
1391 +#define MAC_CONTROL_ASTP BIT(8) /* Auto pad strip */
1392 +#define MAC_CONTROL_DRTY BIT(10) /* Disable retry */
1393 +#define MAC_CONTROL_DBF BIT(11) /* Disable bcast frames */
1394 +#define MAC_CONTROL_LCC BIT(12) /* late collision ctrl */
1395 +#define MAC_CONTROL_HP BIT(13) /* Hash Perfect filtering */
1396 +#define MAC_CONTROL_HASH BIT(14) /* Unicast hash filtering */
1397 +#define MAC_CONTROL_HO BIT(15) /* Hash only filtering */
1398 +#define MAC_CONTROL_PB BIT(16) /* Pass Bad frames */
1399 +#define MAC_CONTROL_IF BIT(17) /* Inverse filtering */
1400 +#define MAC_CONTROL_PR BIT(18) /* promis mode (valid frames only) */
1401 +#define MAC_CONTROL_PM BIT(19) /* pass multicast */
1402 +#define MAC_CONTROL_F BIT(20) /* full-duplex */
1403 +#define MAC_CONTROL_DRO BIT(23) /* Disable Receive Own */
1404 +#define MAC_CONTROL_HBD BIT(28) /* heart-beat disabled (MUST BE SET) */
1405 +#define MAC_CONTROL_BLE BIT(30) /* big endian mode */
1406 +#define MAC_CONTROL_RA BIT(31) /* rcv all (valid and invalid frames) */
1407 +
1408 +#define MII_ADDR_BUSY BIT(0)
1409 +#define MII_ADDR_WRITE BIT(1)
1410 +#define MII_ADDR_REG_SHIFT 6
1411 +#define MII_ADDR_PHY_SHIFT 11
1412 +#define MII_DATA_SHIFT 0
1413 +
1414 +#define FLOW_CONTROL_FCE BIT(1)
1415 +
1416 +#define DMA_BUS_MODE_SWR BIT(0) /* software reset */
1417 +#define DMA_BUS_MODE_BLE BIT(7) /* big endian mode */
1418 +#define DMA_BUS_MODE_PBL_SHIFT 8 /* programmable burst length 32 */
1419 +#define DMA_BUS_MODE_DBO BIT(20) /* big-endian descriptors */
1420 +
1421 +#define DMA_STATUS_TI BIT(0) /* transmit interrupt */
1422 +#define DMA_STATUS_TPS BIT(1) /* transmit process stopped */
1423 +#define DMA_STATUS_TU BIT(2) /* transmit buffer unavailable */
1424 +#define DMA_STATUS_TJT BIT(3) /* transmit buffer timeout */
1425 +#define DMA_STATUS_UNF BIT(5) /* transmit underflow */
1426 +#define DMA_STATUS_RI BIT(6) /* receive interrupt */
1427 +#define DMA_STATUS_RU BIT(7) /* receive buffer unavailable */
1428 +#define DMA_STATUS_RPS BIT(8) /* receive process stopped */
1429 +#define DMA_STATUS_ETI BIT(10) /* early transmit interrupt */
1430 +#define DMA_STATUS_FBE BIT(13) /* fatal bus interrupt */
1431 +#define DMA_STATUS_ERI BIT(14) /* early receive interrupt */
1432 +#define DMA_STATUS_AIS BIT(15) /* abnormal interrupt summary */
1433 +#define DMA_STATUS_NIS BIT(16) /* normal interrupt summary */
1434 +#define DMA_STATUS_RS_SHIFT 17 /* receive process state */
1435 +#define DMA_STATUS_TS_SHIFT 20 /* transmit process state */
1436 +#define DMA_STATUS_EB_SHIFT 23 /* error bits */
1437 +
1438 +#define DMA_CONTROL_SR BIT(1) /* start receive */
1439 +#define DMA_CONTROL_ST BIT(13) /* start transmit */
1440 +#define DMA_CONTROL_SF BIT(21) /* store and forward */
1441 +
1442 +
1443 +typedef struct {
1444 + volatile unsigned int status; /* OWN, Device control and status. */
1445 + volatile unsigned int devcs; /* pkt Control bits + Length */
1446 + volatile unsigned int addr; /* Current Address. */
1447 + volatile unsigned int descr; /* Next descriptor in chain. */
1448 +} ar231x_descr_t;
1449 +
1450 +
1451 +
1452 +/**
1453 + * New Combo structure for Both Eth0 AND eth1
1454 + */
1455 +typedef struct {
1456 + volatile unsigned int mac_control; /* 0x00 */
1457 + volatile unsigned int mac_addr[2]; /* 0x04 - 0x08 */
1458 + volatile unsigned int mcast_table[2]; /* 0x0c - 0x10 */
1459 + volatile unsigned int mii_addr; /* 0x14 */
1460 + volatile unsigned int mii_data; /* 0x18 */
1461 + volatile unsigned int flow_control; /* 0x1c */
1462 + volatile unsigned int vlan_tag; /* 0x20 */
1463 + volatile unsigned int pad[7]; /* 0x24 - 0x3c */
1464 + volatile unsigned int ucast_table[8]; /* 0x40-0x5c */
1465 +
1466 +} ETHERNET_STRUCT;
1467 +
1468 +/********************************************************************
1469 + * Interrupt controller
1470 + ********************************************************************/
1471 +
1472 +typedef struct {
1473 + volatile unsigned int wdog_control; /* 0x08 */
1474 + volatile unsigned int wdog_timer; /* 0x0c */
1475 + volatile unsigned int misc_status; /* 0x10 */
1476 + volatile unsigned int misc_mask; /* 0x14 */
1477 + volatile unsigned int global_status; /* 0x18 */
1478 + volatile unsigned int reserved; /* 0x1c */
1479 + volatile unsigned int reset_control; /* 0x20 */
1480 +} INTERRUPT;
1481 +
1482 +/********************************************************************
1483 + * DMA controller
1484 + ********************************************************************/
1485 +typedef struct {
1486 + volatile unsigned int bus_mode; /* 0x00 (CSR0) */
1487 + volatile unsigned int xmt_poll; /* 0x04 (CSR1) */
1488 + volatile unsigned int rcv_poll; /* 0x08 (CSR2) */
1489 + volatile unsigned int rcv_base; /* 0x0c (CSR3) */
1490 + volatile unsigned int xmt_base; /* 0x10 (CSR4) */
1491 + volatile unsigned int status; /* 0x14 (CSR5) */
1492 + volatile unsigned int control; /* 0x18 (CSR6) */
1493 + volatile unsigned int intr_ena; /* 0x1c (CSR7) */
1494 + volatile unsigned int rcv_missed; /* 0x20 (CSR8) */
1495 + volatile unsigned int reserved[11]; /* 0x24-0x4c (CSR9-19) */
1496 + volatile unsigned int cur_tx_buf_addr; /* 0x50 (CSR20) */
1497 + volatile unsigned int cur_rx_buf_addr; /* 0x50 (CSR21) */
1498 +} DMA;
1499 +
1500 +/**
1501 + * Struct private for the Sibyte.
1502 + *
1503 + * Elements are grouped so variables used by the tx handling goes
1504 + * together, and will go into the same cache lines etc. in order to
1505 + * avoid cache line contention between the rx and tx handling on SMP.
1506 + *
1507 + * Frequently accessed variables are put at the beginning of the
1508 + * struct to help the compiler generate better/shorter code.
1509 + */
1510 +struct ar231x_private {
1511 + struct net_device *dev;
1512 + int version;
1513 + u32 mb[2];
1514 +
1515 + volatile ETHERNET_STRUCT *phy_regs;
1516 + volatile ETHERNET_STRUCT *eth_regs;
1517 + volatile DMA *dma_regs;
1518 + volatile u32 *int_regs;
1519 + struct ar231x_eth *cfg;
1520 +
1521 + spinlock_t lock; /* Serialise access to device */
1522 +
1523 + /* RX and TX descriptors, must be adjacent */
1524 + ar231x_descr_t *rx_ring;
1525 + ar231x_descr_t *tx_ring;
1526 +
1527 +
1528 + struct sk_buff **rx_skb;
1529 + struct sk_buff **tx_skb;
1530 +
1531 + /* RX elements */
1532 + u32 rx_skbprd;
1533 + u32 cur_rx;
1534 +
1535 + /* TX elements */
1536 + u32 tx_prd;
1537 + u32 tx_csm;
1538 +
1539 + /* Misc elements */
1540 + char name[48];
1541 + struct {
1542 + u32 address;
1543 + u32 length;
1544 + char *mapping;
1545 + } desc;
1546 +
1547 +
1548 + struct timer_list link_timer;
1549 + unsigned short phy; /* merlot phy = 1, samsung phy = 0x1f */
1550 + unsigned short mac;
1551 + unsigned short link; /* 0 - link down, 1 - link up */
1552 + u16 phy_data;
1553 +
1554 + struct tasklet_struct rx_tasklet;
1555 + int unloading;
1556 +
1557 + struct phy_device *phy_dev;
1558 + struct mii_bus *mii_bus;
1559 + int oldduplex;
1560 +};
1561 +
1562 +
1563 +/* Prototypes */
1564 +static int ar231x_init(struct net_device *dev);
1565 +#ifdef TX_TIMEOUT
1566 +static void ar231x_tx_timeout(struct net_device *dev);
1567 +#endif
1568 +static int ar231x_restart(struct net_device *dev);
1569 +static void ar231x_load_rx_ring(struct net_device *dev, int bufs);
1570 +static irqreturn_t ar231x_interrupt(int irq, void *dev_id);
1571 +static int ar231x_open(struct net_device *dev);
1572 +static int ar231x_start_xmit(struct sk_buff *skb, struct net_device *dev);
1573 +static int ar231x_close(struct net_device *dev);
1574 +static int ar231x_ioctl(struct net_device *dev, struct ifreq *ifr,
1575 + int cmd);
1576 +static void ar231x_init_cleanup(struct net_device *dev);
1577 +static int ar231x_setup_timer(struct net_device *dev);
1578 +static void ar231x_link_timer_fn(unsigned long data);
1579 +static void ar231x_check_link(struct net_device *dev);
1580 +#endif /* _AR2313_H_ */
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