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atheros[ar231x-eth]: move driver to atheros subdirectory
[openwrt/svn-archive/archive.git] / target / linux / atheros / patches-3.10 / 110-ar2313_ethernet.patch
1 --- a/drivers/net/ethernet/atheros/Makefile
2 +++ b/drivers/net/ethernet/atheros/Makefile
3 @@ -7,3 +7,4 @@ obj-$(CONFIG_ATL2) += atlx/
4 obj-$(CONFIG_ATL1E) += atl1e/
5 obj-$(CONFIG_ATL1C) += atl1c/
6 obj-$(CONFIG_ALX) += alx/
7 +obj-$(CONFIG_NET_AR231X) += ar231x/
8 --- a/drivers/net/ethernet/atheros/Kconfig
9 +++ b/drivers/net/ethernet/atheros/Kconfig
10 @@ -5,7 +5,7 @@
11 config NET_VENDOR_ATHEROS
12 bool "Atheros devices"
13 default y
14 - depends on PCI
15 + depends on (PCI || ATHEROS_AR231X)
16 ---help---
17 If you have a network (Ethernet) card belonging to this class, say Y
18 and read the Ethernet-HOWTO, available from
19 @@ -85,4 +85,10 @@ config ALX
20 To compile this driver as a module, choose M here. The module
21 will be called alx.
22
23 +config NET_AR231X
24 + tristate "Atheros AR231X built-in Ethernet support"
25 + depends on ATHEROS_AR231X
26 + help
27 + Support for the AR231x/531x ethernet controller
28 +
29 endif # NET_VENDOR_ATHEROS
30 --- /dev/null
31 +++ b/drivers/net/ethernet/atheros/ar231x/Makefile
32 @@ -0,0 +1 @@
33 +obj-$(CONFIG_NET_AR231X) += ar231x.o
34 --- /dev/null
35 +++ b/drivers/net/ethernet/atheros/ar231x/ar231x.c
36 @@ -0,0 +1,1249 @@
37 +/*
38 + * ar231x.c: Linux driver for the Atheros AR231x Ethernet device.
39 + *
40 + * Copyright (C) 2004 by Sameer Dekate <sdekate@arubanetworks.com>
41 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
42 + * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
43 + *
44 + * Thanks to Atheros for providing hardware and documentation
45 + * enabling me to write this driver.
46 + *
47 + * This program is free software; you can redistribute it and/or modify
48 + * it under the terms of the GNU General Public License as published by
49 + * the Free Software Foundation; either version 2 of the License, or
50 + * (at your option) any later version.
51 + *
52 + * Additional credits:
53 + * This code is taken from John Taylor's Sibyte driver and then
54 + * modified for the AR2313.
55 + */
56 +
57 +#include <linux/module.h>
58 +#include <linux/version.h>
59 +#include <linux/types.h>
60 +#include <linux/errno.h>
61 +#include <linux/ioport.h>
62 +#include <linux/pci.h>
63 +#include <linux/netdevice.h>
64 +#include <linux/etherdevice.h>
65 +#include <linux/interrupt.h>
66 +#include <linux/hardirq.h>
67 +#include <linux/skbuff.h>
68 +#include <linux/init.h>
69 +#include <linux/delay.h>
70 +#include <linux/mm.h>
71 +#include <linux/highmem.h>
72 +#include <linux/sockios.h>
73 +#include <linux/pkt_sched.h>
74 +#include <linux/mii.h>
75 +#include <linux/phy.h>
76 +#include <linux/ethtool.h>
77 +#include <linux/ctype.h>
78 +#include <linux/platform_device.h>
79 +#include <linux/io.h>
80 +#include <linux/uaccess.h>
81 +
82 +#include <net/sock.h>
83 +#include <net/ip.h>
84 +
85 +#define AR2313_MTU 1692
86 +#define AR2313_PRIOS 1
87 +#define AR2313_QUEUES (2*AR2313_PRIOS)
88 +#define AR2313_DESCR_ENTRIES 64
89 +
90 +
91 +#ifndef min
92 +#define min(a, b) (((a) < (b)) ? (a) : (b))
93 +#endif
94 +
95 +#ifndef SMP_CACHE_BYTES
96 +#define SMP_CACHE_BYTES L1_CACHE_BYTES
97 +#endif
98 +
99 +#define AR2313_MBOX_SET_BIT 0x8
100 +
101 +#include "ar231x.h"
102 +
103 +/**
104 + * New interrupt handler strategy:
105 + *
106 + * An old interrupt handler worked using the traditional method of
107 + * replacing an skbuff with a new one when a packet arrives. However
108 + * the rx rings do not need to contain a static number of buffer
109 + * descriptors, thus it makes sense to move the memory allocation out
110 + * of the main interrupt handler and do it in a bottom half handler
111 + * and only allocate new buffers when the number of buffers in the
112 + * ring is below a certain threshold. In order to avoid starving the
113 + * NIC under heavy load it is however necessary to force allocation
114 + * when hitting a minimum threshold. The strategy for alloction is as
115 + * follows:
116 + *
117 + * RX_LOW_BUF_THRES - allocate buffers in the bottom half
118 + * RX_PANIC_LOW_THRES - we are very low on buffers, allocate
119 + * the buffers in the interrupt handler
120 + * RX_RING_THRES - maximum number of buffers in the rx ring
121 + *
122 + * One advantagous side effect of this allocation approach is that the
123 + * entire rx processing can be done without holding any spin lock
124 + * since the rx rings and registers are totally independent of the tx
125 + * ring and its registers. This of course includes the kmalloc's of
126 + * new skb's. Thus start_xmit can run in parallel with rx processing
127 + * and the memory allocation on SMP systems.
128 + *
129 + * Note that running the skb reallocation in a bottom half opens up
130 + * another can of races which needs to be handled properly. In
131 + * particular it can happen that the interrupt handler tries to run
132 + * the reallocation while the bottom half is either running on another
133 + * CPU or was interrupted on the same CPU. To get around this the
134 + * driver uses bitops to prevent the reallocation routines from being
135 + * reentered.
136 + *
137 + * TX handling can also be done without holding any spin lock, wheee
138 + * this is fun! since tx_csm is only written to by the interrupt
139 + * handler.
140 + */
141 +
142 +/**
143 + * Threshold values for RX buffer allocation - the low water marks for
144 + * when to start refilling the rings are set to 75% of the ring
145 + * sizes. It seems to make sense to refill the rings entirely from the
146 + * intrrupt handler once it gets below the panic threshold, that way
147 + * we don't risk that the refilling is moved to another CPU when the
148 + * one running the interrupt handler just got the slab code hot in its
149 + * cache.
150 + */
151 +#define RX_RING_SIZE AR2313_DESCR_ENTRIES
152 +#define RX_PANIC_THRES (RX_RING_SIZE/4)
153 +#define RX_LOW_THRES ((3*RX_RING_SIZE)/4)
154 +#define CRC_LEN 4
155 +#define RX_OFFSET 2
156 +
157 +#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
158 +#define VLAN_HDR 4
159 +#else
160 +#define VLAN_HDR 0
161 +#endif
162 +
163 +#define AR2313_BUFSIZE (AR2313_MTU + VLAN_HDR + ETH_HLEN + CRC_LEN + \
164 + RX_OFFSET)
165 +
166 +#ifdef MODULE
167 +MODULE_LICENSE("GPL");
168 +MODULE_AUTHOR("Sameer Dekate <sdekate@arubanetworks.com>, Imre Kaloz <kaloz@openwrt.org>, Felix Fietkau <nbd@openwrt.org>");
169 +MODULE_DESCRIPTION("AR231x Ethernet driver");
170 +#endif
171 +
172 +#define virt_to_phys(x) ((u32)(x) & 0x1fffffff)
173 +
174 +/* prototypes */
175 +static void ar231x_halt(struct net_device *dev);
176 +static void rx_tasklet_func(unsigned long data);
177 +static void rx_tasklet_cleanup(struct net_device *dev);
178 +static void ar231x_multicast_list(struct net_device *dev);
179 +static void ar231x_tx_timeout(struct net_device *dev);
180 +
181 +static int ar231x_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum);
182 +static int ar231x_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum,
183 + u16 value);
184 +static int ar231x_mdiobus_reset(struct mii_bus *bus);
185 +static int ar231x_mdiobus_probe(struct net_device *dev);
186 +static void ar231x_adjust_link(struct net_device *dev);
187 +
188 +#ifndef ERR
189 +#define ERR(fmt, args...) printk("%s: " fmt, __func__, ##args)
190 +#endif
191 +
192 +#ifdef CONFIG_NET_POLL_CONTROLLER
193 +static void
194 +ar231x_netpoll(struct net_device *dev)
195 +{
196 + unsigned long flags;
197 +
198 + local_irq_save(flags);
199 + ar231x_interrupt(dev->irq, dev);
200 + local_irq_restore(flags);
201 +}
202 +#endif
203 +
204 +static const struct net_device_ops ar231x_ops = {
205 + .ndo_open = ar231x_open,
206 + .ndo_stop = ar231x_close,
207 + .ndo_start_xmit = ar231x_start_xmit,
208 + .ndo_set_rx_mode = ar231x_multicast_list,
209 + .ndo_do_ioctl = ar231x_ioctl,
210 + .ndo_change_mtu = eth_change_mtu,
211 + .ndo_validate_addr = eth_validate_addr,
212 + .ndo_set_mac_address = eth_mac_addr,
213 + .ndo_tx_timeout = ar231x_tx_timeout,
214 +#ifdef CONFIG_NET_POLL_CONTROLLER
215 + .ndo_poll_controller = ar231x_netpoll,
216 +#endif
217 +};
218 +
219 +int ar231x_probe(struct platform_device *pdev)
220 +{
221 + struct net_device *dev;
222 + struct ar231x_private *sp;
223 + struct resource *res;
224 + unsigned long ar_eth_base;
225 + char buf[64];
226 +
227 + dev = alloc_etherdev(sizeof(struct ar231x_private));
228 +
229 + if (dev == NULL) {
230 + printk(KERN_ERR
231 + "ar231x: Unable to allocate net_device structure!\n");
232 + return -ENOMEM;
233 + }
234 +
235 + platform_set_drvdata(pdev, dev);
236 +
237 + sp = netdev_priv(dev);
238 + sp->dev = dev;
239 + sp->cfg = pdev->dev.platform_data;
240 +
241 + sprintf(buf, "eth%d_membase", pdev->id);
242 + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, buf);
243 + if (!res)
244 + return -ENODEV;
245 +
246 + sp->link = 0;
247 + ar_eth_base = res->start;
248 +
249 + sprintf(buf, "eth%d_irq", pdev->id);
250 + dev->irq = platform_get_irq_byname(pdev, buf);
251 +
252 + spin_lock_init(&sp->lock);
253 +
254 + dev->features |= NETIF_F_HIGHDMA;
255 + dev->netdev_ops = &ar231x_ops;
256 +
257 + tasklet_init(&sp->rx_tasklet, rx_tasklet_func, (unsigned long) dev);
258 + tasklet_disable(&sp->rx_tasklet);
259 +
260 + sp->eth_regs = ioremap_nocache(virt_to_phys(ar_eth_base),
261 + sizeof(*sp->eth_regs));
262 + if (!sp->eth_regs) {
263 + printk("Can't remap eth registers\n");
264 + return -ENXIO;
265 + }
266 +
267 + /**
268 + * When there's only one MAC, PHY regs are typically on ENET0,
269 + * even though the MAC might be on ENET1.
270 + * Needto remap PHY regs separately in this case
271 + */
272 + if (virt_to_phys(ar_eth_base) == virt_to_phys(sp->phy_regs))
273 + sp->phy_regs = sp->eth_regs;
274 + else {
275 + sp->phy_regs =
276 + ioremap_nocache(virt_to_phys(sp->cfg->phy_base),
277 + sizeof(*sp->phy_regs));
278 + if (!sp->phy_regs) {
279 + printk("Can't remap phy registers\n");
280 + return -ENXIO;
281 + }
282 + }
283 +
284 + sp->dma_regs =
285 + ioremap_nocache(virt_to_phys(ar_eth_base + 0x1000),
286 + sizeof(*sp->dma_regs));
287 + dev->base_addr = (unsigned int) sp->dma_regs;
288 + if (!sp->dma_regs) {
289 + printk("Can't remap DMA registers\n");
290 + return -ENXIO;
291 + }
292 +
293 + strncpy(sp->name, "Atheros AR231x", sizeof(sp->name) - 1);
294 + sp->name[sizeof(sp->name) - 1] = '\0';
295 + memcpy(dev->dev_addr, sp->cfg->macaddr, 6);
296 +
297 + if (ar231x_init(dev)) {
298 + /* ar231x_init() calls ar231x_init_cleanup() on error */
299 + kfree(dev);
300 + return -ENODEV;
301 + }
302 +
303 + if (register_netdev(dev)) {
304 + printk("%s: register_netdev failed\n", __func__);
305 + return -1;
306 + }
307 +
308 + printk("%s: %s: %pM, irq %d\n", dev->name, sp->name, dev->dev_addr,
309 + dev->irq);
310 +
311 + sp->mii_bus = mdiobus_alloc();
312 + if (sp->mii_bus == NULL)
313 + return -1;
314 +
315 + sp->mii_bus->priv = dev;
316 + sp->mii_bus->read = ar231x_mdiobus_read;
317 + sp->mii_bus->write = ar231x_mdiobus_write;
318 + sp->mii_bus->reset = ar231x_mdiobus_reset;
319 + sp->mii_bus->name = "ar231x_eth_mii";
320 + snprintf(sp->mii_bus->id, MII_BUS_ID_SIZE, "%d", pdev->id);
321 + sp->mii_bus->irq = kmalloc(sizeof(int), GFP_KERNEL);
322 + *sp->mii_bus->irq = PHY_POLL;
323 +
324 + mdiobus_register(sp->mii_bus);
325 +
326 + if (ar231x_mdiobus_probe(dev) != 0) {
327 + printk(KERN_ERR "%s: mdiobus_probe failed\n", dev->name);
328 + rx_tasklet_cleanup(dev);
329 + ar231x_init_cleanup(dev);
330 + unregister_netdev(dev);
331 + kfree(dev);
332 + return -ENODEV;
333 + }
334 +
335 + /* start link poll timer */
336 + ar231x_setup_timer(dev);
337 +
338 + return 0;
339 +}
340 +
341 +
342 +static void ar231x_multicast_list(struct net_device *dev)
343 +{
344 + struct ar231x_private *sp = netdev_priv(dev);
345 + unsigned int filter;
346 +
347 + filter = sp->eth_regs->mac_control;
348 +
349 + if (dev->flags & IFF_PROMISC)
350 + filter |= MAC_CONTROL_PR;
351 + else
352 + filter &= ~MAC_CONTROL_PR;
353 + if ((dev->flags & IFF_ALLMULTI) || (netdev_mc_count(dev) > 0))
354 + filter |= MAC_CONTROL_PM;
355 + else
356 + filter &= ~MAC_CONTROL_PM;
357 +
358 + sp->eth_regs->mac_control = filter;
359 +}
360 +
361 +static void rx_tasklet_cleanup(struct net_device *dev)
362 +{
363 + struct ar231x_private *sp = netdev_priv(dev);
364 +
365 + /**
366 + * Tasklet may be scheduled. Need to get it removed from the list
367 + * since we're about to free the struct.
368 + */
369 +
370 + sp->unloading = 1;
371 + tasklet_enable(&sp->rx_tasklet);
372 + tasklet_kill(&sp->rx_tasklet);
373 +}
374 +
375 +static int ar231x_remove(struct platform_device *pdev)
376 +{
377 + struct net_device *dev = platform_get_drvdata(pdev);
378 + struct ar231x_private *sp = netdev_priv(dev);
379 + rx_tasklet_cleanup(dev);
380 + ar231x_init_cleanup(dev);
381 + unregister_netdev(dev);
382 + mdiobus_unregister(sp->mii_bus);
383 + mdiobus_free(sp->mii_bus);
384 + kfree(dev);
385 + return 0;
386 +}
387 +
388 +
389 +/**
390 + * Restart the AR2313 ethernet controller.
391 + */
392 +static int ar231x_restart(struct net_device *dev)
393 +{
394 + /* disable interrupts */
395 + disable_irq(dev->irq);
396 +
397 + /* stop mac */
398 + ar231x_halt(dev);
399 +
400 + /* initialize */
401 + ar231x_init(dev);
402 +
403 + /* enable interrupts */
404 + enable_irq(dev->irq);
405 +
406 + return 0;
407 +}
408 +
409 +static struct platform_driver ar231x_driver = {
410 + .driver.name = "ar231x-eth",
411 + .probe = ar231x_probe,
412 + .remove = ar231x_remove,
413 +};
414 +
415 +module_platform_driver(ar231x_driver);
416 +
417 +static void ar231x_free_descriptors(struct net_device *dev)
418 +{
419 + struct ar231x_private *sp = netdev_priv(dev);
420 + if (sp->rx_ring != NULL) {
421 + kfree((void *)KSEG0ADDR(sp->rx_ring));
422 + sp->rx_ring = NULL;
423 + sp->tx_ring = NULL;
424 + }
425 +}
426 +
427 +
428 +static int ar231x_allocate_descriptors(struct net_device *dev)
429 +{
430 + struct ar231x_private *sp = netdev_priv(dev);
431 + int size;
432 + int j;
433 + ar231x_descr_t *space;
434 +
435 + if (sp->rx_ring != NULL) {
436 + printk("%s: already done.\n", __func__);
437 + return 0;
438 + }
439 +
440 + size = sizeof(ar231x_descr_t) * (AR2313_DESCR_ENTRIES * AR2313_QUEUES);
441 + space = kmalloc(size, GFP_KERNEL);
442 + if (space == NULL)
443 + return 1;
444 +
445 + /* invalidate caches */
446 + dma_cache_inv((unsigned int) space, size);
447 +
448 + /* now convert pointer to KSEG1 */
449 + space = (ar231x_descr_t *)KSEG1ADDR(space);
450 +
451 + memset((void *)space, 0, size);
452 +
453 + sp->rx_ring = space;
454 + space += AR2313_DESCR_ENTRIES;
455 +
456 + sp->tx_ring = space;
457 + space += AR2313_DESCR_ENTRIES;
458 +
459 + /* Initialize the transmit Descriptors */
460 + for (j = 0; j < AR2313_DESCR_ENTRIES; j++) {
461 + ar231x_descr_t *td = &sp->tx_ring[j];
462 + td->status = 0;
463 + td->devcs = DMA_TX1_CHAINED;
464 + td->addr = 0;
465 + td->descr = virt_to_phys(&sp->tx_ring[DSC_NEXT(j)]);
466 + }
467 +
468 + return 0;
469 +}
470 +
471 +
472 +/**
473 + * Generic cleanup handling data allocated during init. Used when the
474 + * module is unloaded or if an error occurs during initialization
475 + */
476 +static void ar231x_init_cleanup(struct net_device *dev)
477 +{
478 + struct ar231x_private *sp = netdev_priv(dev);
479 + struct sk_buff *skb;
480 + int j;
481 +
482 + ar231x_free_descriptors(dev);
483 +
484 + if (sp->eth_regs)
485 + iounmap((void *)sp->eth_regs);
486 + if (sp->dma_regs)
487 + iounmap((void *)sp->dma_regs);
488 +
489 + if (sp->rx_skb) {
490 + for (j = 0; j < AR2313_DESCR_ENTRIES; j++) {
491 + skb = sp->rx_skb[j];
492 + if (skb) {
493 + sp->rx_skb[j] = NULL;
494 + dev_kfree_skb(skb);
495 + }
496 + }
497 + kfree(sp->rx_skb);
498 + sp->rx_skb = NULL;
499 + }
500 +
501 + if (sp->tx_skb) {
502 + for (j = 0; j < AR2313_DESCR_ENTRIES; j++) {
503 + skb = sp->tx_skb[j];
504 + if (skb) {
505 + sp->tx_skb[j] = NULL;
506 + dev_kfree_skb(skb);
507 + }
508 + }
509 + kfree(sp->tx_skb);
510 + sp->tx_skb = NULL;
511 + }
512 +}
513 +
514 +static int ar231x_setup_timer(struct net_device *dev)
515 +{
516 + struct ar231x_private *sp = netdev_priv(dev);
517 +
518 + init_timer(&sp->link_timer);
519 +
520 + sp->link_timer.function = ar231x_link_timer_fn;
521 + sp->link_timer.data = (int) dev;
522 + sp->link_timer.expires = jiffies + HZ;
523 +
524 + add_timer(&sp->link_timer);
525 + return 0;
526 +}
527 +
528 +static void ar231x_link_timer_fn(unsigned long data)
529 +{
530 + struct net_device *dev = (struct net_device *)data;
531 + struct ar231x_private *sp = netdev_priv(dev);
532 +
533 + /**
534 + * See if the link status changed.
535 + * This was needed to make sure we set the PHY to the
536 + * autonegotiated value of half or full duplex.
537 + */
538 + ar231x_check_link(dev);
539 +
540 + /**
541 + * Loop faster when we don't have link.
542 + * This was needed to speed up the AP bootstrap time.
543 + */
544 + if (sp->link == 0)
545 + mod_timer(&sp->link_timer, jiffies + HZ / 2);
546 + else
547 + mod_timer(&sp->link_timer, jiffies + LINK_TIMER);
548 +}
549 +
550 +static void ar231x_check_link(struct net_device *dev)
551 +{
552 + struct ar231x_private *sp = netdev_priv(dev);
553 + u16 phy_data;
554 +
555 + phy_data = ar231x_mdiobus_read(sp->mii_bus, sp->phy, MII_BMSR);
556 + if (sp->phy_data != phy_data) {
557 + if (phy_data & BMSR_LSTATUS) {
558 + /**
559 + * Link is present, ready link partner ability to
560 + * deterine duplexity.
561 + */
562 + int duplex = 0;
563 + u16 reg;
564 +
565 + sp->link = 1;
566 + reg = ar231x_mdiobus_read(sp->mii_bus, sp->phy,
567 + MII_BMCR);
568 + if (reg & BMCR_ANENABLE) {
569 + /* auto neg enabled */
570 + reg = ar231x_mdiobus_read(sp->mii_bus, sp->phy,
571 + MII_LPA);
572 + duplex = reg & (LPA_100FULL | LPA_10FULL) ?
573 + 1 : 0;
574 + } else {
575 + /* no auto neg, just read duplex config */
576 + duplex = (reg & BMCR_FULLDPLX) ? 1 : 0;
577 + }
578 +
579 + printk(KERN_INFO "%s: Configuring MAC for %s duplex\n",
580 + dev->name, (duplex) ? "full" : "half");
581 +
582 + if (duplex) {
583 + /* full duplex */
584 + sp->eth_regs->mac_control =
585 + (sp->eth_regs->mac_control |
586 + MAC_CONTROL_F) & ~MAC_CONTROL_DRO;
587 + } else {
588 + /* half duplex */
589 + sp->eth_regs->mac_control =
590 + (sp->eth_regs->mac_control |
591 + MAC_CONTROL_DRO) & ~MAC_CONTROL_F;
592 + }
593 + } else {
594 + /* no link */
595 + sp->link = 0;
596 + }
597 + sp->phy_data = phy_data;
598 + }
599 +}
600 +
601 +static int ar231x_reset_reg(struct net_device *dev)
602 +{
603 + struct ar231x_private *sp = netdev_priv(dev);
604 + unsigned int ethsal, ethsah;
605 + unsigned int flags;
606 +
607 + sp->cfg->reset_set(sp->cfg->reset_mac);
608 + mdelay(10);
609 + sp->cfg->reset_clear(sp->cfg->reset_mac);
610 + mdelay(10);
611 + sp->cfg->reset_set(sp->cfg->reset_phy);
612 + mdelay(10);
613 + sp->cfg->reset_clear(sp->cfg->reset_phy);
614 + mdelay(10);
615 +
616 + sp->dma_regs->bus_mode = (DMA_BUS_MODE_SWR);
617 + mdelay(10);
618 + sp->dma_regs->bus_mode =
619 + ((32 << DMA_BUS_MODE_PBL_SHIFT) | DMA_BUS_MODE_BLE);
620 +
621 + /* enable interrupts */
622 + sp->dma_regs->intr_ena = DMA_STATUS_AIS | DMA_STATUS_NIS |
623 + DMA_STATUS_RI | DMA_STATUS_TI |
624 + DMA_STATUS_FBE;
625 + sp->dma_regs->xmt_base = virt_to_phys(sp->tx_ring);
626 + sp->dma_regs->rcv_base = virt_to_phys(sp->rx_ring);
627 + sp->dma_regs->control =
628 + (DMA_CONTROL_SR | DMA_CONTROL_ST | DMA_CONTROL_SF);
629 +
630 + sp->eth_regs->flow_control = (FLOW_CONTROL_FCE);
631 + sp->eth_regs->vlan_tag = (0x8100);
632 +
633 + /* Enable Ethernet Interface */
634 + flags = (MAC_CONTROL_TE | /* transmit enable */
635 + MAC_CONTROL_PM | /* pass mcast */
636 + MAC_CONTROL_F | /* full duplex */
637 + MAC_CONTROL_HBD); /* heart beat disabled */
638 +
639 + if (dev->flags & IFF_PROMISC) { /* set promiscuous mode */
640 + flags |= MAC_CONTROL_PR;
641 + }
642 + sp->eth_regs->mac_control = flags;
643 +
644 + /* Set all Ethernet station address registers to their initial values */
645 + ethsah = (((u_int) (dev->dev_addr[5]) << 8) & (u_int) 0x0000FF00) |
646 + (((u_int) (dev->dev_addr[4]) << 0) & (u_int) 0x000000FF);
647 +
648 + ethsal = (((u_int) (dev->dev_addr[3]) << 24) & (u_int) 0xFF000000) |
649 + (((u_int) (dev->dev_addr[2]) << 16) & (u_int) 0x00FF0000) |
650 + (((u_int) (dev->dev_addr[1]) << 8) & (u_int) 0x0000FF00) |
651 + (((u_int) (dev->dev_addr[0]) << 0) & (u_int) 0x000000FF);
652 +
653 + sp->eth_regs->mac_addr[0] = ethsah;
654 + sp->eth_regs->mac_addr[1] = ethsal;
655 +
656 + mdelay(10);
657 +
658 + return 0;
659 +}
660 +
661 +
662 +static int ar231x_init(struct net_device *dev)
663 +{
664 + struct ar231x_private *sp = netdev_priv(dev);
665 + int ecode = 0;
666 +
667 + /* Allocate descriptors */
668 + if (ar231x_allocate_descriptors(dev)) {
669 + printk("%s: %s: ar231x_allocate_descriptors failed\n",
670 + dev->name, __func__);
671 + ecode = -EAGAIN;
672 + goto init_error;
673 + }
674 +
675 + /* Get the memory for the skb rings */
676 + if (sp->rx_skb == NULL) {
677 + sp->rx_skb =
678 + kmalloc(sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES,
679 + GFP_KERNEL);
680 + if (!(sp->rx_skb)) {
681 + printk("%s: %s: rx_skb kmalloc failed\n",
682 + dev->name, __func__);
683 + ecode = -EAGAIN;
684 + goto init_error;
685 + }
686 + }
687 + memset(sp->rx_skb, 0, sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES);
688 +
689 + if (sp->tx_skb == NULL) {
690 + sp->tx_skb =
691 + kmalloc(sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES,
692 + GFP_KERNEL);
693 + if (!(sp->tx_skb)) {
694 + printk("%s: %s: tx_skb kmalloc failed\n",
695 + dev->name, __func__);
696 + ecode = -EAGAIN;
697 + goto init_error;
698 + }
699 + }
700 + memset(sp->tx_skb, 0, sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES);
701 +
702 + /**
703 + * Set tx_csm before we start receiving interrupts, otherwise
704 + * the interrupt handler might think it is supposed to process
705 + * tx ints before we are up and running, which may cause a null
706 + * pointer access in the int handler.
707 + */
708 + sp->rx_skbprd = 0;
709 + sp->cur_rx = 0;
710 + sp->tx_prd = 0;
711 + sp->tx_csm = 0;
712 +
713 + /* Zero the stats before starting the interface */
714 + memset(&dev->stats, 0, sizeof(dev->stats));
715 +
716 + /**
717 + * We load the ring here as there seem to be no way to tell the
718 + * firmware to wipe the ring without re-initializing it.
719 + */
720 + ar231x_load_rx_ring(dev, RX_RING_SIZE);
721 +
722 + /* Init hardware */
723 + ar231x_reset_reg(dev);
724 +
725 + /* Get the IRQ */
726 + ecode =
727 + request_irq(dev->irq, &ar231x_interrupt,
728 + IRQF_DISABLED,
729 + dev->name, dev);
730 + if (ecode) {
731 + printk(KERN_WARNING "%s: %s: Requested IRQ %d is busy\n",
732 + dev->name, __func__, dev->irq);
733 + goto init_error;
734 + }
735 +
736 +
737 + tasklet_enable(&sp->rx_tasklet);
738 +
739 + return 0;
740 +
741 +init_error:
742 + ar231x_init_cleanup(dev);
743 + return ecode;
744 +}
745 +
746 +/**
747 + * Load the rx ring.
748 + *
749 + * Loading rings is safe without holding the spin lock since this is
750 + * done only before the device is enabled, thus no interrupts are
751 + * generated and by the interrupt handler/tasklet handler.
752 + */
753 +static void ar231x_load_rx_ring(struct net_device *dev, int nr_bufs)
754 +{
755 + struct ar231x_private *sp = netdev_priv(dev);
756 + short i, idx;
757 +
758 + idx = sp->rx_skbprd;
759 +
760 + for (i = 0; i < nr_bufs; i++) {
761 + struct sk_buff *skb;
762 + ar231x_descr_t *rd;
763 +
764 + if (sp->rx_skb[idx])
765 + break;
766 +
767 + skb = netdev_alloc_skb_ip_align(dev, AR2313_BUFSIZE);
768 + if (!skb) {
769 + printk("\n\n\n\n %s: No memory in system\n\n\n\n",
770 + __func__);
771 + break;
772 + }
773 +
774 + /* Make sure IP header starts on a fresh cache line */
775 + skb->dev = dev;
776 + sp->rx_skb[idx] = skb;
777 +
778 + rd = (ar231x_descr_t *)&sp->rx_ring[idx];
779 +
780 + /* initialize dma descriptor */
781 + rd->devcs = ((AR2313_BUFSIZE << DMA_RX1_BSIZE_SHIFT) |
782 + DMA_RX1_CHAINED);
783 + rd->addr = virt_to_phys(skb->data);
784 + rd->descr = virt_to_phys(&sp->rx_ring[DSC_NEXT(idx)]);
785 + rd->status = DMA_RX_OWN;
786 +
787 + idx = DSC_NEXT(idx);
788 + }
789 +
790 + if (i)
791 + sp->rx_skbprd = idx;
792 +
793 + return;
794 +}
795 +
796 +#define AR2313_MAX_PKTS_PER_CALL 64
797 +
798 +static int ar231x_rx_int(struct net_device *dev)
799 +{
800 + struct ar231x_private *sp = netdev_priv(dev);
801 + struct sk_buff *skb, *skb_new;
802 + ar231x_descr_t *rxdesc;
803 + unsigned int status;
804 + u32 idx;
805 + int pkts = 0;
806 + int rval;
807 +
808 + idx = sp->cur_rx;
809 +
810 + /* process at most the entire ring and then wait for another int */
811 + while (1) {
812 + rxdesc = &sp->rx_ring[idx];
813 + status = rxdesc->status;
814 +
815 + if (status & DMA_RX_OWN) {
816 + /* SiByte owns descriptor or descr not yet filled in */
817 + rval = 0;
818 + break;
819 + }
820 +
821 + if (++pkts > AR2313_MAX_PKTS_PER_CALL) {
822 + rval = 1;
823 + break;
824 + }
825 +
826 + if ((status & DMA_RX_ERROR) && !(status & DMA_RX_LONG)) {
827 + dev->stats.rx_errors++;
828 + dev->stats.rx_dropped++;
829 +
830 + /* add statistics counters */
831 + if (status & DMA_RX_ERR_CRC)
832 + dev->stats.rx_crc_errors++;
833 + if (status & DMA_RX_ERR_COL)
834 + dev->stats.rx_over_errors++;
835 + if (status & DMA_RX_ERR_LENGTH)
836 + dev->stats.rx_length_errors++;
837 + if (status & DMA_RX_ERR_RUNT)
838 + dev->stats.rx_over_errors++;
839 + if (status & DMA_RX_ERR_DESC)
840 + dev->stats.rx_over_errors++;
841 +
842 + } else {
843 + /* alloc new buffer. */
844 + skb_new = netdev_alloc_skb_ip_align(dev,
845 + AR2313_BUFSIZE);
846 + if (skb_new != NULL) {
847 + skb = sp->rx_skb[idx];
848 + /* set skb */
849 + skb_put(skb, ((status >> DMA_RX_LEN_SHIFT) &
850 + 0x3fff) - CRC_LEN);
851 +
852 + dev->stats.rx_bytes += skb->len;
853 + skb->protocol = eth_type_trans(skb, dev);
854 + /* pass the packet to upper layers */
855 + netif_rx(skb);
856 +
857 + skb_new->dev = dev;
858 + /* reset descriptor's curr_addr */
859 + rxdesc->addr = virt_to_phys(skb_new->data);
860 +
861 + dev->stats.rx_packets++;
862 + sp->rx_skb[idx] = skb_new;
863 + } else {
864 + dev->stats.rx_dropped++;
865 + }
866 + }
867 +
868 + rxdesc->devcs = ((AR2313_BUFSIZE << DMA_RX1_BSIZE_SHIFT) |
869 + DMA_RX1_CHAINED);
870 + rxdesc->status = DMA_RX_OWN;
871 +
872 + idx = DSC_NEXT(idx);
873 + }
874 +
875 + sp->cur_rx = idx;
876 +
877 + return rval;
878 +}
879 +
880 +
881 +static void ar231x_tx_int(struct net_device *dev)
882 +{
883 + struct ar231x_private *sp = netdev_priv(dev);
884 + u32 idx;
885 + struct sk_buff *skb;
886 + ar231x_descr_t *txdesc;
887 + unsigned int status = 0;
888 +
889 + idx = sp->tx_csm;
890 +
891 + while (idx != sp->tx_prd) {
892 + txdesc = &sp->tx_ring[idx];
893 + status = txdesc->status;
894 +
895 + if (status & DMA_TX_OWN) {
896 + /* ar231x dma still owns descr */
897 + break;
898 + }
899 + /* done with this descriptor */
900 + dma_unmap_single(NULL, txdesc->addr,
901 + txdesc->devcs & DMA_TX1_BSIZE_MASK,
902 + DMA_TO_DEVICE);
903 + txdesc->status = 0;
904 +
905 + if (status & DMA_TX_ERROR) {
906 + dev->stats.tx_errors++;
907 + dev->stats.tx_dropped++;
908 + if (status & DMA_TX_ERR_UNDER)
909 + dev->stats.tx_fifo_errors++;
910 + if (status & DMA_TX_ERR_HB)
911 + dev->stats.tx_heartbeat_errors++;
912 + if (status & (DMA_TX_ERR_LOSS | DMA_TX_ERR_LINK))
913 + dev->stats.tx_carrier_errors++;
914 + if (status & (DMA_TX_ERR_LATE | DMA_TX_ERR_COL |
915 + DMA_TX_ERR_JABBER | DMA_TX_ERR_DEFER))
916 + dev->stats.tx_aborted_errors++;
917 + } else {
918 + /* transmit OK */
919 + dev->stats.tx_packets++;
920 + }
921 +
922 + skb = sp->tx_skb[idx];
923 + sp->tx_skb[idx] = NULL;
924 + idx = DSC_NEXT(idx);
925 + dev->stats.tx_bytes += skb->len;
926 + dev_kfree_skb_irq(skb);
927 + }
928 +
929 + sp->tx_csm = idx;
930 +
931 + return;
932 +}
933 +
934 +
935 +static void rx_tasklet_func(unsigned long data)
936 +{
937 + struct net_device *dev = (struct net_device *)data;
938 + struct ar231x_private *sp = netdev_priv(dev);
939 +
940 + if (sp->unloading)
941 + return;
942 +
943 + if (ar231x_rx_int(dev)) {
944 + tasklet_hi_schedule(&sp->rx_tasklet);
945 + } else {
946 + unsigned long flags;
947 + spin_lock_irqsave(&sp->lock, flags);
948 + sp->dma_regs->intr_ena |= DMA_STATUS_RI;
949 + spin_unlock_irqrestore(&sp->lock, flags);
950 + }
951 +}
952 +
953 +static void rx_schedule(struct net_device *dev)
954 +{
955 + struct ar231x_private *sp = netdev_priv(dev);
956 +
957 + sp->dma_regs->intr_ena &= ~DMA_STATUS_RI;
958 +
959 + tasklet_hi_schedule(&sp->rx_tasklet);
960 +}
961 +
962 +static irqreturn_t ar231x_interrupt(int irq, void *dev_id)
963 +{
964 + struct net_device *dev = (struct net_device *)dev_id;
965 + struct ar231x_private *sp = netdev_priv(dev);
966 + unsigned int status, enabled;
967 +
968 + /* clear interrupt */
969 + /* Don't clear RI bit if currently disabled */
970 + status = sp->dma_regs->status;
971 + enabled = sp->dma_regs->intr_ena;
972 + sp->dma_regs->status = status & enabled;
973 +
974 + if (status & DMA_STATUS_NIS) {
975 + /* normal status */
976 + /**
977 + * Don't schedule rx processing if interrupt
978 + * is already disabled.
979 + */
980 + if (status & enabled & DMA_STATUS_RI) {
981 + /* receive interrupt */
982 + rx_schedule(dev);
983 + }
984 + if (status & DMA_STATUS_TI) {
985 + /* transmit interrupt */
986 + ar231x_tx_int(dev);
987 + }
988 + }
989 +
990 + /* abnormal status */
991 + if (status & (DMA_STATUS_FBE | DMA_STATUS_TPS))
992 + ar231x_restart(dev);
993 +
994 + return IRQ_HANDLED;
995 +}
996 +
997 +
998 +static int ar231x_open(struct net_device *dev)
999 +{
1000 + struct ar231x_private *sp = netdev_priv(dev);
1001 + unsigned int ethsal, ethsah;
1002 +
1003 + /* reset the hardware, in case the MAC address changed */
1004 + ethsah = (((u_int) (dev->dev_addr[5]) << 8) & (u_int) 0x0000FF00) |
1005 + (((u_int) (dev->dev_addr[4]) << 0) & (u_int) 0x000000FF);
1006 +
1007 + ethsal = (((u_int) (dev->dev_addr[3]) << 24) & (u_int) 0xFF000000) |
1008 + (((u_int) (dev->dev_addr[2]) << 16) & (u_int) 0x00FF0000) |
1009 + (((u_int) (dev->dev_addr[1]) << 8) & (u_int) 0x0000FF00) |
1010 + (((u_int) (dev->dev_addr[0]) << 0) & (u_int) 0x000000FF);
1011 +
1012 + sp->eth_regs->mac_addr[0] = ethsah;
1013 + sp->eth_regs->mac_addr[1] = ethsal;
1014 +
1015 + mdelay(10);
1016 +
1017 + dev->mtu = 1500;
1018 + netif_start_queue(dev);
1019 +
1020 + sp->eth_regs->mac_control |= MAC_CONTROL_RE;
1021 +
1022 + return 0;
1023 +}
1024 +
1025 +static void ar231x_tx_timeout(struct net_device *dev)
1026 +{
1027 + struct ar231x_private *sp = netdev_priv(dev);
1028 + unsigned long flags;
1029 +
1030 + spin_lock_irqsave(&sp->lock, flags);
1031 + ar231x_restart(dev);
1032 + spin_unlock_irqrestore(&sp->lock, flags);
1033 +}
1034 +
1035 +static void ar231x_halt(struct net_device *dev)
1036 +{
1037 + struct ar231x_private *sp = netdev_priv(dev);
1038 + int j;
1039 +
1040 + tasklet_disable(&sp->rx_tasklet);
1041 +
1042 + /* kill the MAC */
1043 + sp->eth_regs->mac_control &= ~(MAC_CONTROL_RE | /* disable Receives */
1044 + MAC_CONTROL_TE); /* disable Transmits */
1045 + /* stop dma */
1046 + sp->dma_regs->control = 0;
1047 + sp->dma_regs->bus_mode = DMA_BUS_MODE_SWR;
1048 +
1049 + /* place phy and MAC in reset */
1050 + sp->cfg->reset_set(sp->cfg->reset_mac);
1051 + sp->cfg->reset_set(sp->cfg->reset_phy);
1052 +
1053 + /* free buffers on tx ring */
1054 + for (j = 0; j < AR2313_DESCR_ENTRIES; j++) {
1055 + struct sk_buff *skb;
1056 + ar231x_descr_t *txdesc;
1057 +
1058 + txdesc = &sp->tx_ring[j];
1059 + txdesc->descr = 0;
1060 +
1061 + skb = sp->tx_skb[j];
1062 + if (skb) {
1063 + dev_kfree_skb(skb);
1064 + sp->tx_skb[j] = NULL;
1065 + }
1066 + }
1067 +}
1068 +
1069 +/**
1070 + * close should do nothing. Here's why. It's called when
1071 + * 'ifconfig bond0 down' is run. If it calls free_irq then
1072 + * the irq is gone forever ! When bond0 is made 'up' again,
1073 + * the ar231x_open () does not call request_irq (). Worse,
1074 + * the call to ar231x_halt() generates a WDOG reset due to
1075 + * the write to reset register and the box reboots.
1076 + * Commenting this out is good since it allows the
1077 + * system to resume when bond0 is made up again.
1078 + */
1079 +static int ar231x_close(struct net_device *dev)
1080 +{
1081 +#if 0
1082 + /* Disable interrupts */
1083 + disable_irq(dev->irq);
1084 +
1085 + /**
1086 + * Without (or before) releasing irq and stopping hardware, this
1087 + * is an absolute non-sense, by the way. It will be reset instantly
1088 + * by the first irq.
1089 + */
1090 + netif_stop_queue(dev);
1091 +
1092 + /* stop the MAC and DMA engines */
1093 + ar231x_halt(dev);
1094 +
1095 + /* release the interrupt */
1096 + free_irq(dev->irq, dev);
1097 +
1098 +#endif
1099 + return 0;
1100 +}
1101 +
1102 +static int ar231x_start_xmit(struct sk_buff *skb, struct net_device *dev)
1103 +{
1104 + struct ar231x_private *sp = netdev_priv(dev);
1105 + ar231x_descr_t *td;
1106 + u32 idx;
1107 +
1108 + idx = sp->tx_prd;
1109 + td = &sp->tx_ring[idx];
1110 +
1111 + if (td->status & DMA_TX_OWN) {
1112 + /* free skbuf and lie to the caller that we sent it out */
1113 + dev->stats.tx_dropped++;
1114 + dev_kfree_skb(skb);
1115 +
1116 + /* restart transmitter in case locked */
1117 + sp->dma_regs->xmt_poll = 0;
1118 + return 0;
1119 + }
1120 +
1121 + /* Setup the transmit descriptor. */
1122 + td->devcs = ((skb->len << DMA_TX1_BSIZE_SHIFT) |
1123 + (DMA_TX1_LS | DMA_TX1_IC | DMA_TX1_CHAINED));
1124 + td->addr = dma_map_single(NULL, skb->data, skb->len, DMA_TO_DEVICE);
1125 + td->status = DMA_TX_OWN;
1126 +
1127 + /* kick transmitter last */
1128 + sp->dma_regs->xmt_poll = 0;
1129 +
1130 + sp->tx_skb[idx] = skb;
1131 + idx = DSC_NEXT(idx);
1132 + sp->tx_prd = idx;
1133 +
1134 + return 0;
1135 +}
1136 +
1137 +static int ar231x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1138 +{
1139 + struct ar231x_private *sp = netdev_priv(dev);
1140 + int ret;
1141 +
1142 + switch (cmd) {
1143 + case SIOCETHTOOL:
1144 + spin_lock_irq(&sp->lock);
1145 + ret = phy_ethtool_ioctl(sp->phy_dev, (void *)ifr->ifr_data);
1146 + spin_unlock_irq(&sp->lock);
1147 + return ret;
1148 +
1149 + case SIOCSIFHWADDR:
1150 + if (copy_from_user
1151 + (dev->dev_addr, ifr->ifr_data, sizeof(dev->dev_addr)))
1152 + return -EFAULT;
1153 + return 0;
1154 +
1155 + case SIOCGIFHWADDR:
1156 + if (copy_to_user
1157 + (ifr->ifr_data, dev->dev_addr, sizeof(dev->dev_addr)))
1158 + return -EFAULT;
1159 + return 0;
1160 +
1161 + case SIOCGMIIPHY:
1162 + case SIOCGMIIREG:
1163 + case SIOCSMIIREG:
1164 + return phy_mii_ioctl(sp->phy_dev, ifr, cmd);
1165 +
1166 + default:
1167 + break;
1168 + }
1169 +
1170 + return -EOPNOTSUPP;
1171 +}
1172 +
1173 +static void ar231x_adjust_link(struct net_device *dev)
1174 +{
1175 + struct ar231x_private *sp = netdev_priv(dev);
1176 + unsigned int mc;
1177 +
1178 + if (!sp->phy_dev->link)
1179 + return;
1180 +
1181 + if (sp->phy_dev->duplex != sp->oldduplex) {
1182 + mc = readl(&sp->eth_regs->mac_control);
1183 + mc &= ~(MAC_CONTROL_F | MAC_CONTROL_DRO);
1184 + if (sp->phy_dev->duplex)
1185 + mc |= MAC_CONTROL_F;
1186 + else
1187 + mc |= MAC_CONTROL_DRO;
1188 + writel(mc, &sp->eth_regs->mac_control);
1189 + sp->oldduplex = sp->phy_dev->duplex;
1190 + }
1191 +}
1192 +
1193 +#define MII_ADDR(phy, reg) \
1194 + ((reg << MII_ADDR_REG_SHIFT) | (phy << MII_ADDR_PHY_SHIFT))
1195 +
1196 +static int
1197 +ar231x_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum)
1198 +{
1199 + struct net_device *const dev = bus->priv;
1200 + struct ar231x_private *sp = netdev_priv(dev);
1201 + volatile ETHERNET_STRUCT *ethernet = sp->phy_regs;
1202 +
1203 + ethernet->mii_addr = MII_ADDR(phy_addr, regnum);
1204 + while (ethernet->mii_addr & MII_ADDR_BUSY)
1205 + ;
1206 + return ethernet->mii_data >> MII_DATA_SHIFT;
1207 +}
1208 +
1209 +static int
1210 +ar231x_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum, u16 value)
1211 +{
1212 + struct net_device *const dev = bus->priv;
1213 + struct ar231x_private *sp = netdev_priv(dev);
1214 + volatile ETHERNET_STRUCT *ethernet = sp->phy_regs;
1215 +
1216 + while (ethernet->mii_addr & MII_ADDR_BUSY)
1217 + ;
1218 + ethernet->mii_data = value << MII_DATA_SHIFT;
1219 + ethernet->mii_addr = MII_ADDR(phy_addr, regnum) | MII_ADDR_WRITE;
1220 +
1221 + return 0;
1222 +}
1223 +
1224 +static int ar231x_mdiobus_reset(struct mii_bus *bus)
1225 +{
1226 + struct net_device *const dev = bus->priv;
1227 +
1228 + ar231x_reset_reg(dev);
1229 +
1230 + return 0;
1231 +}
1232 +
1233 +static int ar231x_mdiobus_probe(struct net_device *dev)
1234 +{
1235 + struct ar231x_private *const sp = netdev_priv(dev);
1236 + struct phy_device *phydev = NULL;
1237 + int phy_addr;
1238 +
1239 + /* find the first (lowest address) PHY on the current MAC's MII bus */
1240 + for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++)
1241 + if (sp->mii_bus->phy_map[phy_addr]) {
1242 + phydev = sp->mii_bus->phy_map[phy_addr];
1243 + sp->phy = phy_addr;
1244 + break; /* break out with first one found */
1245 + }
1246 +
1247 + if (!phydev) {
1248 + printk(KERN_ERR "ar231x: %s: no PHY found\n", dev->name);
1249 + return -1;
1250 + }
1251 +
1252 + /* now we are supposed to have a proper phydev, to attach to... */
1253 + BUG_ON(!phydev);
1254 + BUG_ON(phydev->attached_dev);
1255 +
1256 + phydev = phy_connect(dev, dev_name(&phydev->dev), &ar231x_adjust_link,
1257 + PHY_INTERFACE_MODE_MII);
1258 +
1259 + if (IS_ERR(phydev)) {
1260 + printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
1261 + return PTR_ERR(phydev);
1262 + }
1263 +
1264 + /* mask with MAC supported features */
1265 + phydev->supported &= (SUPPORTED_10baseT_Half
1266 + | SUPPORTED_10baseT_Full
1267 + | SUPPORTED_100baseT_Half
1268 + | SUPPORTED_100baseT_Full
1269 + | SUPPORTED_Autoneg
1270 + /* | SUPPORTED_Pause | SUPPORTED_Asym_Pause */
1271 + | SUPPORTED_MII
1272 + | SUPPORTED_TP);
1273 +
1274 + phydev->advertising = phydev->supported;
1275 +
1276 + sp->oldduplex = -1;
1277 + sp->phy_dev = phydev;
1278 +
1279 + printk(KERN_INFO "%s: attached PHY driver [%s] "
1280 + "(mii_bus:phy_addr=%s)\n",
1281 + dev->name, phydev->drv->name, dev_name(&phydev->dev));
1282 +
1283 + return 0;
1284 +}
1285 +
1286 --- /dev/null
1287 +++ b/drivers/net/ethernet/atheros/ar231x/ar231x.h
1288 @@ -0,0 +1,287 @@
1289 +/*
1290 + * ar231x.h: Linux driver for the Atheros AR231x Ethernet device.
1291 + *
1292 + * Copyright (C) 2004 by Sameer Dekate <sdekate@arubanetworks.com>
1293 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
1294 + * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
1295 + *
1296 + * Thanks to Atheros for providing hardware and documentation
1297 + * enabling me to write this driver.
1298 + *
1299 + * This program is free software; you can redistribute it and/or modify
1300 + * it under the terms of the GNU General Public License as published by
1301 + * the Free Software Foundation; either version 2 of the License, or
1302 + * (at your option) any later version.
1303 + */
1304 +
1305 +#ifndef _AR2313_H_
1306 +#define _AR2313_H_
1307 +
1308 +#include <linux/interrupt.h>
1309 +#include <generated/autoconf.h>
1310 +#include <linux/bitops.h>
1311 +#include <ar231x_platform.h>
1312 +
1313 +/* probe link timer - 5 secs */
1314 +#define LINK_TIMER (5*HZ)
1315 +
1316 +#define IS_DMA_TX_INT(X) (((X) & (DMA_STATUS_TI)) != 0)
1317 +#define IS_DMA_RX_INT(X) (((X) & (DMA_STATUS_RI)) != 0)
1318 +#define IS_DRIVER_OWNED(X) (((X) & (DMA_TX_OWN)) == 0)
1319 +
1320 +#define AR2313_TX_TIMEOUT (HZ/4)
1321 +
1322 +/* Rings */
1323 +#define DSC_RING_ENTRIES_SIZE (AR2313_DESCR_ENTRIES * sizeof(struct desc))
1324 +#define DSC_NEXT(idx) ((idx + 1) & (AR2313_DESCR_ENTRIES - 1))
1325 +
1326 +#define AR2313_MBGET 2
1327 +#define AR2313_MBSET 3
1328 +#define AR2313_PCI_RECONFIG 4
1329 +#define AR2313_PCI_DUMP 5
1330 +#define AR2313_TEST_PANIC 6
1331 +#define AR2313_TEST_NULLPTR 7
1332 +#define AR2313_READ_DATA 8
1333 +#define AR2313_WRITE_DATA 9
1334 +#define AR2313_GET_VERSION 10
1335 +#define AR2313_TEST_HANG 11
1336 +#define AR2313_SYNC 12
1337 +
1338 +#define DMA_RX_ERR_CRC BIT(1)
1339 +#define DMA_RX_ERR_DRIB BIT(2)
1340 +#define DMA_RX_ERR_MII BIT(3)
1341 +#define DMA_RX_EV2 BIT(5)
1342 +#define DMA_RX_ERR_COL BIT(6)
1343 +#define DMA_RX_LONG BIT(7)
1344 +#define DMA_RX_LS BIT(8) /* last descriptor */
1345 +#define DMA_RX_FS BIT(9) /* first descriptor */
1346 +#define DMA_RX_MF BIT(10) /* multicast frame */
1347 +#define DMA_RX_ERR_RUNT BIT(11) /* runt frame */
1348 +#define DMA_RX_ERR_LENGTH BIT(12) /* length error */
1349 +#define DMA_RX_ERR_DESC BIT(14) /* descriptor error */
1350 +#define DMA_RX_ERROR BIT(15) /* error summary */
1351 +#define DMA_RX_LEN_MASK 0x3fff0000
1352 +#define DMA_RX_LEN_SHIFT 16
1353 +#define DMA_RX_FILT BIT(30)
1354 +#define DMA_RX_OWN BIT(31) /* desc owned by DMA controller */
1355 +
1356 +#define DMA_RX1_BSIZE_MASK 0x000007ff
1357 +#define DMA_RX1_BSIZE_SHIFT 0
1358 +#define DMA_RX1_CHAINED BIT(24)
1359 +#define DMA_RX1_RER BIT(25)
1360 +
1361 +#define DMA_TX_ERR_UNDER BIT(1) /* underflow error */
1362 +#define DMA_TX_ERR_DEFER BIT(2) /* excessive deferral */
1363 +#define DMA_TX_COL_MASK 0x78
1364 +#define DMA_TX_COL_SHIFT 3
1365 +#define DMA_TX_ERR_HB BIT(7) /* hearbeat failure */
1366 +#define DMA_TX_ERR_COL BIT(8) /* excessive collisions */
1367 +#define DMA_TX_ERR_LATE BIT(9) /* late collision */
1368 +#define DMA_TX_ERR_LINK BIT(10) /* no carrier */
1369 +#define DMA_TX_ERR_LOSS BIT(11) /* loss of carrier */
1370 +#define DMA_TX_ERR_JABBER BIT(14) /* transmit jabber timeout */
1371 +#define DMA_TX_ERROR BIT(15) /* frame aborted */
1372 +#define DMA_TX_OWN BIT(31) /* descr owned by DMA controller */
1373 +
1374 +#define DMA_TX1_BSIZE_MASK 0x000007ff
1375 +#define DMA_TX1_BSIZE_SHIFT 0
1376 +#define DMA_TX1_CHAINED BIT(24) /* chained descriptors */
1377 +#define DMA_TX1_TER BIT(25) /* transmit end of ring */
1378 +#define DMA_TX1_FS BIT(29) /* first segment */
1379 +#define DMA_TX1_LS BIT(30) /* last segment */
1380 +#define DMA_TX1_IC BIT(31) /* interrupt on completion */
1381 +
1382 +#define RCVPKT_LENGTH(X) (X >> 16) /* Received pkt Length */
1383 +
1384 +#define MAC_CONTROL_RE BIT(2) /* receive enable */
1385 +#define MAC_CONTROL_TE BIT(3) /* transmit enable */
1386 +#define MAC_CONTROL_DC BIT(5) /* Deferral check */
1387 +#define MAC_CONTROL_ASTP BIT(8) /* Auto pad strip */
1388 +#define MAC_CONTROL_DRTY BIT(10) /* Disable retry */
1389 +#define MAC_CONTROL_DBF BIT(11) /* Disable bcast frames */
1390 +#define MAC_CONTROL_LCC BIT(12) /* late collision ctrl */
1391 +#define MAC_CONTROL_HP BIT(13) /* Hash Perfect filtering */
1392 +#define MAC_CONTROL_HASH BIT(14) /* Unicast hash filtering */
1393 +#define MAC_CONTROL_HO BIT(15) /* Hash only filtering */
1394 +#define MAC_CONTROL_PB BIT(16) /* Pass Bad frames */
1395 +#define MAC_CONTROL_IF BIT(17) /* Inverse filtering */
1396 +#define MAC_CONTROL_PR BIT(18) /* promis mode (valid frames only) */
1397 +#define MAC_CONTROL_PM BIT(19) /* pass multicast */
1398 +#define MAC_CONTROL_F BIT(20) /* full-duplex */
1399 +#define MAC_CONTROL_DRO BIT(23) /* Disable Receive Own */
1400 +#define MAC_CONTROL_HBD BIT(28) /* heart-beat disabled (MUST BE SET) */
1401 +#define MAC_CONTROL_BLE BIT(30) /* big endian mode */
1402 +#define MAC_CONTROL_RA BIT(31) /* rcv all (valid and invalid frames) */
1403 +
1404 +#define MII_ADDR_BUSY BIT(0)
1405 +#define MII_ADDR_WRITE BIT(1)
1406 +#define MII_ADDR_REG_SHIFT 6
1407 +#define MII_ADDR_PHY_SHIFT 11
1408 +#define MII_DATA_SHIFT 0
1409 +
1410 +#define FLOW_CONTROL_FCE BIT(1)
1411 +
1412 +#define DMA_BUS_MODE_SWR BIT(0) /* software reset */
1413 +#define DMA_BUS_MODE_BLE BIT(7) /* big endian mode */
1414 +#define DMA_BUS_MODE_PBL_SHIFT 8 /* programmable burst length 32 */
1415 +#define DMA_BUS_MODE_DBO BIT(20) /* big-endian descriptors */
1416 +
1417 +#define DMA_STATUS_TI BIT(0) /* transmit interrupt */
1418 +#define DMA_STATUS_TPS BIT(1) /* transmit process stopped */
1419 +#define DMA_STATUS_TU BIT(2) /* transmit buffer unavailable */
1420 +#define DMA_STATUS_TJT BIT(3) /* transmit buffer timeout */
1421 +#define DMA_STATUS_UNF BIT(5) /* transmit underflow */
1422 +#define DMA_STATUS_RI BIT(6) /* receive interrupt */
1423 +#define DMA_STATUS_RU BIT(7) /* receive buffer unavailable */
1424 +#define DMA_STATUS_RPS BIT(8) /* receive process stopped */
1425 +#define DMA_STATUS_ETI BIT(10) /* early transmit interrupt */
1426 +#define DMA_STATUS_FBE BIT(13) /* fatal bus interrupt */
1427 +#define DMA_STATUS_ERI BIT(14) /* early receive interrupt */
1428 +#define DMA_STATUS_AIS BIT(15) /* abnormal interrupt summary */
1429 +#define DMA_STATUS_NIS BIT(16) /* normal interrupt summary */
1430 +#define DMA_STATUS_RS_SHIFT 17 /* receive process state */
1431 +#define DMA_STATUS_TS_SHIFT 20 /* transmit process state */
1432 +#define DMA_STATUS_EB_SHIFT 23 /* error bits */
1433 +
1434 +#define DMA_CONTROL_SR BIT(1) /* start receive */
1435 +#define DMA_CONTROL_ST BIT(13) /* start transmit */
1436 +#define DMA_CONTROL_SF BIT(21) /* store and forward */
1437 +
1438 +
1439 +typedef struct {
1440 + volatile unsigned int status; /* OWN, Device control and status. */
1441 + volatile unsigned int devcs; /* pkt Control bits + Length */
1442 + volatile unsigned int addr; /* Current Address. */
1443 + volatile unsigned int descr; /* Next descriptor in chain. */
1444 +} ar231x_descr_t;
1445 +
1446 +
1447 +
1448 +/**
1449 + * New Combo structure for Both Eth0 AND eth1
1450 + */
1451 +typedef struct {
1452 + volatile unsigned int mac_control; /* 0x00 */
1453 + volatile unsigned int mac_addr[2]; /* 0x04 - 0x08 */
1454 + volatile unsigned int mcast_table[2]; /* 0x0c - 0x10 */
1455 + volatile unsigned int mii_addr; /* 0x14 */
1456 + volatile unsigned int mii_data; /* 0x18 */
1457 + volatile unsigned int flow_control; /* 0x1c */
1458 + volatile unsigned int vlan_tag; /* 0x20 */
1459 + volatile unsigned int pad[7]; /* 0x24 - 0x3c */
1460 + volatile unsigned int ucast_table[8]; /* 0x40-0x5c */
1461 +
1462 +} ETHERNET_STRUCT;
1463 +
1464 +/********************************************************************
1465 + * Interrupt controller
1466 + ********************************************************************/
1467 +
1468 +typedef struct {
1469 + volatile unsigned int wdog_control; /* 0x08 */
1470 + volatile unsigned int wdog_timer; /* 0x0c */
1471 + volatile unsigned int misc_status; /* 0x10 */
1472 + volatile unsigned int misc_mask; /* 0x14 */
1473 + volatile unsigned int global_status; /* 0x18 */
1474 + volatile unsigned int reserved; /* 0x1c */
1475 + volatile unsigned int reset_control; /* 0x20 */
1476 +} INTERRUPT;
1477 +
1478 +/********************************************************************
1479 + * DMA controller
1480 + ********************************************************************/
1481 +typedef struct {
1482 + volatile unsigned int bus_mode; /* 0x00 (CSR0) */
1483 + volatile unsigned int xmt_poll; /* 0x04 (CSR1) */
1484 + volatile unsigned int rcv_poll; /* 0x08 (CSR2) */
1485 + volatile unsigned int rcv_base; /* 0x0c (CSR3) */
1486 + volatile unsigned int xmt_base; /* 0x10 (CSR4) */
1487 + volatile unsigned int status; /* 0x14 (CSR5) */
1488 + volatile unsigned int control; /* 0x18 (CSR6) */
1489 + volatile unsigned int intr_ena; /* 0x1c (CSR7) */
1490 + volatile unsigned int rcv_missed; /* 0x20 (CSR8) */
1491 + volatile unsigned int reserved[11]; /* 0x24-0x4c (CSR9-19) */
1492 + volatile unsigned int cur_tx_buf_addr; /* 0x50 (CSR20) */
1493 + volatile unsigned int cur_rx_buf_addr; /* 0x50 (CSR21) */
1494 +} DMA;
1495 +
1496 +/**
1497 + * Struct private for the Sibyte.
1498 + *
1499 + * Elements are grouped so variables used by the tx handling goes
1500 + * together, and will go into the same cache lines etc. in order to
1501 + * avoid cache line contention between the rx and tx handling on SMP.
1502 + *
1503 + * Frequently accessed variables are put at the beginning of the
1504 + * struct to help the compiler generate better/shorter code.
1505 + */
1506 +struct ar231x_private {
1507 + struct net_device *dev;
1508 + int version;
1509 + u32 mb[2];
1510 +
1511 + volatile ETHERNET_STRUCT *phy_regs;
1512 + volatile ETHERNET_STRUCT *eth_regs;
1513 + volatile DMA *dma_regs;
1514 + struct ar231x_eth *cfg;
1515 +
1516 + spinlock_t lock; /* Serialise access to device */
1517 +
1518 + /* RX and TX descriptors, must be adjacent */
1519 + ar231x_descr_t *rx_ring;
1520 + ar231x_descr_t *tx_ring;
1521 +
1522 +
1523 + struct sk_buff **rx_skb;
1524 + struct sk_buff **tx_skb;
1525 +
1526 + /* RX elements */
1527 + u32 rx_skbprd;
1528 + u32 cur_rx;
1529 +
1530 + /* TX elements */
1531 + u32 tx_prd;
1532 + u32 tx_csm;
1533 +
1534 + /* Misc elements */
1535 + char name[48];
1536 + struct {
1537 + u32 address;
1538 + u32 length;
1539 + char *mapping;
1540 + } desc;
1541 +
1542 +
1543 + struct timer_list link_timer;
1544 + unsigned short phy; /* merlot phy = 1, samsung phy = 0x1f */
1545 + unsigned short mac;
1546 + unsigned short link; /* 0 - link down, 1 - link up */
1547 + u16 phy_data;
1548 +
1549 + struct tasklet_struct rx_tasklet;
1550 + int unloading;
1551 +
1552 + struct phy_device *phy_dev;
1553 + struct mii_bus *mii_bus;
1554 + int oldduplex;
1555 +};
1556 +
1557 +
1558 +/* Prototypes */
1559 +static int ar231x_init(struct net_device *dev);
1560 +#ifdef TX_TIMEOUT
1561 +static void ar231x_tx_timeout(struct net_device *dev);
1562 +#endif
1563 +static int ar231x_restart(struct net_device *dev);
1564 +static void ar231x_load_rx_ring(struct net_device *dev, int bufs);
1565 +static irqreturn_t ar231x_interrupt(int irq, void *dev_id);
1566 +static int ar231x_open(struct net_device *dev);
1567 +static int ar231x_start_xmit(struct sk_buff *skb, struct net_device *dev);
1568 +static int ar231x_close(struct net_device *dev);
1569 +static int ar231x_ioctl(struct net_device *dev, struct ifreq *ifr,
1570 + int cmd);
1571 +static void ar231x_init_cleanup(struct net_device *dev);
1572 +static int ar231x_setup_timer(struct net_device *dev);
1573 +static void ar231x_link_timer_fn(unsigned long data);
1574 +static void ar231x_check_link(struct net_device *dev);
1575 +#endif /* _AR2313_H_ */
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