atheros: various printk(...) fixes
[openwrt/svn-archive/archive.git] / target / linux / atheros / patches-3.10 / 120-spiflash.patch
1 --- a/drivers/mtd/devices/Kconfig
2 +++ b/drivers/mtd/devices/Kconfig
3 @@ -135,6 +135,10 @@ config MTD_BCM47XXSFLASH
4 registered by bcma as platform devices. This enables driver for
5 serial flash memories (only read-only mode is implemented).
6
7 +config MTD_AR2315
8 + tristate "Atheros AR2315+ SPI Flash support"
9 + depends on ATHEROS_AR2315
10 +
11 config MTD_SLRAM
12 tristate "Uncached system RAM"
13 help
14 --- a/drivers/mtd/devices/Makefile
15 +++ b/drivers/mtd/devices/Makefile
16 @@ -15,6 +15,7 @@ obj-$(CONFIG_MTD_M25P80) += m25p80.o
17 obj-$(CONFIG_MTD_NAND_OMAP_BCH) += elm.o
18 obj-$(CONFIG_MTD_SPEAR_SMI) += spear_smi.o
19 obj-$(CONFIG_MTD_SST25L) += sst25l.o
20 +obj-$(CONFIG_MTD_AR2315) += ar2315.o
21 obj-$(CONFIG_MTD_BCM47XXSFLASH) += bcm47xxsflash.o
22
23
24 --- /dev/null
25 +++ b/drivers/mtd/devices/ar2315.c
26 @@ -0,0 +1,515 @@
27 +
28 +/*
29 + * MTD driver for the SPI Flash Memory support on Atheros AR2315
30 + *
31 + * Copyright (c) 2005-2006 Atheros Communications Inc.
32 + * Copyright (C) 2006-2007 FON Technology, SL.
33 + * Copyright (C) 2006-2007 Imre Kaloz <kaloz@openwrt.org>
34 + * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
35 + * Copyright (C) 2012 Alexandros C. Couloumbis <alex@ozo.com>
36 + *
37 + * This code is free software; you can redistribute it and/or modify
38 + * it under the terms of the GNU General Public License version 2 as
39 + * published by the Free Software Foundation.
40 + *
41 + */
42 +
43 +#include <linux/kernel.h>
44 +#include <linux/module.h>
45 +#include <linux/types.h>
46 +#include <linux/version.h>
47 +#include <linux/errno.h>
48 +#include <linux/slab.h>
49 +#include <linux/mtd/mtd.h>
50 +#include <linux/mtd/partitions.h>
51 +#include <linux/platform_device.h>
52 +#include <linux/sched.h>
53 +#include <linux/root_dev.h>
54 +#include <linux/delay.h>
55 +#include <asm/delay.h>
56 +#include <asm/io.h>
57 +
58 +#include <ar2315_spiflash.h>
59 +#include <ar231x_platform.h>
60 +#include <ar231x.h>
61 +
62 +
63 +#define SPIFLASH "spiflash: "
64 +#define busy_wait(_priv, _condition, _wait) do { \
65 + while (_condition) { \
66 + spin_unlock_bh(&_priv->lock); \
67 + if (_wait > 1) \
68 + msleep(_wait); \
69 + else if ((_wait == 1) && need_resched()) \
70 + schedule(); \
71 + else \
72 + udelay(1); \
73 + spin_lock_bh(&_priv->lock); \
74 + } \
75 +} while (0)
76 +
77 +enum {
78 + FLASH_NONE,
79 + FLASH_1MB,
80 + FLASH_2MB,
81 + FLASH_4MB,
82 + FLASH_8MB,
83 + FLASH_16MB,
84 +};
85 +
86 +/* Flash configuration table */
87 +struct flashconfig {
88 + u32 byte_cnt;
89 + u32 sector_cnt;
90 + u32 sector_size;
91 +};
92 +
93 +const struct flashconfig flashconfig_tbl[] = {
94 + [FLASH_NONE] = { 0, 0, 0},
95 + [FLASH_1MB] = { STM_1MB_BYTE_COUNT, STM_1MB_SECTOR_COUNT, STM_1MB_SECTOR_SIZE},
96 + [FLASH_2MB] = { STM_2MB_BYTE_COUNT, STM_2MB_SECTOR_COUNT, STM_2MB_SECTOR_SIZE},
97 + [FLASH_4MB] = { STM_4MB_BYTE_COUNT, STM_4MB_SECTOR_COUNT, STM_4MB_SECTOR_SIZE},
98 + [FLASH_8MB] = { STM_8MB_BYTE_COUNT, STM_8MB_SECTOR_COUNT, STM_8MB_SECTOR_SIZE},
99 + [FLASH_16MB] = { STM_16MB_BYTE_COUNT, STM_16MB_SECTOR_COUNT, STM_16MB_SECTOR_SIZE}
100 +};
101 +
102 +/* Mapping of generic opcodes to STM serial flash opcodes */
103 +enum {
104 + SPI_WRITE_ENABLE,
105 + SPI_WRITE_DISABLE,
106 + SPI_RD_STATUS,
107 + SPI_WR_STATUS,
108 + SPI_RD_DATA,
109 + SPI_FAST_RD_DATA,
110 + SPI_PAGE_PROGRAM,
111 + SPI_SECTOR_ERASE,
112 + SPI_BULK_ERASE,
113 + SPI_DEEP_PWRDOWN,
114 + SPI_RD_SIG,
115 +};
116 +
117 +struct opcodes {
118 + __u16 code;
119 + __s8 tx_cnt;
120 + __s8 rx_cnt;
121 +};
122 +const struct opcodes stm_opcodes[] = {
123 + [SPI_WRITE_ENABLE] = {STM_OP_WR_ENABLE, 1, 0},
124 + [SPI_WRITE_DISABLE] = {STM_OP_WR_DISABLE, 1, 0},
125 + [SPI_RD_STATUS] = {STM_OP_RD_STATUS, 1, 1},
126 + [SPI_WR_STATUS] = {STM_OP_WR_STATUS, 1, 0},
127 + [SPI_RD_DATA] = {STM_OP_RD_DATA, 4, 4},
128 + [SPI_FAST_RD_DATA] = {STM_OP_FAST_RD_DATA, 5, 0},
129 + [SPI_PAGE_PROGRAM] = {STM_OP_PAGE_PGRM, 8, 0},
130 + [SPI_SECTOR_ERASE] = {STM_OP_SECTOR_ERASE, 4, 0},
131 + [SPI_BULK_ERASE] = {STM_OP_BULK_ERASE, 1, 0},
132 + [SPI_DEEP_PWRDOWN] = {STM_OP_DEEP_PWRDOWN, 1, 0},
133 + [SPI_RD_SIG] = {STM_OP_RD_SIG, 4, 1},
134 +};
135 +
136 +/* Driver private data structure */
137 +struct spiflash_priv {
138 + struct mtd_info mtd;
139 + void *readaddr; /* memory mapped data for read */
140 + void *mmraddr; /* memory mapped register space */
141 + wait_queue_head_t wq;
142 + spinlock_t lock;
143 + int state;
144 +};
145 +
146 +#define to_spiflash(_mtd) container_of(_mtd, struct spiflash_priv, mtd)
147 +
148 +enum {
149 + FL_READY,
150 + FL_READING,
151 + FL_ERASING,
152 + FL_WRITING
153 +};
154 +
155 +/***************************************************************************************************/
156 +
157 +static u32
158 +spiflash_read_reg(struct spiflash_priv *priv, int reg)
159 +{
160 + return ar231x_read_reg((u32) priv->mmraddr + reg);
161 +}
162 +
163 +static void
164 +spiflash_write_reg(struct spiflash_priv *priv, int reg, u32 data)
165 +{
166 + ar231x_write_reg((u32) priv->mmraddr + reg, data);
167 +}
168 +
169 +static u32
170 +spiflash_wait_busy(struct spiflash_priv *priv)
171 +{
172 + u32 reg;
173 +
174 + busy_wait(priv, (reg = spiflash_read_reg(priv, SPI_FLASH_CTL)) &
175 + SPI_CTL_BUSY, 0);
176 + return reg;
177 +}
178 +
179 +static u32
180 +spiflash_sendcmd (struct spiflash_priv *priv, int opcode, u32 addr)
181 +{
182 + const struct opcodes *op;
183 + u32 reg, mask;
184 +
185 + op = &stm_opcodes[opcode];
186 + reg = spiflash_wait_busy(priv);
187 + spiflash_write_reg(priv, SPI_FLASH_OPCODE,
188 + ((u32) op->code) | (addr << 8));
189 +
190 + reg &= ~SPI_CTL_TX_RX_CNT_MASK;
191 + reg |= SPI_CTL_START | op->tx_cnt | (op->rx_cnt << 4);
192 +
193 + spiflash_write_reg(priv, SPI_FLASH_CTL, reg);
194 + spiflash_wait_busy(priv);
195 +
196 + if (!op->rx_cnt)
197 + return 0;
198 +
199 + reg = spiflash_read_reg(priv, SPI_FLASH_DATA);
200 +
201 + switch (op->rx_cnt) {
202 + case 1:
203 + mask = 0x000000ff;
204 + break;
205 + case 2:
206 + mask = 0x0000ffff;
207 + break;
208 + case 3:
209 + mask = 0x00ffffff;
210 + break;
211 + default:
212 + mask = 0xffffffff;
213 + break;
214 + }
215 + reg &= mask;
216 +
217 + return reg;
218 +}
219 +
220 +
221 +/*
222 + * Probe SPI flash device
223 + * Function returns 0 for failure.
224 + * and flashconfig_tbl array index for success.
225 + */
226 +static int
227 +spiflash_probe_chip (struct spiflash_priv *priv)
228 +{
229 + u32 sig;
230 + int flash_size;
231 +
232 + /* Read the signature on the flash device */
233 + spin_lock_bh(&priv->lock);
234 + sig = spiflash_sendcmd(priv, SPI_RD_SIG, 0);
235 + spin_unlock_bh(&priv->lock);
236 +
237 + switch (sig) {
238 + case STM_8MBIT_SIGNATURE:
239 + flash_size = FLASH_1MB;
240 + break;
241 + case STM_16MBIT_SIGNATURE:
242 + flash_size = FLASH_2MB;
243 + break;
244 + case STM_32MBIT_SIGNATURE:
245 + flash_size = FLASH_4MB;
246 + break;
247 + case STM_64MBIT_SIGNATURE:
248 + flash_size = FLASH_8MB;
249 + break;
250 + case STM_128MBIT_SIGNATURE:
251 + flash_size = FLASH_16MB;
252 + break;
253 + default:
254 + pr_warn(SPIFLASH "Read of flash device signature failed!\n");
255 + return 0;
256 + }
257 +
258 + return flash_size;
259 +}
260 +
261 +
262 +/* wait until the flash chip is ready and grab a lock */
263 +static int spiflash_wait_ready(struct spiflash_priv *priv, int state)
264 +{
265 + DECLARE_WAITQUEUE(wait, current);
266 +
267 +retry:
268 + spin_lock_bh(&priv->lock);
269 + if (priv->state != FL_READY) {
270 + set_current_state(TASK_UNINTERRUPTIBLE);
271 + add_wait_queue(&priv->wq, &wait);
272 + spin_unlock_bh(&priv->lock);
273 + schedule();
274 + remove_wait_queue(&priv->wq, &wait);
275 +
276 + if(signal_pending(current))
277 + return 0;
278 +
279 + goto retry;
280 + }
281 + priv->state = state;
282 +
283 + return 1;
284 +}
285 +
286 +static inline void spiflash_done(struct spiflash_priv *priv)
287 +{
288 + priv->state = FL_READY;
289 + spin_unlock_bh(&priv->lock);
290 + wake_up(&priv->wq);
291 +}
292 +
293 +static void
294 +spiflash_wait_complete(struct spiflash_priv *priv, unsigned int timeout)
295 +{
296 + busy_wait(priv, spiflash_sendcmd(priv, SPI_RD_STATUS, 0) &
297 + SPI_STATUS_WIP, timeout);
298 + spiflash_done(priv);
299 +}
300 +
301 +
302 +
303 +static int
304 +spiflash_erase (struct mtd_info *mtd, struct erase_info *instr)
305 +{
306 + struct spiflash_priv *priv = to_spiflash(mtd);
307 + const struct opcodes *op;
308 + u32 temp, reg;
309 +
310 + if (instr->addr + instr->len > mtd->size)
311 + return -EINVAL;
312 +
313 + if (!spiflash_wait_ready(priv, FL_ERASING))
314 + return -EINTR;
315 +
316 + spiflash_sendcmd(priv, SPI_WRITE_ENABLE, 0);
317 + reg = spiflash_wait_busy(priv);
318 +
319 + op = &stm_opcodes[SPI_SECTOR_ERASE];
320 + temp = ((u32)instr->addr << 8) | (u32)(op->code);
321 + spiflash_write_reg(priv, SPI_FLASH_OPCODE, temp);
322 +
323 + reg &= ~SPI_CTL_TX_RX_CNT_MASK;
324 + reg |= op->tx_cnt | SPI_CTL_START;
325 + spiflash_write_reg(priv, SPI_FLASH_CTL, reg);
326 +
327 + spiflash_wait_complete(priv, 20);
328 +
329 + instr->state = MTD_ERASE_DONE;
330 + mtd_erase_callback(instr);
331 +
332 + return 0;
333 +}
334 +
335 +static int
336 +spiflash_read (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf)
337 +{
338 + struct spiflash_priv *priv = to_spiflash(mtd);
339 + u8 *read_addr;
340 +
341 + if (!len)
342 + return 0;
343 +
344 + if (from + len > mtd->size)
345 + return -EINVAL;
346 +
347 + *retlen = len;
348 +
349 + if (!spiflash_wait_ready(priv, FL_READING))
350 + return -EINTR;
351 +
352 + read_addr = (u8 *)(priv->readaddr + from);
353 + memcpy_fromio(buf, read_addr, len);
354 + spiflash_done(priv);
355 +
356 + return 0;
357 +}
358 +
359 +static int
360 +spiflash_write (struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen, const u8 *buf)
361 +{
362 + struct spiflash_priv *priv = to_spiflash(mtd);
363 + u32 opcode, bytes_left;
364 +
365 + *retlen = 0;
366 +
367 + if (!len)
368 + return 0;
369 +
370 + if (to + len > mtd->size)
371 + return -EINVAL;
372 +
373 + bytes_left = len;
374 +
375 + do {
376 + u32 read_len, reg, page_offset, spi_data = 0;
377 +
378 + read_len = min(bytes_left, sizeof(u32));
379 +
380 + /* 32-bit writes cannot span across a page boundary
381 + * (256 bytes). This types of writes require two page
382 + * program operations to handle it correctly. The STM part
383 + * will write the overflow data to the beginning of the
384 + * current page as opposed to the subsequent page.
385 + */
386 + page_offset = (to & (STM_PAGE_SIZE - 1)) + read_len;
387 +
388 + if (page_offset > STM_PAGE_SIZE)
389 + read_len -= (page_offset - STM_PAGE_SIZE);
390 +
391 + if (!spiflash_wait_ready(priv, FL_WRITING))
392 + return -EINTR;
393 +
394 + spiflash_sendcmd(priv, SPI_WRITE_ENABLE, 0);
395 + spi_data = 0;
396 + switch (read_len) {
397 + case 4:
398 + spi_data |= buf[3] << 24;
399 + /* fall through */
400 + case 3:
401 + spi_data |= buf[2] << 16;
402 + /* fall through */
403 + case 2:
404 + spi_data |= buf[1] << 8;
405 + /* fall through */
406 + case 1:
407 + spi_data |= buf[0] & 0xff;
408 + break;
409 + default:
410 + break;
411 + }
412 +
413 + spiflash_write_reg(priv, SPI_FLASH_DATA, spi_data);
414 + opcode = stm_opcodes[SPI_PAGE_PROGRAM].code |
415 + (to & 0x00ffffff) << 8;
416 + spiflash_write_reg(priv, SPI_FLASH_OPCODE, opcode);
417 +
418 + reg = spiflash_read_reg(priv, SPI_FLASH_CTL);
419 + reg &= ~SPI_CTL_TX_RX_CNT_MASK;
420 + reg |= (read_len + 4) | SPI_CTL_START;
421 + spiflash_write_reg(priv, SPI_FLASH_CTL, reg);
422 +
423 + spiflash_wait_complete(priv, 1);
424 +
425 + bytes_left -= read_len;
426 + to += read_len;
427 + buf += read_len;
428 +
429 + *retlen += read_len;
430 + } while (bytes_left != 0);
431 +
432 + return 0;
433 +}
434 +
435 +
436 +#if defined CONFIG_MTD_REDBOOT_PARTS || CONFIG_MTD_MYLOADER_PARTS
437 +static const char *part_probe_types[] = { "cmdlinepart", "RedBoot", "MyLoader", NULL };
438 +#endif
439 +
440 +
441 +static int
442 +spiflash_probe(struct platform_device *pdev)
443 +{
444 + struct spiflash_priv *priv;
445 + struct mtd_info *mtd;
446 + int index;
447 + int result = 0;
448 +
449 + priv = kzalloc(sizeof(struct spiflash_priv), GFP_KERNEL);
450 + spin_lock_init(&priv->lock);
451 + init_waitqueue_head(&priv->wq);
452 + priv->state = FL_READY;
453 + mtd = &priv->mtd;
454 +
455 + priv->mmraddr = ioremap_nocache(SPI_FLASH_MMR, SPI_FLASH_MMR_SIZE);
456 + if (!priv->mmraddr) {
457 + dev_warn(&pdev->dev, SPIFLASH "Failed to map flash device\n");
458 + goto error;
459 + }
460 +
461 + index = spiflash_probe_chip(priv);
462 + if (!index) {
463 + dev_warn(&pdev->dev, SPIFLASH "Found no flash device\n");
464 + goto error;
465 + }
466 +
467 + priv->readaddr = ioremap_nocache(SPI_FLASH_READ, flashconfig_tbl[index].byte_cnt);
468 + if (!priv->readaddr) {
469 + dev_warn(&pdev->dev, SPIFLASH "Failed to map flash device\n");
470 + goto error;
471 + }
472 +
473 + platform_set_drvdata(pdev, priv);
474 + mtd->name = "spiflash";
475 + mtd->type = MTD_NORFLASH;
476 + mtd->flags = (MTD_CAP_NORFLASH|MTD_WRITEABLE);
477 + mtd->size = flashconfig_tbl[index].byte_cnt;
478 + mtd->erasesize = flashconfig_tbl[index].sector_size;
479 + mtd->writesize = 1;
480 + mtd->numeraseregions = 0;
481 + mtd->eraseregions = NULL;
482 + mtd->_erase = spiflash_erase;
483 + mtd->_read = spiflash_read;
484 + mtd->_write = spiflash_write;
485 + mtd->owner = THIS_MODULE;
486 +
487 +#if defined CONFIG_MTD_REDBOOT_PARTS || CONFIG_MTD_MYLOADER_PARTS
488 + /* parse redboot partitions */
489 +
490 + result = mtd_device_parse_register(mtd, part_probe_types,
491 + NULL, NULL, 0);
492 +#endif
493 +
494 + return result;
495 +
496 +error:
497 + if (priv->mmraddr)
498 + iounmap(priv->mmraddr);
499 + kfree(priv);
500 + return -ENXIO;
501 +}
502 +
503 +static int
504 +spiflash_remove (struct platform_device *pdev)
505 +{
506 + struct spiflash_priv *priv = platform_get_drvdata(pdev);
507 + struct mtd_info *mtd = &priv->mtd;
508 +
509 + mtd_device_unregister(mtd);
510 + iounmap(priv->mmraddr);
511 + iounmap(priv->readaddr);
512 + kfree(priv);
513 +
514 + return 0;
515 +}
516 +
517 +struct platform_driver spiflash_driver = {
518 + .driver.name = "spiflash",
519 + .probe = spiflash_probe,
520 + .remove = spiflash_remove,
521 +};
522 +
523 +int __init
524 +spiflash_init (void)
525 +{
526 + return platform_driver_register(&spiflash_driver);
527 +}
528 +
529 +void __exit
530 +spiflash_exit (void)
531 +{
532 + return platform_driver_unregister(&spiflash_driver);
533 +}
534 +
535 +module_init (spiflash_init);
536 +module_exit (spiflash_exit);
537 +
538 +MODULE_LICENSE("GPL");
539 +MODULE_AUTHOR("OpenWrt.org, Atheros Communications Inc");
540 +MODULE_DESCRIPTION("MTD driver for SPI Flash on Atheros SOC");
541 +
542 --- /dev/null
543 +++ b/arch/mips/include/asm/mach-ar231x/ar2315_spiflash.h
544 @@ -0,0 +1,116 @@
545 +/*
546 + * SPI Flash Memory support header file.
547 + *
548 + * Copyright (c) 2005, Atheros Communications Inc.
549 + * Copyright (C) 2006 FON Technology, SL.
550 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
551 + * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
552 + *
553 + * This code is free software; you can redistribute it and/or modify
554 + * it under the terms of the GNU General Public License version 2 as
555 + * published by the Free Software Foundation.
556 + *
557 + */
558 +#ifndef __AR2315_SPIFLASH_H
559 +#define __AR2315_SPIFLASH_H
560 +
561 +#define STM_PAGE_SIZE 256
562 +
563 +#define SFI_WRITE_BUFFER_SIZE 4
564 +#define SFI_FLASH_ADDR_MASK 0x00ffffff
565 +
566 +#define STM_8MBIT_SIGNATURE 0x13
567 +#define STM_M25P80_BYTE_COUNT 1048576
568 +#define STM_M25P80_SECTOR_COUNT 16
569 +#define STM_M25P80_SECTOR_SIZE 0x10000
570 +
571 +#define STM_16MBIT_SIGNATURE 0x14
572 +#define STM_M25P16_BYTE_COUNT 2097152
573 +#define STM_M25P16_SECTOR_COUNT 32
574 +#define STM_M25P16_SECTOR_SIZE 0x10000
575 +
576 +#define STM_32MBIT_SIGNATURE 0x15
577 +#define STM_M25P32_BYTE_COUNT 4194304
578 +#define STM_M25P32_SECTOR_COUNT 64
579 +#define STM_M25P32_SECTOR_SIZE 0x10000
580 +
581 +#define STM_64MBIT_SIGNATURE 0x16
582 +#define STM_M25P64_BYTE_COUNT 8388608
583 +#define STM_M25P64_SECTOR_COUNT 128
584 +#define STM_M25P64_SECTOR_SIZE 0x10000
585 +
586 +#define STM_128MBIT_SIGNATURE 0x17
587 +#define STM_M25P128_BYTE_COUNT 16777216
588 +#define STM_M25P128_SECTOR_COUNT 256
589 +#define STM_M25P128_SECTOR_SIZE 0x10000
590 +
591 +#define STM_1MB_BYTE_COUNT STM_M25P80_BYTE_COUNT
592 +#define STM_1MB_SECTOR_COUNT STM_M25P80_SECTOR_COUNT
593 +#define STM_1MB_SECTOR_SIZE STM_M25P80_SECTOR_SIZE
594 +#define STM_2MB_BYTE_COUNT STM_M25P16_BYTE_COUNT
595 +#define STM_2MB_SECTOR_COUNT STM_M25P16_SECTOR_COUNT
596 +#define STM_2MB_SECTOR_SIZE STM_M25P16_SECTOR_SIZE
597 +#define STM_4MB_BYTE_COUNT STM_M25P32_BYTE_COUNT
598 +#define STM_4MB_SECTOR_COUNT STM_M25P32_SECTOR_COUNT
599 +#define STM_4MB_SECTOR_SIZE STM_M25P32_SECTOR_SIZE
600 +#define STM_8MB_BYTE_COUNT STM_M25P64_BYTE_COUNT
601 +#define STM_8MB_SECTOR_COUNT STM_M25P64_SECTOR_COUNT
602 +#define STM_8MB_SECTOR_SIZE STM_M25P64_SECTOR_SIZE
603 +#define STM_16MB_BYTE_COUNT STM_M25P128_BYTE_COUNT
604 +#define STM_16MB_SECTOR_COUNT STM_M25P128_SECTOR_COUNT
605 +#define STM_16MB_SECTOR_SIZE STM_M25P128_SECTOR_SIZE
606 +
607 +/*
608 + * ST Microelectronics Opcodes for Serial Flash
609 + */
610 +
611 +#define STM_OP_WR_ENABLE 0x06 /* Write Enable */
612 +#define STM_OP_WR_DISABLE 0x04 /* Write Disable */
613 +#define STM_OP_RD_STATUS 0x05 /* Read Status */
614 +#define STM_OP_WR_STATUS 0x01 /* Write Status */
615 +#define STM_OP_RD_DATA 0x03 /* Read Data */
616 +#define STM_OP_FAST_RD_DATA 0x0b /* Fast Read Data */
617 +#define STM_OP_PAGE_PGRM 0x02 /* Page Program */
618 +#define STM_OP_SECTOR_ERASE 0xd8 /* Sector Erase */
619 +#define STM_OP_BULK_ERASE 0xc7 /* Bulk Erase */
620 +#define STM_OP_DEEP_PWRDOWN 0xb9 /* Deep Power-Down Mode */
621 +#define STM_OP_RD_SIG 0xab /* Read Electronic Signature */
622 +
623 +#define STM_STATUS_WIP 0x01 /* Write-In-Progress */
624 +#define STM_STATUS_WEL 0x02 /* Write Enable Latch */
625 +#define STM_STATUS_BP0 0x04 /* Block Protect 0 */
626 +#define STM_STATUS_BP1 0x08 /* Block Protect 1 */
627 +#define STM_STATUS_BP2 0x10 /* Block Protect 2 */
628 +#define STM_STATUS_SRWD 0x80 /* Status Register Write Disable */
629 +
630 +/*
631 + * SPI Flash Interface Registers
632 + */
633 +#define AR531XPLUS_SPI_READ 0x08000000
634 +#define AR531XPLUS_SPI_MMR 0x11300000
635 +#define AR531XPLUS_SPI_MMR_SIZE 12
636 +
637 +#define AR531XPLUS_SPI_CTL 0x00
638 +#define AR531XPLUS_SPI_OPCODE 0x04
639 +#define AR531XPLUS_SPI_DATA 0x08
640 +
641 +#define SPI_FLASH_READ AR531XPLUS_SPI_READ
642 +#define SPI_FLASH_MMR AR531XPLUS_SPI_MMR
643 +#define SPI_FLASH_MMR_SIZE AR531XPLUS_SPI_MMR_SIZE
644 +#define SPI_FLASH_CTL AR531XPLUS_SPI_CTL
645 +#define SPI_FLASH_OPCODE AR531XPLUS_SPI_OPCODE
646 +#define SPI_FLASH_DATA AR531XPLUS_SPI_DATA
647 +
648 +#define SPI_CTL_START 0x00000100
649 +#define SPI_CTL_BUSY 0x00010000
650 +#define SPI_CTL_TXCNT_MASK 0x0000000f
651 +#define SPI_CTL_RXCNT_MASK 0x000000f0
652 +#define SPI_CTL_TX_RX_CNT_MASK 0x000000ff
653 +#define SPI_CTL_SIZE_MASK 0x00060000
654 +
655 +#define SPI_CTL_CLK_SEL_MASK 0x03000000
656 +#define SPI_OPCODE_MASK 0x000000ff
657 +
658 +#define SPI_STATUS_WIP STM_STATUS_WIP
659 +
660 +#endif