projects / openwrt / svn-archive / archive.git / blob
? search:


383ffa3ef89180248cb5f319d8391d688d826758
[openwrt/svn-archive/archive.git] / target / linux / atheros / patches-3.14 / 100-board.patch
1 --- a/arch/mips/Kconfig
2 +++ b/arch/mips/Kconfig
3 @@ -144,6 +144,19 @@ config BCM63XX
4 help
5 Support for BCM63XX based boards
6
7 +config ATHEROS_AR231X
8 + bool "Atheros 231x/531x SoC support"
9 + select CEVT_R4K
10 + select CSRC_R4K
11 + select DMA_NONCOHERENT
12 + select IRQ_CPU
13 + select SYS_HAS_CPU_MIPS32_R1
14 + select SYS_SUPPORTS_BIG_ENDIAN
15 + select SYS_SUPPORTS_32BIT_KERNEL
16 + select ARCH_REQUIRE_GPIOLIB
17 + help
18 + Support for AR231x and AR531x based boards
19 +
20 config MIPS_COBALT
21 bool "Cobalt Server"
22 select CEVT_R4K
23 @@ -795,6 +808,7 @@ config NLM_XLP_BOARD
24
25 endchoice
26
27 +source "arch/mips/ar231x/Kconfig"
28 source "arch/mips/alchemy/Kconfig"
29 source "arch/mips/ath79/Kconfig"
30 source "arch/mips/bcm47xx/Kconfig"
31 --- a/arch/mips/Kbuild.platforms
32 +++ b/arch/mips/Kbuild.platforms
33 @@ -6,6 +6,7 @@ platforms += ath79
34 platforms += bcm47xx
35 platforms += bcm63xx
36 platforms += cavium-octeon
37 +platforms += ar231x
38 platforms += cobalt
39 platforms += dec
40 platforms += emma
41 --- /dev/null
42 +++ b/arch/mips/ar231x/Platform
43 @@ -0,0 +1,6 @@
44 +#
45 +# Atheros AR531X/AR231X WiSoC
46 +#
47 +platform-$(CONFIG_ATHEROS_AR231X) += ar231x/
48 +cflags-$(CONFIG_ATHEROS_AR231X) += -I$(srctree)/arch/mips/include/asm/mach-ar231x
49 +load-$(CONFIG_ATHEROS_AR231X) += 0xffffffff80041000
50 --- /dev/null
51 +++ b/arch/mips/ar231x/Kconfig
52 @@ -0,0 +1,16 @@
53 +config ATHEROS_AR5312
54 + bool "Atheros 5312/2312+ support"
55 + depends on ATHEROS_AR231X
56 + default y
57 +
58 +config ATHEROS_AR2315
59 + bool "Atheros 2315+ support"
60 + depends on ATHEROS_AR231X
61 + select DMA_NONCOHERENT
62 + select CEVT_R4K
63 + select CSRC_R4K
64 + select IRQ_CPU
65 + select SYS_HAS_CPU_MIPS32_R1
66 + select SYS_SUPPORTS_32BIT_KERNEL
67 + select SYS_SUPPORTS_BIG_ENDIAN
68 + default y
69 --- /dev/null
70 +++ b/arch/mips/ar231x/Makefile
71 @@ -0,0 +1,13 @@
72 +#
73 +# This file is subject to the terms and conditions of the GNU General Public
74 +# License. See the file "COPYING" in the main directory of this archive
75 +# for more details.
76 +#
77 +# Copyright (C) 2006 FON Technology, SL.
78 +# Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
79 +# Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
80 +#
81 +
82 +obj-y += board.o prom.o devices.o
83 +obj-$(CONFIG_ATHEROS_AR5312) += ar5312.o
84 +obj-$(CONFIG_ATHEROS_AR2315) += ar2315.o
85 --- /dev/null
86 +++ b/arch/mips/ar231x/board.c
87 @@ -0,0 +1,263 @@
88 +/*
89 + * This file is subject to the terms and conditions of the GNU General Public
90 + * License. See the file "COPYING" in the main directory of this archive
91 + * for more details.
92 + *
93 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
94 + * Copyright (C) 2006 FON Technology, SL.
95 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
96 + * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
97 + */
98 +
99 +#include <generated/autoconf.h>
100 +#include <linux/init.h>
101 +#include <linux/module.h>
102 +#include <linux/types.h>
103 +#include <linux/string.h>
104 +#include <linux/platform_device.h>
105 +#include <linux/kernel.h>
106 +#include <linux/random.h>
107 +#include <linux/etherdevice.h>
108 +#include <linux/irq.h>
109 +#include <linux/io.h>
110 +#include <asm/irq_cpu.h>
111 +#include <asm/reboot.h>
112 +#include <asm/bootinfo.h>
113 +#include <asm/time.h>
114 +
115 +#include <ar231x_platform.h>
116 +#include "devices.h"
117 +#include "ar5312.h"
118 +#include "ar2315.h"
119 +
120 +void (*ar231x_irq_dispatch)(void);
121 +
122 +static inline bool
123 +check_radio_magic(u8 *addr)
124 +{
125 + addr += 0x7a; /* offset for flash magic */
126 + if ((addr[0] == 0x5a) && (addr[1] == 0xa5))
127 + return 1;
128 +
129 + return 0;
130 +}
131 +
132 +static inline bool
133 +check_board_data(u8 *flash_limit, u8 *addr, bool broken)
134 +{
135 + /* config magic found */
136 + if (*((u32 *)addr) == AR231X_BD_MAGIC)
137 + return 1;
138 +
139 + if (!broken)
140 + return 0;
141 +
142 + if (check_radio_magic(addr + 0xf8))
143 + ar231x_board.radio = addr + 0xf8;
144 + if ((addr < flash_limit + 0x10000) &&
145 + check_radio_magic(addr + 0x10000))
146 + ar231x_board.radio = addr + 0x10000;
147 +
148 + if (ar231x_board.radio) {
149 + /* broken board data detected, use radio data to find the
150 + * offset, user will fix this */
151 + return 1;
152 + }
153 + return 0;
154 +}
155 +
156 +static u8 *
157 +find_board_config(u8 *flash_limit, bool broken)
158 +{
159 + u8 *addr;
160 + int found = 0;
161 +
162 + for (addr = flash_limit - 0x1000;
163 + addr >= flash_limit - 0x30000;
164 + addr -= 0x1000) {
165 +
166 + if (check_board_data(flash_limit, addr, broken)) {
167 + found = 1;
168 + break;
169 + }
170 + }
171 +
172 + if (!found)
173 + addr = NULL;
174 +
175 + return addr;
176 +}
177 +
178 +static u8 *
179 +find_radio_config(u8 *flash_limit, u8 *board_config)
180 +{
181 + int found;
182 + u8 *radio_config;
183 +
184 + /*
185 + * Now find the start of Radio Configuration data, using heuristics:
186 + * Search forward from Board Configuration data by 0x1000 bytes
187 + * at a time until we find non-0xffffffff.
188 + */
189 + found = 0;
190 + for (radio_config = board_config + 0x1000;
191 + (radio_config < flash_limit);
192 + radio_config += 0x1000) {
193 + if ((*(u32 *)radio_config != 0xffffffff) &&
194 + check_radio_magic(radio_config)) {
195 + found = 1;
196 + break;
197 + }
198 + }
199 +
200 + /* AR2316 relocates radio config to new location */
201 + if (!found) {
202 + for (radio_config = board_config + 0xf8;
203 + (radio_config < flash_limit - 0x1000 + 0xf8);
204 + radio_config += 0x1000) {
205 + if ((*(u32 *)radio_config != 0xffffffff) &&
206 + check_radio_magic(radio_config)) {
207 + found = 1;
208 + break;
209 + }
210 + }
211 + }
212 +
213 + if (!found) {
214 + pr_warn("WARNING: Could not find Radio Configuration data\n");
215 + radio_config = 0;
216 + }
217 +
218 + return radio_config;
219 +}
220 +
221 +int __init
222 +ar231x_find_config(u8 *flash_limit)
223 +{
224 + struct ar231x_boarddata *config;
225 + unsigned int rcfg_size;
226 + int broken_boarddata = 0;
227 + u8 *bcfg, *rcfg;
228 + u8 *board_data;
229 + u8 *radio_data;
230 + u8 *mac_addr;
231 + u32 offset;
232 +
233 + ar231x_board.config = NULL;
234 + ar231x_board.radio = NULL;
235 + /* Copy the board and radio data to RAM, because accessing the mapped
236 + * memory of the flash directly after booting is not safe */
237 +
238 + /* Try to find valid board and radio data */
239 + bcfg = find_board_config(flash_limit, false);
240 +
241 + /* If that fails, try to at least find valid radio data */
242 + if (!bcfg) {
243 + bcfg = find_board_config(flash_limit, true);
244 + broken_boarddata = 1;
245 + }
246 +
247 + if (!bcfg) {
248 + pr_warn("WARNING: No board configuration data found!\n");
249 + return -ENODEV;
250 + }
251 +
252 + board_data = kzalloc(BOARD_CONFIG_BUFSZ, GFP_KERNEL);
253 + ar231x_board.config = (struct ar231x_boarddata *)board_data;
254 + memcpy(board_data, bcfg, 0x100);
255 + if (broken_boarddata) {
256 + pr_warn("WARNING: broken board data detected\n");
257 + config = ar231x_board.config;
258 + if (!memcmp(config->enet0_mac, "\x00\x00\x00\x00\x00\x00", 6)) {
259 + pr_info("Fixing up empty mac addresses\n");
260 + config->reset_config_gpio = 0xffff;
261 + config->sys_led_gpio = 0xffff;
262 + random_ether_addr(config->wlan0_mac);
263 + config->wlan0_mac[0] &= ~0x06;
264 + random_ether_addr(config->enet0_mac);
265 + random_ether_addr(config->enet1_mac);
266 + }
267 + }
268 +
269 +
270 + /* Radio config starts 0x100 bytes after board config, regardless
271 + * of what the physical layout on the flash chip looks like */
272 +
273 + if (ar231x_board.radio)
274 + rcfg = (u8 *)ar231x_board.radio;
275 + else
276 + rcfg = find_radio_config(flash_limit, bcfg);
277 +
278 + if (!rcfg)
279 + return -ENODEV;
280 +
281 + radio_data = board_data + 0x100 + ((rcfg - bcfg) & 0xfff);
282 + ar231x_board.radio = radio_data;
283 + offset = radio_data - board_data;
284 + pr_info("Radio config found at offset 0x%x (0x%x)\n", rcfg - bcfg,
285 + offset);
286 + rcfg_size = BOARD_CONFIG_BUFSZ - offset;
287 + memcpy(radio_data, rcfg, rcfg_size);
288 +
289 + mac_addr = &radio_data[0x1d * 2];
290 + if (is_broadcast_ether_addr(mac_addr)) {
291 + pr_info("Radio MAC is blank; using board-data\n");
292 + memcpy(mac_addr, ar231x_board.config->wlan0_mac, ETH_ALEN);
293 + }
294 +
295 + return 0;
296 +}
297 +
298 +static void
299 +ar231x_halt(void)
300 +{
301 + local_irq_disable();
302 + while (1)
303 + ;
304 +}
305 +
306 +void __init
307 +plat_mem_setup(void)
308 +{
309 + _machine_halt = ar231x_halt;
310 + pm_power_off = ar231x_halt;
311 +
312 + ar5312_plat_setup();
313 + ar2315_plat_setup();
314 +
315 + /* Disable data watchpoints */
316 + write_c0_watchlo0(0);
317 +}
318 +
319 +
320 +asmlinkage void
321 +plat_irq_dispatch(void)
322 +{
323 + ar231x_irq_dispatch();
324 +}
325 +
326 +void __init
327 +plat_time_init(void)
328 +{
329 + ar5312_time_init();
330 + ar2315_time_init();
331 +}
332 +
333 +unsigned int __cpuinit
334 +get_c0_compare_int(void)
335 +{
336 + return CP0_LEGACY_COMPARE_IRQ;
337 +}
338 +
339 +void __init
340 +arch_init_irq(void)
341 +{
342 + clear_c0_status(ST0_IM);
343 + mips_cpu_irq_init();
344 +
345 + /* Initialize interrupt controllers */
346 + ar5312_irq_init();
347 + ar2315_irq_init();
348 +}
349 +
350 +
351 --- /dev/null
352 +++ b/arch/mips/ar231x/prom.c
353 @@ -0,0 +1,37 @@
354 +/*
355 + * This file is subject to the terms and conditions of the GNU General Public
356 + * License. See the file "COPYING" in the main directory of this archive
357 + * for more details.
358 + *
359 + * Copyright MontaVista Software Inc
360 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
361 + * Copyright (C) 2006 FON Technology, SL.
362 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
363 + * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
364 + */
365 +
366 +/*
367 + * Prom setup file for ar231x
368 + */
369 +
370 +#include <linux/init.h>
371 +#include <generated/autoconf.h>
372 +#include <linux/kernel.h>
373 +#include <linux/string.h>
374 +#include <linux/mm.h>
375 +#include <linux/bootmem.h>
376 +
377 +#include <asm/bootinfo.h>
378 +#include <asm/addrspace.h>
379 +#include "ar5312.h"
380 +#include "ar2315.h"
381 +
382 +void __init prom_init(void)
383 +{
384 + ar5312_prom_init();
385 + ar2315_prom_init();
386 +}
387 +
388 +void __init prom_free_prom_memory(void)
389 +{
390 +}
391 --- /dev/null
392 +++ b/arch/mips/include/asm/mach-ar231x/ar231x_platform.h
393 @@ -0,0 +1,83 @@
394 +#ifndef __ASM_MACH_AR231X_PLATFORM_H
395 +#define __ASM_MACH_AR231X_PLATFORM_H
396 +
397 +/*
398 + * This is board-specific data that is stored in a "fixed" location in flash.
399 + * It is shared across operating systems, so it should not be changed lightly.
400 + * The main reason we need it is in order to extract the ethernet MAC
401 + * address(es).
402 + */
403 +struct ar231x_boarddata {
404 + u32 magic; /* board data is valid */
405 +#define AR231X_BD_MAGIC 0x35333131 /* "5311", for all 531x/231x platforms */
406 + u16 cksum; /* checksum (starting with BD_REV 2) */
407 + u16 rev; /* revision of this struct */
408 +#define BD_REV 4
409 + char board_name[64]; /* Name of board */
410 + u16 major; /* Board major number */
411 + u16 minor; /* Board minor number */
412 + u32 flags; /* Board configuration */
413 +#define BD_ENET0 0x00000001 /* ENET0 is stuffed */
414 +#define BD_ENET1 0x00000002 /* ENET1 is stuffed */
415 +#define BD_UART1 0x00000004 /* UART1 is stuffed */
416 +#define BD_UART0 0x00000008 /* UART0 is stuffed (dma) */
417 +#define BD_RSTFACTORY 0x00000010 /* Reset factory defaults stuffed */
418 +#define BD_SYSLED 0x00000020 /* System LED stuffed */
419 +#define BD_EXTUARTCLK 0x00000040 /* External UART clock */
420 +#define BD_CPUFREQ 0x00000080 /* cpu freq is valid in nvram */
421 +#define BD_SYSFREQ 0x00000100 /* sys freq is set in nvram */
422 +#define BD_WLAN0 0x00000200 /* Enable WLAN0 */
423 +#define BD_MEMCAP 0x00000400 /* CAP SDRAM @ mem_cap for testing */
424 +#define BD_DISWATCHDOG 0x00000800 /* disable system watchdog */
425 +#define BD_WLAN1 0x00001000 /* Enable WLAN1 (ar5212) */
426 +#define BD_ISCASPER 0x00002000 /* FLAG for AR2312 */
427 +#define BD_WLAN0_2G_EN 0x00004000 /* FLAG for radio0_2G */
428 +#define BD_WLAN0_5G_EN 0x00008000 /* FLAG for radio0_2G */
429 +#define BD_WLAN1_2G_EN 0x00020000 /* FLAG for radio0_2G */
430 +#define BD_WLAN1_5G_EN 0x00040000 /* FLAG for radio0_2G */
431 + u16 reset_config_gpio; /* Reset factory GPIO pin */
432 + u16 sys_led_gpio; /* System LED GPIO pin */
433 +
434 + u32 cpu_freq; /* CPU core frequency in Hz */
435 + u32 sys_freq; /* System frequency in Hz */
436 + u32 cnt_freq; /* Calculated C0_COUNT frequency */
437 +
438 + u8 wlan0_mac[6];
439 + u8 enet0_mac[6];
440 + u8 enet1_mac[6];
441 +
442 + u16 pci_id; /* Pseudo PCIID for common code */
443 + u16 mem_cap; /* cap bank1 in MB */
444 +
445 + /* version 3 */
446 + u8 wlan1_mac[6]; /* (ar5212) */
447 +};
448 +
449 +#define BOARD_CONFIG_BUFSZ 0x1000
450 +
451 +/*
452 + * Platform device information for the Wireless MAC
453 + */
454 +struct ar231x_board_config {
455 + u16 devid;
456 +
457 + /* board config data */
458 + struct ar231x_boarddata *config;
459 +
460 + /* radio calibration data */
461 + const char *radio;
462 +};
463 +
464 +/*
465 + * Platform device information for the Ethernet MAC
466 + */
467 +struct ar231x_eth {
468 + void (*reset_set)(u32);
469 + void (*reset_clear)(u32);
470 + u32 reset_mac;
471 + u32 reset_phy;
472 + struct ar231x_board_config *config;
473 + char *macaddr;
474 +};
475 +
476 +#endif /* __ASM_MACH_AR231X_PLATFORM_H */
477 --- /dev/null
478 +++ b/arch/mips/include/asm/mach-ar231x/cpu-feature-overrides.h
479 @@ -0,0 +1,84 @@
480 +/*
481 + * Atheros AR231x/AR531x SoC specific CPU feature overrides
482 + *
483 + * Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
484 + *
485 + * This file was derived from: include/asm-mips/cpu-features.h
486 + * Copyright (C) 2003, 2004 Ralf Baechle
487 + * Copyright (C) 2004 Maciej W. Rozycki
488 + *
489 + * This program is free software; you can redistribute it and/or modify it
490 + * under the terms of the GNU General Public License version 2 as published
491 + * by the Free Software Foundation.
492 + *
493 + */
494 +#ifndef __ASM_MACH_AR231X_CPU_FEATURE_OVERRIDES_H
495 +#define __ASM_MACH_AR231X_CPU_FEATURE_OVERRIDES_H
496 +
497 +/*
498 + * The Atheros AR531x/AR231x SoCs have MIPS 4Kc/4KEc core.
499 + */
500 +#define cpu_has_tlb 1
501 +#define cpu_has_4kex 1
502 +#define cpu_has_3k_cache 0
503 +#define cpu_has_4k_cache 1
504 +#define cpu_has_tx39_cache 0
505 +#define cpu_has_sb1_cache 0
506 +#define cpu_has_fpu 0
507 +#define cpu_has_32fpr 0
508 +#define cpu_has_counter 1
509 +/* #define cpu_has_watch ? */
510 +/* #define cpu_has_divec ? */
511 +/* #define cpu_has_vce ? */
512 +/* #define cpu_has_cache_cdex_p ? */
513 +/* #define cpu_has_cache_cdex_s ? */
514 +/* #define cpu_has_prefetch ? */
515 +/* #define cpu_has_mcheck ? */
516 +#define cpu_has_ejtag 1
517 +
518 +#if !defined(CONFIG_ATHEROS_AR5312)
519 +# define cpu_has_llsc 1
520 +#else
521 +/*
522 + * The MIPS 4Kc V0.9 core in the AR5312/AR2312 have problems with the
523 + * ll/sc instructions.
524 + */
525 +# define cpu_has_llsc 0
526 +#endif
527 +
528 +#define cpu_has_mips16 0
529 +#define cpu_has_mdmx 0
530 +#define cpu_has_mips3d 0
531 +#define cpu_has_smartmips 0
532 +
533 +/* #define cpu_has_vtag_icache ? */
534 +/* #define cpu_has_dc_aliases ? */
535 +/* #define cpu_has_ic_fills_f_dc ? */
536 +/* #define cpu_has_pindexed_dcache ? */
537 +
538 +/* #define cpu_icache_snoops_remote_store ? */
539 +
540 +#define cpu_has_mips32r1 1
541 +
542 +#if !defined(CONFIG_ATHEROS_AR5312)
543 +# define cpu_has_mips32r2 1
544 +#endif
545 +
546 +#define cpu_has_mips64r1 0
547 +#define cpu_has_mips64r2 0
548 +
549 +#define cpu_has_dsp 0
550 +#define cpu_has_mipsmt 0
551 +
552 +/* #define cpu_has_nofpuex ? */
553 +#define cpu_has_64bits 0
554 +#define cpu_has_64bit_zero_reg 0
555 +#define cpu_has_64bit_gp_regs 0
556 +#define cpu_has_64bit_addresses 0
557 +
558 +/* #define cpu_has_inclusive_pcaches ? */
559 +
560 +/* #define cpu_dcache_line_size() ? */
561 +/* #define cpu_icache_line_size() ? */
562 +
563 +#endif /* __ASM_MACH_AR231X_CPU_FEATURE_OVERRIDES_H */
564 --- /dev/null
565 +++ b/arch/mips/include/asm/mach-ar231x/dma-coherence.h
566 @@ -0,0 +1,79 @@
567 +/*
568 + * This file is subject to the terms and conditions of the GNU General Public
569 + * License. See the file "COPYING" in the main directory of this archive
570 + * for more details.
571 + *
572 + * Copyright (C) 2006 Ralf Baechle <ralf@linux-mips.org>
573 + * Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
574 + *
575 + */
576 +#ifndef __ASM_MACH_AR231X_DMA_COHERENCE_H
577 +#define __ASM_MACH_AR231X_DMA_COHERENCE_H
578 +
579 +#define PCI_DMA_OFFSET 0x20000000
580 +
581 +#include <linux/device.h>
582 +
583 +static inline dma_addr_t ar231x_dev_offset(struct device *dev)
584 +{
585 +#ifdef CONFIG_PCI
586 + extern struct bus_type pci_bus_type;
587 +
588 + if (dev && dev->bus == &pci_bus_type)
589 + return PCI_DMA_OFFSET;
590 + else
591 +#endif
592 + return 0;
593 +}
594 +
595 +static inline dma_addr_t
596 +plat_map_dma_mem(struct device *dev, void *addr, size_t size)
597 +{
598 + return virt_to_phys(addr) + ar231x_dev_offset(dev);
599 +}
600 +
601 +static inline dma_addr_t
602 +plat_map_dma_mem_page(struct device *dev, struct page *page)
603 +{
604 + return page_to_phys(page) + ar231x_dev_offset(dev);
605 +}
606 +
607 +static inline unsigned long
608 +plat_dma_addr_to_phys(struct device *dev, dma_addr_t dma_addr)
609 +{
610 + return dma_addr - ar231x_dev_offset(dev);
611 +}
612 +
613 +static inline void
614 +plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr, size_t size,
615 + enum dma_data_direction direction)
616 +{
617 +}
618 +
619 +static inline int plat_dma_supported(struct device *dev, u64 mask)
620 +{
621 + return 1;
622 +}
623 +
624 +static inline void plat_extra_sync_for_device(struct device *dev)
625 +{
626 + return;
627 +}
628 +
629 +static inline int plat_dma_mapping_error(struct device *dev,
630 + dma_addr_t dma_addr)
631 +{
632 + return 0;
633 +}
634 +
635 +static inline int plat_device_is_coherent(struct device *dev)
636 +{
637 +#ifdef CONFIG_DMA_COHERENT
638 + return 1;
639 +#endif
640 +#ifdef CONFIG_DMA_NONCOHERENT
641 + return 0;
642 +#endif
643 +}
644 +
645 +#endif /* __ASM_MACH_AR231X_DMA_COHERENCE_H */
646 --- /dev/null
647 +++ b/arch/mips/include/asm/mach-ar231x/gpio.h
648 @@ -0,0 +1,30 @@
649 +#ifndef __ASM_MACH_AR231X_GPIO_H
650 +#define __ASM_MACH_AR231X_GPIO_H
651 +
652 +#include <ar231x.h>
653 +
654 +#define gpio_get_value __gpio_get_value
655 +#define gpio_set_value __gpio_set_value
656 +#define gpio_cansleep __gpio_cansleep
657 +
658 +/*
659 + * Wrappers for the generic GPIO layer
660 + */
661 +
662 +/* not sure if these are used? */
663 +
664 +/* Returns IRQ to attach for gpio. Unchecked function */
665 +static inline int gpio_to_irq(unsigned gpio)
666 +{
667 + return AR231X_GPIO_IRQ(gpio);
668 +}
669 +
670 +/* Returns gpio for IRQ attached. Unchecked function */
671 +static inline int irq_to_gpio(unsigned irq)
672 +{
673 + return irq - AR231X_GPIO_IRQ(0);
674 +}
675 +
676 +#include <asm-generic/gpio.h> /* cansleep wrappers */
677 +
678 +#endif /* __ASM_MACH_AR231X_GPIO_H */
679 --- /dev/null
680 +++ b/arch/mips/include/asm/mach-ar231x/reset.h
681 @@ -0,0 +1,6 @@
682 +#ifndef __ASM_MACH_AR231X_RESET_H
683 +#define __ASM_MACH_AR231X_RESET_H
684 +
685 +void ar231x_disable_reset_button(void);
686 +
687 +#endif /* __ASM_MACH_AR231X_RESET_H */
688 --- /dev/null
689 +++ b/arch/mips/include/asm/mach-ar231x/war.h
690 @@ -0,0 +1,25 @@
691 +/*
692 + * This file is subject to the terms and conditions of the GNU General Public
693 + * License. See the file "COPYING" in the main directory of this archive
694 + * for more details.
695 + *
696 + * Copyright (C) 2008 Felix Fietkau <nbd@openwrt.org>
697 + */
698 +#ifndef __ASM_MACH_AR231X_WAR_H
699 +#define __ASM_MACH_AR231X_WAR_H
700 +
701 +#define R4600_V1_INDEX_ICACHEOP_WAR 0
702 +#define R4600_V1_HIT_CACHEOP_WAR 0
703 +#define R4600_V2_HIT_CACHEOP_WAR 0
704 +#define R5432_CP0_INTERRUPT_WAR 0
705 +#define BCM1250_M3_WAR 0
706 +#define SIBYTE_1956_WAR 0
707 +#define MIPS4K_ICACHE_REFILL_WAR 0
708 +#define MIPS_CACHE_SYNC_WAR 0
709 +#define TX49XX_ICACHE_INDEX_INV_WAR 0
710 +#define RM9000_CDEX_SMP_WAR 0
711 +#define ICACHE_REFILLS_WORKAROUND_WAR 0
712 +#define R10000_LLSC_WAR 0
713 +#define MIPS34K_MISSED_ITLB_WAR 0
714 +
715 +#endif /* __ASM_MACH_AR231X_WAR_H */
716 --- /dev/null
717 +++ b/arch/mips/include/asm/mach-ar231x/ar2315_regs.h
718 @@ -0,0 +1,617 @@
719 +/*
720 + * Register definitions for AR2315+
721 + *
722 + * This file is subject to the terms and conditions of the GNU General Public
723 + * License. See the file "COPYING" in the main directory of this archive
724 + * for more details.
725 + *
726 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
727 + * Copyright (C) 2006 FON Technology, SL.
728 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
729 + * Copyright (C) 2006-2008 Felix Fietkau <nbd@openwrt.org>
730 + */
731 +
732 +#ifndef __ASM_MACH_AR231X_AR2315_REGS_H
733 +#define __ASM_MACH_AR231X_AR2315_REGS_H
734 +
735 +/*
736 + * IRQs
737 + */
738 +#define AR2315_IRQ_MISC_INTRS (MIPS_CPU_IRQ_BASE+2) /* C0_CAUSE: 0x0400 */
739 +#define AR2315_IRQ_WLAN0_INTRS (MIPS_CPU_IRQ_BASE+3) /* C0_CAUSE: 0x0800 */
740 +#define AR2315_IRQ_ENET0_INTRS (MIPS_CPU_IRQ_BASE+4) /* C0_CAUSE: 0x1000 */
741 +#define AR2315_IRQ_LCBUS_PCI (MIPS_CPU_IRQ_BASE+5) /* C0_CAUSE: 0x2000 */
742 +#define AR2315_IRQ_WLAN0_POLL (MIPS_CPU_IRQ_BASE+6) /* C0_CAUSE: 0x4000 */
743 +
744 +
745 +/*
746 + * Miscellaneous interrupts, which share IP2.
747 + */
748 +#define AR2315_MISC_IRQ_NONE (AR231X_MISC_IRQ_BASE+0)
749 +#define AR2315_MISC_IRQ_UART0 (AR231X_MISC_IRQ_BASE+1)
750 +#define AR2315_MISC_IRQ_I2C_RSVD (AR231X_MISC_IRQ_BASE+2)
751 +#define AR2315_MISC_IRQ_SPI (AR231X_MISC_IRQ_BASE+3)
752 +#define AR2315_MISC_IRQ_AHB (AR231X_MISC_IRQ_BASE+4)
753 +#define AR2315_MISC_IRQ_APB (AR231X_MISC_IRQ_BASE+5)
754 +#define AR2315_MISC_IRQ_TIMER (AR231X_MISC_IRQ_BASE+6)
755 +#define AR2315_MISC_IRQ_GPIO (AR231X_MISC_IRQ_BASE+7)
756 +#define AR2315_MISC_IRQ_WATCHDOG (AR231X_MISC_IRQ_BASE+8)
757 +#define AR2315_MISC_IRQ_IR_RSVD (AR231X_MISC_IRQ_BASE+9)
758 +#define AR2315_MISC_IRQ_COUNT 10
759 +
760 +
761 +/*
762 + * Address map
763 + */
764 +#define AR2315_SPI_READ 0x08000000 /* SPI FLASH */
765 +#define AR2315_WLAN0 0x10000000 /* Wireless MMR */
766 +#define AR2315_PCI 0x10100000 /* PCI MMR */
767 +#define AR2315_SDRAMCTL 0x10300000 /* SDRAM MMR */
768 +#define AR2315_LOCAL 0x10400000 /* LOCAL BUS MMR */
769 +#define AR2315_ENET0 0x10500000 /* ETHERNET MMR */
770 +#define AR2315_DSLBASE 0x11000000 /* RESET CONTROL MMR */
771 +#define AR2315_UART0 0x11100000 /* UART MMR */
772 +#define AR2315_SPI_MMR 0x11300000 /* SPI FLASH MMR */
773 +#define AR2315_PCIEXT 0x80000000 /* pci external */
774 +
775 +/* MII registers offset inside Ethernet MMR region */
776 +#define AR2315_ENET0_MII (AR2315_ENET0 + 0x14)
777 +
778 +/*
779 + * Reset Register
780 + */
781 +#define AR2315_COLD_RESET (AR2315_DSLBASE + 0x0000)
782 +
783 +#define AR2315_RESET_COLD_AHB 0x00000001
784 +#define AR2315_RESET_COLD_APB 0x00000002
785 +#define AR2315_RESET_COLD_CPU 0x00000004
786 +#define AR2315_RESET_COLD_CPUWARM 0x00000008
787 +#define AR2315_RESET_SYSTEM \
788 + (RESET_COLD_CPU |\
789 + RESET_COLD_APB |\
790 + RESET_COLD_AHB) /* full system */
791 +#define AR2317_RESET_SYSTEM 0x00000010
792 +
793 +
794 +#define AR2315_RESET (AR2315_DSLBASE + 0x0004)
795 +
796 +/* warm reset WLAN0 MAC */
797 +#define AR2315_RESET_WARM_WLAN0_MAC 0x00000001
798 +/* warm reset WLAN0 BaseBand */
799 +#define AR2315_RESET_WARM_WLAN0_BB 0x00000002
800 +/* warm reset MPEG-TS */
801 +#define AR2315_RESET_MPEGTS_RSVD 0x00000004
802 +/* warm reset PCI ahb/dma */
803 +#define AR2315_RESET_PCIDMA 0x00000008
804 +/* warm reset memory controller */
805 +#define AR2315_RESET_MEMCTL 0x00000010
806 +/* warm reset local bus */
807 +#define AR2315_RESET_LOCAL 0x00000020
808 +/* warm reset I2C bus */
809 +#define AR2315_RESET_I2C_RSVD 0x00000040
810 +/* warm reset SPI interface */
811 +#define AR2315_RESET_SPI 0x00000080
812 +/* warm reset UART0 */
813 +#define AR2315_RESET_UART0 0x00000100
814 +/* warm reset IR interface */
815 +#define AR2315_RESET_IR_RSVD 0x00000200
816 +/* cold reset ENET0 phy */
817 +#define AR2315_RESET_EPHY0 0x00000400
818 +/* cold reset ENET0 mac */
819 +#define AR2315_RESET_ENET0 0x00000800
820 +
821 +/*
822 + * AHB master arbitration control
823 + */
824 +#define AR2315_AHB_ARB_CTL (AR2315_DSLBASE + 0x0008)
825 +
826 +/* CPU, default */
827 +#define AR2315_ARB_CPU 0x00000001
828 +/* WLAN */
829 +#define AR2315_ARB_WLAN 0x00000002
830 +/* MPEG-TS */
831 +#define AR2315_ARB_MPEGTS_RSVD 0x00000004
832 +/* LOCAL */
833 +#define AR2315_ARB_LOCAL 0x00000008
834 +/* PCI */
835 +#define AR2315_ARB_PCI 0x00000010
836 +/* Ethernet */
837 +#define AR2315_ARB_ETHERNET 0x00000020
838 +/* retry policy, debug only */
839 +#define AR2315_ARB_RETRY 0x00000100
840 +
841 +/*
842 + * Config Register
843 + */
844 +#define AR2315_ENDIAN_CTL (AR2315_DSLBASE + 0x000c)
845 +
846 +/* EC - AHB bridge endianess */
847 +#define AR2315_CONFIG_AHB 0x00000001
848 +/* WLAN byteswap */
849 +#define AR2315_CONFIG_WLAN 0x00000002
850 +/* MPEG-TS byteswap */
851 +#define AR2315_CONFIG_MPEGTS_RSVD 0x00000004
852 +/* PCI byteswap */
853 +#define AR2315_CONFIG_PCI 0x00000008
854 +/* Memory controller endianess */
855 +#define AR2315_CONFIG_MEMCTL 0x00000010
856 +/* Local bus byteswap */
857 +#define AR2315_CONFIG_LOCAL 0x00000020
858 +/* Ethernet byteswap */
859 +#define AR2315_CONFIG_ETHERNET 0x00000040
860 +
861 +/* CPU write buffer merge */
862 +#define AR2315_CONFIG_MERGE 0x00000200
863 +/* CPU big endian */
864 +#define AR2315_CONFIG_CPU 0x00000400
865 +#define AR2315_CONFIG_PCIAHB 0x00000800
866 +#define AR2315_CONFIG_PCIAHB_BRIDGE 0x00001000
867 +/* SPI byteswap */
868 +#define AR2315_CONFIG_SPI 0x00008000
869 +#define AR2315_CONFIG_CPU_DRAM 0x00010000
870 +#define AR2315_CONFIG_CPU_PCI 0x00020000
871 +#define AR2315_CONFIG_CPU_MMR 0x00040000
872 +#define AR2315_CONFIG_BIG 0x00000400
873 +
874 +
875 +/*
876 + * NMI control
877 + */
878 +#define AR2315_NMI_CTL (AR2315_DSLBASE + 0x0010)
879 +
880 +#define AR2315_NMI_EN 1
881 +
882 +/*
883 + * Revision Register - Initial value is 0x3010 (WMAC 3.0, AR231X 1.0).
884 + */
885 +#define AR2315_SREV (AR2315_DSLBASE + 0x0014)
886 +
887 +#define AR2315_REV_MAJ 0x00f0
888 +#define AR2315_REV_MAJ_S 4
889 +#define AR2315_REV_MIN 0x000f
890 +#define AR2315_REV_MIN_S 0
891 +#define AR2315_REV_CHIP (AR2315_REV_MAJ|AR2315_REV_MIN)
892 +
893 +/*
894 + * Interface Enable
895 + */
896 +#define AR2315_IF_CTL (AR2315_DSLBASE + 0x0018)
897 +
898 +#define AR2315_IF_MASK 0x00000007
899 +#define AR2315_IF_DISABLED 0
900 +#define AR2315_IF_PCI 1
901 +#define AR2315_IF_TS_LOCAL 2
902 +/* only for emulation with separate pins */
903 +#define AR2315_IF_ALL 3
904 +#define AR2315_IF_LOCAL_HOST 0x00000008
905 +#define AR2315_IF_PCI_HOST 0x00000010
906 +#define AR2315_IF_PCI_INTR 0x00000020
907 +#define AR2315_IF_PCI_CLK_MASK 0x00030000
908 +#define AR2315_IF_PCI_CLK_INPUT 0
909 +#define AR2315_IF_PCI_CLK_OUTPUT_LOW 1
910 +#define AR2315_IF_PCI_CLK_OUTPUT_CLK 2
911 +#define AR2315_IF_PCI_CLK_OUTPUT_HIGH 3
912 +#define AR2315_IF_PCI_CLK_SHIFT 16
913 +
914 +/*
915 + * APB Interrupt control
916 + */
917 +
918 +#define AR2315_ISR (AR2315_DSLBASE + 0x0020)
919 +#define AR2315_IMR (AR2315_DSLBASE + 0x0024)
920 +#define AR2315_GISR (AR2315_DSLBASE + 0x0028)
921 +
922 +#define AR2315_ISR_UART0 0x0001 /* high speed UART */
923 +#define AR2315_ISR_I2C_RSVD 0x0002 /* I2C bus */
924 +#define AR2315_ISR_SPI 0x0004 /* SPI bus */
925 +#define AR2315_ISR_AHB 0x0008 /* AHB error */
926 +#define AR2315_ISR_APB 0x0010 /* APB error */
927 +#define AR2315_ISR_TIMER 0x0020 /* timer */
928 +#define AR2315_ISR_GPIO 0x0040 /* GPIO */
929 +#define AR2315_ISR_WD 0x0080 /* watchdog */
930 +#define AR2315_ISR_IR_RSVD 0x0100 /* IR */
931 +
932 +#define AR2315_GISR_MISC 0x0001
933 +#define AR2315_GISR_WLAN0 0x0002
934 +#define AR2315_GISR_MPEGTS_RSVD 0x0004
935 +#define AR2315_GISR_LOCALPCI 0x0008
936 +#define AR2315_GISR_WMACPOLL 0x0010
937 +#define AR2315_GISR_TIMER 0x0020
938 +#define AR2315_GISR_ETHERNET 0x0040
939 +
940 +/*
941 + * Interrupt routing from IO to the processor IP bits
942 + * Define our inter mask and level
943 + */
944 +#define AR2315_INTR_MISCIO SR_IBIT3
945 +#define AR2315_INTR_WLAN0 SR_IBIT4
946 +#define AR2315_INTR_ENET0 SR_IBIT5
947 +#define AR2315_INTR_LOCALPCI SR_IBIT6
948 +#define AR2315_INTR_WMACPOLL SR_IBIT7
949 +#define AR2315_INTR_COMPARE SR_IBIT8
950 +
951 +/*
952 + * Timers
953 + */
954 +#define AR2315_TIMER (AR2315_DSLBASE + 0x0030)
955 +#define AR2315_RELOAD (AR2315_DSLBASE + 0x0034)
956 +#define AR2315_WD (AR2315_DSLBASE + 0x0038)
957 +#define AR2315_WDC (AR2315_DSLBASE + 0x003c)
958 +
959 +#define AR2315_WDC_IGNORE_EXPIRATION 0x00000000
960 +#define AR2315_WDC_NMI 0x00000001 /* NMI on watchdog */
961 +#define AR2315_WDC_RESET 0x00000002 /* reset on watchdog */
962 +
963 +/*
964 + * CPU Performance Counters
965 + */
966 +#define AR2315_PERFCNT0 (AR2315_DSLBASE + 0x0048)
967 +#define AR2315_PERFCNT1 (AR2315_DSLBASE + 0x004c)
968 +
969 +#define AR2315_PERF0_DATAHIT 0x0001 /* Count Data Cache Hits */
970 +#define AR2315_PERF0_DATAMISS 0x0002 /* Count Data Cache Misses */
971 +#define AR2315_PERF0_INSTHIT 0x0004 /* Count Instruction Cache Hits */
972 +#define AR2315_PERF0_INSTMISS 0x0008 /* Count Instruction Cache Misses */
973 +#define AR2315_PERF0_ACTIVE 0x0010 /* Count Active Processor Cycles */
974 +#define AR2315_PERF0_WBHIT 0x0020 /* Count CPU Write Buffer Hits */
975 +#define AR2315_PERF0_WBMISS 0x0040 /* Count CPU Write Buffer Misses */
976 +
977 +#define AR2315_PERF1_EB_ARDY 0x0001 /* Count EB_ARdy signal */
978 +#define AR2315_PERF1_EB_AVALID 0x0002 /* Count EB_AValid signal */
979 +#define AR2315_PERF1_EB_WDRDY 0x0004 /* Count EB_WDRdy signal */
980 +#define AR2315_PERF1_EB_RDVAL 0x0008 /* Count EB_RdVal signal */
981 +#define AR2315_PERF1_VRADDR 0x0010 /* Count valid read address cycles */
982 +#define AR2315_PERF1_VWADDR 0x0020 /* Count valid write address cycles */
983 +#define AR2315_PERF1_VWDATA 0x0040 /* Count valid write data cycles */
984 +
985 +/*
986 + * AHB Error Reporting.
987 + */
988 +#define AR2315_AHB_ERR0 (AR2315_DSLBASE + 0x0050) /* error */
989 +#define AR2315_AHB_ERR1 (AR2315_DSLBASE + 0x0054) /* haddr */
990 +#define AR2315_AHB_ERR2 (AR2315_DSLBASE + 0x0058) /* hwdata */
991 +#define AR2315_AHB_ERR3 (AR2315_DSLBASE + 0x005c) /* hrdata */
992 +#define AR2315_AHB_ERR4 (AR2315_DSLBASE + 0x0060) /* status */
993 +
994 +#define AHB_ERROR_DET 1 /* AHB Error has been detected, */
995 + /* write 1 to clear all bits in ERR0 */
996 +#define AHB_ERROR_OVR 2 /* AHB Error overflow has been detected */
997 +#define AHB_ERROR_WDT 4 /* AHB Error due to wdt instead of hresp */
998 +
999 +#define AR2315_PROCERR_HMAST 0x0000000f
1000 +#define AR2315_PROCERR_HMAST_DFLT 0
1001 +#define AR2315_PROCERR_HMAST_WMAC 1
1002 +#define AR2315_PROCERR_HMAST_ENET 2
1003 +#define AR2315_PROCERR_HMAST_PCIENDPT 3
1004 +#define AR2315_PROCERR_HMAST_LOCAL 4
1005 +#define AR2315_PROCERR_HMAST_CPU 5
1006 +#define AR2315_PROCERR_HMAST_PCITGT 6
1007 +
1008 +#define AR2315_PROCERR_HMAST_S 0
1009 +#define AR2315_PROCERR_HWRITE 0x00000010
1010 +#define AR2315_PROCERR_HSIZE 0x00000060
1011 +#define AR2315_PROCERR_HSIZE_S 5
1012 +#define AR2315_PROCERR_HTRANS 0x00000180
1013 +#define AR2315_PROCERR_HTRANS_S 7
1014 +#define AR2315_PROCERR_HBURST 0x00000e00
1015 +#define AR2315_PROCERR_HBURST_S 9
1016 +
1017 +/*
1018 + * Clock Control
1019 + */
1020 +#define AR2315_PLLC_CTL (AR2315_DSLBASE + 0x0064)
1021 +#define AR2315_PLLV_CTL (AR2315_DSLBASE + 0x0068)
1022 +#define AR2315_CPUCLK (AR2315_DSLBASE + 0x006c)
1023 +#define AR2315_AMBACLK (AR2315_DSLBASE + 0x0070)
1024 +#define AR2315_SYNCCLK (AR2315_DSLBASE + 0x0074)
1025 +#define AR2315_DSL_SLEEP_CTL (AR2315_DSLBASE + 0x0080)
1026 +#define AR2315_DSL_SLEEP_DUR (AR2315_DSLBASE + 0x0084)
1027 +
1028 +/* PLLc Control fields */
1029 +#define PLLC_REF_DIV_M 0x00000003
1030 +#define PLLC_REF_DIV_S 0
1031 +#define PLLC_FDBACK_DIV_M 0x0000007C
1032 +#define PLLC_FDBACK_DIV_S 2
1033 +#define PLLC_ADD_FDBACK_DIV_M 0x00000080
1034 +#define PLLC_ADD_FDBACK_DIV_S 7
1035 +#define PLLC_CLKC_DIV_M 0x0001c000
1036 +#define PLLC_CLKC_DIV_S 14
1037 +#define PLLC_CLKM_DIV_M 0x00700000
1038 +#define PLLC_CLKM_DIV_S 20
1039 +
1040 +/* CPU CLK Control fields */
1041 +#define CPUCLK_CLK_SEL_M 0x00000003
1042 +#define CPUCLK_CLK_SEL_S 0
1043 +#define CPUCLK_CLK_DIV_M 0x0000000c
1044 +#define CPUCLK_CLK_DIV_S 2
1045 +
1046 +/* AMBA CLK Control fields */
1047 +#define AMBACLK_CLK_SEL_M 0x00000003
1048 +#define AMBACLK_CLK_SEL_S 0
1049 +#define AMBACLK_CLK_DIV_M 0x0000000c
1050 +#define AMBACLK_CLK_DIV_S 2
1051 +
1052 +/*
1053 + * GPIO
1054 + */
1055 +#define AR2315_GPIO_DI (AR2315_DSLBASE + 0x0088)
1056 +#define AR2315_GPIO_DO (AR2315_DSLBASE + 0x0090)
1057 +#define AR2315_GPIO_DIR (AR2315_DSLBASE + 0x0098)
1058 +#define AR2315_GPIO_INT (AR2315_DSLBASE + 0x00a0)
1059 +
1060 +#define AR2315_GPIO_DIR_M(x) (1 << (x)) /* mask for i/o */
1061 +#define AR2315_GPIO_DIR_O(x) (1 << (x)) /* output */
1062 +#define AR2315_GPIO_DIR_I(x) (0) /* input */
1063 +
1064 +#define AR2315_GPIO_INT_S(x) (x) /* interrupt enable */
1065 +#define AR2315_GPIO_INT_M (0x3F) /* mask for int */
1066 +#define AR2315_GPIO_INT_LVL(x) ((x) << 6) /* interrupt level */
1067 +#define AR2315_GPIO_INT_LVL_M ((0x3) << 6) /* mask for int level */
1068 +
1069 +#define AR2315_GPIO_INT_MAX_Y 1 /* Maximum value of Y for
1070 + * AR2315_GPIO_INT_* macros */
1071 +#define AR2315_GPIO_INT_LVL_OFF 0 /* Triggerring off */
1072 +#define AR2315_GPIO_INT_LVL_LOW 1 /* Low Level Triggered */
1073 +#define AR2315_GPIO_INT_LVL_HIGH 2 /* High Level Triggered */
1074 +#define AR2315_GPIO_INT_LVL_EDGE 3 /* Edge Triggered */
1075 +
1076 +#define AR2315_RESET_GPIO 5
1077 +#define AR2315_NUM_GPIO 22
1078 +
1079 +/*
1080 + * PCI Clock Control
1081 + */
1082 +#define AR2315_PCICLK (AR2315_DSLBASE + 0x00a4)
1083 +
1084 +#define AR2315_PCICLK_INPUT_M 0x3
1085 +#define AR2315_PCICLK_INPUT_S 0
1086 +
1087 +#define AR2315_PCICLK_PLLC_CLKM 0
1088 +#define AR2315_PCICLK_PLLC_CLKM1 1
1089 +#define AR2315_PCICLK_PLLC_CLKC 2
1090 +#define AR2315_PCICLK_REF_CLK 3
1091 +
1092 +#define AR2315_PCICLK_DIV_M 0xc
1093 +#define AR2315_PCICLK_DIV_S 2
1094 +
1095 +#define AR2315_PCICLK_IN_FREQ 0
1096 +#define AR2315_PCICLK_IN_FREQ_DIV_6 1
1097 +#define AR2315_PCICLK_IN_FREQ_DIV_8 2
1098 +#define AR2315_PCICLK_IN_FREQ_DIV_10 3
1099 +
1100 +/*
1101 + * Observation Control Register
1102 + */
1103 +#define AR2315_OCR (AR2315_DSLBASE + 0x00b0)
1104 +#define OCR_GPIO0_IRIN 0x0040
1105 +#define OCR_GPIO1_IROUT 0x0080
1106 +#define OCR_GPIO3_RXCLR 0x0200
1107 +
1108 +/*
1109 + * General Clock Control
1110 + */
1111 +
1112 +#define AR2315_MISCCLK (AR2315_DSLBASE + 0x00b4)
1113 +#define MISCCLK_PLLBYPASS_EN 0x00000001
1114 +#define MISCCLK_PROCREFCLK 0x00000002
1115 +
1116 +/*
1117 + * SDRAM Controller
1118 + * - No read or write buffers are included.
1119 + */
1120 +#define AR2315_MEM_CFG (AR2315_SDRAMCTL + 0x00)
1121 +#define AR2315_MEM_CTRL (AR2315_SDRAMCTL + 0x0c)
1122 +#define AR2315_MEM_REF (AR2315_SDRAMCTL + 0x10)
1123 +
1124 +#define SDRAM_DATA_WIDTH_M 0x00006000
1125 +#define SDRAM_DATA_WIDTH_S 13
1126 +
1127 +#define SDRAM_COL_WIDTH_M 0x00001E00
1128 +#define SDRAM_COL_WIDTH_S 9
1129 +
1130 +#define SDRAM_ROW_WIDTH_M 0x000001E0
1131 +#define SDRAM_ROW_WIDTH_S 5
1132 +
1133 +#define SDRAM_BANKADDR_BITS_M 0x00000018
1134 +#define SDRAM_BANKADDR_BITS_S 3
1135 +
1136 +/*
1137 + * PCI Bus Interface Registers
1138 + */
1139 +#define AR2315_PCI_1MS_REG (AR2315_PCI + 0x0008)
1140 +#define AR2315_PCI_1MS_MASK 0x3FFFF /* # of AHB clk cycles in 1ms */
1141 +
1142 +#define AR2315_PCI_MISC_CONFIG (AR2315_PCI + 0x000c)
1143 +#define AR2315_PCIMISC_TXD_EN 0x00000001 /* Enable TXD for fragments */
1144 +#define AR2315_PCIMISC_CFG_SEL 0x00000002 /* mem or config cycles */
1145 +#define AR2315_PCIMISC_GIG_MASK 0x0000000C /* bits 31-30 for pci req */
1146 +#define AR2315_PCIMISC_RST_MODE 0x00000030
1147 +#define AR2315_PCIRST_INPUT 0x00000000 /* 4:5=0 rst is input */
1148 +#define AR2315_PCIRST_LOW 0x00000010 /* 4:5=1 rst to GND */
1149 +#define AR2315_PCIRST_HIGH 0x00000020 /* 4:5=2 rst to VDD */
1150 +#define AR2315_PCIGRANT_EN 0x00000000 /* 6:7=0 early grant en */
1151 +#define AR2315_PCIGRANT_FRAME 0x00000040 /* 6:7=1 grant waits 4 frame */
1152 +#define AR2315_PCIGRANT_IDLE 0x00000080 /* 6:7=2 grant waits 4 idle */
1153 +#define AR2315_PCIGRANT_GAP 0x00000000 /* 6:7=2 grant waits 4 idle */
1154 +#define AR2315_PCICACHE_DIS 0x00001000 /* PCI external access cache
1155 + * disable */
1156 +
1157 +#define AR2315_PCI_OUT_TSTAMP (AR2315_PCI + 0x0010)
1158 +
1159 +#define AR2315_PCI_UNCACHE_CFG (AR2315_PCI + 0x0014)
1160 +
1161 +#define AR2315_PCI_IN_EN (AR2315_PCI + 0x0100)
1162 +#define AR2315_PCI_IN_EN0 0x01 /* Enable chain 0 */
1163 +#define AR2315_PCI_IN_EN1 0x02 /* Enable chain 1 */
1164 +#define AR2315_PCI_IN_EN2 0x04 /* Enable chain 2 */
1165 +#define AR2315_PCI_IN_EN3 0x08 /* Enable chain 3 */
1166 +
1167 +#define AR2315_PCI_IN_DIS (AR2315_PCI + 0x0104)
1168 +#define AR2315_PCI_IN_DIS0 0x01 /* Disable chain 0 */
1169 +#define AR2315_PCI_IN_DIS1 0x02 /* Disable chain 1 */
1170 +#define AR2315_PCI_IN_DIS2 0x04 /* Disable chain 2 */
1171 +#define AR2315_PCI_IN_DIS3 0x08 /* Disable chain 3 */
1172 +
1173 +#define AR2315_PCI_IN_PTR (AR2315_PCI + 0x0200)
1174 +
1175 +#define AR2315_PCI_OUT_EN (AR2315_PCI + 0x0400)
1176 +#define AR2315_PCI_OUT_EN0 0x01 /* Enable chain 0 */
1177 +
1178 +#define AR2315_PCI_OUT_DIS (AR2315_PCI + 0x0404)
1179 +#define AR2315_PCI_OUT_DIS0 0x01 /* Disable chain 0 */
1180 +
1181 +#define AR2315_PCI_OUT_PTR (AR2315_PCI + 0x0408)
1182 +
1183 +#define AR2315_PCI_INT_STATUS (AR2315_PCI + 0x0500) /* write one to clr */
1184 +#define AR2315_PCI_TXINT 0x00000001 /* Desc In Completed */
1185 +#define AR2315_PCI_TXOK 0x00000002 /* Desc In OK */
1186 +#define AR2315_PCI_TXERR 0x00000004 /* Desc In ERR */
1187 +#define AR2315_PCI_TXEOL 0x00000008 /* Desc In End-of-List */
1188 +#define AR2315_PCI_RXINT 0x00000010 /* Desc Out Completed */
1189 +#define AR2315_PCI_RXOK 0x00000020 /* Desc Out OK */
1190 +#define AR2315_PCI_RXERR 0x00000040 /* Desc Out ERR */
1191 +#define AR2315_PCI_RXEOL 0x00000080 /* Desc Out EOL */
1192 +#define AR2315_PCI_TXOOD 0x00000200 /* Desc In Out-of-Desc */
1193 +#define AR2315_PCI_MASK 0x0000FFFF /* Desc Mask */
1194 +#define AR2315_PCI_EXT_INT 0x02000000
1195 +#define AR2315_PCI_ABORT_INT 0x04000000
1196 +
1197 +#define AR2315_PCI_INT_MASK (AR2315_PCI + 0x0504) /* same as INT_STATUS */
1198 +
1199 +#define AR2315_PCI_INTEN_REG (AR2315_PCI + 0x0508)
1200 +#define AR2315_PCI_INT_DISABLE 0x00 /* disable pci interrupts */
1201 +#define AR2315_PCI_INT_ENABLE 0x01 /* enable pci interrupts */
1202 +
1203 +#define AR2315_PCI_HOST_IN_EN (AR2315_PCI + 0x0800)
1204 +#define AR2315_PCI_HOST_IN_DIS (AR2315_PCI + 0x0804)
1205 +#define AR2315_PCI_HOST_IN_PTR (AR2315_PCI + 0x0810)
1206 +#define AR2315_PCI_HOST_OUT_EN (AR2315_PCI + 0x0900)
1207 +#define AR2315_PCI_HOST_OUT_DIS (AR2315_PCI + 0x0904)
1208 +#define AR2315_PCI_HOST_OUT_PTR (AR2315_PCI + 0x0908)
1209 +
1210 +
1211 +/*
1212 + * Local Bus Interface Registers
1213 + */
1214 +#define AR2315_LB_CONFIG (AR2315_LOCAL + 0x0000)
1215 +#define AR2315_LBCONF_OE 0x00000001 /* =1 OE is low-true */
1216 +#define AR2315_LBCONF_CS0 0x00000002 /* =1 first CS is low-true */
1217 +#define AR2315_LBCONF_CS1 0x00000004 /* =1 2nd CS is low-true */
1218 +#define AR2315_LBCONF_RDY 0x00000008 /* =1 RDY is low-true */
1219 +#define AR2315_LBCONF_WE 0x00000010 /* =1 Write En is low-true */
1220 +#define AR2315_LBCONF_WAIT 0x00000020 /* =1 WAIT is low-true */
1221 +#define AR2315_LBCONF_ADS 0x00000040 /* =1 Adr Strobe is low-true */
1222 +#define AR2315_LBCONF_MOT 0x00000080 /* =0 Intel, =1 Motorola */
1223 +#define AR2315_LBCONF_8CS 0x00000100 /* =1 8 bits CS, 0= 16bits */
1224 +#define AR2315_LBCONF_8DS 0x00000200 /* =1 8 bits Data S, 0=16bits */
1225 +#define AR2315_LBCONF_ADS_EN 0x00000400 /* =1 Enable ADS */
1226 +#define AR2315_LBCONF_ADR_OE 0x00000800 /* =1 Adr cap on OE, WE or DS */
1227 +#define AR2315_LBCONF_ADDT_MUX 0x00001000 /* =1 Adr and Data share bus */
1228 +#define AR2315_LBCONF_DATA_OE 0x00002000 /* =1 Data cap on OE, WE, DS */
1229 +#define AR2315_LBCONF_16DATA 0x00004000 /* =1 Data is 16 bits wide */
1230 +#define AR2315_LBCONF_SWAPDT 0x00008000 /* =1 Byte swap data */
1231 +#define AR2315_LBCONF_SYNC 0x00010000 /* =1 Bus synchronous to clk */
1232 +#define AR2315_LBCONF_INT 0x00020000 /* =1 Intr is low true */
1233 +#define AR2315_LBCONF_INT_CTR0 0x00000000 /* GND high-Z, Vdd is high-Z */
1234 +#define AR2315_LBCONF_INT_CTR1 0x00040000 /* GND drive, Vdd is high-Z */
1235 +#define AR2315_LBCONF_INT_CTR2 0x00080000 /* GND high-Z, Vdd drive */
1236 +#define AR2315_LBCONF_INT_CTR3 0x000C0000 /* GND drive, Vdd drive */
1237 +#define AR2315_LBCONF_RDY_WAIT 0x00100000 /* =1 RDY is negative of WAIT */
1238 +#define AR2315_LBCONF_INT_PULSE 0x00200000 /* =1 Interrupt is a pulse */
1239 +#define AR2315_LBCONF_ENABLE 0x00400000 /* =1 Falcon respond to LB */
1240 +
1241 +#define AR2315_LB_CLKSEL (AR2315_LOCAL + 0x0004)
1242 +#define AR2315_LBCLK_EXT 0x0001 /* use external clk for lb */
1243 +
1244 +#define AR2315_LB_1MS (AR2315_LOCAL + 0x0008)
1245 +#define AR2315_LB1MS_MASK 0x3FFFF /* # of AHB clk cycles in 1ms */
1246 +
1247 +#define AR2315_LB_MISCCFG (AR2315_LOCAL + 0x000C)
1248 +#define AR2315_LBM_TXD_EN 0x00000001 /* Enable TXD for fragments */
1249 +#define AR2315_LBM_RX_INTEN 0x00000002 /* Enable LB ints on RX ready */
1250 +#define AR2315_LBM_MBOXWR_INTEN 0x00000004 /* Enable LB ints on mbox wr */
1251 +#define AR2315_LBM_MBOXRD_INTEN 0x00000008 /* Enable LB ints on mbox rd */
1252 +#define AR2315_LMB_DESCSWAP_EN 0x00000010 /* Byte swap desc enable */
1253 +#define AR2315_LBM_TIMEOUT_MASK 0x00FFFF80
1254 +#define AR2315_LBM_TIMEOUT_SHFT 7
1255 +#define AR2315_LBM_PORTMUX 0x07000000
1256 +
1257 +
1258 +#define AR2315_LB_RXTSOFF (AR2315_LOCAL + 0x0010)
1259 +
1260 +#define AR2315_LB_TX_CHAIN_EN (AR2315_LOCAL + 0x0100)
1261 +#define AR2315_LB_TXEN_0 0x01
1262 +#define AR2315_LB_TXEN_1 0x02
1263 +#define AR2315_LB_TXEN_2 0x04
1264 +#define AR2315_LB_TXEN_3 0x08
1265 +
1266 +#define AR2315_LB_TX_CHAIN_DIS (AR2315_LOCAL + 0x0104)
1267 +#define AR2315_LB_TX_DESC_PTR (AR2315_LOCAL + 0x0200)
1268 +
1269 +#define AR2315_LB_RX_CHAIN_EN (AR2315_LOCAL + 0x0400)
1270 +#define AR2315_LB_RXEN 0x01
1271 +
1272 +#define AR2315_LB_RX_CHAIN_DIS (AR2315_LOCAL + 0x0404)
1273 +#define AR2315_LB_RX_DESC_PTR (AR2315_LOCAL + 0x0408)
1274 +
1275 +#define AR2315_LB_INT_STATUS (AR2315_LOCAL + 0x0500)
1276 +#define AR2315_INT_TX_DESC 0x0001
1277 +#define AR2315_INT_TX_OK 0x0002
1278 +#define AR2315_INT_TX_ERR 0x0004
1279 +#define AR2315_INT_TX_EOF 0x0008
1280 +#define AR2315_INT_RX_DESC 0x0010
1281 +#define AR2315_INT_RX_OK 0x0020
1282 +#define AR2315_INT_RX_ERR 0x0040
1283 +#define AR2315_INT_RX_EOF 0x0080
1284 +#define AR2315_INT_TX_TRUNC 0x0100
1285 +#define AR2315_INT_TX_STARVE 0x0200
1286 +#define AR2315_INT_LB_TIMEOUT 0x0400
1287 +#define AR2315_INT_LB_ERR 0x0800
1288 +#define AR2315_INT_MBOX_WR 0x1000
1289 +#define AR2315_INT_MBOX_RD 0x2000
1290 +
1291 +/* Bit definitions for INT MASK are the same as INT_STATUS */
1292 +#define AR2315_LB_INT_MASK (AR2315_LOCAL + 0x0504)
1293 +
1294 +#define AR2315_LB_INT_EN (AR2315_LOCAL + 0x0508)
1295 +#define AR2315_LB_MBOX (AR2315_LOCAL + 0x0600)
1296 +
1297 +/*
1298 + * IR Interface Registers
1299 + */
1300 +#define AR2315_IR_PKTDATA (AR2315_IR + 0x0000)
1301 +
1302 +#define AR2315_IR_PKTLEN (AR2315_IR + 0x07fc) /* 0 - 63 */
1303 +
1304 +#define AR2315_IR_CONTROL (AR2315_IR + 0x0800)
1305 +#define AR2315_IRCTL_TX 0x00000000 /* use as tranmitter */
1306 +#define AR2315_IRCTL_RX 0x00000001 /* use as receiver */
1307 +#define AR2315_IRCTL_SAMPLECLK_MASK 0x00003ffe /* Sample clk divisor */
1308 +#define AR2315_IRCTL_SAMPLECLK_SHFT 1
1309 +#define AR2315_IRCTL_OUTPUTCLK_MASK 0x03ffc000 /* Output clk div */
1310 +#define AR2315_IRCTL_OUTPUTCLK_SHFT 14
1311 +
1312 +#define AR2315_IR_STATUS (AR2315_IR + 0x0804)
1313 +#define AR2315_IRSTS_RX 0x00000001 /* receive in progress */
1314 +#define AR2315_IRSTS_TX 0x00000002 /* transmit in progress */
1315 +
1316 +#define AR2315_IR_CONFIG (AR2315_IR + 0x0808)
1317 +#define AR2315_IRCFG_INVIN 0x00000001 /* invert in polarity */
1318 +#define AR2315_IRCFG_INVOUT 0x00000002 /* invert out polarity */
1319 +#define AR2315_IRCFG_SEQ_START_WIN_SEL 0x00000004 /* 1 => 28, 0 => 7 */
1320 +#define AR2315_IRCFG_SEQ_START_THRESH 0x000000f0
1321 +#define AR2315_IRCFG_SEQ_END_UNIT_SEL 0x00000100
1322 +#define AR2315_IRCFG_SEQ_END_UNIT_THRESH 0x00007e00
1323 +#define AR2315_IRCFG_SEQ_END_WIN_SEL 0x00008000
1324 +#define AR2315_IRCFG_SEQ_END_WIN_THRESH 0x001f0000
1325 +#define AR2315_IRCFG_NUM_BACKOFF_WORDS 0x01e00000
1326 +
1327 +#define HOST_PCI_DEV_ID 3
1328 +#define HOST_PCI_MBAR0 0x10000000
1329 +#define HOST_PCI_MBAR1 0x20000000
1330 +#define HOST_PCI_MBAR2 0x30000000
1331 +
1332 +#define HOST_PCI_SDRAM_BASEADDR HOST_PCI_MBAR1
1333 +#define PCI_DEVICE_MEM_SPACE 0x800000
1334 +
1335 +#endif /* __ASM_MACH_AR231X_AR2315_REGS_H */
1336 --- /dev/null
1337 +++ b/arch/mips/include/asm/mach-ar231x/ar5312_regs.h
1338 @@ -0,0 +1,253 @@
1339 +/*
1340 + * This file is subject to the terms and conditions of the GNU General Public
1341 + * License. See the file "COPYING" in the main directory of this archive
1342 + * for more details.
1343 + *
1344 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
1345 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
1346 + * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
1347 + */
1348 +
1349 +#ifndef __ASM_MACH_AR231X_AR5312_REGS_H
1350 +#define __ASM_MACH_AR231X_AR5312_REGS_H
1351 +
1352 +#include <asm/addrspace.h>
1353 +
1354 +/*
1355 + * IRQs
1356 + */
1357 +
1358 +#define AR5312_IRQ_WLAN0_INTRS (MIPS_CPU_IRQ_BASE+2) /* C0_CAUSE: 0x0400 */
1359 +#define AR5312_IRQ_ENET0_INTRS (MIPS_CPU_IRQ_BASE+3) /* C0_CAUSE: 0x0800 */
1360 +#define AR5312_IRQ_ENET1_INTRS (MIPS_CPU_IRQ_BASE+4) /* C0_CAUSE: 0x1000 */
1361 +#define AR5312_IRQ_WLAN1_INTRS (MIPS_CPU_IRQ_BASE+5) /* C0_CAUSE: 0x2000 */
1362 +#define AR5312_IRQ_MISC_INTRS (MIPS_CPU_IRQ_BASE+6) /* C0_CAUSE: 0x4000 */
1363 +
1364 +
1365 +/*
1366 + * Miscellaneous interrupts, which share IP6.
1367 + */
1368 +#define AR5312_MISC_IRQ_NONE (AR231X_MISC_IRQ_BASE+0)
1369 +#define AR5312_MISC_IRQ_TIMER (AR231X_MISC_IRQ_BASE+1)
1370 +#define AR5312_MISC_IRQ_AHB_PROC (AR231X_MISC_IRQ_BASE+2)
1371 +#define AR5312_MISC_IRQ_AHB_DMA (AR231X_MISC_IRQ_BASE+3)
1372 +#define AR5312_MISC_IRQ_GPIO (AR231X_MISC_IRQ_BASE+4)
1373 +#define AR5312_MISC_IRQ_UART0 (AR231X_MISC_IRQ_BASE+5)
1374 +#define AR5312_MISC_IRQ_UART0_DMA (AR231X_MISC_IRQ_BASE+6)
1375 +#define AR5312_MISC_IRQ_WATCHDOG (AR231X_MISC_IRQ_BASE+7)
1376 +#define AR5312_MISC_IRQ_LOCAL (AR231X_MISC_IRQ_BASE+8)
1377 +#define AR5312_MISC_IRQ_SPI (AR231X_MISC_IRQ_BASE+9)
1378 +#define AR5312_MISC_IRQ_COUNT 10
1379 +
1380 +
1381 +/* Address Map */
1382 +#define AR5312_WLAN0 0x18000000
1383 +#define AR5312_WLAN1 0x18500000
1384 +#define AR5312_ENET0 0x18100000
1385 +#define AR5312_ENET1 0x18200000
1386 +#define AR5312_SDRAMCTL 0x18300000
1387 +#define AR5312_FLASHCTL 0x18400000
1388 +#define AR5312_APBBASE 0x1c000000
1389 +#define AR5312_UART0 0x1c000000 /* UART MMR */
1390 +#define AR5312_FLASH 0x1e000000
1391 +
1392 +/*
1393 + * AR5312_NUM_ENET_MAC defines the number of ethernet MACs that
1394 + * should be considered available. The AR5312 supports 2 enet MACS,
1395 + * even though many reference boards only actually use 1 of them
1396 + * (i.e. Only MAC 0 is actually connected to an enet PHY or PHY switch.
1397 + * The AR2312 supports 1 enet MAC.
1398 + */
1399 +#define AR5312_NUM_ENET_MAC 2
1400 +
1401 +/*
1402 + * Need these defines to determine true number of ethernet MACs
1403 + */
1404 +#define AR5312_AR5312_REV2 0x0052 /* AR5312 WMAC (AP31) */
1405 +#define AR5312_AR5312_REV7 0x0057 /* AR5312 WMAC (AP30-040) */
1406 +#define AR5312_AR2313_REV8 0x0058 /* AR2313 WMAC (AP43-030) */
1407 +
1408 +/* MII registers offset inside Ethernet MMR region */
1409 +#define AR5312_ENET0_MII (AR5312_ENET0 + 0x14)
1410 +#define AR5312_ENET1_MII (AR5312_ENET1 + 0x14)
1411 +
1412 +/*
1413 + * AR5312_NUM_WMAC defines the number of Wireless MACs that\
1414 + * should be considered available.
1415 + */
1416 +#define AR5312_NUM_WMAC 2
1417 +
1418 +/* Reset/Timer Block Address Map */
1419 +#define AR5312_RESETTMR (AR5312_APBBASE + 0x3000)
1420 +#define AR5312_TIMER (AR5312_RESETTMR + 0x0000) /* countdown timer */
1421 +#define AR5312_WD_CTRL (AR5312_RESETTMR + 0x0008) /* watchdog cntrl */
1422 +#define AR5312_WD_TIMER (AR5312_RESETTMR + 0x000c) /* watchdog timer */
1423 +#define AR5312_ISR (AR5312_RESETTMR + 0x0010) /* Intr Status Reg */
1424 +#define AR5312_IMR (AR5312_RESETTMR + 0x0014) /* Intr Mask Reg */
1425 +#define AR5312_RESET (AR5312_RESETTMR + 0x0020)
1426 +#define AR5312_CLOCKCTL1 (AR5312_RESETTMR + 0x0064)
1427 +#define AR5312_SCRATCH (AR5312_RESETTMR + 0x006c)
1428 +#define AR5312_PROCADDR (AR5312_RESETTMR + 0x0070)
1429 +#define AR5312_PROC1 (AR5312_RESETTMR + 0x0074)
1430 +#define AR5312_DMAADDR (AR5312_RESETTMR + 0x0078)
1431 +#define AR5312_DMA1 (AR5312_RESETTMR + 0x007c)
1432 +#define AR5312_ENABLE (AR5312_RESETTMR + 0x0080) /* interface enb */
1433 +#define AR5312_REV (AR5312_RESETTMR + 0x0090) /* revision */
1434 +
1435 +/* AR5312_WD_CTRL register bit field definitions */
1436 +#define AR5312_WD_CTRL_IGNORE_EXPIRATION 0x0000
1437 +#define AR5312_WD_CTRL_NMI 0x0001
1438 +#define AR5312_WD_CTRL_RESET 0x0002
1439 +
1440 +/* AR5312_ISR register bit field definitions */
1441 +#define AR5312_ISR_NONE 0x0000
1442 +#define AR5312_ISR_TIMER 0x0001
1443 +#define AR5312_ISR_AHBPROC 0x0002
1444 +#define AR5312_ISR_AHBDMA 0x0004
1445 +#define AR5312_ISR_GPIO 0x0008
1446 +#define AR5312_ISR_UART0 0x0010
1447 +#define AR5312_ISR_UART0DMA 0x0020
1448 +#define AR5312_ISR_WD 0x0040
1449 +#define AR5312_ISR_LOCAL 0x0080
1450 +
1451 +/* AR5312_RESET register bit field definitions */
1452 +#define AR5312_RESET_SYSTEM 0x00000001 /* cold reset full system */
1453 +#define AR5312_RESET_PROC 0x00000002 /* cold reset MIPS core */
1454 +#define AR5312_RESET_WLAN0 0x00000004 /* cold reset WLAN MAC and BB */
1455 +#define AR5312_RESET_EPHY0 0x00000008 /* cold reset ENET0 phy */
1456 +#define AR5312_RESET_EPHY1 0x00000010 /* cold reset ENET1 phy */
1457 +#define AR5312_RESET_ENET0 0x00000020 /* cold reset ENET0 mac */
1458 +#define AR5312_RESET_ENET1 0x00000040 /* cold reset ENET1 mac */
1459 +#define AR5312_RESET_UART0 0x00000100 /* cold reset UART0 (high speed) */
1460 +#define AR5312_RESET_WLAN1 0x00000200 /* cold reset WLAN MAC/BB */
1461 +#define AR5312_RESET_APB 0x00000400 /* cold reset APB (ar5312) */
1462 +#define AR5312_RESET_WARM_PROC 0x00001000 /* warm reset MIPS core */
1463 +#define AR5312_RESET_WARM_WLAN0_MAC 0x00002000 /* warm reset WLAN0 MAC */
1464 +#define AR5312_RESET_WARM_WLAN0_BB 0x00004000 /* warm reset WLAN0 BaseBand */
1465 +#define AR5312_RESET_NMI 0x00010000 /* send an NMI to the processor */
1466 +#define AR5312_RESET_WARM_WLAN1_MAC 0x00020000 /* warm reset WLAN1 mac */
1467 +#define AR5312_RESET_WARM_WLAN1_BB 0x00040000 /* warm reset WLAN1 baseband */
1468 +#define AR5312_RESET_LOCAL_BUS 0x00080000 /* reset local bus */
1469 +#define AR5312_RESET_WDOG 0x00100000 /* last reset was a watchdog */
1470 +
1471 +#define AR5312_RESET_WMAC0_BITS \
1472 + (AR5312_RESET_WLAN0 |\
1473 + AR5312_RESET_WARM_WLAN0_MAC |\
1474 + AR5312_RESET_WARM_WLAN0_BB)
1475 +
1476 +#define AR5312_RESET_WMAC1_BITS \
1477 + (AR5312_RESET_WLAN1 |\
1478 + AR5312_RESET_WARM_WLAN1_MAC |\
1479 + AR5312_RESET_WARM_WLAN1_BB)
1480 +
1481 +/* AR5312_CLOCKCTL1 register bit field definitions */
1482 +#define AR5312_CLOCKCTL1_PREDIVIDE_MASK 0x00000030
1483 +#define AR5312_CLOCKCTL1_PREDIVIDE_SHIFT 4
1484 +#define AR5312_CLOCKCTL1_MULTIPLIER_MASK 0x00001f00
1485 +#define AR5312_CLOCKCTL1_MULTIPLIER_SHIFT 8
1486 +#define AR5312_CLOCKCTL1_DOUBLER_MASK 0x00010000
1487 +
1488 +/* Valid for AR5312 and AR2312 */
1489 +#define AR5312_CLOCKCTL1_PREDIVIDE_MASK 0x00000030
1490 +#define AR5312_CLOCKCTL1_PREDIVIDE_SHIFT 4
1491 +#define AR5312_CLOCKCTL1_MULTIPLIER_MASK 0x00001f00
1492 +#define AR5312_CLOCKCTL1_MULTIPLIER_SHIFT 8
1493 +#define AR5312_CLOCKCTL1_DOUBLER_MASK 0x00010000
1494 +
1495 +/* Valid for AR2313 */
1496 +#define AR2313_CLOCKCTL1_PREDIVIDE_MASK 0x00003000
1497 +#define AR2313_CLOCKCTL1_PREDIVIDE_SHIFT 12
1498 +#define AR2313_CLOCKCTL1_MULTIPLIER_MASK 0x001f0000
1499 +#define AR2313_CLOCKCTL1_MULTIPLIER_SHIFT 16
1500 +#define AR2313_CLOCKCTL1_DOUBLER_MASK 0x00000000
1501 +
1502 +
1503 +/* AR5312_ENABLE register bit field definitions */
1504 +#define AR5312_ENABLE_WLAN0 0x0001
1505 +#define AR5312_ENABLE_ENET0 0x0002
1506 +#define AR5312_ENABLE_ENET1 0x0004
1507 +#define AR5312_ENABLE_UART_AND_WLAN1_PIO 0x0008 /* UART, and WLAN1 PIOs */
1508 +#define AR5312_ENABLE_WLAN1_DMA 0x0010 /* WLAN1 DMAs */
1509 +#define AR5312_ENABLE_WLAN1 \
1510 + (AR5312_ENABLE_UART_AND_WLAN1_PIO |\
1511 + AR5312_ENABLE_WLAN1_DMA)
1512 +
1513 +/* AR5312_REV register bit field definitions */
1514 +#define AR5312_REV_WMAC_MAJ 0xf000
1515 +#define AR5312_REV_WMAC_MAJ_S 12
1516 +#define AR5312_REV_WMAC_MIN 0x0f00
1517 +#define AR5312_REV_WMAC_MIN_S 8
1518 +#define AR5312_REV_MAJ 0x00f0
1519 +#define AR5312_REV_MAJ_S 4
1520 +#define AR5312_REV_MIN 0x000f
1521 +#define AR5312_REV_MIN_S 0
1522 +#define AR5312_REV_CHIP (AR5312_REV_MAJ|AR5312_REV_MIN)
1523 +
1524 +/* Major revision numbers, bits 7..4 of Revision ID register */
1525 +#define AR5312_REV_MAJ_AR5312 0x4
1526 +#define AR5312_REV_MAJ_AR2313 0x5
1527 +
1528 +/* Minor revision numbers, bits 3..0 of Revision ID register */
1529 +#define AR5312_REV_MIN_DUAL 0x0 /* Dual WLAN version */
1530 +#define AR5312_REV_MIN_SINGLE 0x1 /* Single WLAN version */
1531 +
1532 +/* AR5312_FLASHCTL register bit field definitions */
1533 +#define FLASHCTL_IDCY 0x0000000f /* Idle cycle turn around time */
1534 +#define FLASHCTL_IDCY_S 0
1535 +#define FLASHCTL_WST1 0x000003e0 /* Wait state 1 */
1536 +#define FLASHCTL_WST1_S 5
1537 +#define FLASHCTL_RBLE 0x00000400 /* Read byte lane enable */
1538 +#define FLASHCTL_WST2 0x0000f800 /* Wait state 2 */
1539 +#define FLASHCTL_WST2_S 11
1540 +#define FLASHCTL_AC 0x00070000 /* Flash address check (added) */
1541 +#define FLASHCTL_AC_S 16
1542 +#define FLASHCTL_AC_128K 0x00000000
1543 +#define FLASHCTL_AC_256K 0x00010000
1544 +#define FLASHCTL_AC_512K 0x00020000
1545 +#define FLASHCTL_AC_1M 0x00030000
1546 +#define FLASHCTL_AC_2M 0x00040000
1547 +#define FLASHCTL_AC_4M 0x00050000
1548 +#define FLASHCTL_AC_8M 0x00060000
1549 +#define FLASHCTL_AC_RES 0x00070000 /* 16MB is not supported */
1550 +#define FLASHCTL_E 0x00080000 /* Flash bank enable (added) */
1551 +#define FLASHCTL_BUSERR 0x01000000 /* Bus transfer error status flag */
1552 +#define FLASHCTL_WPERR 0x02000000 /* Write protect error status flag */
1553 +#define FLASHCTL_WP 0x04000000 /* Write protect */
1554 +#define FLASHCTL_BM 0x08000000 /* Burst mode */
1555 +#define FLASHCTL_MW 0x30000000 /* Memory width */
1556 +#define FLASHCTL_MWx8 0x00000000 /* Memory width x8 */
1557 +#define FLASHCTL_MWx16 0x10000000 /* Memory width x16 */
1558 +#define FLASHCTL_MWx32 0x20000000 /* Memory width x32 (not supported) */
1559 +#define FLASHCTL_ATNR 0x00000000 /* Access type == no retry */
1560 +#define FLASHCTL_ATR 0x80000000 /* Access type == retry every */
1561 +#define FLASHCTL_ATR4 0xc0000000 /* Access type == retry every 4 */
1562 +
1563 +/* ARM Flash Controller -- 3 flash banks with either x8 or x16 devices. */
1564 +#define AR5312_FLASHCTL0 (AR5312_FLASHCTL + 0x00)
1565 +#define AR5312_FLASHCTL1 (AR5312_FLASHCTL + 0x04)
1566 +#define AR5312_FLASHCTL2 (AR5312_FLASHCTL + 0x08)
1567 +
1568 +/* ARM SDRAM Controller -- just enough to determine memory size */
1569 +#define AR5312_MEM_CFG1 (AR5312_SDRAMCTL + 0x04)
1570 +#define MEM_CFG1_AC0 0x00000700 /* bank 0: SDRAM addr check (added) */
1571 +#define MEM_CFG1_AC0_S 8
1572 +#define MEM_CFG1_AC1 0x00007000 /* bank 1: SDRAM addr check (added) */
1573 +#define MEM_CFG1_AC1_S 12
1574 +
1575 +/* GPIO Address Map */
1576 +#define AR5312_GPIO (AR5312_APBBASE + 0x2000)
1577 +#define AR5312_GPIO_DO (AR5312_GPIO + 0x00) /* output register */
1578 +#define AR5312_GPIO_DI (AR5312_GPIO + 0x04) /* intput register */
1579 +#define AR5312_GPIO_CR (AR5312_GPIO + 0x08) /* control register */
1580 +
1581 +/* GPIO Control Register bit field definitions */
1582 +#define AR5312_GPIO_CR_M(x) (1 << (x)) /* mask for i/o */
1583 +#define AR5312_GPIO_CR_O(x) (0 << (x)) /* mask for output */
1584 +#define AR5312_GPIO_CR_I(x) (1 << (x)) /* mask for input */
1585 +#define AR5312_GPIO_CR_INT(x) (1 << ((x)+8)) /* mask for interrupt*/
1586 +#define AR5312_GPIO_CR_UART(x) (1 << ((x)+16)) /* uart multiplex */
1587 +#define AR5312_NUM_GPIO 8
1588 +
1589 +
1590 +#endif /* __ASM_MACH_AR231X_AR5312_REGS_H */
1591 +
1592 --- /dev/null
1593 +++ b/arch/mips/ar231x/ar5312.c
1594 @@ -0,0 +1,540 @@
1595 +/*
1596 + * This file is subject to the terms and conditions of the GNU General Public
1597 + * License. See the file "COPYING" in the main directory of this archive
1598 + * for more details.
1599 + *
1600 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
1601 + * Copyright (C) 2006 FON Technology, SL.
1602 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
1603 + * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
1604 + * Copyright (C) 2012 Alexandros C. Couloumbis <alex@ozo.com>
1605 + */
1606 +
1607 +/*
1608 + * Platform devices for Atheros SoCs
1609 + */
1610 +
1611 +#include <generated/autoconf.h>
1612 +#include <linux/init.h>
1613 +#include <linux/module.h>
1614 +#include <linux/types.h>
1615 +#include <linux/string.h>
1616 +#include <linux/mtd/physmap.h>
1617 +#include <linux/platform_device.h>
1618 +#include <linux/kernel.h>
1619 +#include <linux/reboot.h>
1620 +#include <linux/leds.h>
1621 +#include <linux/gpio.h>
1622 +#include <asm/bootinfo.h>
1623 +#include <asm/reboot.h>
1624 +#include <asm/time.h>
1625 +#include <linux/irq.h>
1626 +#include <linux/io.h>
1627 +
1628 +#include <ar231x_platform.h>
1629 +#include <ar5312_regs.h>
1630 +#include <ar231x.h>
1631 +#include "devices.h"
1632 +#include "ar5312.h"
1633 +
1634 +static void ar5312_misc_irq_handler(unsigned irq, struct irq_desc *desc)
1635 +{
1636 + unsigned int ar231x_misc_intrs = ar231x_read_reg(AR5312_ISR) &
1637 + ar231x_read_reg(AR5312_IMR);
1638 +
1639 + if (ar231x_misc_intrs & AR5312_ISR_TIMER) {
1640 + do_IRQ(AR5312_MISC_IRQ_TIMER);
1641 + (void)ar231x_read_reg(AR5312_TIMER);
1642 + } else if (ar231x_misc_intrs & AR5312_ISR_AHBPROC)
1643 + do_IRQ(AR5312_MISC_IRQ_AHB_PROC);
1644 + else if ((ar231x_misc_intrs & AR5312_ISR_UART0))
1645 + do_IRQ(AR5312_MISC_IRQ_UART0);
1646 + else if (ar231x_misc_intrs & AR5312_ISR_WD)
1647 + do_IRQ(AR5312_MISC_IRQ_WATCHDOG);
1648 + else
1649 + do_IRQ(AR5312_MISC_IRQ_NONE);
1650 +}
1651 +
1652 +static asmlinkage void
1653 +ar5312_irq_dispatch(void)
1654 +{
1655 + int pending = read_c0_status() & read_c0_cause();
1656 +
1657 + if (pending & CAUSEF_IP2)
1658 + do_IRQ(AR5312_IRQ_WLAN0_INTRS);
1659 + else if (pending & CAUSEF_IP3)
1660 + do_IRQ(AR5312_IRQ_ENET0_INTRS);
1661 + else if (pending & CAUSEF_IP4)
1662 + do_IRQ(AR5312_IRQ_ENET1_INTRS);
1663 + else if (pending & CAUSEF_IP5)
1664 + do_IRQ(AR5312_IRQ_WLAN1_INTRS);
1665 + else if (pending & CAUSEF_IP6)
1666 + do_IRQ(AR5312_IRQ_MISC_INTRS);
1667 + else if (pending & CAUSEF_IP7)
1668 + do_IRQ(AR231X_IRQ_CPU_CLOCK);
1669 +}
1670 +
1671 +
1672 +/* Enable the specified AR5312_MISC_IRQ interrupt */
1673 +static void
1674 +ar5312_misc_irq_unmask(struct irq_data *d)
1675 +{
1676 + unsigned int imr;
1677 +
1678 + imr = ar231x_read_reg(AR5312_IMR);
1679 + imr |= (1 << (d->irq - AR231X_MISC_IRQ_BASE - 1));
1680 + ar231x_write_reg(AR5312_IMR, imr);
1681 +}
1682 +
1683 +/* Disable the specified AR5312_MISC_IRQ interrupt */
1684 +static void
1685 +ar5312_misc_irq_mask(struct irq_data *d)
1686 +{
1687 + unsigned int imr;
1688 +
1689 + imr = ar231x_read_reg(AR5312_IMR);
1690 + imr &= ~(1 << (d->irq - AR231X_MISC_IRQ_BASE - 1));
1691 + ar231x_write_reg(AR5312_IMR, imr);
1692 + ar231x_read_reg(AR5312_IMR); /* flush write buffer */
1693 +}
1694 +
1695 +static struct irq_chip ar5312_misc_irq_chip = {
1696 + .name = "AR5312-MISC",
1697 + .irq_unmask = ar5312_misc_irq_unmask,
1698 + .irq_mask = ar5312_misc_irq_mask,
1699 +};
1700 +
1701 +
1702 +static irqreturn_t ar5312_ahb_proc_handler(int cpl, void *dev_id)
1703 +{
1704 + u32 proc1 = ar231x_read_reg(AR5312_PROC1);
1705 + u32 proc_addr = ar231x_read_reg(AR5312_PROCADDR); /* clears error */
1706 + u32 dma1 = ar231x_read_reg(AR5312_DMA1);
1707 + u32 dma_addr = ar231x_read_reg(AR5312_DMAADDR); /* clears error */
1708 +
1709 + pr_emerg("AHB interrupt: PROCADDR=0x%8.8x PROC1=0x%8.8x "
1710 + "DMAADDR=0x%8.8x DMA1=0x%8.8x\n", proc_addr, proc1, dma_addr,
1711 + dma1);
1712 +
1713 + machine_restart("AHB error"); /* Catastrophic failure */
1714 + return IRQ_HANDLED;
1715 +}
1716 +
1717 +
1718 +static struct irqaction ar5312_ahb_proc_interrupt = {
1719 + .handler = ar5312_ahb_proc_handler,
1720 + .name = "ar5312_ahb_proc_interrupt",
1721 +};
1722 +
1723 +
1724 +void __init ar5312_irq_init(void)
1725 +{
1726 + int i;
1727 +
1728 + if (!is_5312())
1729 + return;
1730 +
1731 + ar231x_irq_dispatch = ar5312_irq_dispatch;
1732 + for (i = 0; i < AR5312_MISC_IRQ_COUNT; i++) {
1733 + int irq = AR231X_MISC_IRQ_BASE + i;
1734 + irq_set_chip_and_handler(irq, &ar5312_misc_irq_chip,
1735 + handle_level_irq);
1736 + }
1737 + setup_irq(AR5312_MISC_IRQ_AHB_PROC, &ar5312_ahb_proc_interrupt);
1738 + irq_set_chained_handler(AR5312_IRQ_MISC_INTRS, ar5312_misc_irq_handler);
1739 +}
1740 +
1741 +/*
1742 + * gpiolib implementations
1743 + */
1744 +static int
1745 +ar5312_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
1746 +{
1747 + return (ar231x_read_reg(AR5312_GPIO_DI) >> gpio) & 1;
1748 +}
1749 +
1750 +static void
1751 +ar5312_gpio_set_value(struct gpio_chip *chip, unsigned gpio, int value)
1752 +{
1753 + u32 reg = ar231x_read_reg(AR5312_GPIO_DO);
1754 + reg = value ? reg | (1 << gpio) : reg & ~(1 << gpio);
1755 + ar231x_write_reg(AR5312_GPIO_DO, reg);
1756 +}
1757 +
1758 +static int
1759 +ar5312_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
1760 +{
1761 + ar231x_mask_reg(AR5312_GPIO_CR, 0, 1 << gpio);
1762 + return 0;
1763 +}
1764 +
1765 +static int
1766 +ar5312_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, int value)
1767 +{
1768 + ar231x_mask_reg(AR5312_GPIO_CR, 1 << gpio, 0);
1769 + ar5312_gpio_set_value(chip, gpio, value);
1770 + return 0;
1771 +}
1772 +
1773 +static struct gpio_chip ar5312_gpio_chip = {
1774 + .label = "ar5312-gpio",
1775 + .direction_input = ar5312_gpio_direction_input,
1776 + .direction_output = ar5312_gpio_direction_output,
1777 + .set = ar5312_gpio_set_value,
1778 + .get = ar5312_gpio_get_value,
1779 + .base = 0,
1780 + .ngpio = AR5312_NUM_GPIO, /* 8 */
1781 +};
1782 +
1783 +/* end of gpiolib */
1784 +
1785 +static void ar5312_device_reset_set(u32 mask)
1786 +{
1787 + u32 val;
1788 +
1789 + val = ar231x_read_reg(AR5312_RESET);
1790 + ar231x_write_reg(AR5312_RESET, val | mask);
1791 +}
1792 +
1793 +static void ar5312_device_reset_clear(u32 mask)
1794 +{
1795 + u32 val;
1796 +
1797 + val = ar231x_read_reg(AR5312_RESET);
1798 + ar231x_write_reg(AR5312_RESET, val & ~mask);
1799 +}
1800 +
1801 +static struct physmap_flash_data ar5312_flash_data = {
1802 + .width = 2,
1803 +};
1804 +
1805 +static struct resource ar5312_flash_resource = {
1806 + .start = AR5312_FLASH,
1807 + .end = AR5312_FLASH + 0x800000 - 1,
1808 + .flags = IORESOURCE_MEM,
1809 +};
1810 +
1811 +static struct ar231x_eth ar5312_eth0_data = {
1812 + .reset_set = ar5312_device_reset_set,
1813 + .reset_clear = ar5312_device_reset_clear,
1814 + .reset_mac = AR5312_RESET_ENET0,
1815 + .reset_phy = AR5312_RESET_EPHY0,
1816 + .config = &ar231x_board,
1817 +};
1818 +
1819 +static struct ar231x_eth ar5312_eth1_data = {
1820 + .reset_set = ar5312_device_reset_set,
1821 + .reset_clear = ar5312_device_reset_clear,
1822 + .reset_mac = AR5312_RESET_ENET1,
1823 + .reset_phy = AR5312_RESET_EPHY1,
1824 + .config = &ar231x_board,
1825 +};
1826 +
1827 +static struct platform_device ar5312_physmap_flash = {
1828 + .name = "physmap-flash",
1829 + .id = 0,
1830 + .dev.platform_data = &ar5312_flash_data,
1831 + .resource = &ar5312_flash_resource,
1832 + .num_resources = 1,
1833 +};
1834 +
1835 +#ifdef CONFIG_LEDS_GPIO
1836 +static struct gpio_led ar5312_leds[] = {
1837 + { .name = "wlan", .gpio = 0, .active_low = 1, },
1838 +};
1839 +
1840 +static const struct gpio_led_platform_data ar5312_led_data = {
1841 + .num_leds = ARRAY_SIZE(ar5312_leds),
1842 + .leds = (void *)ar5312_leds,
1843 +};
1844 +
1845 +static struct platform_device ar5312_gpio_leds = {
1846 + .name = "leds-gpio",
1847 + .id = -1,
1848 + .dev.platform_data = (void *)&ar5312_led_data,
1849 +};
1850 +#endif
1851 +
1852 +/*
1853 + * NB: This mapping size is larger than the actual flash size,
1854 + * but this shouldn't be a problem here, because the flash
1855 + * will simply be mapped multiple times.
1856 + */
1857 +static char __init *ar5312_flash_limit(void)
1858 +{
1859 + u32 ctl;
1860 + /*
1861 + * Configure flash bank 0.
1862 + * Assume 8M window size. Flash will be aliased if it's smaller
1863 + */
1864 + ctl = FLASHCTL_E |
1865 + FLASHCTL_AC_8M |
1866 + FLASHCTL_RBLE |
1867 + (0x01 << FLASHCTL_IDCY_S) |
1868 + (0x07 << FLASHCTL_WST1_S) |
1869 + (0x07 << FLASHCTL_WST2_S) |
1870 + (ar231x_read_reg(AR5312_FLASHCTL0) & FLASHCTL_MW);
1871 +
1872 + ar231x_write_reg(AR5312_FLASHCTL0, ctl);
1873 +
1874 + /* Disable other flash banks */
1875 + ar231x_write_reg(AR5312_FLASHCTL1,
1876 + ar231x_read_reg(AR5312_FLASHCTL1) &
1877 + ~(FLASHCTL_E | FLASHCTL_AC));
1878 +
1879 + ar231x_write_reg(AR5312_FLASHCTL2,
1880 + ar231x_read_reg(AR5312_FLASHCTL2) &
1881 + ~(FLASHCTL_E | FLASHCTL_AC));
1882 +
1883 + return (char *)KSEG1ADDR(AR5312_FLASH + 0x800000);
1884 +}
1885 +
1886 +int __init ar5312_init_devices(void)
1887 +{
1888 + struct ar231x_boarddata *config;
1889 + u32 fctl = 0;
1890 + u8 *c;
1891 +
1892 + if (!is_5312())
1893 + return 0;
1894 +
1895 + /* Locate board/radio config data */
1896 + ar231x_find_config(ar5312_flash_limit());
1897 + config = ar231x_board.config;
1898 +
1899 + /* AR2313 has CPU minor rev. 10 */
1900 + if ((current_cpu_data.processor_id & 0xff) == 0x0a)
1901 + ar231x_devtype = DEV_TYPE_AR2313;
1902 +
1903 + /* AR2312 shares the same Silicon ID as AR5312 */
1904 + else if (config->flags & BD_ISCASPER)
1905 + ar231x_devtype = DEV_TYPE_AR2312;
1906 +
1907 + /* Everything else is probably AR5312 or compatible */
1908 + else
1909 + ar231x_devtype = DEV_TYPE_AR5312;
1910 +
1911 + /* fixup flash width */
1912 + fctl = ar231x_read_reg(AR5312_FLASHCTL) & FLASHCTL_MW;
1913 + switch (fctl) {
1914 + case FLASHCTL_MWx16:
1915 + ar5312_flash_data.width = 2;
1916 + break;
1917 + case FLASHCTL_MWx8:
1918 + default:
1919 + ar5312_flash_data.width = 1;
1920 + break;
1921 + }
1922 +
1923 + platform_device_register(&ar5312_physmap_flash);
1924 +
1925 +#ifdef CONFIG_LEDS_GPIO
1926 + ar5312_leds[0].gpio = config->sys_led_gpio;
1927 + platform_device_register(&ar5312_gpio_leds);
1928 +#endif
1929 +
1930 + /* Fix up MAC addresses if necessary */
1931 + if (!memcmp(config->enet0_mac, "\xff\xff\xff\xff\xff\xff", 6))
1932 + memcpy(config->enet0_mac, config->enet1_mac, 6);
1933 +
1934 + /* If ENET0 and ENET1 have the same mac address,
1935 + * increment the one from ENET1 */
1936 + if (memcmp(config->enet0_mac, config->enet1_mac, 6) == 0) {
1937 + c = config->enet1_mac + 5;
1938 + while ((c >= config->enet1_mac) && !(++(*c)))
1939 + c--;
1940 + }
1941 +
1942 + switch (ar231x_devtype) {
1943 + case DEV_TYPE_AR5312:
1944 + ar5312_eth0_data.macaddr = config->enet0_mac;
1945 + ar231x_add_ethernet(0, AR5312_ENET0, "eth0_mii",
1946 + AR5312_ENET0_MII, AR5312_IRQ_ENET0_INTRS,
1947 + &ar5312_eth0_data);
1948 +
1949 + ar5312_eth1_data.macaddr = config->enet1_mac;
1950 + ar231x_add_ethernet(1, AR5312_ENET1, "eth1_mii",
1951 + AR5312_ENET1_MII, AR5312_IRQ_ENET1_INTRS,
1952 + &ar5312_eth1_data);
1953 +
1954 + if (!ar231x_board.radio)
1955 + return 0;
1956 +
1957 + if (!(config->flags & BD_WLAN0))
1958 + break;
1959 +
1960 + ar231x_add_wmac(0, AR5312_WLAN0, AR5312_IRQ_WLAN0_INTRS);
1961 + break;
1962 + /*
1963 + * AR2312/3 ethernet uses the PHY of ENET0, but the MAC
1964 + * of ENET1. Atheros calls it 'twisted' for a reason :)
1965 + */
1966 + case DEV_TYPE_AR2312:
1967 + case DEV_TYPE_AR2313:
1968 + ar5312_eth1_data.reset_phy = ar5312_eth0_data.reset_phy;
1969 + ar5312_eth1_data.macaddr = config->enet0_mac;
1970 + ar231x_add_ethernet(1, AR5312_ENET1, "eth0_mii",
1971 + AR5312_ENET0_MII, AR5312_IRQ_ENET1_INTRS,
1972 + &ar5312_eth1_data);
1973 +
1974 + if (!ar231x_board.radio)
1975 + return 0;
1976 + break;
1977 + default:
1978 + break;
1979 + }
1980 +
1981 + if (config->flags & BD_WLAN1)
1982 + ar231x_add_wmac(1, AR5312_WLAN1, AR5312_IRQ_WLAN1_INTRS);
1983 +
1984 + return 0;
1985 +}
1986 +
1987 +
1988 +static void ar5312_restart(char *command)
1989 +{
1990 + /* reset the system */
1991 + local_irq_disable();
1992 + while (1)
1993 + ar231x_write_reg(AR5312_RESET, AR5312_RESET_SYSTEM);
1994 +}
1995 +
1996 +
1997 +/*
1998 + * This table is indexed by bits 5..4 of the CLOCKCTL1 register
1999 + * to determine the predevisor value.
2000 + */
2001 +static int clockctl1_predivide_table[4] __initdata = { 1, 2, 4, 5 };
2002 +
2003 +
2004 +static int __init
2005 +ar5312_cpu_frequency(void)
2006 +{
2007 + unsigned int scratch;
2008 + unsigned int predivide_mask, predivide_shift;
2009 + unsigned int multiplier_mask, multiplier_shift;
2010 + unsigned int clock_ctl1, predivide_select, predivisor, multiplier;
2011 + unsigned int doubler_mask;
2012 + u16 devid;
2013 +
2014 + /* Trust the bootrom's idea of cpu frequency. */
2015 + scratch = ar231x_read_reg(AR5312_SCRATCH);
2016 + if (scratch)
2017 + return scratch;
2018 +
2019 + devid = ar231x_read_reg(AR5312_REV);
2020 + devid &= AR5312_REV_MAJ;
2021 + devid >>= AR5312_REV_MAJ_S;
2022 + if (devid == AR5312_REV_MAJ_AR2313) {
2023 + predivide_mask = AR2313_CLOCKCTL1_PREDIVIDE_MASK;
2024 + predivide_shift = AR2313_CLOCKCTL1_PREDIVIDE_SHIFT;
2025 + multiplier_mask = AR2313_CLOCKCTL1_MULTIPLIER_MASK;
2026 + multiplier_shift = AR2313_CLOCKCTL1_MULTIPLIER_SHIFT;
2027 + doubler_mask = AR2313_CLOCKCTL1_DOUBLER_MASK;
2028 + } else { /* AR5312 and AR2312 */
2029 + predivide_mask = AR5312_CLOCKCTL1_PREDIVIDE_MASK;
2030 + predivide_shift = AR5312_CLOCKCTL1_PREDIVIDE_SHIFT;
2031 + multiplier_mask = AR5312_CLOCKCTL1_MULTIPLIER_MASK;
2032 + multiplier_shift = AR5312_CLOCKCTL1_MULTIPLIER_SHIFT;
2033 + doubler_mask = AR5312_CLOCKCTL1_DOUBLER_MASK;
2034 + }
2035 +
2036 + /*
2037 + * Clocking is derived from a fixed 40MHz input clock.
2038 + *
2039 + * cpu_freq = input_clock * MULT (where MULT is PLL multiplier)
2040 + * sys_freq = cpu_freq / 4 (used for APB clock, serial,
2041 + * flash, Timer, Watchdog Timer)
2042 + *
2043 + * cnt_freq = cpu_freq / 2 (use for CPU count/compare)
2044 + *
2045 + * So, for example, with a PLL multiplier of 5, we have
2046 + *
2047 + * cpu_freq = 200MHz
2048 + * sys_freq = 50MHz
2049 + * cnt_freq = 100MHz
2050 + *
2051 + * We compute the CPU frequency, based on PLL settings.
2052 + */
2053 +
2054 + clock_ctl1 = ar231x_read_reg(AR5312_CLOCKCTL1);
2055 + predivide_select = (clock_ctl1 & predivide_mask) >> predivide_shift;
2056 + predivisor = clockctl1_predivide_table[predivide_select];
2057 + multiplier = (clock_ctl1 & multiplier_mask) >> multiplier_shift;
2058 +
2059 + if (clock_ctl1 & doubler_mask)
2060 + multiplier = multiplier << 1;
2061 +
2062 + return (40000000 / predivisor) * multiplier;
2063 +}
2064 +
2065 +static inline int
2066 +ar5312_sys_frequency(void)
2067 +{
2068 + return ar5312_cpu_frequency() / 4;
2069 +}
2070 +
2071 +void __init
2072 +ar5312_time_init(void)
2073 +{
2074 + if (!is_5312())
2075 + return;
2076 +
2077 + mips_hpt_frequency = ar5312_cpu_frequency() / 2;
2078 +}
2079 +
2080 +static int __init
2081 +ar5312_gpio_init(void)
2082 +{
2083 + int ret;
2084 + ret = gpiochip_add(&ar5312_gpio_chip);
2085 + if (ret) {
2086 + pr_err("%s: failed to add gpiochip\n", ar5312_gpio_chip.label);
2087 + return ret;
2088 + }
2089 + pr_info("%s: registered %d GPIOs\n", ar5312_gpio_chip.label,
2090 + ar5312_gpio_chip.ngpio);
2091 + return ret;
2092 +}
2093 +
2094 +void __init
2095 +ar5312_prom_init(void)
2096 +{
2097 + u32 memsize, memcfg, bank0AC, bank1AC;
2098 + u32 devid;
2099 +
2100 + if (!is_5312())
2101 + return;
2102 +
2103 + /* Detect memory size */
2104 + memcfg = ar231x_read_reg(AR5312_MEM_CFG1);
2105 + bank0AC = (memcfg & MEM_CFG1_AC0) >> MEM_CFG1_AC0_S;
2106 + bank1AC = (memcfg & MEM_CFG1_AC1) >> MEM_CFG1_AC1_S;
2107 + memsize = (bank0AC ? (1 << (bank0AC+1)) : 0) +
2108 + (bank1AC ? (1 << (bank1AC+1)) : 0);
2109 + memsize <<= 20;
2110 + add_memory_region(0, memsize, BOOT_MEM_RAM);
2111 +
2112 + devid = ar231x_read_reg(AR5312_REV);
2113 + devid >>= AR5312_REV_WMAC_MIN_S;
2114 + devid &= AR5312_REV_CHIP;
2115 + ar231x_board.devid = (u16) devid;
2116 + ar5312_gpio_init();
2117 +}
2118 +
2119 +void __init
2120 +ar5312_plat_setup(void)
2121 +{
2122 + if (!is_5312())
2123 + return;
2124 +
2125 + /* Clear any lingering AHB errors */
2126 + ar231x_read_reg(AR5312_PROCADDR);
2127 + ar231x_read_reg(AR5312_DMAADDR);
2128 + ar231x_write_reg(AR5312_WD_CTRL, AR5312_WD_CTRL_IGNORE_EXPIRATION);
2129 +
2130 + _machine_restart = ar5312_restart;
2131 + ar231x_serial_setup(AR5312_UART0, AR5312_MISC_IRQ_UART0,
2132 + ar5312_sys_frequency());
2133 +}
2134 +
2135 --- /dev/null
2136 +++ b/arch/mips/ar231x/ar2315.c
2137 @@ -0,0 +1,556 @@
2138 +/*
2139 + * This file is subject to the terms and conditions of the GNU General Public
2140 + * License. See the file "COPYING" in the main directory of this archive
2141 + * for more details.
2142 + *
2143 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
2144 + * Copyright (C) 2006 FON Technology, SL.
2145 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
2146 + * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
2147 + * Copyright (C) 2012 Alexandros C. Couloumbis <alex@ozo.com>
2148 + */
2149 +
2150 +/*
2151 + * Platform devices for Atheros SoCs
2152 + */
2153 +
2154 +#include <generated/autoconf.h>
2155 +#include <linux/init.h>
2156 +#include <linux/module.h>
2157 +#include <linux/types.h>
2158 +#include <linux/string.h>
2159 +#include <linux/platform_device.h>
2160 +#include <linux/kernel.h>
2161 +#include <linux/reboot.h>
2162 +#include <linux/delay.h>
2163 +#include <linux/leds.h>
2164 +#include <linux/gpio.h>
2165 +#include <asm/bootinfo.h>
2166 +#include <asm/reboot.h>
2167 +#include <asm/time.h>
2168 +#include <linux/irq.h>
2169 +#include <linux/io.h>
2170 +
2171 +#include <ar231x_platform.h>
2172 +#include <ar2315_regs.h>
2173 +#include <ar231x.h>
2174 +#include "devices.h"
2175 +#include "ar2315.h"
2176 +
2177 +static u32 gpiointmask, gpiointval;
2178 +
2179 +static void ar2315_gpio_irq_handler(unsigned irq, struct irq_desc *desc)
2180 +{
2181 + u32 pend;
2182 + int bit = -1;
2183 +
2184 + /* only do one gpio interrupt at a time */
2185 + pend = (ar231x_read_reg(AR2315_GPIO_DI) ^ gpiointval) & gpiointmask;
2186 +
2187 + if (pend) {
2188 + bit = fls(pend) - 1;
2189 + pend &= ~(1 << bit);
2190 + gpiointval ^= (1 << bit);
2191 + }
2192 +
2193 + if (!pend)
2194 + ar231x_write_reg(AR2315_ISR, AR2315_ISR_GPIO);
2195 +
2196 + /* Enable interrupt with edge detection */
2197 + if ((ar231x_read_reg(AR2315_GPIO_DIR) & AR2315_GPIO_DIR_M(bit)) !=
2198 + AR2315_GPIO_DIR_I(bit))
2199 + return;
2200 +
2201 + if (bit >= 0)
2202 + do_IRQ(AR231X_GPIO_IRQ_BASE + bit);
2203 +}
2204 +
2205 +static void ar2315_misc_irq_handler(unsigned irq, struct irq_desc *desc)
2206 +{
2207 + unsigned int misc_intr = ar231x_read_reg(AR2315_ISR) &
2208 + ar231x_read_reg(AR2315_IMR);
2209 +
2210 + if (misc_intr & AR2315_ISR_SPI)
2211 + do_IRQ(AR2315_MISC_IRQ_SPI);
2212 + else if (misc_intr & AR2315_ISR_TIMER)
2213 + do_IRQ(AR2315_MISC_IRQ_TIMER);
2214 + else if (misc_intr & AR2315_ISR_AHB)
2215 + do_IRQ(AR2315_MISC_IRQ_AHB);
2216 + else if (misc_intr & AR2315_ISR_GPIO)
2217 + do_IRQ(AR2315_MISC_IRQ_GPIO);
2218 + else if (misc_intr & AR2315_ISR_UART0)
2219 + do_IRQ(AR2315_MISC_IRQ_UART0);
2220 + else if (misc_intr & AR2315_ISR_WD) {
2221 + ar231x_write_reg(AR2315_ISR, AR2315_ISR_WD);
2222 + do_IRQ(AR2315_MISC_IRQ_WATCHDOG);
2223 + } else
2224 + do_IRQ(AR2315_MISC_IRQ_NONE);
2225 +}
2226 +
2227 +/*
2228 + * Called when an interrupt is received, this function
2229 + * determines exactly which interrupt it was, and it
2230 + * invokes the appropriate handler.
2231 + *
2232 + * Implicitly, we also define interrupt priority by
2233 + * choosing which to dispatch first.
2234 + */
2235 +static asmlinkage void
2236 +ar2315_irq_dispatch(void)
2237 +{
2238 + int pending = read_c0_status() & read_c0_cause();
2239 +
2240 + if (pending & CAUSEF_IP3)
2241 + do_IRQ(AR2315_IRQ_WLAN0_INTRS);
2242 + else if (pending & CAUSEF_IP4)
2243 + do_IRQ(AR2315_IRQ_ENET0_INTRS);
2244 + else if (pending & CAUSEF_IP2)
2245 + do_IRQ(AR2315_IRQ_MISC_INTRS);
2246 + else if (pending & CAUSEF_IP7)
2247 + do_IRQ(AR231X_IRQ_CPU_CLOCK);
2248 +}
2249 +
2250 +static void ar2315_set_gpiointmask(int gpio, int level)
2251 +{
2252 + u32 reg;
2253 +
2254 + reg = ar231x_read_reg(AR2315_GPIO_INT);
2255 + reg &= ~(AR2315_GPIO_INT_M | AR2315_GPIO_INT_LVL_M);
2256 + reg |= gpio | AR2315_GPIO_INT_LVL(level);
2257 + ar231x_write_reg(AR2315_GPIO_INT, reg);
2258 +}
2259 +
2260 +static void ar2315_gpio_irq_unmask(struct irq_data *d)
2261 +{
2262 + unsigned int gpio = d->irq - AR231X_GPIO_IRQ_BASE;
2263 +
2264 + /* Enable interrupt with edge detection */
2265 + if ((ar231x_read_reg(AR2315_GPIO_DIR) & AR2315_GPIO_DIR_M(gpio)) !=
2266 + AR2315_GPIO_DIR_I(gpio))
2267 + return;
2268 +
2269 + gpiointmask |= (1 << gpio);
2270 + ar2315_set_gpiointmask(gpio, 3);
2271 +}
2272 +
2273 +static void ar2315_gpio_irq_mask(struct irq_data *d)
2274 +{
2275 + unsigned int gpio = d->irq - AR231X_GPIO_IRQ_BASE;
2276 +
2277 + /* Disable interrupt */
2278 + gpiointmask &= ~(1 << gpio);
2279 + ar2315_set_gpiointmask(gpio, 0);
2280 +}
2281 +
2282 +static struct irq_chip ar2315_gpio_irq_chip = {
2283 + .name = "AR2315-GPIO",
2284 + .irq_unmask = ar2315_gpio_irq_unmask,
2285 + .irq_mask = ar2315_gpio_irq_mask,
2286 +};
2287 +
2288 +static void
2289 +ar2315_misc_irq_unmask(struct irq_data *d)
2290 +{
2291 + unsigned int imr;
2292 +
2293 + imr = ar231x_read_reg(AR2315_IMR);
2294 + imr |= 1 << (d->irq - AR231X_MISC_IRQ_BASE - 1);
2295 + ar231x_write_reg(AR2315_IMR, imr);
2296 +}
2297 +
2298 +static void
2299 +ar2315_misc_irq_mask(struct irq_data *d)
2300 +{
2301 + unsigned int imr;
2302 +
2303 + imr = ar231x_read_reg(AR2315_IMR);
2304 + imr &= ~(1 << (d->irq - AR231X_MISC_IRQ_BASE - 1));
2305 + ar231x_write_reg(AR2315_IMR, imr);
2306 +}
2307 +
2308 +static struct irq_chip ar2315_misc_irq_chip = {
2309 + .name = "AR2315-MISC",
2310 + .irq_unmask = ar2315_misc_irq_unmask,
2311 + .irq_mask = ar2315_misc_irq_mask,
2312 +};
2313 +
2314 +static irqreturn_t ar2315_ahb_proc_handler(int cpl, void *dev_id)
2315 +{
2316 + ar231x_write_reg(AR2315_AHB_ERR0, AHB_ERROR_DET);
2317 + ar231x_read_reg(AR2315_AHB_ERR1);
2318 +
2319 + pr_emerg("AHB fatal error\n");
2320 + machine_restart("AHB error"); /* Catastrophic failure */
2321 +
2322 + return IRQ_HANDLED;
2323 +}
2324 +
2325 +static struct irqaction ar2315_ahb_proc_interrupt = {
2326 + .handler = ar2315_ahb_proc_handler,
2327 + .name = "ar2315_ahb_proc_interrupt",
2328 +};
2329 +
2330 +void
2331 +ar2315_irq_init(void)
2332 +{
2333 + int i;
2334 +
2335 + if (!is_2315())
2336 + return;
2337 +
2338 + ar231x_irq_dispatch = ar2315_irq_dispatch;
2339 + gpiointval = ar231x_read_reg(AR2315_GPIO_DI);
2340 + for (i = 0; i < AR2315_MISC_IRQ_COUNT; i++) {
2341 + int irq = AR231X_MISC_IRQ_BASE + i;
2342 + irq_set_chip_and_handler(irq, &ar2315_misc_irq_chip,
2343 + handle_level_irq);
2344 + }
2345 + for (i = 0; i < AR2315_NUM_GPIO; i++) {
2346 + int irq = AR231X_GPIO_IRQ_BASE + i;
2347 + irq_set_chip_and_handler(irq, &ar2315_gpio_irq_chip,
2348 + handle_level_irq);
2349 + }
2350 + irq_set_chained_handler(AR2315_MISC_IRQ_GPIO, ar2315_gpio_irq_handler);
2351 + setup_irq(AR2315_MISC_IRQ_AHB, &ar2315_ahb_proc_interrupt);
2352 + irq_set_chained_handler(AR2315_IRQ_MISC_INTRS, ar2315_misc_irq_handler);
2353 +}
2354 +
2355 +/*
2356 + * gpiolib implementation
2357 + */
2358 +static int
2359 +ar2315_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
2360 +{
2361 + return (ar231x_read_reg(AR2315_GPIO_DI) >> gpio) & 1;
2362 +}
2363 +
2364 +static void
2365 +ar2315_gpio_set_value(struct gpio_chip *chip, unsigned gpio, int value)
2366 +{
2367 + u32 reg = ar231x_read_reg(AR2315_GPIO_DO);
2368 + reg = value ? reg | (1 << gpio) : reg & ~(1 << gpio);
2369 + ar231x_write_reg(AR2315_GPIO_DO, reg);
2370 +}
2371 +
2372 +static int
2373 +ar2315_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
2374 +{
2375 + ar231x_mask_reg(AR2315_GPIO_DIR, 1 << gpio, 0);
2376 + return 0;
2377 +}
2378 +
2379 +static int
2380 +ar2315_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, int value)
2381 +{
2382 + ar231x_mask_reg(AR2315_GPIO_DIR, 0, 1 << gpio);
2383 + ar2315_gpio_set_value(chip, gpio, value);
2384 + return 0;
2385 +}
2386 +
2387 +static struct gpio_chip ar2315_gpio_chip = {
2388 + .label = "ar2315-gpio",
2389 + .direction_input = ar2315_gpio_direction_input,
2390 + .direction_output = ar2315_gpio_direction_output,
2391 + .set = ar2315_gpio_set_value,
2392 + .get = ar2315_gpio_get_value,
2393 + .base = 0,
2394 + .ngpio = AR2315_NUM_GPIO, /* 22 */
2395 +};
2396 +
2397 +/* end of gpiolib */
2398 +
2399 +static void ar2315_device_reset_set(u32 mask)
2400 +{
2401 + u32 val;
2402 +
2403 + val = ar231x_read_reg(AR2315_RESET);
2404 + ar231x_write_reg(AR2315_RESET, val | mask);
2405 +}
2406 +
2407 +static void ar2315_device_reset_clear(u32 mask)
2408 +{
2409 + u32 val;
2410 +
2411 + val = ar231x_read_reg(AR2315_RESET);
2412 + ar231x_write_reg(AR2315_RESET, val & ~mask);
2413 +}
2414 +
2415 +static struct ar231x_eth ar2315_eth_data = {
2416 + .reset_set = ar2315_device_reset_set,
2417 + .reset_clear = ar2315_device_reset_clear,
2418 + .reset_mac = AR2315_RESET_ENET0,
2419 + .reset_phy = AR2315_RESET_EPHY0,
2420 + .config = &ar231x_board,
2421 +};
2422 +
2423 +static struct resource ar2315_spiflash_res[] = {
2424 + {
2425 + .name = "spiflash_read",
2426 + .flags = IORESOURCE_MEM,
2427 + .start = AR2315_SPI_READ,
2428 + .end = AR2315_SPI_READ + 0x1000000 - 1,
2429 + },
2430 + {
2431 + .name = "spiflash_mmr",
2432 + .flags = IORESOURCE_MEM,
2433 + .start = AR2315_SPI_MMR,
2434 + .end = AR2315_SPI_MMR + 12 - 1,
2435 + },
2436 +};
2437 +
2438 +static struct platform_device ar2315_spiflash = {
2439 + .id = 0,
2440 + .name = "ar2315-spiflash",
2441 + .resource = ar2315_spiflash_res,
2442 + .num_resources = ARRAY_SIZE(ar2315_spiflash_res)
2443 +};
2444 +
2445 +static struct resource ar2315_wdt_res[] = {
2446 + {
2447 + .flags = IORESOURCE_MEM,
2448 + .start = AR2315_WD,
2449 + .end = AR2315_WD + 8 - 1,
2450 + },
2451 + {
2452 + .flags = IORESOURCE_IRQ,
2453 + .start = AR2315_MISC_IRQ_WATCHDOG,
2454 + .end = AR2315_MISC_IRQ_WATCHDOG,
2455 + }
2456 +};
2457 +
2458 +static struct platform_device ar2315_wdt = {
2459 + .id = 0,
2460 + .name = "ar2315-wdt",
2461 + .resource = ar2315_wdt_res,
2462 + .num_resources = ARRAY_SIZE(ar2315_wdt_res)
2463 +};
2464 +
2465 +/*
2466 + * NB: We use mapping size that is larger than the actual flash size,
2467 + * but this shouldn't be a problem here, because the flash will simply
2468 + * be mapped multiple times.
2469 + */
2470 +static u8 __init *ar2315_flash_limit(void)
2471 +{
2472 + return (u8 *)KSEG1ADDR(ar2315_spiflash_res[0].end + 1);
2473 +}
2474 +
2475 +#ifdef CONFIG_LEDS_GPIO
2476 +static struct gpio_led ar2315_leds[6];
2477 +static struct gpio_led_platform_data ar2315_led_data = {
2478 + .leds = (void *)ar2315_leds,
2479 +};
2480 +
2481 +static struct platform_device ar2315_gpio_leds = {
2482 + .name = "leds-gpio",
2483 + .id = -1,
2484 + .dev = {
2485 + .platform_data = (void *)&ar2315_led_data,
2486 + }
2487 +};
2488 +
2489 +static void __init
2490 +ar2315_init_gpio_leds(void)
2491 +{
2492 + static char led_names[6][6];
2493 + int i, led = 0;
2494 +
2495 + ar2315_led_data.num_leds = 0;
2496 + for (i = 1; i < 8; i++) {
2497 + if ((i == AR2315_RESET_GPIO) ||
2498 + (i == ar231x_board.config->reset_config_gpio))
2499 + continue;
2500 +
2501 + if (i == ar231x_board.config->sys_led_gpio)
2502 + strcpy(led_names[led], "wlan");
2503 + else
2504 + sprintf(led_names[led], "gpio%d", i);
2505 +
2506 + ar2315_leds[led].name = led_names[led];
2507 + ar2315_leds[led].gpio = i;
2508 + ar2315_leds[led].active_low = 0;
2509 + led++;
2510 + }
2511 + ar2315_led_data.num_leds = led;
2512 + platform_device_register(&ar2315_gpio_leds);
2513 +}
2514 +#else
2515 +static inline void ar2315_init_gpio_leds(void)
2516 +{
2517 +}
2518 +#endif
2519 +
2520 +int __init
2521 +ar2315_init_devices(void)
2522 +{
2523 + if (!is_2315())
2524 + return 0;
2525 +
2526 + /* Find board configuration */
2527 + ar231x_find_config(ar2315_flash_limit());
2528 + ar2315_eth_data.macaddr = ar231x_board.config->enet0_mac;
2529 +
2530 + ar2315_init_gpio_leds();
2531 + platform_device_register(&ar2315_wdt);
2532 + platform_device_register(&ar2315_spiflash);
2533 + ar231x_add_ethernet(0, AR2315_ENET0, "eth0_mii", AR2315_ENET0_MII,
2534 + AR2315_IRQ_ENET0_INTRS, &ar2315_eth_data);
2535 + ar231x_add_wmac(0, AR2315_WLAN0, AR2315_IRQ_WLAN0_INTRS);
2536 +
2537 + return 0;
2538 +}
2539 +
2540 +static void
2541 +ar2315_restart(char *command)
2542 +{
2543 + void (*mips_reset_vec)(void) = (void *)0xbfc00000;
2544 +
2545 + local_irq_disable();
2546 +
2547 + /* try reset the system via reset control */
2548 + ar231x_write_reg(AR2315_COLD_RESET, AR2317_RESET_SYSTEM);
2549 +
2550 + /* Cold reset does not work on the AR2315/6, use the GPIO reset bits
2551 + * a workaround. Give it some time to attempt a gpio based hardware
2552 + * reset (atheros reference design workaround) */
2553 + gpio_request_one(AR2315_RESET_GPIO, GPIOF_OUT_INIT_LOW, "Reset");
2554 + mdelay(100);
2555 +
2556 + /* Some boards (e.g. Senao EOC-2610) don't implement the reset logic
2557 + * workaround. Attempt to jump to the mips reset location -
2558 + * the boot loader itself might be able to recover the system */
2559 + mips_reset_vec();
2560 +}
2561 +
2562 +
2563 +/*
2564 + * This table is indexed by bits 5..4 of the CLOCKCTL1 register
2565 + * to determine the predevisor value.
2566 + */
2567 +static int clockctl1_predivide_table[4] __initdata = { 1, 2, 4, 5 };
2568 +static int pllc_divide_table[5] __initdata = { 2, 3, 4, 6, 3 };
2569 +
2570 +static unsigned int __init
2571 +ar2315_sys_clk(unsigned int clock_ctl)
2572 +{
2573 + unsigned int pllc_ctrl, cpu_div;
2574 + unsigned int pllc_out, refdiv, fdiv, divby2;
2575 + unsigned int clk_div;
2576 +
2577 + pllc_ctrl = ar231x_read_reg(AR2315_PLLC_CTL);
2578 + refdiv = (pllc_ctrl & PLLC_REF_DIV_M) >> PLLC_REF_DIV_S;
2579 + refdiv = clockctl1_predivide_table[refdiv];
2580 + fdiv = (pllc_ctrl & PLLC_FDBACK_DIV_M) >> PLLC_FDBACK_DIV_S;
2581 + divby2 = (pllc_ctrl & PLLC_ADD_FDBACK_DIV_M) >> PLLC_ADD_FDBACK_DIV_S;
2582 + divby2 += 1;
2583 + pllc_out = (40000000/refdiv)*(2*divby2)*fdiv;
2584 +
2585 + /* clkm input selected */
2586 + switch (clock_ctl & CPUCLK_CLK_SEL_M) {
2587 + case 0:
2588 + case 1:
2589 + clk_div = pllc_divide_table[(pllc_ctrl & PLLC_CLKM_DIV_M) >>
2590 + PLLC_CLKM_DIV_S];
2591 + break;
2592 + case 2:
2593 + clk_div = pllc_divide_table[(pllc_ctrl & PLLC_CLKC_DIV_M) >>
2594 + PLLC_CLKC_DIV_S];
2595 + break;
2596 + default:
2597 + pllc_out = 40000000;
2598 + clk_div = 1;
2599 + break;
2600 + }
2601 +
2602 + cpu_div = (clock_ctl & CPUCLK_CLK_DIV_M) >> CPUCLK_CLK_DIV_S;
2603 + cpu_div = cpu_div * 2 ?: 1;
2604 +
2605 + return pllc_out / (clk_div * cpu_div);
2606 +}
2607 +
2608 +static inline unsigned int
2609 +ar2315_cpu_frequency(void)
2610 +{
2611 + return ar2315_sys_clk(ar231x_read_reg(AR2315_CPUCLK));
2612 +}
2613 +
2614 +static inline unsigned int
2615 +ar2315_apb_frequency(void)
2616 +{
2617 + return ar2315_sys_clk(ar231x_read_reg(AR2315_AMBACLK));
2618 +}
2619 +
2620 +void __init
2621 +ar2315_time_init(void)
2622 +{
2623 + if (!is_2315())
2624 + return;
2625 +
2626 + mips_hpt_frequency = ar2315_cpu_frequency() / 2;
2627 +}
2628 +
2629 +static int __init
2630 +ar2315_gpio_init(void)
2631 +{
2632 + int ret;
2633 + ret = gpiochip_add(&ar2315_gpio_chip);
2634 + if (ret) {
2635 + pr_err("%s: failed to add gpiochip\n", ar2315_gpio_chip.label);
2636 + return ret;
2637 + }
2638 + pr_info("%s: registered %d GPIOs\n", ar2315_gpio_chip.label,
2639 + ar2315_gpio_chip.ngpio);
2640 + return ret;
2641 +}
2642 +
2643 +
2644 +
2645 +void __init
2646 +ar2315_prom_init(void)
2647 +{
2648 + u32 memsize, memcfg, devid;
2649 +
2650 + if (!is_2315())
2651 + return;
2652 +
2653 + memcfg = ar231x_read_reg(AR2315_MEM_CFG);
2654 + memsize = 1 + ((memcfg & SDRAM_DATA_WIDTH_M) >> SDRAM_DATA_WIDTH_S);
2655 + memsize <<= 1 + ((memcfg & SDRAM_COL_WIDTH_M) >> SDRAM_COL_WIDTH_S);
2656 + memsize <<= 1 + ((memcfg & SDRAM_ROW_WIDTH_M) >> SDRAM_ROW_WIDTH_S);
2657 + memsize <<= 3;
2658 + add_memory_region(0, memsize, BOOT_MEM_RAM);
2659 +
2660 + /* Detect the hardware based on the device ID */
2661 + devid = ar231x_read_reg(AR2315_SREV) & AR2315_REV_CHIP;
2662 + switch (devid) {
2663 + case 0x90:
2664 + case 0x91:
2665 + ar231x_devtype = DEV_TYPE_AR2317;
2666 + break;
2667 + default:
2668 + ar231x_devtype = DEV_TYPE_AR2315;
2669 + break;
2670 + }
2671 + ar2315_gpio_init();
2672 + ar231x_board.devid = devid;
2673 +}
2674 +
2675 +void __init
2676 +ar2315_plat_setup(void)
2677 +{
2678 + u32 config;
2679 +
2680 + if (!is_2315())
2681 + return;
2682 +
2683 + /* Clear any lingering AHB errors */
2684 + config = read_c0_config();
2685 + write_c0_config(config & ~0x3);
2686 + ar231x_write_reg(AR2315_AHB_ERR0, AHB_ERROR_DET);
2687 + ar231x_read_reg(AR2315_AHB_ERR1);
2688 + ar231x_write_reg(AR2315_WDC, AR2315_WDC_IGNORE_EXPIRATION);
2689 +
2690 + _machine_restart = ar2315_restart;
2691 + ar231x_serial_setup(AR2315_UART0, AR2315_MISC_IRQ_UART0,
2692 + ar2315_apb_frequency());
2693 +}
2694 --- /dev/null
2695 +++ b/arch/mips/ar231x/ar2315.h
2696 @@ -0,0 +1,37 @@
2697 +#ifndef __AR2315_H
2698 +#define __AR2315_H
2699 +
2700 +#ifdef CONFIG_ATHEROS_AR2315
2701 +
2702 +void ar2315_irq_init(void);
2703 +int ar2315_init_devices(void);
2704 +void ar2315_prom_init(void);
2705 +void ar2315_plat_setup(void);
2706 +void ar2315_time_init(void);
2707 +
2708 +#else
2709 +
2710 +static inline void ar2315_irq_init(void)
2711 +{
2712 +}
2713 +
2714 +static inline int ar2315_init_devices(void)
2715 +{
2716 + return 0;
2717 +}
2718 +
2719 +static inline void ar2315_prom_init(void)
2720 +{
2721 +}
2722 +
2723 +static inline void ar2315_plat_setup(void)
2724 +{
2725 +}
2726 +
2727 +static inline void ar2315_time_init(void)
2728 +{
2729 +}
2730 +
2731 +#endif
2732 +
2733 +#endif
2734 --- /dev/null
2735 +++ b/arch/mips/ar231x/ar5312.h
2736 @@ -0,0 +1,37 @@
2737 +#ifndef __AR5312_H
2738 +#define __AR5312_H
2739 +
2740 +#ifdef CONFIG_ATHEROS_AR5312
2741 +
2742 +void ar5312_irq_init(void);
2743 +int ar5312_init_devices(void);
2744 +void ar5312_prom_init(void);
2745 +void ar5312_plat_setup(void);
2746 +void ar5312_time_init(void);
2747 +
2748 +#else
2749 +
2750 +static inline void ar5312_irq_init(void)
2751 +{
2752 +}
2753 +
2754 +static inline int ar5312_init_devices(void)
2755 +{
2756 + return 0;
2757 +}
2758 +
2759 +static inline void ar5312_prom_init(void)
2760 +{
2761 +}
2762 +
2763 +static inline void ar5312_plat_setup(void)
2764 +{
2765 +}
2766 +
2767 +static inline void ar5312_time_init(void)
2768 +{
2769 +}
2770 +
2771 +#endif
2772 +
2773 +#endif
2774 --- /dev/null
2775 +++ b/arch/mips/include/asm/mach-ar231x/ar231x.h
2776 @@ -0,0 +1,43 @@
2777 +#ifndef __ASM_MACH_AR231X_H
2778 +#define __ASM_MACH_AR231X_H
2779 +
2780 +#include <linux/types.h>
2781 +#include <linux/io.h>
2782 +
2783 +#define AR231X_MISC_IRQ_BASE 0x20
2784 +#define AR231X_GPIO_IRQ_BASE 0x30
2785 +
2786 +/* Software's idea of interrupts handled by "CPU Interrupt Controller" */
2787 +#define AR231X_IRQ_NONE (MIPS_CPU_IRQ_BASE+0)
2788 +#define AR231X_IRQ_CPU_CLOCK (MIPS_CPU_IRQ_BASE+7) /* C0_CAUSE: 0x8000 */
2789 +
2790 +/* GPIO Interrupts, share ARXXXX_MISC_IRQ_GPIO */
2791 +#define AR231X_GPIO_IRQ_NONE (AR231X_GPIO_IRQ_BASE+0)
2792 +#define AR231X_GPIO_IRQ(n) (AR231X_GPIO_IRQ_BASE+n)
2793 +
2794 +static inline u32
2795 +ar231x_read_reg(u32 reg)
2796 +{
2797 + return __raw_readl((void __iomem *)KSEG1ADDR(reg));
2798 +}
2799 +
2800 +static inline void
2801 +ar231x_write_reg(u32 reg, u32 val)
2802 +{
2803 + __raw_writel(val, (void __iomem *)KSEG1ADDR(reg));
2804 +}
2805 +
2806 +static inline u32
2807 +ar231x_mask_reg(u32 reg, u32 mask, u32 val)
2808 +{
2809 + u32 ret;
2810 +
2811 + ret = ar231x_read_reg(reg);
2812 + ret &= ~mask;
2813 + ret |= val;
2814 + ar231x_write_reg(reg, ret);
2815 +
2816 + return ret;
2817 +}
2818 +
2819 +#endif /* __ASM_MACH_AR231X_H */
2820 --- /dev/null
2821 +++ b/arch/mips/ar231x/devices.h
2822 @@ -0,0 +1,38 @@
2823 +#ifndef __AR231X_DEVICES_H
2824 +#define __AR231X_DEVICES_H
2825 +
2826 +enum {
2827 + /* handled by ar5312.c */
2828 + DEV_TYPE_AR2312,
2829 + DEV_TYPE_AR2313,
2830 + DEV_TYPE_AR5312,
2831 +
2832 + /* handled by ar2315.c */
2833 + DEV_TYPE_AR2315,
2834 + DEV_TYPE_AR2316,
2835 + DEV_TYPE_AR2317,
2836 +
2837 + DEV_TYPE_UNKNOWN
2838 +};
2839 +
2840 +extern int ar231x_devtype;
2841 +extern struct ar231x_board_config ar231x_board;
2842 +extern asmlinkage void (*ar231x_irq_dispatch)(void);
2843 +
2844 +int ar231x_find_config(u8 *flash_limit);
2845 +void ar231x_serial_setup(u32 mapbase, int irq, unsigned int uartclk);
2846 +int ar231x_add_wmac(int nr, u32 base, int irq);
2847 +int ar231x_add_ethernet(int nr, u32 base, const char *mii_name, u32 mii_base,
2848 + int irq, void *pdata);
2849 +
2850 +static inline bool is_2315(void)
2851 +{
2852 + return (current_cpu_data.cputype == CPU_4KEC);
2853 +}
2854 +
2855 +static inline bool is_5312(void)
2856 +{
2857 + return !is_2315();
2858 +}
2859 +
2860 +#endif
2861 --- /dev/null
2862 +++ b/arch/mips/ar231x/devices.c
2863 @@ -0,0 +1,182 @@
2864 +#include <linux/kernel.h>
2865 +#include <linux/init.h>
2866 +#include <linux/serial.h>
2867 +#include <linux/serial_core.h>
2868 +#include <linux/serial_8250.h>
2869 +#include <linux/platform_device.h>
2870 +#include <asm/bootinfo.h>
2871 +
2872 +#include <ar231x_platform.h>
2873 +#include <ar231x.h>
2874 +#include "devices.h"
2875 +#include "ar5312.h"
2876 +#include "ar2315.h"
2877 +
2878 +struct ar231x_board_config ar231x_board;
2879 +int ar231x_devtype = DEV_TYPE_UNKNOWN;
2880 +
2881 +static struct resource ar231x_eth0_res[] = {
2882 + {
2883 + .name = "eth0_membase",
2884 + .flags = IORESOURCE_MEM,
2885 + },
2886 + {
2887 + .name = "eth0_mii",
2888 + .flags = IORESOURCE_MEM,
2889 + },
2890 + {
2891 + .name = "eth0_irq",
2892 + .flags = IORESOURCE_IRQ,
2893 + }
2894 +};
2895 +
2896 +static struct resource ar231x_eth1_res[] = {
2897 + {
2898 + .name = "eth1_membase",
2899 + .flags = IORESOURCE_MEM,
2900 + },
2901 + {
2902 + .name = "eth1_mii",
2903 + .flags = IORESOURCE_MEM,
2904 + },
2905 + {
2906 + .name = "eth1_irq",
2907 + .flags = IORESOURCE_IRQ,
2908 + }
2909 +};
2910 +
2911 +static struct platform_device ar231x_eth[] = {
2912 + {
2913 + .id = 0,
2914 + .name = "ar231x-eth",
2915 + .resource = ar231x_eth0_res,
2916 + .num_resources = ARRAY_SIZE(ar231x_eth0_res)
2917 + },
2918 + {
2919 + .id = 1,
2920 + .name = "ar231x-eth",
2921 + .resource = ar231x_eth1_res,
2922 + .num_resources = ARRAY_SIZE(ar231x_eth1_res)
2923 + }
2924 +};
2925 +
2926 +static struct resource ar231x_wmac0_res[] = {
2927 + {
2928 + .name = "wmac0_membase",
2929 + .flags = IORESOURCE_MEM,
2930 + },
2931 + {
2932 + .name = "wmac0_irq",
2933 + .flags = IORESOURCE_IRQ,
2934 + }
2935 +};
2936 +
2937 +static struct resource ar231x_wmac1_res[] = {
2938 + {
2939 + .name = "wmac1_membase",
2940 + .flags = IORESOURCE_MEM,
2941 + },
2942 + {
2943 + .name = "wmac1_irq",
2944 + .flags = IORESOURCE_IRQ,
2945 + }
2946 +};
2947 +
2948 +
2949 +static struct platform_device ar231x_wmac[] = {
2950 + {
2951 + .id = 0,
2952 + .name = "ar231x-wmac",
2953 + .resource = ar231x_wmac0_res,
2954 + .num_resources = ARRAY_SIZE(ar231x_wmac0_res),
2955 + .dev.platform_data = &ar231x_board,
2956 + },
2957 + {
2958 + .id = 1,
2959 + .name = "ar231x-wmac",
2960 + .resource = ar231x_wmac1_res,
2961 + .num_resources = ARRAY_SIZE(ar231x_wmac1_res),
2962 + .dev.platform_data = &ar231x_board,
2963 + },
2964 +};
2965 +
2966 +static const char * const devtype_strings[] = {
2967 + [DEV_TYPE_AR5312] = "Atheros AR5312",
2968 + [DEV_TYPE_AR2312] = "Atheros AR2312",
2969 + [DEV_TYPE_AR2313] = "Atheros AR2313",
2970 + [DEV_TYPE_AR2315] = "Atheros AR2315",
2971 + [DEV_TYPE_AR2316] = "Atheros AR2316",
2972 + [DEV_TYPE_AR2317] = "Atheros AR2317",
2973 + [DEV_TYPE_UNKNOWN] = "Atheros (unknown)",
2974 +};
2975 +
2976 +const char *get_system_type(void)
2977 +{
2978 + if ((ar231x_devtype >= ARRAY_SIZE(devtype_strings)) ||
2979 + !devtype_strings[ar231x_devtype])
2980 + return devtype_strings[DEV_TYPE_UNKNOWN];
2981 + return devtype_strings[ar231x_devtype];
2982 +}
2983 +
2984 +
2985 +int __init
2986 +ar231x_add_ethernet(int nr, u32 base, const char *mii_name, u32 mii_base,
2987 + int irq, void *pdata)
2988 +{
2989 + struct resource *res;
2990 +
2991 + ar231x_eth[nr].dev.platform_data = pdata;
2992 + res = &ar231x_eth[nr].resource[0];
2993 + res->start = base;
2994 + res->end = base + 0x2000 - 1;
2995 + res++;
2996 + res->name = mii_name;
2997 + res->start = mii_base;
2998 + res->end = mii_base + 8 - 1;
2999 + res++;
3000 + res->start = irq;
3001 + res->end = irq;
3002 + return platform_device_register(&ar231x_eth[nr]);
3003 +}
3004 +
3005 +void __init
3006 +ar231x_serial_setup(u32 mapbase, int irq, unsigned int uartclk)
3007 +{
3008 + struct uart_port s;
3009 +
3010 + memset(&s, 0, sizeof(s));
3011 +
3012 + s.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP;
3013 + s.iotype = UPIO_MEM32;
3014 + s.irq = irq;
3015 + s.regshift = 2;
3016 + s.mapbase = mapbase;
3017 + s.uartclk = uartclk;
3018 +
3019 + early_serial_setup(&s);
3020 +}
3021 +
3022 +int __init
3023 +ar231x_add_wmac(int nr, u32 base, int irq)
3024 +{
3025 + struct resource *res;
3026 +
3027 + ar231x_wmac[nr].dev.platform_data = &ar231x_board;
3028 + res = &ar231x_wmac[nr].resource[0];
3029 + res->start = base;
3030 + res->end = base + 0x10000 - 1;
3031 + res++;
3032 + res->start = irq;
3033 + res->end = irq;
3034 + return platform_device_register(&ar231x_wmac[nr]);
3035 +}
3036 +
3037 +static int __init ar231x_register_devices(void)
3038 +{
3039 + ar5312_init_devices();
3040 + ar2315_init_devices();
3041 +
3042 + return 0;
3043 +}
3044 +
3045 +device_initcall(ar231x_register_devices);
OpenWrt SVN history