projects / openwrt / svn-archive / archive.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
atheros: add 3.14 configuration
[openwrt/svn-archive/archive.git] / target / linux / atheros / patches-3.14 / 100-board.patch
1 --- a/arch/mips/Kconfig
2 +++ b/arch/mips/Kconfig
3 @@ -144,6 +144,19 @@ config BCM63XX
4 help
5 Support for BCM63XX based boards
6
7 +config ATHEROS_AR231X
8 + bool "Atheros 231x/531x SoC support"
9 + select CEVT_R4K
10 + select CSRC_R4K
11 + select DMA_NONCOHERENT
12 + select IRQ_CPU
13 + select SYS_HAS_CPU_MIPS32_R1
14 + select SYS_SUPPORTS_BIG_ENDIAN
15 + select SYS_SUPPORTS_32BIT_KERNEL
16 + select ARCH_REQUIRE_GPIOLIB
17 + help
18 + Support for AR231x and AR531x based boards
19 +
20 config MIPS_COBALT
21 bool "Cobalt Server"
22 select CEVT_R4K
23 @@ -795,6 +808,7 @@ config NLM_XLP_BOARD
24
25 endchoice
26
27 +source "arch/mips/ar231x/Kconfig"
28 source "arch/mips/alchemy/Kconfig"
29 source "arch/mips/ath79/Kconfig"
30 source "arch/mips/bcm47xx/Kconfig"
31 --- a/arch/mips/Kbuild.platforms
32 +++ b/arch/mips/Kbuild.platforms
33 @@ -6,6 +6,7 @@ platforms += ath79
34 platforms += bcm47xx
35 platforms += bcm63xx
36 platforms += cavium-octeon
37 +platforms += ar231x
38 platforms += cobalt
39 platforms += dec
40 platforms += emma
41 --- /dev/null
42 +++ b/arch/mips/ar231x/Platform
43 @@ -0,0 +1,6 @@
44 +#
45 +# Atheros AR531X/AR231X WiSoC
46 +#
47 +platform-$(CONFIG_ATHEROS_AR231X) += ar231x/
48 +cflags-$(CONFIG_ATHEROS_AR231X) += -I$(srctree)/arch/mips/include/asm/mach-ar231x
49 +load-$(CONFIG_ATHEROS_AR231X) += 0xffffffff80041000
50 --- /dev/null
51 +++ b/arch/mips/ar231x/Kconfig
52 @@ -0,0 +1,16 @@
53 +config ATHEROS_AR5312
54 + bool "Atheros 5312/2312+ support"
55 + depends on ATHEROS_AR231X
56 + default y
57 +
58 +config ATHEROS_AR2315
59 + bool "Atheros 2315+ support"
60 + depends on ATHEROS_AR231X
61 + select DMA_NONCOHERENT
62 + select CEVT_R4K
63 + select CSRC_R4K
64 + select IRQ_CPU
65 + select SYS_HAS_CPU_MIPS32_R1
66 + select SYS_SUPPORTS_32BIT_KERNEL
67 + select SYS_SUPPORTS_BIG_ENDIAN
68 + default y
69 --- /dev/null
70 +++ b/arch/mips/ar231x/Makefile
71 @@ -0,0 +1,13 @@
72 +#
73 +# This file is subject to the terms and conditions of the GNU General Public
74 +# License. See the file "COPYING" in the main directory of this archive
75 +# for more details.
76 +#
77 +# Copyright (C) 2006 FON Technology, SL.
78 +# Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
79 +# Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
80 +#
81 +
82 +obj-y += board.o prom.o devices.o
83 +obj-$(CONFIG_ATHEROS_AR5312) += ar5312.o
84 +obj-$(CONFIG_ATHEROS_AR2315) += ar2315.o
85 --- /dev/null
86 +++ b/arch/mips/ar231x/board.c
87 @@ -0,0 +1,261 @@
88 +/*
89 + * This file is subject to the terms and conditions of the GNU General Public
90 + * License. See the file "COPYING" in the main directory of this archive
91 + * for more details.
92 + *
93 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
94 + * Copyright (C) 2006 FON Technology, SL.
95 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
96 + * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
97 + */
98 +
99 +#include <generated/autoconf.h>
100 +#include <linux/init.h>
101 +#include <linux/module.h>
102 +#include <linux/types.h>
103 +#include <linux/string.h>
104 +#include <linux/platform_device.h>
105 +#include <linux/kernel.h>
106 +#include <linux/random.h>
107 +#include <linux/etherdevice.h>
108 +#include <linux/irq.h>
109 +#include <linux/io.h>
110 +#include <asm/irq_cpu.h>
111 +#include <asm/reboot.h>
112 +
113 +#include <ar231x_platform.h>
114 +#include "devices.h"
115 +#include "ar5312.h"
116 +#include "ar2315.h"
117 +
118 +void (*ar231x_irq_dispatch)(void);
119 +
120 +static inline bool
121 +check_radio_magic(u8 *addr)
122 +{
123 + addr += 0x7a; /* offset for flash magic */
124 + if ((addr[0] == 0x5a) && (addr[1] == 0xa5))
125 + return 1;
126 +
127 + return 0;
128 +}
129 +
130 +static inline bool
131 +check_board_data(u8 *flash_limit, u8 *addr, bool broken)
132 +{
133 + /* config magic found */
134 + if (*((u32 *)addr) == AR231X_BD_MAGIC)
135 + return 1;
136 +
137 + if (!broken)
138 + return 0;
139 +
140 + if (check_radio_magic(addr + 0xf8))
141 + ar231x_board.radio = addr + 0xf8;
142 + if ((addr < flash_limit + 0x10000) &&
143 + check_radio_magic(addr + 0x10000))
144 + ar231x_board.radio = addr + 0x10000;
145 +
146 + if (ar231x_board.radio) {
147 + /* broken board data detected, use radio data to find the
148 + * offset, user will fix this */
149 + return 1;
150 + }
151 + return 0;
152 +}
153 +
154 +static u8 *
155 +find_board_config(u8 *flash_limit, bool broken)
156 +{
157 + u8 *addr;
158 + int found = 0;
159 +
160 + for (addr = flash_limit - 0x1000;
161 + addr >= flash_limit - 0x30000;
162 + addr -= 0x1000) {
163 +
164 + if (check_board_data(flash_limit, addr, broken)) {
165 + found = 1;
166 + break;
167 + }
168 + }
169 +
170 + if (!found)
171 + addr = NULL;
172 +
173 + return addr;
174 +}
175 +
176 +static u8 *
177 +find_radio_config(u8 *flash_limit, u8 *board_config)
178 +{
179 + int found;
180 + u8 *radio_config;
181 +
182 + /*
183 + * Now find the start of Radio Configuration data, using heuristics:
184 + * Search forward from Board Configuration data by 0x1000 bytes
185 + * at a time until we find non-0xffffffff.
186 + */
187 + found = 0;
188 + for (radio_config = board_config + 0x1000;
189 + (radio_config < flash_limit);
190 + radio_config += 0x1000) {
191 + if ((*(u32 *)radio_config != 0xffffffff) &&
192 + check_radio_magic(radio_config)) {
193 + found = 1;
194 + break;
195 + }
196 + }
197 +
198 + /* AR2316 relocates radio config to new location */
199 + if (!found) {
200 + for (radio_config = board_config + 0xf8;
201 + (radio_config < flash_limit - 0x1000 + 0xf8);
202 + radio_config += 0x1000) {
203 + if ((*(u32 *)radio_config != 0xffffffff) &&
204 + check_radio_magic(radio_config)) {
205 + found = 1;
206 + break;
207 + }
208 + }
209 + }
210 +
211 + if (!found) {
212 + pr_warn("WARNING: Could not find Radio Configuration data\n");
213 + radio_config = 0;
214 + }
215 +
216 + return radio_config;
217 +}
218 +
219 +int __init
220 +ar231x_find_config(u8 *flash_limit)
221 +{
222 + struct ar231x_boarddata *config;
223 + unsigned int rcfg_size;
224 + int broken_boarddata = 0;
225 + u8 *bcfg, *rcfg;
226 + u8 *board_data;
227 + u8 *radio_data;
228 + u8 *mac_addr;
229 + u32 offset;
230 +
231 + ar231x_board.config = NULL;
232 + ar231x_board.radio = NULL;
233 + /* Copy the board and radio data to RAM, because accessing the mapped
234 + * memory of the flash directly after booting is not safe */
235 +
236 + /* Try to find valid board and radio data */
237 + bcfg = find_board_config(flash_limit, false);
238 +
239 + /* If that fails, try to at least find valid radio data */
240 + if (!bcfg) {
241 + bcfg = find_board_config(flash_limit, true);
242 + broken_boarddata = 1;
243 + }
244 +
245 + if (!bcfg) {
246 + pr_warn("WARNING: No board configuration data found!\n");
247 + return -ENODEV;
248 + }
249 +
250 + board_data = kzalloc(BOARD_CONFIG_BUFSZ, GFP_KERNEL);
251 + ar231x_board.config = (struct ar231x_boarddata *)board_data;
252 + memcpy(board_data, bcfg, 0x100);
253 + if (broken_boarddata) {
254 + pr_warn("WARNING: broken board data detected\n");
255 + config = ar231x_board.config;
256 + if (!memcmp(config->enet0_mac, "\x00\x00\x00\x00\x00\x00", 6)) {
257 + pr_info("Fixing up empty mac addresses\n");
258 + config->reset_config_gpio = 0xffff;
259 + config->sys_led_gpio = 0xffff;
260 + random_ether_addr(config->wlan0_mac);
261 + config->wlan0_mac[0] &= ~0x06;
262 + random_ether_addr(config->enet0_mac);
263 + random_ether_addr(config->enet1_mac);
264 + }
265 + }
266 +
267 +
268 + /* Radio config starts 0x100 bytes after board config, regardless
269 + * of what the physical layout on the flash chip looks like */
270 +
271 + if (ar231x_board.radio)
272 + rcfg = (u8 *)ar231x_board.radio;
273 + else
274 + rcfg = find_radio_config(flash_limit, bcfg);
275 +
276 + if (!rcfg)
277 + return -ENODEV;
278 +
279 + radio_data = board_data + 0x100 + ((rcfg - bcfg) & 0xfff);
280 + ar231x_board.radio = radio_data;
281 + offset = radio_data - board_data;
282 + pr_info("Radio config found at offset 0x%x (0x%x)\n", rcfg - bcfg,
283 + offset);
284 + rcfg_size = BOARD_CONFIG_BUFSZ - offset;
285 + memcpy(radio_data, rcfg, rcfg_size);
286 +
287 + mac_addr = &radio_data[0x1d * 2];
288 + if (is_broadcast_ether_addr(mac_addr)) {
289 + pr_info("Radio MAC is blank; using board-data\n");
290 + memcpy(mac_addr, ar231x_board.config->wlan0_mac, ETH_ALEN);
291 + }
292 +
293 + return 0;
294 +}
295 +
296 +static void
297 +ar231x_halt(void)
298 +{
299 + local_irq_disable();
300 + while (1)
301 + ;
302 +}
303 +
304 +void __init
305 +plat_mem_setup(void)
306 +{
307 + _machine_halt = ar231x_halt;
308 + pm_power_off = ar231x_halt;
309 +
310 + ar5312_plat_setup();
311 + ar2315_plat_setup();
312 +
313 + /* Disable data watchpoints */
314 + write_c0_watchlo0(0);
315 +}
316 +
317 +
318 +asmlinkage void
319 +plat_irq_dispatch(void)
320 +{
321 + ar231x_irq_dispatch();
322 +}
323 +
324 +void __init
325 +plat_time_init(void)
326 +{
327 + ar5312_time_init();
328 + ar2315_time_init();
329 +}
330 +
331 +unsigned int __cpuinit
332 +get_c0_compare_int(void)
333 +{
334 + return CP0_LEGACY_COMPARE_IRQ;
335 +}
336 +
337 +void __init
338 +arch_init_irq(void)
339 +{
340 + clear_c0_status(ST0_IM);
341 + mips_cpu_irq_init();
342 +
343 + /* Initialize interrupt controllers */
344 + ar5312_irq_init();
345 + ar2315_irq_init();
346 +}
347 +
348 +
349 --- /dev/null
350 +++ b/arch/mips/ar231x/prom.c
351 @@ -0,0 +1,37 @@
352 +/*
353 + * This file is subject to the terms and conditions of the GNU General Public
354 + * License. See the file "COPYING" in the main directory of this archive
355 + * for more details.
356 + *
357 + * Copyright MontaVista Software Inc
358 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
359 + * Copyright (C) 2006 FON Technology, SL.
360 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
361 + * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
362 + */
363 +
364 +/*
365 + * Prom setup file for ar231x
366 + */
367 +
368 +#include <linux/init.h>
369 +#include <generated/autoconf.h>
370 +#include <linux/kernel.h>
371 +#include <linux/string.h>
372 +#include <linux/mm.h>
373 +#include <linux/bootmem.h>
374 +
375 +#include <asm/bootinfo.h>
376 +#include <asm/addrspace.h>
377 +#include "ar5312.h"
378 +#include "ar2315.h"
379 +
380 +void __init prom_init(void)
381 +{
382 + ar5312_prom_init();
383 + ar2315_prom_init();
384 +}
385 +
386 +void __init prom_free_prom_memory(void)
387 +{
388 +}
389 --- /dev/null
390 +++ b/arch/mips/include/asm/mach-ar231x/ar231x_platform.h
391 @@ -0,0 +1,83 @@
392 +#ifndef __ASM_MACH_AR231X_PLATFORM_H
393 +#define __ASM_MACH_AR231X_PLATFORM_H
394 +
395 +/*
396 + * This is board-specific data that is stored in a "fixed" location in flash.
397 + * It is shared across operating systems, so it should not be changed lightly.
398 + * The main reason we need it is in order to extract the ethernet MAC
399 + * address(es).
400 + */
401 +struct ar231x_boarddata {
402 + u32 magic; /* board data is valid */
403 +#define AR231X_BD_MAGIC 0x35333131 /* "5311", for all 531x/231x platforms */
404 + u16 cksum; /* checksum (starting with BD_REV 2) */
405 + u16 rev; /* revision of this struct */
406 +#define BD_REV 4
407 + char board_name[64]; /* Name of board */
408 + u16 major; /* Board major number */
409 + u16 minor; /* Board minor number */
410 + u32 flags; /* Board configuration */
411 +#define BD_ENET0 0x00000001 /* ENET0 is stuffed */
412 +#define BD_ENET1 0x00000002 /* ENET1 is stuffed */
413 +#define BD_UART1 0x00000004 /* UART1 is stuffed */
414 +#define BD_UART0 0x00000008 /* UART0 is stuffed (dma) */
415 +#define BD_RSTFACTORY 0x00000010 /* Reset factory defaults stuffed */
416 +#define BD_SYSLED 0x00000020 /* System LED stuffed */
417 +#define BD_EXTUARTCLK 0x00000040 /* External UART clock */
418 +#define BD_CPUFREQ 0x00000080 /* cpu freq is valid in nvram */
419 +#define BD_SYSFREQ 0x00000100 /* sys freq is set in nvram */
420 +#define BD_WLAN0 0x00000200 /* Enable WLAN0 */
421 +#define BD_MEMCAP 0x00000400 /* CAP SDRAM @ mem_cap for testing */
422 +#define BD_DISWATCHDOG 0x00000800 /* disable system watchdog */
423 +#define BD_WLAN1 0x00001000 /* Enable WLAN1 (ar5212) */
424 +#define BD_ISCASPER 0x00002000 /* FLAG for AR2312 */
425 +#define BD_WLAN0_2G_EN 0x00004000 /* FLAG for radio0_2G */
426 +#define BD_WLAN0_5G_EN 0x00008000 /* FLAG for radio0_2G */
427 +#define BD_WLAN1_2G_EN 0x00020000 /* FLAG for radio0_2G */
428 +#define BD_WLAN1_5G_EN 0x00040000 /* FLAG for radio0_2G */
429 + u16 reset_config_gpio; /* Reset factory GPIO pin */
430 + u16 sys_led_gpio; /* System LED GPIO pin */
431 +
432 + u32 cpu_freq; /* CPU core frequency in Hz */
433 + u32 sys_freq; /* System frequency in Hz */
434 + u32 cnt_freq; /* Calculated C0_COUNT frequency */
435 +
436 + u8 wlan0_mac[6];
437 + u8 enet0_mac[6];
438 + u8 enet1_mac[6];
439 +
440 + u16 pci_id; /* Pseudo PCIID for common code */
441 + u16 mem_cap; /* cap bank1 in MB */
442 +
443 + /* version 3 */
444 + u8 wlan1_mac[6]; /* (ar5212) */
445 +};
446 +
447 +#define BOARD_CONFIG_BUFSZ 0x1000
448 +
449 +/*
450 + * Platform device information for the Wireless MAC
451 + */
452 +struct ar231x_board_config {
453 + u16 devid;
454 +
455 + /* board config data */
456 + struct ar231x_boarddata *config;
457 +
458 + /* radio calibration data */
459 + const char *radio;
460 +};
461 +
462 +/*
463 + * Platform device information for the Ethernet MAC
464 + */
465 +struct ar231x_eth {
466 + void (*reset_set)(u32);
467 + void (*reset_clear)(u32);
468 + u32 reset_mac;
469 + u32 reset_phy;
470 + struct ar231x_board_config *config;
471 + char *macaddr;
472 +};
473 +
474 +#endif /* __ASM_MACH_AR231X_PLATFORM_H */
475 --- /dev/null
476 +++ b/arch/mips/include/asm/mach-ar231x/cpu-feature-overrides.h
477 @@ -0,0 +1,84 @@
478 +/*
479 + * Atheros AR231x/AR531x SoC specific CPU feature overrides
480 + *
481 + * Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
482 + *
483 + * This file was derived from: include/asm-mips/cpu-features.h
484 + * Copyright (C) 2003, 2004 Ralf Baechle
485 + * Copyright (C) 2004 Maciej W. Rozycki
486 + *
487 + * This program is free software; you can redistribute it and/or modify it
488 + * under the terms of the GNU General Public License version 2 as published
489 + * by the Free Software Foundation.
490 + *
491 + */
492 +#ifndef __ASM_MACH_AR231X_CPU_FEATURE_OVERRIDES_H
493 +#define __ASM_MACH_AR231X_CPU_FEATURE_OVERRIDES_H
494 +
495 +/*
496 + * The Atheros AR531x/AR231x SoCs have MIPS 4Kc/4KEc core.
497 + */
498 +#define cpu_has_tlb 1
499 +#define cpu_has_4kex 1
500 +#define cpu_has_3k_cache 0
501 +#define cpu_has_4k_cache 1
502 +#define cpu_has_tx39_cache 0
503 +#define cpu_has_sb1_cache 0
504 +#define cpu_has_fpu 0
505 +#define cpu_has_32fpr 0
506 +#define cpu_has_counter 1
507 +/* #define cpu_has_watch ? */
508 +/* #define cpu_has_divec ? */
509 +/* #define cpu_has_vce ? */
510 +/* #define cpu_has_cache_cdex_p ? */
511 +/* #define cpu_has_cache_cdex_s ? */
512 +/* #define cpu_has_prefetch ? */
513 +/* #define cpu_has_mcheck ? */
514 +#define cpu_has_ejtag 1
515 +
516 +#if !defined(CONFIG_ATHEROS_AR5312)
517 +# define cpu_has_llsc 1
518 +#else
519 +/*
520 + * The MIPS 4Kc V0.9 core in the AR5312/AR2312 have problems with the
521 + * ll/sc instructions.
522 + */
523 +# define cpu_has_llsc 0
524 +#endif
525 +
526 +#define cpu_has_mips16 0
527 +#define cpu_has_mdmx 0
528 +#define cpu_has_mips3d 0
529 +#define cpu_has_smartmips 0
530 +
531 +/* #define cpu_has_vtag_icache ? */
532 +/* #define cpu_has_dc_aliases ? */
533 +/* #define cpu_has_ic_fills_f_dc ? */
534 +/* #define cpu_has_pindexed_dcache ? */
535 +
536 +/* #define cpu_icache_snoops_remote_store ? */
537 +
538 +#define cpu_has_mips32r1 1
539 +
540 +#if !defined(CONFIG_ATHEROS_AR5312)
541 +# define cpu_has_mips32r2 1
542 +#endif
543 +
544 +#define cpu_has_mips64r1 0
545 +#define cpu_has_mips64r2 0
546 +
547 +#define cpu_has_dsp 0
548 +#define cpu_has_mipsmt 0
549 +
550 +/* #define cpu_has_nofpuex ? */
551 +#define cpu_has_64bits 0
552 +#define cpu_has_64bit_zero_reg 0
553 +#define cpu_has_64bit_gp_regs 0
554 +#define cpu_has_64bit_addresses 0
555 +
556 +/* #define cpu_has_inclusive_pcaches ? */
557 +
558 +/* #define cpu_dcache_line_size() ? */
559 +/* #define cpu_icache_line_size() ? */
560 +
561 +#endif /* __ASM_MACH_AR231X_CPU_FEATURE_OVERRIDES_H */
562 --- /dev/null
563 +++ b/arch/mips/include/asm/mach-ar231x/dma-coherence.h
564 @@ -0,0 +1,79 @@
565 +/*
566 + * This file is subject to the terms and conditions of the GNU General Public
567 + * License. See the file "COPYING" in the main directory of this archive
568 + * for more details.
569 + *
570 + * Copyright (C) 2006 Ralf Baechle <ralf@linux-mips.org>
571 + * Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
572 + *
573 + */
574 +#ifndef __ASM_MACH_AR231X_DMA_COHERENCE_H
575 +#define __ASM_MACH_AR231X_DMA_COHERENCE_H
576 +
577 +#define PCI_DMA_OFFSET 0x20000000
578 +
579 +#include <linux/device.h>
580 +
581 +static inline dma_addr_t ar231x_dev_offset(struct device *dev)
582 +{
583 +#ifdef CONFIG_PCI
584 + extern struct bus_type pci_bus_type;
585 +
586 + if (dev && dev->bus == &pci_bus_type)
587 + return PCI_DMA_OFFSET;
588 + else
589 +#endif
590 + return 0;
591 +}
592 +
593 +static inline dma_addr_t
594 +plat_map_dma_mem(struct device *dev, void *addr, size_t size)
595 +{
596 + return virt_to_phys(addr) + ar231x_dev_offset(dev);
597 +}
598 +
599 +static inline dma_addr_t
600 +plat_map_dma_mem_page(struct device *dev, struct page *page)
601 +{
602 + return page_to_phys(page) + ar231x_dev_offset(dev);
603 +}
604 +
605 +static inline unsigned long
606 +plat_dma_addr_to_phys(struct device *dev, dma_addr_t dma_addr)
607 +{
608 + return dma_addr - ar231x_dev_offset(dev);
609 +}
610 +
611 +static inline void
612 +plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr, size_t size,
613 + enum dma_data_direction direction)
614 +{
615 +}
616 +
617 +static inline int plat_dma_supported(struct device *dev, u64 mask)
618 +{
619 + return 1;
620 +}
621 +
622 +static inline void plat_extra_sync_for_device(struct device *dev)
623 +{
624 + return;
625 +}
626 +
627 +static inline int plat_dma_mapping_error(struct device *dev,
628 + dma_addr_t dma_addr)
629 +{
630 + return 0;
631 +}
632 +
633 +static inline int plat_device_is_coherent(struct device *dev)
634 +{
635 +#ifdef CONFIG_DMA_COHERENT
636 + return 1;
637 +#endif
638 +#ifdef CONFIG_DMA_NONCOHERENT
639 + return 0;
640 +#endif
641 +}
642 +
643 +#endif /* __ASM_MACH_AR231X_DMA_COHERENCE_H */
644 --- /dev/null
645 +++ b/arch/mips/include/asm/mach-ar231x/gpio.h
646 @@ -0,0 +1,30 @@
647 +#ifndef __ASM_MACH_AR231X_GPIO_H
648 +#define __ASM_MACH_AR231X_GPIO_H
649 +
650 +#include <ar231x.h>
651 +
652 +#define gpio_get_value __gpio_get_value
653 +#define gpio_set_value __gpio_set_value
654 +#define gpio_cansleep __gpio_cansleep
655 +
656 +/*
657 + * Wrappers for the generic GPIO layer
658 + */
659 +
660 +/* not sure if these are used? */
661 +
662 +/* Returns IRQ to attach for gpio. Unchecked function */
663 +static inline int gpio_to_irq(unsigned gpio)
664 +{
665 + return AR231X_GPIO_IRQ(gpio);
666 +}
667 +
668 +/* Returns gpio for IRQ attached. Unchecked function */
669 +static inline int irq_to_gpio(unsigned irq)
670 +{
671 + return irq - AR231X_GPIO_IRQ(0);
672 +}
673 +
674 +#include <asm-generic/gpio.h> /* cansleep wrappers */
675 +
676 +#endif /* __ASM_MACH_AR231X_GPIO_H */
677 --- /dev/null
678 +++ b/arch/mips/include/asm/mach-ar231x/reset.h
679 @@ -0,0 +1,6 @@
680 +#ifndef __ASM_MACH_AR231X_RESET_H
681 +#define __ASM_MACH_AR231X_RESET_H
682 +
683 +void ar231x_disable_reset_button(void);
684 +
685 +#endif /* __ASM_MACH_AR231X_RESET_H */
686 --- /dev/null
687 +++ b/arch/mips/include/asm/mach-ar231x/war.h
688 @@ -0,0 +1,25 @@
689 +/*
690 + * This file is subject to the terms and conditions of the GNU General Public
691 + * License. See the file "COPYING" in the main directory of this archive
692 + * for more details.
693 + *
694 + * Copyright (C) 2008 Felix Fietkau <nbd@openwrt.org>
695 + */
696 +#ifndef __ASM_MACH_AR231X_WAR_H
697 +#define __ASM_MACH_AR231X_WAR_H
698 +
699 +#define R4600_V1_INDEX_ICACHEOP_WAR 0
700 +#define R4600_V1_HIT_CACHEOP_WAR 0
701 +#define R4600_V2_HIT_CACHEOP_WAR 0
702 +#define R5432_CP0_INTERRUPT_WAR 0
703 +#define BCM1250_M3_WAR 0
704 +#define SIBYTE_1956_WAR 0
705 +#define MIPS4K_ICACHE_REFILL_WAR 0
706 +#define MIPS_CACHE_SYNC_WAR 0
707 +#define TX49XX_ICACHE_INDEX_INV_WAR 0
708 +#define RM9000_CDEX_SMP_WAR 0
709 +#define ICACHE_REFILLS_WORKAROUND_WAR 0
710 +#define R10000_LLSC_WAR 0
711 +#define MIPS34K_MISSED_ITLB_WAR 0
712 +
713 +#endif /* __ASM_MACH_AR231X_WAR_H */
714 --- /dev/null
715 +++ b/arch/mips/include/asm/mach-ar231x/ar2315_regs.h
716 @@ -0,0 +1,617 @@
717 +/*
718 + * Register definitions for AR2315+
719 + *
720 + * This file is subject to the terms and conditions of the GNU General Public
721 + * License. See the file "COPYING" in the main directory of this archive
722 + * for more details.
723 + *
724 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
725 + * Copyright (C) 2006 FON Technology, SL.
726 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
727 + * Copyright (C) 2006-2008 Felix Fietkau <nbd@openwrt.org>
728 + */
729 +
730 +#ifndef __ASM_MACH_AR231X_AR2315_REGS_H
731 +#define __ASM_MACH_AR231X_AR2315_REGS_H
732 +
733 +/*
734 + * IRQs
735 + */
736 +#define AR2315_IRQ_MISC_INTRS (MIPS_CPU_IRQ_BASE+2) /* C0_CAUSE: 0x0400 */
737 +#define AR2315_IRQ_WLAN0_INTRS (MIPS_CPU_IRQ_BASE+3) /* C0_CAUSE: 0x0800 */
738 +#define AR2315_IRQ_ENET0_INTRS (MIPS_CPU_IRQ_BASE+4) /* C0_CAUSE: 0x1000 */
739 +#define AR2315_IRQ_LCBUS_PCI (MIPS_CPU_IRQ_BASE+5) /* C0_CAUSE: 0x2000 */
740 +#define AR2315_IRQ_WLAN0_POLL (MIPS_CPU_IRQ_BASE+6) /* C0_CAUSE: 0x4000 */
741 +
742 +
743 +/*
744 + * Miscellaneous interrupts, which share IP2.
745 + */
746 +#define AR2315_MISC_IRQ_NONE (AR231X_MISC_IRQ_BASE+0)
747 +#define AR2315_MISC_IRQ_UART0 (AR231X_MISC_IRQ_BASE+1)
748 +#define AR2315_MISC_IRQ_I2C_RSVD (AR231X_MISC_IRQ_BASE+2)
749 +#define AR2315_MISC_IRQ_SPI (AR231X_MISC_IRQ_BASE+3)
750 +#define AR2315_MISC_IRQ_AHB (AR231X_MISC_IRQ_BASE+4)
751 +#define AR2315_MISC_IRQ_APB (AR231X_MISC_IRQ_BASE+5)
752 +#define AR2315_MISC_IRQ_TIMER (AR231X_MISC_IRQ_BASE+6)
753 +#define AR2315_MISC_IRQ_GPIO (AR231X_MISC_IRQ_BASE+7)
754 +#define AR2315_MISC_IRQ_WATCHDOG (AR231X_MISC_IRQ_BASE+8)
755 +#define AR2315_MISC_IRQ_IR_RSVD (AR231X_MISC_IRQ_BASE+9)
756 +#define AR2315_MISC_IRQ_COUNT 10
757 +
758 +
759 +/*
760 + * Address map
761 + */
762 +#define AR2315_SPI_READ 0x08000000 /* SPI FLASH */
763 +#define AR2315_WLAN0 0x10000000 /* Wireless MMR */
764 +#define AR2315_PCI 0x10100000 /* PCI MMR */
765 +#define AR2315_SDRAMCTL 0x10300000 /* SDRAM MMR */
766 +#define AR2315_LOCAL 0x10400000 /* LOCAL BUS MMR */
767 +#define AR2315_ENET0 0x10500000 /* ETHERNET MMR */
768 +#define AR2315_DSLBASE 0x11000000 /* RESET CONTROL MMR */
769 +#define AR2315_UART0 0x11100000 /* UART MMR */
770 +#define AR2315_SPI_MMR 0x11300000 /* SPI FLASH MMR */
771 +#define AR2315_PCIEXT 0x80000000 /* pci external */
772 +
773 +/* MII registers offset inside Ethernet MMR region */
774 +#define AR2315_ENET0_MII (AR2315_ENET0 + 0x14)
775 +
776 +/*
777 + * Reset Register
778 + */
779 +#define AR2315_COLD_RESET (AR2315_DSLBASE + 0x0000)
780 +
781 +#define AR2315_RESET_COLD_AHB 0x00000001
782 +#define AR2315_RESET_COLD_APB 0x00000002
783 +#define AR2315_RESET_COLD_CPU 0x00000004
784 +#define AR2315_RESET_COLD_CPUWARM 0x00000008
785 +#define AR2315_RESET_SYSTEM \
786 + (RESET_COLD_CPU |\
787 + RESET_COLD_APB |\
788 + RESET_COLD_AHB) /* full system */
789 +#define AR2317_RESET_SYSTEM 0x00000010
790 +
791 +
792 +#define AR2315_RESET (AR2315_DSLBASE + 0x0004)
793 +
794 +/* warm reset WLAN0 MAC */
795 +#define AR2315_RESET_WARM_WLAN0_MAC 0x00000001
796 +/* warm reset WLAN0 BaseBand */
797 +#define AR2315_RESET_WARM_WLAN0_BB 0x00000002
798 +/* warm reset MPEG-TS */
799 +#define AR2315_RESET_MPEGTS_RSVD 0x00000004
800 +/* warm reset PCI ahb/dma */
801 +#define AR2315_RESET_PCIDMA 0x00000008
802 +/* warm reset memory controller */
803 +#define AR2315_RESET_MEMCTL 0x00000010
804 +/* warm reset local bus */
805 +#define AR2315_RESET_LOCAL 0x00000020
806 +/* warm reset I2C bus */
807 +#define AR2315_RESET_I2C_RSVD 0x00000040
808 +/* warm reset SPI interface */
809 +#define AR2315_RESET_SPI 0x00000080
810 +/* warm reset UART0 */
811 +#define AR2315_RESET_UART0 0x00000100
812 +/* warm reset IR interface */
813 +#define AR2315_RESET_IR_RSVD 0x00000200
814 +/* cold reset ENET0 phy */
815 +#define AR2315_RESET_EPHY0 0x00000400
816 +/* cold reset ENET0 mac */
817 +#define AR2315_RESET_ENET0 0x00000800
818 +
819 +/*
820 + * AHB master arbitration control
821 + */
822 +#define AR2315_AHB_ARB_CTL (AR2315_DSLBASE + 0x0008)
823 +
824 +/* CPU, default */
825 +#define AR2315_ARB_CPU 0x00000001
826 +/* WLAN */
827 +#define AR2315_ARB_WLAN 0x00000002
828 +/* MPEG-TS */
829 +#define AR2315_ARB_MPEGTS_RSVD 0x00000004
830 +/* LOCAL */
831 +#define AR2315_ARB_LOCAL 0x00000008
832 +/* PCI */
833 +#define AR2315_ARB_PCI 0x00000010
834 +/* Ethernet */
835 +#define AR2315_ARB_ETHERNET 0x00000020
836 +/* retry policy, debug only */
837 +#define AR2315_ARB_RETRY 0x00000100
838 +
839 +/*
840 + * Config Register
841 + */
842 +#define AR2315_ENDIAN_CTL (AR2315_DSLBASE + 0x000c)
843 +
844 +/* EC - AHB bridge endianess */
845 +#define AR2315_CONFIG_AHB 0x00000001
846 +/* WLAN byteswap */
847 +#define AR2315_CONFIG_WLAN 0x00000002
848 +/* MPEG-TS byteswap */
849 +#define AR2315_CONFIG_MPEGTS_RSVD 0x00000004
850 +/* PCI byteswap */
851 +#define AR2315_CONFIG_PCI 0x00000008
852 +/* Memory controller endianess */
853 +#define AR2315_CONFIG_MEMCTL 0x00000010
854 +/* Local bus byteswap */
855 +#define AR2315_CONFIG_LOCAL 0x00000020
856 +/* Ethernet byteswap */
857 +#define AR2315_CONFIG_ETHERNET 0x00000040
858 +
859 +/* CPU write buffer merge */
860 +#define AR2315_CONFIG_MERGE 0x00000200
861 +/* CPU big endian */
862 +#define AR2315_CONFIG_CPU 0x00000400
863 +#define AR2315_CONFIG_PCIAHB 0x00000800
864 +#define AR2315_CONFIG_PCIAHB_BRIDGE 0x00001000
865 +/* SPI byteswap */
866 +#define AR2315_CONFIG_SPI 0x00008000
867 +#define AR2315_CONFIG_CPU_DRAM 0x00010000
868 +#define AR2315_CONFIG_CPU_PCI 0x00020000
869 +#define AR2315_CONFIG_CPU_MMR 0x00040000
870 +#define AR2315_CONFIG_BIG 0x00000400
871 +
872 +
873 +/*
874 + * NMI control
875 + */
876 +#define AR2315_NMI_CTL (AR2315_DSLBASE + 0x0010)
877 +
878 +#define AR2315_NMI_EN 1
879 +
880 +/*
881 + * Revision Register - Initial value is 0x3010 (WMAC 3.0, AR231X 1.0).
882 + */
883 +#define AR2315_SREV (AR2315_DSLBASE + 0x0014)
884 +
885 +#define AR2315_REV_MAJ 0x00f0
886 +#define AR2315_REV_MAJ_S 4
887 +#define AR2315_REV_MIN 0x000f
888 +#define AR2315_REV_MIN_S 0
889 +#define AR2315_REV_CHIP (AR2315_REV_MAJ|AR2315_REV_MIN)
890 +
891 +/*
892 + * Interface Enable
893 + */
894 +#define AR2315_IF_CTL (AR2315_DSLBASE + 0x0018)
895 +
896 +#define AR2315_IF_MASK 0x00000007
897 +#define AR2315_IF_DISABLED 0
898 +#define AR2315_IF_PCI 1
899 +#define AR2315_IF_TS_LOCAL 2
900 +/* only for emulation with separate pins */
901 +#define AR2315_IF_ALL 3
902 +#define AR2315_IF_LOCAL_HOST 0x00000008
903 +#define AR2315_IF_PCI_HOST 0x00000010
904 +#define AR2315_IF_PCI_INTR 0x00000020
905 +#define AR2315_IF_PCI_CLK_MASK 0x00030000
906 +#define AR2315_IF_PCI_CLK_INPUT 0
907 +#define AR2315_IF_PCI_CLK_OUTPUT_LOW 1
908 +#define AR2315_IF_PCI_CLK_OUTPUT_CLK 2
909 +#define AR2315_IF_PCI_CLK_OUTPUT_HIGH 3
910 +#define AR2315_IF_PCI_CLK_SHIFT 16
911 +
912 +/*
913 + * APB Interrupt control
914 + */
915 +
916 +#define AR2315_ISR (AR2315_DSLBASE + 0x0020)
917 +#define AR2315_IMR (AR2315_DSLBASE + 0x0024)
918 +#define AR2315_GISR (AR2315_DSLBASE + 0x0028)
919 +
920 +#define AR2315_ISR_UART0 0x0001 /* high speed UART */
921 +#define AR2315_ISR_I2C_RSVD 0x0002 /* I2C bus */
922 +#define AR2315_ISR_SPI 0x0004 /* SPI bus */
923 +#define AR2315_ISR_AHB 0x0008 /* AHB error */
924 +#define AR2315_ISR_APB 0x0010 /* APB error */
925 +#define AR2315_ISR_TIMER 0x0020 /* timer */
926 +#define AR2315_ISR_GPIO 0x0040 /* GPIO */
927 +#define AR2315_ISR_WD 0x0080 /* watchdog */
928 +#define AR2315_ISR_IR_RSVD 0x0100 /* IR */
929 +
930 +#define AR2315_GISR_MISC 0x0001
931 +#define AR2315_GISR_WLAN0 0x0002
932 +#define AR2315_GISR_MPEGTS_RSVD 0x0004
933 +#define AR2315_GISR_LOCALPCI 0x0008
934 +#define AR2315_GISR_WMACPOLL 0x0010
935 +#define AR2315_GISR_TIMER 0x0020
936 +#define AR2315_GISR_ETHERNET 0x0040
937 +
938 +/*
939 + * Interrupt routing from IO to the processor IP bits
940 + * Define our inter mask and level
941 + */
942 +#define AR2315_INTR_MISCIO SR_IBIT3
943 +#define AR2315_INTR_WLAN0 SR_IBIT4
944 +#define AR2315_INTR_ENET0 SR_IBIT5
945 +#define AR2315_INTR_LOCALPCI SR_IBIT6
946 +#define AR2315_INTR_WMACPOLL SR_IBIT7
947 +#define AR2315_INTR_COMPARE SR_IBIT8
948 +
949 +/*
950 + * Timers
951 + */
952 +#define AR2315_TIMER (AR2315_DSLBASE + 0x0030)
953 +#define AR2315_RELOAD (AR2315_DSLBASE + 0x0034)
954 +#define AR2315_WD (AR2315_DSLBASE + 0x0038)
955 +#define AR2315_WDC (AR2315_DSLBASE + 0x003c)
956 +
957 +#define AR2315_WDC_IGNORE_EXPIRATION 0x00000000
958 +#define AR2315_WDC_NMI 0x00000001 /* NMI on watchdog */
959 +#define AR2315_WDC_RESET 0x00000002 /* reset on watchdog */
960 +
961 +/*
962 + * CPU Performance Counters
963 + */
964 +#define AR2315_PERFCNT0 (AR2315_DSLBASE + 0x0048)
965 +#define AR2315_PERFCNT1 (AR2315_DSLBASE + 0x004c)
966 +
967 +#define AR2315_PERF0_DATAHIT 0x0001 /* Count Data Cache Hits */
968 +#define AR2315_PERF0_DATAMISS 0x0002 /* Count Data Cache Misses */
969 +#define AR2315_PERF0_INSTHIT 0x0004 /* Count Instruction Cache Hits */
970 +#define AR2315_PERF0_INSTMISS 0x0008 /* Count Instruction Cache Misses */
971 +#define AR2315_PERF0_ACTIVE 0x0010 /* Count Active Processor Cycles */
972 +#define AR2315_PERF0_WBHIT 0x0020 /* Count CPU Write Buffer Hits */
973 +#define AR2315_PERF0_WBMISS 0x0040 /* Count CPU Write Buffer Misses */
974 +
975 +#define AR2315_PERF1_EB_ARDY 0x0001 /* Count EB_ARdy signal */
976 +#define AR2315_PERF1_EB_AVALID 0x0002 /* Count EB_AValid signal */
977 +#define AR2315_PERF1_EB_WDRDY 0x0004 /* Count EB_WDRdy signal */
978 +#define AR2315_PERF1_EB_RDVAL 0x0008 /* Count EB_RdVal signal */
979 +#define AR2315_PERF1_VRADDR 0x0010 /* Count valid read address cycles */
980 +#define AR2315_PERF1_VWADDR 0x0020 /* Count valid write address cycles */
981 +#define AR2315_PERF1_VWDATA 0x0040 /* Count valid write data cycles */
982 +
983 +/*
984 + * AHB Error Reporting.
985 + */
986 +#define AR2315_AHB_ERR0 (AR2315_DSLBASE + 0x0050) /* error */
987 +#define AR2315_AHB_ERR1 (AR2315_DSLBASE + 0x0054) /* haddr */
988 +#define AR2315_AHB_ERR2 (AR2315_DSLBASE + 0x0058) /* hwdata */
989 +#define AR2315_AHB_ERR3 (AR2315_DSLBASE + 0x005c) /* hrdata */
990 +#define AR2315_AHB_ERR4 (AR2315_DSLBASE + 0x0060) /* status */
991 +
992 +#define AHB_ERROR_DET 1 /* AHB Error has been detected, */
993 + /* write 1 to clear all bits in ERR0 */
994 +#define AHB_ERROR_OVR 2 /* AHB Error overflow has been detected */
995 +#define AHB_ERROR_WDT 4 /* AHB Error due to wdt instead of hresp */
996 +
997 +#define AR2315_PROCERR_HMAST 0x0000000f
998 +#define AR2315_PROCERR_HMAST_DFLT 0
999 +#define AR2315_PROCERR_HMAST_WMAC 1
1000 +#define AR2315_PROCERR_HMAST_ENET 2
1001 +#define AR2315_PROCERR_HMAST_PCIENDPT 3
1002 +#define AR2315_PROCERR_HMAST_LOCAL 4
1003 +#define AR2315_PROCERR_HMAST_CPU 5
1004 +#define AR2315_PROCERR_HMAST_PCITGT 6
1005 +
1006 +#define AR2315_PROCERR_HMAST_S 0
1007 +#define AR2315_PROCERR_HWRITE 0x00000010
1008 +#define AR2315_PROCERR_HSIZE 0x00000060
1009 +#define AR2315_PROCERR_HSIZE_S 5
1010 +#define AR2315_PROCERR_HTRANS 0x00000180
1011 +#define AR2315_PROCERR_HTRANS_S 7
1012 +#define AR2315_PROCERR_HBURST 0x00000e00
1013 +#define AR2315_PROCERR_HBURST_S 9
1014 +
1015 +/*
1016 + * Clock Control
1017 + */
1018 +#define AR2315_PLLC_CTL (AR2315_DSLBASE + 0x0064)
1019 +#define AR2315_PLLV_CTL (AR2315_DSLBASE + 0x0068)
1020 +#define AR2315_CPUCLK (AR2315_DSLBASE + 0x006c)
1021 +#define AR2315_AMBACLK (AR2315_DSLBASE + 0x0070)
1022 +#define AR2315_SYNCCLK (AR2315_DSLBASE + 0x0074)
1023 +#define AR2315_DSL_SLEEP_CTL (AR2315_DSLBASE + 0x0080)
1024 +#define AR2315_DSL_SLEEP_DUR (AR2315_DSLBASE + 0x0084)
1025 +
1026 +/* PLLc Control fields */
1027 +#define PLLC_REF_DIV_M 0x00000003
1028 +#define PLLC_REF_DIV_S 0
1029 +#define PLLC_FDBACK_DIV_M 0x0000007C
1030 +#define PLLC_FDBACK_DIV_S 2
1031 +#define PLLC_ADD_FDBACK_DIV_M 0x00000080
1032 +#define PLLC_ADD_FDBACK_DIV_S 7
1033 +#define PLLC_CLKC_DIV_M 0x0001c000
1034 +#define PLLC_CLKC_DIV_S 14
1035 +#define PLLC_CLKM_DIV_M 0x00700000
1036 +#define PLLC_CLKM_DIV_S 20
1037 +
1038 +/* CPU CLK Control fields */
1039 +#define CPUCLK_CLK_SEL_M 0x00000003
1040 +#define CPUCLK_CLK_SEL_S 0
1041 +#define CPUCLK_CLK_DIV_M 0x0000000c
1042 +#define CPUCLK_CLK_DIV_S 2
1043 +
1044 +/* AMBA CLK Control fields */
1045 +#define AMBACLK_CLK_SEL_M 0x00000003
1046 +#define AMBACLK_CLK_SEL_S 0
1047 +#define AMBACLK_CLK_DIV_M 0x0000000c
1048 +#define AMBACLK_CLK_DIV_S 2
1049 +
1050 +/*
1051 + * GPIO
1052 + */
1053 +#define AR2315_GPIO_DI (AR2315_DSLBASE + 0x0088)
1054 +#define AR2315_GPIO_DO (AR2315_DSLBASE + 0x0090)
1055 +#define AR2315_GPIO_DIR (AR2315_DSLBASE + 0x0098)
1056 +#define AR2315_GPIO_INT (AR2315_DSLBASE + 0x00a0)
1057 +
1058 +#define AR2315_GPIO_DIR_M(x) (1 << (x)) /* mask for i/o */
1059 +#define AR2315_GPIO_DIR_O(x) (1 << (x)) /* output */
1060 +#define AR2315_GPIO_DIR_I(x) (0) /* input */
1061 +
1062 +#define AR2315_GPIO_INT_S(x) (x) /* interrupt enable */
1063 +#define AR2315_GPIO_INT_M (0x3F) /* mask for int */
1064 +#define AR2315_GPIO_INT_LVL(x) ((x) << 6) /* interrupt level */
1065 +#define AR2315_GPIO_INT_LVL_M ((0x3) << 6) /* mask for int level */
1066 +
1067 +#define AR2315_GPIO_INT_MAX_Y 1 /* Maximum value of Y for
1068 + * AR2315_GPIO_INT_* macros */
1069 +#define AR2315_GPIO_INT_LVL_OFF 0 /* Triggerring off */
1070 +#define AR2315_GPIO_INT_LVL_LOW 1 /* Low Level Triggered */
1071 +#define AR2315_GPIO_INT_LVL_HIGH 2 /* High Level Triggered */
1072 +#define AR2315_GPIO_INT_LVL_EDGE 3 /* Edge Triggered */
1073 +
1074 +#define AR2315_RESET_GPIO 5
1075 +#define AR2315_NUM_GPIO 22
1076 +
1077 +/*
1078 + * PCI Clock Control
1079 + */
1080 +#define AR2315_PCICLK (AR2315_DSLBASE + 0x00a4)
1081 +
1082 +#define AR2315_PCICLK_INPUT_M 0x3
1083 +#define AR2315_PCICLK_INPUT_S 0
1084 +
1085 +#define AR2315_PCICLK_PLLC_CLKM 0
1086 +#define AR2315_PCICLK_PLLC_CLKM1 1
1087 +#define AR2315_PCICLK_PLLC_CLKC 2
1088 +#define AR2315_PCICLK_REF_CLK 3
1089 +
1090 +#define AR2315_PCICLK_DIV_M 0xc
1091 +#define AR2315_PCICLK_DIV_S 2
1092 +
1093 +#define AR2315_PCICLK_IN_FREQ 0
1094 +#define AR2315_PCICLK_IN_FREQ_DIV_6 1
1095 +#define AR2315_PCICLK_IN_FREQ_DIV_8 2
1096 +#define AR2315_PCICLK_IN_FREQ_DIV_10 3
1097 +
1098 +/*
1099 + * Observation Control Register
1100 + */
1101 +#define AR2315_OCR (AR2315_DSLBASE + 0x00b0)
1102 +#define OCR_GPIO0_IRIN 0x0040
1103 +#define OCR_GPIO1_IROUT 0x0080
1104 +#define OCR_GPIO3_RXCLR 0x0200
1105 +
1106 +/*
1107 + * General Clock Control
1108 + */
1109 +
1110 +#define AR2315_MISCCLK (AR2315_DSLBASE + 0x00b4)
1111 +#define MISCCLK_PLLBYPASS_EN 0x00000001
1112 +#define MISCCLK_PROCREFCLK 0x00000002
1113 +
1114 +/*
1115 + * SDRAM Controller
1116 + * - No read or write buffers are included.
1117 + */
1118 +#define AR2315_MEM_CFG (AR2315_SDRAMCTL + 0x00)
1119 +#define AR2315_MEM_CTRL (AR2315_SDRAMCTL + 0x0c)
1120 +#define AR2315_MEM_REF (AR2315_SDRAMCTL + 0x10)
1121 +
1122 +#define SDRAM_DATA_WIDTH_M 0x00006000
1123 +#define SDRAM_DATA_WIDTH_S 13
1124 +
1125 +#define SDRAM_COL_WIDTH_M 0x00001E00
1126 +#define SDRAM_COL_WIDTH_S 9
1127 +
1128 +#define SDRAM_ROW_WIDTH_M 0x000001E0
1129 +#define SDRAM_ROW_WIDTH_S 5
1130 +
1131 +#define SDRAM_BANKADDR_BITS_M 0x00000018
1132 +#define SDRAM_BANKADDR_BITS_S 3
1133 +
1134 +/*
1135 + * PCI Bus Interface Registers
1136 + */
1137 +#define AR2315_PCI_1MS_REG (AR2315_PCI + 0x0008)
1138 +#define AR2315_PCI_1MS_MASK 0x3FFFF /* # of AHB clk cycles in 1ms */
1139 +
1140 +#define AR2315_PCI_MISC_CONFIG (AR2315_PCI + 0x000c)
1141 +#define AR2315_PCIMISC_TXD_EN 0x00000001 /* Enable TXD for fragments */
1142 +#define AR2315_PCIMISC_CFG_SEL 0x00000002 /* mem or config cycles */
1143 +#define AR2315_PCIMISC_GIG_MASK 0x0000000C /* bits 31-30 for pci req */
1144 +#define AR2315_PCIMISC_RST_MODE 0x00000030
1145 +#define AR2315_PCIRST_INPUT 0x00000000 /* 4:5=0 rst is input */
1146 +#define AR2315_PCIRST_LOW 0x00000010 /* 4:5=1 rst to GND */
1147 +#define AR2315_PCIRST_HIGH 0x00000020 /* 4:5=2 rst to VDD */
1148 +#define AR2315_PCIGRANT_EN 0x00000000 /* 6:7=0 early grant en */
1149 +#define AR2315_PCIGRANT_FRAME 0x00000040 /* 6:7=1 grant waits 4 frame */
1150 +#define AR2315_PCIGRANT_IDLE 0x00000080 /* 6:7=2 grant waits 4 idle */
1151 +#define AR2315_PCIGRANT_GAP 0x00000000 /* 6:7=2 grant waits 4 idle */
1152 +#define AR2315_PCICACHE_DIS 0x00001000 /* PCI external access cache
1153 + * disable */
1154 +
1155 +#define AR2315_PCI_OUT_TSTAMP (AR2315_PCI + 0x0010)
1156 +
1157 +#define AR2315_PCI_UNCACHE_CFG (AR2315_PCI + 0x0014)
1158 +
1159 +#define AR2315_PCI_IN_EN (AR2315_PCI + 0x0100)
1160 +#define AR2315_PCI_IN_EN0 0x01 /* Enable chain 0 */
1161 +#define AR2315_PCI_IN_EN1 0x02 /* Enable chain 1 */
1162 +#define AR2315_PCI_IN_EN2 0x04 /* Enable chain 2 */
1163 +#define AR2315_PCI_IN_EN3 0x08 /* Enable chain 3 */
1164 +
1165 +#define AR2315_PCI_IN_DIS (AR2315_PCI + 0x0104)
1166 +#define AR2315_PCI_IN_DIS0 0x01 /* Disable chain 0 */
1167 +#define AR2315_PCI_IN_DIS1 0x02 /* Disable chain 1 */
1168 +#define AR2315_PCI_IN_DIS2 0x04 /* Disable chain 2 */
1169 +#define AR2315_PCI_IN_DIS3 0x08 /* Disable chain 3 */
1170 +
1171 +#define AR2315_PCI_IN_PTR (AR2315_PCI + 0x0200)
1172 +
1173 +#define AR2315_PCI_OUT_EN (AR2315_PCI + 0x0400)
1174 +#define AR2315_PCI_OUT_EN0 0x01 /* Enable chain 0 */
1175 +
1176 +#define AR2315_PCI_OUT_DIS (AR2315_PCI + 0x0404)
1177 +#define AR2315_PCI_OUT_DIS0 0x01 /* Disable chain 0 */
1178 +
1179 +#define AR2315_PCI_OUT_PTR (AR2315_PCI + 0x0408)
1180 +
1181 +#define AR2315_PCI_INT_STATUS (AR2315_PCI + 0x0500) /* write one to clr */
1182 +#define AR2315_PCI_TXINT 0x00000001 /* Desc In Completed */
1183 +#define AR2315_PCI_TXOK 0x00000002 /* Desc In OK */
1184 +#define AR2315_PCI_TXERR 0x00000004 /* Desc In ERR */
1185 +#define AR2315_PCI_TXEOL 0x00000008 /* Desc In End-of-List */
1186 +#define AR2315_PCI_RXINT 0x00000010 /* Desc Out Completed */
1187 +#define AR2315_PCI_RXOK 0x00000020 /* Desc Out OK */
1188 +#define AR2315_PCI_RXERR 0x00000040 /* Desc Out ERR */
1189 +#define AR2315_PCI_RXEOL 0x00000080 /* Desc Out EOL */
1190 +#define AR2315_PCI_TXOOD 0x00000200 /* Desc In Out-of-Desc */
1191 +#define AR2315_PCI_MASK 0x0000FFFF /* Desc Mask */
1192 +#define AR2315_PCI_EXT_INT 0x02000000
1193 +#define AR2315_PCI_ABORT_INT 0x04000000
1194 +
1195 +#define AR2315_PCI_INT_MASK (AR2315_PCI + 0x0504) /* same as INT_STATUS */
1196 +
1197 +#define AR2315_PCI_INTEN_REG (AR2315_PCI + 0x0508)
1198 +#define AR2315_PCI_INT_DISABLE 0x00 /* disable pci interrupts */
1199 +#define AR2315_PCI_INT_ENABLE 0x01 /* enable pci interrupts */
1200 +
1201 +#define AR2315_PCI_HOST_IN_EN (AR2315_PCI + 0x0800)
1202 +#define AR2315_PCI_HOST_IN_DIS (AR2315_PCI + 0x0804)
1203 +#define AR2315_PCI_HOST_IN_PTR (AR2315_PCI + 0x0810)
1204 +#define AR2315_PCI_HOST_OUT_EN (AR2315_PCI + 0x0900)
1205 +#define AR2315_PCI_HOST_OUT_DIS (AR2315_PCI + 0x0904)
1206 +#define AR2315_PCI_HOST_OUT_PTR (AR2315_PCI + 0x0908)
1207 +
1208 +
1209 +/*
1210 + * Local Bus Interface Registers
1211 + */
1212 +#define AR2315_LB_CONFIG (AR2315_LOCAL + 0x0000)
1213 +#define AR2315_LBCONF_OE 0x00000001 /* =1 OE is low-true */
1214 +#define AR2315_LBCONF_CS0 0x00000002 /* =1 first CS is low-true */
1215 +#define AR2315_LBCONF_CS1 0x00000004 /* =1 2nd CS is low-true */
1216 +#define AR2315_LBCONF_RDY 0x00000008 /* =1 RDY is low-true */
1217 +#define AR2315_LBCONF_WE 0x00000010 /* =1 Write En is low-true */
1218 +#define AR2315_LBCONF_WAIT 0x00000020 /* =1 WAIT is low-true */
1219 +#define AR2315_LBCONF_ADS 0x00000040 /* =1 Adr Strobe is low-true */
1220 +#define AR2315_LBCONF_MOT 0x00000080 /* =0 Intel, =1 Motorola */
1221 +#define AR2315_LBCONF_8CS 0x00000100 /* =1 8 bits CS, 0= 16bits */
1222 +#define AR2315_LBCONF_8DS 0x00000200 /* =1 8 bits Data S, 0=16bits */
1223 +#define AR2315_LBCONF_ADS_EN 0x00000400 /* =1 Enable ADS */
1224 +#define AR2315_LBCONF_ADR_OE 0x00000800 /* =1 Adr cap on OE, WE or DS */
1225 +#define AR2315_LBCONF_ADDT_MUX 0x00001000 /* =1 Adr and Data share bus */
1226 +#define AR2315_LBCONF_DATA_OE 0x00002000 /* =1 Data cap on OE, WE, DS */
1227 +#define AR2315_LBCONF_16DATA 0x00004000 /* =1 Data is 16 bits wide */
1228 +#define AR2315_LBCONF_SWAPDT 0x00008000 /* =1 Byte swap data */
1229 +#define AR2315_LBCONF_SYNC 0x00010000 /* =1 Bus synchronous to clk */
1230 +#define AR2315_LBCONF_INT 0x00020000 /* =1 Intr is low true */
1231 +#define AR2315_LBCONF_INT_CTR0 0x00000000 /* GND high-Z, Vdd is high-Z */
1232 +#define AR2315_LBCONF_INT_CTR1 0x00040000 /* GND drive, Vdd is high-Z */
1233 +#define AR2315_LBCONF_INT_CTR2 0x00080000 /* GND high-Z, Vdd drive */
1234 +#define AR2315_LBCONF_INT_CTR3 0x000C0000 /* GND drive, Vdd drive */
1235 +#define AR2315_LBCONF_RDY_WAIT 0x00100000 /* =1 RDY is negative of WAIT */
1236 +#define AR2315_LBCONF_INT_PULSE 0x00200000 /* =1 Interrupt is a pulse */
1237 +#define AR2315_LBCONF_ENABLE 0x00400000 /* =1 Falcon respond to LB */
1238 +
1239 +#define AR2315_LB_CLKSEL (AR2315_LOCAL + 0x0004)
1240 +#define AR2315_LBCLK_EXT 0x0001 /* use external clk for lb */
1241 +
1242 +#define AR2315_LB_1MS (AR2315_LOCAL + 0x0008)
1243 +#define AR2315_LB1MS_MASK 0x3FFFF /* # of AHB clk cycles in 1ms */
1244 +
1245 +#define AR2315_LB_MISCCFG (AR2315_LOCAL + 0x000C)
1246 +#define AR2315_LBM_TXD_EN 0x00000001 /* Enable TXD for fragments */
1247 +#define AR2315_LBM_RX_INTEN 0x00000002 /* Enable LB ints on RX ready */
1248 +#define AR2315_LBM_MBOXWR_INTEN 0x00000004 /* Enable LB ints on mbox wr */
1249 +#define AR2315_LBM_MBOXRD_INTEN 0x00000008 /* Enable LB ints on mbox rd */
1250 +#define AR2315_LMB_DESCSWAP_EN 0x00000010 /* Byte swap desc enable */
1251 +#define AR2315_LBM_TIMEOUT_MASK 0x00FFFF80
1252 +#define AR2315_LBM_TIMEOUT_SHFT 7
1253 +#define AR2315_LBM_PORTMUX 0x07000000
1254 +
1255 +
1256 +#define AR2315_LB_RXTSOFF (AR2315_LOCAL + 0x0010)
1257 +
1258 +#define AR2315_LB_TX_CHAIN_EN (AR2315_LOCAL + 0x0100)
1259 +#define AR2315_LB_TXEN_0 0x01
1260 +#define AR2315_LB_TXEN_1 0x02
1261 +#define AR2315_LB_TXEN_2 0x04
1262 +#define AR2315_LB_TXEN_3 0x08
1263 +
1264 +#define AR2315_LB_TX_CHAIN_DIS (AR2315_LOCAL + 0x0104)
1265 +#define AR2315_LB_TX_DESC_PTR (AR2315_LOCAL + 0x0200)
1266 +
1267 +#define AR2315_LB_RX_CHAIN_EN (AR2315_LOCAL + 0x0400)
1268 +#define AR2315_LB_RXEN 0x01
1269 +
1270 +#define AR2315_LB_RX_CHAIN_DIS (AR2315_LOCAL + 0x0404)
1271 +#define AR2315_LB_RX_DESC_PTR (AR2315_LOCAL + 0x0408)
1272 +
1273 +#define AR2315_LB_INT_STATUS (AR2315_LOCAL + 0x0500)
1274 +#define AR2315_INT_TX_DESC 0x0001
1275 +#define AR2315_INT_TX_OK 0x0002
1276 +#define AR2315_INT_TX_ERR 0x0004
1277 +#define AR2315_INT_TX_EOF 0x0008
1278 +#define AR2315_INT_RX_DESC 0x0010
1279 +#define AR2315_INT_RX_OK 0x0020
1280 +#define AR2315_INT_RX_ERR 0x0040
1281 +#define AR2315_INT_RX_EOF 0x0080
1282 +#define AR2315_INT_TX_TRUNC 0x0100
1283 +#define AR2315_INT_TX_STARVE 0x0200
1284 +#define AR2315_INT_LB_TIMEOUT 0x0400
1285 +#define AR2315_INT_LB_ERR 0x0800
1286 +#define AR2315_INT_MBOX_WR 0x1000
1287 +#define AR2315_INT_MBOX_RD 0x2000
1288 +
1289 +/* Bit definitions for INT MASK are the same as INT_STATUS */
1290 +#define AR2315_LB_INT_MASK (AR2315_LOCAL + 0x0504)
1291 +
1292 +#define AR2315_LB_INT_EN (AR2315_LOCAL + 0x0508)
1293 +#define AR2315_LB_MBOX (AR2315_LOCAL + 0x0600)
1294 +
1295 +/*
1296 + * IR Interface Registers
1297 + */
1298 +#define AR2315_IR_PKTDATA (AR2315_IR + 0x0000)
1299 +
1300 +#define AR2315_IR_PKTLEN (AR2315_IR + 0x07fc) /* 0 - 63 */
1301 +
1302 +#define AR2315_IR_CONTROL (AR2315_IR + 0x0800)
1303 +#define AR2315_IRCTL_TX 0x00000000 /* use as tranmitter */
1304 +#define AR2315_IRCTL_RX 0x00000001 /* use as receiver */
1305 +#define AR2315_IRCTL_SAMPLECLK_MASK 0x00003ffe /* Sample clk divisor */
1306 +#define AR2315_IRCTL_SAMPLECLK_SHFT 1
1307 +#define AR2315_IRCTL_OUTPUTCLK_MASK 0x03ffc000 /* Output clk div */
1308 +#define AR2315_IRCTL_OUTPUTCLK_SHFT 14
1309 +
1310 +#define AR2315_IR_STATUS (AR2315_IR + 0x0804)
1311 +#define AR2315_IRSTS_RX 0x00000001 /* receive in progress */
1312 +#define AR2315_IRSTS_TX 0x00000002 /* transmit in progress */
1313 +
1314 +#define AR2315_IR_CONFIG (AR2315_IR + 0x0808)
1315 +#define AR2315_IRCFG_INVIN 0x00000001 /* invert in polarity */
1316 +#define AR2315_IRCFG_INVOUT 0x00000002 /* invert out polarity */
1317 +#define AR2315_IRCFG_SEQ_START_WIN_SEL 0x00000004 /* 1 => 28, 0 => 7 */
1318 +#define AR2315_IRCFG_SEQ_START_THRESH 0x000000f0
1319 +#define AR2315_IRCFG_SEQ_END_UNIT_SEL 0x00000100
1320 +#define AR2315_IRCFG_SEQ_END_UNIT_THRESH 0x00007e00
1321 +#define AR2315_IRCFG_SEQ_END_WIN_SEL 0x00008000
1322 +#define AR2315_IRCFG_SEQ_END_WIN_THRESH 0x001f0000
1323 +#define AR2315_IRCFG_NUM_BACKOFF_WORDS 0x01e00000
1324 +
1325 +#define HOST_PCI_DEV_ID 3
1326 +#define HOST_PCI_MBAR0 0x10000000
1327 +#define HOST_PCI_MBAR1 0x20000000
1328 +#define HOST_PCI_MBAR2 0x30000000
1329 +
1330 +#define HOST_PCI_SDRAM_BASEADDR HOST_PCI_MBAR1
1331 +#define PCI_DEVICE_MEM_SPACE 0x800000
1332 +
1333 +#endif /* __ASM_MACH_AR231X_AR2315_REGS_H */
1334 --- /dev/null
1335 +++ b/arch/mips/include/asm/mach-ar231x/ar5312_regs.h
1336 @@ -0,0 +1,253 @@
1337 +/*
1338 + * This file is subject to the terms and conditions of the GNU General Public
1339 + * License. See the file "COPYING" in the main directory of this archive
1340 + * for more details.
1341 + *
1342 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
1343 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
1344 + * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
1345 + */
1346 +
1347 +#ifndef __ASM_MACH_AR231X_AR5312_REGS_H
1348 +#define __ASM_MACH_AR231X_AR5312_REGS_H
1349 +
1350 +#include <asm/addrspace.h>
1351 +
1352 +/*
1353 + * IRQs
1354 + */
1355 +
1356 +#define AR5312_IRQ_WLAN0_INTRS (MIPS_CPU_IRQ_BASE+2) /* C0_CAUSE: 0x0400 */
1357 +#define AR5312_IRQ_ENET0_INTRS (MIPS_CPU_IRQ_BASE+3) /* C0_CAUSE: 0x0800 */
1358 +#define AR5312_IRQ_ENET1_INTRS (MIPS_CPU_IRQ_BASE+4) /* C0_CAUSE: 0x1000 */
1359 +#define AR5312_IRQ_WLAN1_INTRS (MIPS_CPU_IRQ_BASE+5) /* C0_CAUSE: 0x2000 */
1360 +#define AR5312_IRQ_MISC_INTRS (MIPS_CPU_IRQ_BASE+6) /* C0_CAUSE: 0x4000 */
1361 +
1362 +
1363 +/*
1364 + * Miscellaneous interrupts, which share IP6.
1365 + */
1366 +#define AR5312_MISC_IRQ_NONE (AR231X_MISC_IRQ_BASE+0)
1367 +#define AR5312_MISC_IRQ_TIMER (AR231X_MISC_IRQ_BASE+1)
1368 +#define AR5312_MISC_IRQ_AHB_PROC (AR231X_MISC_IRQ_BASE+2)
1369 +#define AR5312_MISC_IRQ_AHB_DMA (AR231X_MISC_IRQ_BASE+3)
1370 +#define AR5312_MISC_IRQ_GPIO (AR231X_MISC_IRQ_BASE+4)
1371 +#define AR5312_MISC_IRQ_UART0 (AR231X_MISC_IRQ_BASE+5)
1372 +#define AR5312_MISC_IRQ_UART0_DMA (AR231X_MISC_IRQ_BASE+6)
1373 +#define AR5312_MISC_IRQ_WATCHDOG (AR231X_MISC_IRQ_BASE+7)
1374 +#define AR5312_MISC_IRQ_LOCAL (AR231X_MISC_IRQ_BASE+8)
1375 +#define AR5312_MISC_IRQ_SPI (AR231X_MISC_IRQ_BASE+9)
1376 +#define AR5312_MISC_IRQ_COUNT 10
1377 +
1378 +
1379 +/* Address Map */
1380 +#define AR5312_WLAN0 0x18000000
1381 +#define AR5312_WLAN1 0x18500000
1382 +#define AR5312_ENET0 0x18100000
1383 +#define AR5312_ENET1 0x18200000
1384 +#define AR5312_SDRAMCTL 0x18300000
1385 +#define AR5312_FLASHCTL 0x18400000
1386 +#define AR5312_APBBASE 0x1c000000
1387 +#define AR5312_UART0 0x1c000000 /* UART MMR */
1388 +#define AR5312_FLASH 0x1e000000
1389 +
1390 +/*
1391 + * AR5312_NUM_ENET_MAC defines the number of ethernet MACs that
1392 + * should be considered available. The AR5312 supports 2 enet MACS,
1393 + * even though many reference boards only actually use 1 of them
1394 + * (i.e. Only MAC 0 is actually connected to an enet PHY or PHY switch.
1395 + * The AR2312 supports 1 enet MAC.
1396 + */
1397 +#define AR5312_NUM_ENET_MAC 2
1398 +
1399 +/*
1400 + * Need these defines to determine true number of ethernet MACs
1401 + */
1402 +#define AR5312_AR5312_REV2 0x0052 /* AR5312 WMAC (AP31) */
1403 +#define AR5312_AR5312_REV7 0x0057 /* AR5312 WMAC (AP30-040) */
1404 +#define AR5312_AR2313_REV8 0x0058 /* AR2313 WMAC (AP43-030) */
1405 +
1406 +/* MII registers offset inside Ethernet MMR region */
1407 +#define AR5312_ENET0_MII (AR5312_ENET0 + 0x14)
1408 +#define AR5312_ENET1_MII (AR5312_ENET1 + 0x14)
1409 +
1410 +/*
1411 + * AR5312_NUM_WMAC defines the number of Wireless MACs that\
1412 + * should be considered available.
1413 + */
1414 +#define AR5312_NUM_WMAC 2
1415 +
1416 +/* Reset/Timer Block Address Map */
1417 +#define AR5312_RESETTMR (AR5312_APBBASE + 0x3000)
1418 +#define AR5312_TIMER (AR5312_RESETTMR + 0x0000) /* countdown timer */
1419 +#define AR5312_WD_CTRL (AR5312_RESETTMR + 0x0008) /* watchdog cntrl */
1420 +#define AR5312_WD_TIMER (AR5312_RESETTMR + 0x000c) /* watchdog timer */
1421 +#define AR5312_ISR (AR5312_RESETTMR + 0x0010) /* Intr Status Reg */
1422 +#define AR5312_IMR (AR5312_RESETTMR + 0x0014) /* Intr Mask Reg */
1423 +#define AR5312_RESET (AR5312_RESETTMR + 0x0020)
1424 +#define AR5312_CLOCKCTL1 (AR5312_RESETTMR + 0x0064)
1425 +#define AR5312_SCRATCH (AR5312_RESETTMR + 0x006c)
1426 +#define AR5312_PROCADDR (AR5312_RESETTMR + 0x0070)
1427 +#define AR5312_PROC1 (AR5312_RESETTMR + 0x0074)
1428 +#define AR5312_DMAADDR (AR5312_RESETTMR + 0x0078)
1429 +#define AR5312_DMA1 (AR5312_RESETTMR + 0x007c)
1430 +#define AR5312_ENABLE (AR5312_RESETTMR + 0x0080) /* interface enb */
1431 +#define AR5312_REV (AR5312_RESETTMR + 0x0090) /* revision */
1432 +
1433 +/* AR5312_WD_CTRL register bit field definitions */
1434 +#define AR5312_WD_CTRL_IGNORE_EXPIRATION 0x0000
1435 +#define AR5312_WD_CTRL_NMI 0x0001
1436 +#define AR5312_WD_CTRL_RESET 0x0002
1437 +
1438 +/* AR5312_ISR register bit field definitions */
1439 +#define AR5312_ISR_NONE 0x0000
1440 +#define AR5312_ISR_TIMER 0x0001
1441 +#define AR5312_ISR_AHBPROC 0x0002
1442 +#define AR5312_ISR_AHBDMA 0x0004
1443 +#define AR5312_ISR_GPIO 0x0008
1444 +#define AR5312_ISR_UART0 0x0010
1445 +#define AR5312_ISR_UART0DMA 0x0020
1446 +#define AR5312_ISR_WD 0x0040
1447 +#define AR5312_ISR_LOCAL 0x0080
1448 +
1449 +/* AR5312_RESET register bit field definitions */
1450 +#define AR5312_RESET_SYSTEM 0x00000001 /* cold reset full system */
1451 +#define AR5312_RESET_PROC 0x00000002 /* cold reset MIPS core */
1452 +#define AR5312_RESET_WLAN0 0x00000004 /* cold reset WLAN MAC and BB */
1453 +#define AR5312_RESET_EPHY0 0x00000008 /* cold reset ENET0 phy */
1454 +#define AR5312_RESET_EPHY1 0x00000010 /* cold reset ENET1 phy */
1455 +#define AR5312_RESET_ENET0 0x00000020 /* cold reset ENET0 mac */
1456 +#define AR5312_RESET_ENET1 0x00000040 /* cold reset ENET1 mac */
1457 +#define AR5312_RESET_UART0 0x00000100 /* cold reset UART0 (high speed) */
1458 +#define AR5312_RESET_WLAN1 0x00000200 /* cold reset WLAN MAC/BB */
1459 +#define AR5312_RESET_APB 0x00000400 /* cold reset APB (ar5312) */
1460 +#define AR5312_RESET_WARM_PROC 0x00001000 /* warm reset MIPS core */
1461 +#define AR5312_RESET_WARM_WLAN0_MAC 0x00002000 /* warm reset WLAN0 MAC */
1462 +#define AR5312_RESET_WARM_WLAN0_BB 0x00004000 /* warm reset WLAN0 BaseBand */
1463 +#define AR5312_RESET_NMI 0x00010000 /* send an NMI to the processor */
1464 +#define AR5312_RESET_WARM_WLAN1_MAC 0x00020000 /* warm reset WLAN1 mac */
1465 +#define AR5312_RESET_WARM_WLAN1_BB 0x00040000 /* warm reset WLAN1 baseband */
1466 +#define AR5312_RESET_LOCAL_BUS 0x00080000 /* reset local bus */
1467 +#define AR5312_RESET_WDOG 0x00100000 /* last reset was a watchdog */
1468 +
1469 +#define AR5312_RESET_WMAC0_BITS \
1470 + (AR5312_RESET_WLAN0 |\
1471 + AR5312_RESET_WARM_WLAN0_MAC |\
1472 + AR5312_RESET_WARM_WLAN0_BB)
1473 +
1474 +#define AR5312_RESET_WMAC1_BITS \
1475 + (AR5312_RESET_WLAN1 |\
1476 + AR5312_RESET_WARM_WLAN1_MAC |\
1477 + AR5312_RESET_WARM_WLAN1_BB)
1478 +
1479 +/* AR5312_CLOCKCTL1 register bit field definitions */
1480 +#define AR5312_CLOCKCTL1_PREDIVIDE_MASK 0x00000030
1481 +#define AR5312_CLOCKCTL1_PREDIVIDE_SHIFT 4
1482 +#define AR5312_CLOCKCTL1_MULTIPLIER_MASK 0x00001f00
1483 +#define AR5312_CLOCKCTL1_MULTIPLIER_SHIFT 8
1484 +#define AR5312_CLOCKCTL1_DOUBLER_MASK 0x00010000
1485 +
1486 +/* Valid for AR5312 and AR2312 */
1487 +#define AR5312_CLOCKCTL1_PREDIVIDE_MASK 0x00000030
1488 +#define AR5312_CLOCKCTL1_PREDIVIDE_SHIFT 4
1489 +#define AR5312_CLOCKCTL1_MULTIPLIER_MASK 0x00001f00
1490 +#define AR5312_CLOCKCTL1_MULTIPLIER_SHIFT 8
1491 +#define AR5312_CLOCKCTL1_DOUBLER_MASK 0x00010000
1492 +
1493 +/* Valid for AR2313 */
1494 +#define AR2313_CLOCKCTL1_PREDIVIDE_MASK 0x00003000
1495 +#define AR2313_CLOCKCTL1_PREDIVIDE_SHIFT 12
1496 +#define AR2313_CLOCKCTL1_MULTIPLIER_MASK 0x001f0000
1497 +#define AR2313_CLOCKCTL1_MULTIPLIER_SHIFT 16
1498 +#define AR2313_CLOCKCTL1_DOUBLER_MASK 0x00000000
1499 +
1500 +
1501 +/* AR5312_ENABLE register bit field definitions */
1502 +#define AR5312_ENABLE_WLAN0 0x0001
1503 +#define AR5312_ENABLE_ENET0 0x0002
1504 +#define AR5312_ENABLE_ENET1 0x0004
1505 +#define AR5312_ENABLE_UART_AND_WLAN1_PIO 0x0008 /* UART, and WLAN1 PIOs */
1506 +#define AR5312_ENABLE_WLAN1_DMA 0x0010 /* WLAN1 DMAs */
1507 +#define AR5312_ENABLE_WLAN1 \
1508 + (AR5312_ENABLE_UART_AND_WLAN1_PIO |\
1509 + AR5312_ENABLE_WLAN1_DMA)
1510 +
1511 +/* AR5312_REV register bit field definitions */
1512 +#define AR5312_REV_WMAC_MAJ 0xf000
1513 +#define AR5312_REV_WMAC_MAJ_S 12
1514 +#define AR5312_REV_WMAC_MIN 0x0f00
1515 +#define AR5312_REV_WMAC_MIN_S 8
1516 +#define AR5312_REV_MAJ 0x00f0
1517 +#define AR5312_REV_MAJ_S 4
1518 +#define AR5312_REV_MIN 0x000f
1519 +#define AR5312_REV_MIN_S 0
1520 +#define AR5312_REV_CHIP (AR5312_REV_MAJ|AR5312_REV_MIN)
1521 +
1522 +/* Major revision numbers, bits 7..4 of Revision ID register */
1523 +#define AR5312_REV_MAJ_AR5312 0x4
1524 +#define AR5312_REV_MAJ_AR2313 0x5
1525 +
1526 +/* Minor revision numbers, bits 3..0 of Revision ID register */
1527 +#define AR5312_REV_MIN_DUAL 0x0 /* Dual WLAN version */
1528 +#define AR5312_REV_MIN_SINGLE 0x1 /* Single WLAN version */
1529 +
1530 +/* AR5312_FLASHCTL register bit field definitions */
1531 +#define FLASHCTL_IDCY 0x0000000f /* Idle cycle turn around time */
1532 +#define FLASHCTL_IDCY_S 0
1533 +#define FLASHCTL_WST1 0x000003e0 /* Wait state 1 */
1534 +#define FLASHCTL_WST1_S 5
1535 +#define FLASHCTL_RBLE 0x00000400 /* Read byte lane enable */
1536 +#define FLASHCTL_WST2 0x0000f800 /* Wait state 2 */
1537 +#define FLASHCTL_WST2_S 11
1538 +#define FLASHCTL_AC 0x00070000 /* Flash address check (added) */
1539 +#define FLASHCTL_AC_S 16
1540 +#define FLASHCTL_AC_128K 0x00000000
1541 +#define FLASHCTL_AC_256K 0x00010000
1542 +#define FLASHCTL_AC_512K 0x00020000
1543 +#define FLASHCTL_AC_1M 0x00030000
1544 +#define FLASHCTL_AC_2M 0x00040000
1545 +#define FLASHCTL_AC_4M 0x00050000
1546 +#define FLASHCTL_AC_8M 0x00060000
1547 +#define FLASHCTL_AC_RES 0x00070000 /* 16MB is not supported */
1548 +#define FLASHCTL_E 0x00080000 /* Flash bank enable (added) */
1549 +#define FLASHCTL_BUSERR 0x01000000 /* Bus transfer error status flag */
1550 +#define FLASHCTL_WPERR 0x02000000 /* Write protect error status flag */
1551 +#define FLASHCTL_WP 0x04000000 /* Write protect */
1552 +#define FLASHCTL_BM 0x08000000 /* Burst mode */
1553 +#define FLASHCTL_MW 0x30000000 /* Memory width */
1554 +#define FLASHCTL_MWx8 0x00000000 /* Memory width x8 */
1555 +#define FLASHCTL_MWx16 0x10000000 /* Memory width x16 */
1556 +#define FLASHCTL_MWx32 0x20000000 /* Memory width x32 (not supported) */
1557 +#define FLASHCTL_ATNR 0x00000000 /* Access type == no retry */
1558 +#define FLASHCTL_ATR 0x80000000 /* Access type == retry every */
1559 +#define FLASHCTL_ATR4 0xc0000000 /* Access type == retry every 4 */
1560 +
1561 +/* ARM Flash Controller -- 3 flash banks with either x8 or x16 devices. */
1562 +#define AR5312_FLASHCTL0 (AR5312_FLASHCTL + 0x00)
1563 +#define AR5312_FLASHCTL1 (AR5312_FLASHCTL + 0x04)
1564 +#define AR5312_FLASHCTL2 (AR5312_FLASHCTL + 0x08)
1565 +
1566 +/* ARM SDRAM Controller -- just enough to determine memory size */
1567 +#define AR5312_MEM_CFG1 (AR5312_SDRAMCTL + 0x04)
1568 +#define MEM_CFG1_AC0 0x00000700 /* bank 0: SDRAM addr check (added) */
1569 +#define MEM_CFG1_AC0_S 8
1570 +#define MEM_CFG1_AC1 0x00007000 /* bank 1: SDRAM addr check (added) */
1571 +#define MEM_CFG1_AC1_S 12
1572 +
1573 +/* GPIO Address Map */
1574 +#define AR5312_GPIO (AR5312_APBBASE + 0x2000)
1575 +#define AR5312_GPIO_DO (AR5312_GPIO + 0x00) /* output register */
1576 +#define AR5312_GPIO_DI (AR5312_GPIO + 0x04) /* intput register */
1577 +#define AR5312_GPIO_CR (AR5312_GPIO + 0x08) /* control register */
1578 +
1579 +/* GPIO Control Register bit field definitions */
1580 +#define AR5312_GPIO_CR_M(x) (1 << (x)) /* mask for i/o */
1581 +#define AR5312_GPIO_CR_O(x) (0 << (x)) /* mask for output */
1582 +#define AR5312_GPIO_CR_I(x) (1 << (x)) /* mask for input */
1583 +#define AR5312_GPIO_CR_INT(x) (1 << ((x)+8)) /* mask for interrupt*/
1584 +#define AR5312_GPIO_CR_UART(x) (1 << ((x)+16)) /* uart multiplex */
1585 +#define AR5312_NUM_GPIO 8
1586 +
1587 +
1588 +#endif /* __ASM_MACH_AR231X_AR5312_REGS_H */
1589 +
1590 --- /dev/null
1591 +++ b/arch/mips/ar231x/ar5312.c
1592 @@ -0,0 +1,540 @@
1593 +/*
1594 + * This file is subject to the terms and conditions of the GNU General Public
1595 + * License. See the file "COPYING" in the main directory of this archive
1596 + * for more details.
1597 + *
1598 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
1599 + * Copyright (C) 2006 FON Technology, SL.
1600 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
1601 + * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
1602 + * Copyright (C) 2012 Alexandros C. Couloumbis <alex@ozo.com>
1603 + */
1604 +
1605 +/*
1606 + * Platform devices for Atheros SoCs
1607 + */
1608 +
1609 +#include <generated/autoconf.h>
1610 +#include <linux/init.h>
1611 +#include <linux/module.h>
1612 +#include <linux/types.h>
1613 +#include <linux/string.h>
1614 +#include <linux/mtd/physmap.h>
1615 +#include <linux/platform_device.h>
1616 +#include <linux/kernel.h>
1617 +#include <linux/reboot.h>
1618 +#include <linux/leds.h>
1619 +#include <linux/gpio.h>
1620 +#include <asm/bootinfo.h>
1621 +#include <asm/reboot.h>
1622 +#include <asm/time.h>
1623 +#include <linux/irq.h>
1624 +#include <linux/io.h>
1625 +
1626 +#include <ar231x_platform.h>
1627 +#include <ar5312_regs.h>
1628 +#include <ar231x.h>
1629 +#include "devices.h"
1630 +#include "ar5312.h"
1631 +
1632 +static void ar5312_misc_irq_handler(unsigned irq, struct irq_desc *desc)
1633 +{
1634 + unsigned int ar231x_misc_intrs = ar231x_read_reg(AR5312_ISR) &
1635 + ar231x_read_reg(AR5312_IMR);
1636 +
1637 + if (ar231x_misc_intrs & AR5312_ISR_TIMER) {
1638 + do_IRQ(AR5312_MISC_IRQ_TIMER);
1639 + (void)ar231x_read_reg(AR5312_TIMER);
1640 + } else if (ar231x_misc_intrs & AR5312_ISR_AHBPROC)
1641 + do_IRQ(AR5312_MISC_IRQ_AHB_PROC);
1642 + else if ((ar231x_misc_intrs & AR5312_ISR_UART0))
1643 + do_IRQ(AR5312_MISC_IRQ_UART0);
1644 + else if (ar231x_misc_intrs & AR5312_ISR_WD)
1645 + do_IRQ(AR5312_MISC_IRQ_WATCHDOG);
1646 + else
1647 + do_IRQ(AR5312_MISC_IRQ_NONE);
1648 +}
1649 +
1650 +static asmlinkage void
1651 +ar5312_irq_dispatch(void)
1652 +{
1653 + int pending = read_c0_status() & read_c0_cause();
1654 +
1655 + if (pending & CAUSEF_IP2)
1656 + do_IRQ(AR5312_IRQ_WLAN0_INTRS);
1657 + else if (pending & CAUSEF_IP3)
1658 + do_IRQ(AR5312_IRQ_ENET0_INTRS);
1659 + else if (pending & CAUSEF_IP4)
1660 + do_IRQ(AR5312_IRQ_ENET1_INTRS);
1661 + else if (pending & CAUSEF_IP5)
1662 + do_IRQ(AR5312_IRQ_WLAN1_INTRS);
1663 + else if (pending & CAUSEF_IP6)
1664 + do_IRQ(AR5312_IRQ_MISC_INTRS);
1665 + else if (pending & CAUSEF_IP7)
1666 + do_IRQ(AR231X_IRQ_CPU_CLOCK);
1667 +}
1668 +
1669 +
1670 +/* Enable the specified AR5312_MISC_IRQ interrupt */
1671 +static void
1672 +ar5312_misc_irq_unmask(struct irq_data *d)
1673 +{
1674 + unsigned int imr;
1675 +
1676 + imr = ar231x_read_reg(AR5312_IMR);
1677 + imr |= (1 << (d->irq - AR231X_MISC_IRQ_BASE - 1));
1678 + ar231x_write_reg(AR5312_IMR, imr);
1679 +}
1680 +
1681 +/* Disable the specified AR5312_MISC_IRQ interrupt */
1682 +static void
1683 +ar5312_misc_irq_mask(struct irq_data *d)
1684 +{
1685 + unsigned int imr;
1686 +
1687 + imr = ar231x_read_reg(AR5312_IMR);
1688 + imr &= ~(1 << (d->irq - AR231X_MISC_IRQ_BASE - 1));
1689 + ar231x_write_reg(AR5312_IMR, imr);
1690 + ar231x_read_reg(AR5312_IMR); /* flush write buffer */
1691 +}
1692 +
1693 +static struct irq_chip ar5312_misc_irq_chip = {
1694 + .name = "AR5312-MISC",
1695 + .irq_unmask = ar5312_misc_irq_unmask,
1696 + .irq_mask = ar5312_misc_irq_mask,
1697 +};
1698 +
1699 +
1700 +static irqreturn_t ar5312_ahb_proc_handler(int cpl, void *dev_id)
1701 +{
1702 + u32 proc1 = ar231x_read_reg(AR5312_PROC1);
1703 + u32 proc_addr = ar231x_read_reg(AR5312_PROCADDR); /* clears error */
1704 + u32 dma1 = ar231x_read_reg(AR5312_DMA1);
1705 + u32 dma_addr = ar231x_read_reg(AR5312_DMAADDR); /* clears error */
1706 +
1707 + pr_emerg("AHB interrupt: PROCADDR=0x%8.8x PROC1=0x%8.8x "
1708 + "DMAADDR=0x%8.8x DMA1=0x%8.8x\n", proc_addr, proc1, dma_addr,
1709 + dma1);
1710 +
1711 + machine_restart("AHB error"); /* Catastrophic failure */
1712 + return IRQ_HANDLED;
1713 +}
1714 +
1715 +
1716 +static struct irqaction ar5312_ahb_proc_interrupt = {
1717 + .handler = ar5312_ahb_proc_handler,
1718 + .name = "ar5312_ahb_proc_interrupt",
1719 +};
1720 +
1721 +
1722 +void __init ar5312_irq_init(void)
1723 +{
1724 + int i;
1725 +
1726 + if (!is_5312())
1727 + return;
1728 +
1729 + ar231x_irq_dispatch = ar5312_irq_dispatch;
1730 + for (i = 0; i < AR5312_MISC_IRQ_COUNT; i++) {
1731 + int irq = AR231X_MISC_IRQ_BASE + i;
1732 + irq_set_chip_and_handler(irq, &ar5312_misc_irq_chip,
1733 + handle_level_irq);
1734 + }
1735 + setup_irq(AR5312_MISC_IRQ_AHB_PROC, &ar5312_ahb_proc_interrupt);
1736 + irq_set_chained_handler(AR5312_IRQ_MISC_INTRS, ar5312_misc_irq_handler);
1737 +}
1738 +
1739 +/*
1740 + * gpiolib implementations
1741 + */
1742 +static int
1743 +ar5312_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
1744 +{
1745 + return (ar231x_read_reg(AR5312_GPIO_DI) >> gpio) & 1;
1746 +}
1747 +
1748 +static void
1749 +ar5312_gpio_set_value(struct gpio_chip *chip, unsigned gpio, int value)
1750 +{
1751 + u32 reg = ar231x_read_reg(AR5312_GPIO_DO);
1752 + reg = value ? reg | (1 << gpio) : reg & ~(1 << gpio);
1753 + ar231x_write_reg(AR5312_GPIO_DO, reg);
1754 +}
1755 +
1756 +static int
1757 +ar5312_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
1758 +{
1759 + ar231x_mask_reg(AR5312_GPIO_CR, 0, 1 << gpio);
1760 + return 0;
1761 +}
1762 +
1763 +static int
1764 +ar5312_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, int value)
1765 +{
1766 + ar231x_mask_reg(AR5312_GPIO_CR, 1 << gpio, 0);
1767 + ar5312_gpio_set_value(chip, gpio, value);
1768 + return 0;
1769 +}
1770 +
1771 +static struct gpio_chip ar5312_gpio_chip = {
1772 + .label = "ar5312-gpio",
1773 + .direction_input = ar5312_gpio_direction_input,
1774 + .direction_output = ar5312_gpio_direction_output,
1775 + .set = ar5312_gpio_set_value,
1776 + .get = ar5312_gpio_get_value,
1777 + .base = 0,
1778 + .ngpio = AR5312_NUM_GPIO, /* 8 */
1779 +};
1780 +
1781 +/* end of gpiolib */
1782 +
1783 +static void ar5312_device_reset_set(u32 mask)
1784 +{
1785 + u32 val;
1786 +
1787 + val = ar231x_read_reg(AR5312_RESET);
1788 + ar231x_write_reg(AR5312_RESET, val | mask);
1789 +}
1790 +
1791 +static void ar5312_device_reset_clear(u32 mask)
1792 +{
1793 + u32 val;
1794 +
1795 + val = ar231x_read_reg(AR5312_RESET);
1796 + ar231x_write_reg(AR5312_RESET, val & ~mask);
1797 +}
1798 +
1799 +static struct physmap_flash_data ar5312_flash_data = {
1800 + .width = 2,
1801 +};
1802 +
1803 +static struct resource ar5312_flash_resource = {
1804 + .start = AR5312_FLASH,
1805 + .end = AR5312_FLASH + 0x800000 - 1,
1806 + .flags = IORESOURCE_MEM,
1807 +};
1808 +
1809 +static struct ar231x_eth ar5312_eth0_data = {
1810 + .reset_set = ar5312_device_reset_set,
1811 + .reset_clear = ar5312_device_reset_clear,
1812 + .reset_mac = AR5312_RESET_ENET0,
1813 + .reset_phy = AR5312_RESET_EPHY0,
1814 + .config = &ar231x_board,
1815 +};
1816 +
1817 +static struct ar231x_eth ar5312_eth1_data = {
1818 + .reset_set = ar5312_device_reset_set,
1819 + .reset_clear = ar5312_device_reset_clear,
1820 + .reset_mac = AR5312_RESET_ENET1,
1821 + .reset_phy = AR5312_RESET_EPHY1,
1822 + .config = &ar231x_board,
1823 +};
1824 +
1825 +static struct platform_device ar5312_physmap_flash = {
1826 + .name = "physmap-flash",
1827 + .id = 0,
1828 + .dev.platform_data = &ar5312_flash_data,
1829 + .resource = &ar5312_flash_resource,
1830 + .num_resources = 1,
1831 +};
1832 +
1833 +#ifdef CONFIG_LEDS_GPIO
1834 +static struct gpio_led ar5312_leds[] = {
1835 + { .name = "wlan", .gpio = 0, .active_low = 1, },
1836 +};
1837 +
1838 +static const struct gpio_led_platform_data ar5312_led_data = {
1839 + .num_leds = ARRAY_SIZE(ar5312_leds),
1840 + .leds = (void *)ar5312_leds,
1841 +};
1842 +
1843 +static struct platform_device ar5312_gpio_leds = {
1844 + .name = "leds-gpio",
1845 + .id = -1,
1846 + .dev.platform_data = (void *)&ar5312_led_data,
1847 +};
1848 +#endif
1849 +
1850 +/*
1851 + * NB: This mapping size is larger than the actual flash size,
1852 + * but this shouldn't be a problem here, because the flash
1853 + * will simply be mapped multiple times.
1854 + */
1855 +static char __init *ar5312_flash_limit(void)
1856 +{
1857 + u32 ctl;
1858 + /*
1859 + * Configure flash bank 0.
1860 + * Assume 8M window size. Flash will be aliased if it's smaller
1861 + */
1862 + ctl = FLASHCTL_E |
1863 + FLASHCTL_AC_8M |
1864 + FLASHCTL_RBLE |
1865 + (0x01 << FLASHCTL_IDCY_S) |
1866 + (0x07 << FLASHCTL_WST1_S) |
1867 + (0x07 << FLASHCTL_WST2_S) |
1868 + (ar231x_read_reg(AR5312_FLASHCTL0) & FLASHCTL_MW);
1869 +
1870 + ar231x_write_reg(AR5312_FLASHCTL0, ctl);
1871 +
1872 + /* Disable other flash banks */
1873 + ar231x_write_reg(AR5312_FLASHCTL1,
1874 + ar231x_read_reg(AR5312_FLASHCTL1) &
1875 + ~(FLASHCTL_E | FLASHCTL_AC));
1876 +
1877 + ar231x_write_reg(AR5312_FLASHCTL2,
1878 + ar231x_read_reg(AR5312_FLASHCTL2) &
1879 + ~(FLASHCTL_E | FLASHCTL_AC));
1880 +
1881 + return (char *)KSEG1ADDR(AR5312_FLASH + 0x800000);
1882 +}
1883 +
1884 +int __init ar5312_init_devices(void)
1885 +{
1886 + struct ar231x_boarddata *config;
1887 + u32 fctl = 0;
1888 + u8 *c;
1889 +
1890 + if (!is_5312())
1891 + return 0;
1892 +
1893 + /* Locate board/radio config data */
1894 + ar231x_find_config(ar5312_flash_limit());
1895 + config = ar231x_board.config;
1896 +
1897 + /* AR2313 has CPU minor rev. 10 */
1898 + if ((current_cpu_data.processor_id & 0xff) == 0x0a)
1899 + ar231x_devtype = DEV_TYPE_AR2313;
1900 +
1901 + /* AR2312 shares the same Silicon ID as AR5312 */
1902 + else if (config->flags & BD_ISCASPER)
1903 + ar231x_devtype = DEV_TYPE_AR2312;
1904 +
1905 + /* Everything else is probably AR5312 or compatible */
1906 + else
1907 + ar231x_devtype = DEV_TYPE_AR5312;
1908 +
1909 + /* fixup flash width */
1910 + fctl = ar231x_read_reg(AR5312_FLASHCTL) & FLASHCTL_MW;
1911 + switch (fctl) {
1912 + case FLASHCTL_MWx16:
1913 + ar5312_flash_data.width = 2;
1914 + break;
1915 + case FLASHCTL_MWx8:
1916 + default:
1917 + ar5312_flash_data.width = 1;
1918 + break;
1919 + }
1920 +
1921 + platform_device_register(&ar5312_physmap_flash);
1922 +
1923 +#ifdef CONFIG_LEDS_GPIO
1924 + ar5312_leds[0].gpio = config->sys_led_gpio;
1925 + platform_device_register(&ar5312_gpio_leds);
1926 +#endif
1927 +
1928 + /* Fix up MAC addresses if necessary */
1929 + if (!memcmp(config->enet0_mac, "\xff\xff\xff\xff\xff\xff", 6))
1930 + memcpy(config->enet0_mac, config->enet1_mac, 6);
1931 +
1932 + /* If ENET0 and ENET1 have the same mac address,
1933 + * increment the one from ENET1 */
1934 + if (memcmp(config->enet0_mac, config->enet1_mac, 6) == 0) {
1935 + c = config->enet1_mac + 5;
1936 + while ((c >= config->enet1_mac) && !(++(*c)))
1937 + c--;
1938 + }
1939 +
1940 + switch (ar231x_devtype) {
1941 + case DEV_TYPE_AR5312:
1942 + ar5312_eth0_data.macaddr = config->enet0_mac;
1943 + ar231x_add_ethernet(0, AR5312_ENET0, "eth0_mii",
1944 + AR5312_ENET0_MII, AR5312_IRQ_ENET0_INTRS,
1945 + &ar5312_eth0_data);
1946 +
1947 + ar5312_eth1_data.macaddr = config->enet1_mac;
1948 + ar231x_add_ethernet(1, AR5312_ENET1, "eth1_mii",
1949 + AR5312_ENET1_MII, AR5312_IRQ_ENET1_INTRS,
1950 + &ar5312_eth1_data);
1951 +
1952 + if (!ar231x_board.radio)
1953 + return 0;
1954 +
1955 + if (!(config->flags & BD_WLAN0))
1956 + break;
1957 +
1958 + ar231x_add_wmac(0, AR5312_WLAN0, AR5312_IRQ_WLAN0_INTRS);
1959 + break;
1960 + /*
1961 + * AR2312/3 ethernet uses the PHY of ENET0, but the MAC
1962 + * of ENET1. Atheros calls it 'twisted' for a reason :)
1963 + */
1964 + case DEV_TYPE_AR2312:
1965 + case DEV_TYPE_AR2313:
1966 + ar5312_eth1_data.reset_phy = ar5312_eth0_data.reset_phy;
1967 + ar5312_eth1_data.macaddr = config->enet0_mac;
1968 + ar231x_add_ethernet(1, AR5312_ENET1, "eth0_mii",
1969 + AR5312_ENET0_MII, AR5312_IRQ_ENET1_INTRS,
1970 + &ar5312_eth1_data);
1971 +
1972 + if (!ar231x_board.radio)
1973 + return 0;
1974 + break;
1975 + default:
1976 + break;
1977 + }
1978 +
1979 + if (config->flags & BD_WLAN1)
1980 + ar231x_add_wmac(1, AR5312_WLAN1, AR5312_IRQ_WLAN1_INTRS);
1981 +
1982 + return 0;
1983 +}
1984 +
1985 +
1986 +static void ar5312_restart(char *command)
1987 +{
1988 + /* reset the system */
1989 + local_irq_disable();
1990 + while (1)
1991 + ar231x_write_reg(AR5312_RESET, AR5312_RESET_SYSTEM);
1992 +}
1993 +
1994 +
1995 +/*
1996 + * This table is indexed by bits 5..4 of the CLOCKCTL1 register
1997 + * to determine the predevisor value.
1998 + */
1999 +static int clockctl1_predivide_table[4] __initdata = { 1, 2, 4, 5 };
2000 +
2001 +
2002 +static int __init
2003 +ar5312_cpu_frequency(void)
2004 +{
2005 + unsigned int scratch;
2006 + unsigned int predivide_mask, predivide_shift;
2007 + unsigned int multiplier_mask, multiplier_shift;
2008 + unsigned int clock_ctl1, predivide_select, predivisor, multiplier;
2009 + unsigned int doubler_mask;
2010 + u16 devid;
2011 +
2012 + /* Trust the bootrom's idea of cpu frequency. */
2013 + scratch = ar231x_read_reg(AR5312_SCRATCH);
2014 + if (scratch)
2015 + return scratch;
2016 +
2017 + devid = ar231x_read_reg(AR5312_REV);
2018 + devid &= AR5312_REV_MAJ;
2019 + devid >>= AR5312_REV_MAJ_S;
2020 + if (devid == AR5312_REV_MAJ_AR2313) {
2021 + predivide_mask = AR2313_CLOCKCTL1_PREDIVIDE_MASK;
2022 + predivide_shift = AR2313_CLOCKCTL1_PREDIVIDE_SHIFT;
2023 + multiplier_mask = AR2313_CLOCKCTL1_MULTIPLIER_MASK;
2024 + multiplier_shift = AR2313_CLOCKCTL1_MULTIPLIER_SHIFT;
2025 + doubler_mask = AR2313_CLOCKCTL1_DOUBLER_MASK;
2026 + } else { /* AR5312 and AR2312 */
2027 + predivide_mask = AR5312_CLOCKCTL1_PREDIVIDE_MASK;
2028 + predivide_shift = AR5312_CLOCKCTL1_PREDIVIDE_SHIFT;
2029 + multiplier_mask = AR5312_CLOCKCTL1_MULTIPLIER_MASK;
2030 + multiplier_shift = AR5312_CLOCKCTL1_MULTIPLIER_SHIFT;
2031 + doubler_mask = AR5312_CLOCKCTL1_DOUBLER_MASK;
2032 + }
2033 +
2034 + /*
2035 + * Clocking is derived from a fixed 40MHz input clock.
2036 + *
2037 + * cpu_freq = input_clock * MULT (where MULT is PLL multiplier)
2038 + * sys_freq = cpu_freq / 4 (used for APB clock, serial,
2039 + * flash, Timer, Watchdog Timer)
2040 + *
2041 + * cnt_freq = cpu_freq / 2 (use for CPU count/compare)
2042 + *
2043 + * So, for example, with a PLL multiplier of 5, we have
2044 + *
2045 + * cpu_freq = 200MHz
2046 + * sys_freq = 50MHz
2047 + * cnt_freq = 100MHz
2048 + *
2049 + * We compute the CPU frequency, based on PLL settings.
2050 + */
2051 +
2052 + clock_ctl1 = ar231x_read_reg(AR5312_CLOCKCTL1);
2053 + predivide_select = (clock_ctl1 & predivide_mask) >> predivide_shift;
2054 + predivisor = clockctl1_predivide_table[predivide_select];
2055 + multiplier = (clock_ctl1 & multiplier_mask) >> multiplier_shift;
2056 +
2057 + if (clock_ctl1 & doubler_mask)
2058 + multiplier = multiplier << 1;
2059 +
2060 + return (40000000 / predivisor) * multiplier;
2061 +}
2062 +
2063 +static inline int
2064 +ar5312_sys_frequency(void)
2065 +{
2066 + return ar5312_cpu_frequency() / 4;
2067 +}
2068 +
2069 +void __init
2070 +ar5312_time_init(void)
2071 +{
2072 + if (!is_5312())
2073 + return;
2074 +
2075 + mips_hpt_frequency = ar5312_cpu_frequency() / 2;
2076 +}
2077 +
2078 +static int __init
2079 +ar5312_gpio_init(void)
2080 +{
2081 + int ret;
2082 + ret = gpiochip_add(&ar5312_gpio_chip);
2083 + if (ret) {
2084 + pr_err("%s: failed to add gpiochip\n", ar5312_gpio_chip.label);
2085 + return ret;
2086 + }
2087 + pr_info("%s: registered %d GPIOs\n", ar5312_gpio_chip.label,
2088 + ar5312_gpio_chip.ngpio);
2089 + return ret;
2090 +}
2091 +
2092 +void __init
2093 +ar5312_prom_init(void)
2094 +{
2095 + u32 memsize, memcfg, bank0AC, bank1AC;
2096 + u32 devid;
2097 +
2098 + if (!is_5312())
2099 + return;
2100 +
2101 + /* Detect memory size */
2102 + memcfg = ar231x_read_reg(AR5312_MEM_CFG1);
2103 + bank0AC = (memcfg & MEM_CFG1_AC0) >> MEM_CFG1_AC0_S;
2104 + bank1AC = (memcfg & MEM_CFG1_AC1) >> MEM_CFG1_AC1_S;
2105 + memsize = (bank0AC ? (1 << (bank0AC+1)) : 0) +
2106 + (bank1AC ? (1 << (bank1AC+1)) : 0);
2107 + memsize <<= 20;
2108 + add_memory_region(0, memsize, BOOT_MEM_RAM);
2109 +
2110 + devid = ar231x_read_reg(AR5312_REV);
2111 + devid >>= AR5312_REV_WMAC_MIN_S;
2112 + devid &= AR5312_REV_CHIP;
2113 + ar231x_board.devid = (u16) devid;
2114 + ar5312_gpio_init();
2115 +}
2116 +
2117 +void __init
2118 +ar5312_plat_setup(void)
2119 +{
2120 + if (!is_5312())
2121 + return;
2122 +
2123 + /* Clear any lingering AHB errors */
2124 + ar231x_read_reg(AR5312_PROCADDR);
2125 + ar231x_read_reg(AR5312_DMAADDR);
2126 + ar231x_write_reg(AR5312_WD_CTRL, AR5312_WD_CTRL_IGNORE_EXPIRATION);
2127 +
2128 + _machine_restart = ar5312_restart;
2129 + ar231x_serial_setup(AR5312_UART0, AR5312_MISC_IRQ_UART0,
2130 + ar5312_sys_frequency());
2131 +}
2132 +
2133 --- /dev/null
2134 +++ b/arch/mips/ar231x/ar2315.c
2135 @@ -0,0 +1,556 @@
2136 +/*
2137 + * This file is subject to the terms and conditions of the GNU General Public
2138 + * License. See the file "COPYING" in the main directory of this archive
2139 + * for more details.
2140 + *
2141 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
2142 + * Copyright (C) 2006 FON Technology, SL.
2143 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
2144 + * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
2145 + * Copyright (C) 2012 Alexandros C. Couloumbis <alex@ozo.com>
2146 + */
2147 +
2148 +/*
2149 + * Platform devices for Atheros SoCs
2150 + */
2151 +
2152 +#include <generated/autoconf.h>
2153 +#include <linux/init.h>
2154 +#include <linux/module.h>
2155 +#include <linux/types.h>
2156 +#include <linux/string.h>
2157 +#include <linux/platform_device.h>
2158 +#include <linux/kernel.h>
2159 +#include <linux/reboot.h>
2160 +#include <linux/delay.h>
2161 +#include <linux/leds.h>
2162 +#include <linux/gpio.h>
2163 +#include <asm/bootinfo.h>
2164 +#include <asm/reboot.h>
2165 +#include <asm/time.h>
2166 +#include <linux/irq.h>
2167 +#include <linux/io.h>
2168 +
2169 +#include <ar231x_platform.h>
2170 +#include <ar2315_regs.h>
2171 +#include <ar231x.h>
2172 +#include "devices.h"
2173 +#include "ar2315.h"
2174 +
2175 +static u32 gpiointmask, gpiointval;
2176 +
2177 +static void ar2315_gpio_irq_handler(unsigned irq, struct irq_desc *desc)
2178 +{
2179 + u32 pend;
2180 + int bit = -1;
2181 +
2182 + /* only do one gpio interrupt at a time */
2183 + pend = (ar231x_read_reg(AR2315_GPIO_DI) ^ gpiointval) & gpiointmask;
2184 +
2185 + if (pend) {
2186 + bit = fls(pend) - 1;
2187 + pend &= ~(1 << bit);
2188 + gpiointval ^= (1 << bit);
2189 + }
2190 +
2191 + if (!pend)
2192 + ar231x_write_reg(AR2315_ISR, AR2315_ISR_GPIO);
2193 +
2194 + /* Enable interrupt with edge detection */
2195 + if ((ar231x_read_reg(AR2315_GPIO_DIR) & AR2315_GPIO_DIR_M(bit)) !=
2196 + AR2315_GPIO_DIR_I(bit))
2197 + return;
2198 +
2199 + if (bit >= 0)
2200 + do_IRQ(AR231X_GPIO_IRQ_BASE + bit);
2201 +}
2202 +
2203 +static void ar2315_misc_irq_handler(unsigned irq, struct irq_desc *desc)
2204 +{
2205 + unsigned int misc_intr = ar231x_read_reg(AR2315_ISR) &
2206 + ar231x_read_reg(AR2315_IMR);
2207 +
2208 + if (misc_intr & AR2315_ISR_SPI)
2209 + do_IRQ(AR2315_MISC_IRQ_SPI);
2210 + else if (misc_intr & AR2315_ISR_TIMER)
2211 + do_IRQ(AR2315_MISC_IRQ_TIMER);
2212 + else if (misc_intr & AR2315_ISR_AHB)
2213 + do_IRQ(AR2315_MISC_IRQ_AHB);
2214 + else if (misc_intr & AR2315_ISR_GPIO)
2215 + do_IRQ(AR2315_MISC_IRQ_GPIO);
2216 + else if (misc_intr & AR2315_ISR_UART0)
2217 + do_IRQ(AR2315_MISC_IRQ_UART0);
2218 + else if (misc_intr & AR2315_ISR_WD) {
2219 + ar231x_write_reg(AR2315_ISR, AR2315_ISR_WD);
2220 + do_IRQ(AR2315_MISC_IRQ_WATCHDOG);
2221 + } else
2222 + do_IRQ(AR2315_MISC_IRQ_NONE);
2223 +}
2224 +
2225 +/*
2226 + * Called when an interrupt is received, this function
2227 + * determines exactly which interrupt it was, and it
2228 + * invokes the appropriate handler.
2229 + *
2230 + * Implicitly, we also define interrupt priority by
2231 + * choosing which to dispatch first.
2232 + */
2233 +static asmlinkage void
2234 +ar2315_irq_dispatch(void)
2235 +{
2236 + int pending = read_c0_status() & read_c0_cause();
2237 +
2238 + if (pending & CAUSEF_IP3)
2239 + do_IRQ(AR2315_IRQ_WLAN0_INTRS);
2240 + else if (pending & CAUSEF_IP4)
2241 + do_IRQ(AR2315_IRQ_ENET0_INTRS);
2242 + else if (pending & CAUSEF_IP2)
2243 + do_IRQ(AR2315_IRQ_MISC_INTRS);
2244 + else if (pending & CAUSEF_IP7)
2245 + do_IRQ(AR231X_IRQ_CPU_CLOCK);
2246 +}
2247 +
2248 +static void ar2315_set_gpiointmask(int gpio, int level)
2249 +{
2250 + u32 reg;
2251 +
2252 + reg = ar231x_read_reg(AR2315_GPIO_INT);
2253 + reg &= ~(AR2315_GPIO_INT_M | AR2315_GPIO_INT_LVL_M);
2254 + reg |= gpio | AR2315_GPIO_INT_LVL(level);
2255 + ar231x_write_reg(AR2315_GPIO_INT, reg);
2256 +}
2257 +
2258 +static void ar2315_gpio_irq_unmask(struct irq_data *d)
2259 +{
2260 + unsigned int gpio = d->irq - AR231X_GPIO_IRQ_BASE;
2261 +
2262 + /* Enable interrupt with edge detection */
2263 + if ((ar231x_read_reg(AR2315_GPIO_DIR) & AR2315_GPIO_DIR_M(gpio)) !=
2264 + AR2315_GPIO_DIR_I(gpio))
2265 + return;
2266 +
2267 + gpiointmask |= (1 << gpio);
2268 + ar2315_set_gpiointmask(gpio, 3);
2269 +}
2270 +
2271 +static void ar2315_gpio_irq_mask(struct irq_data *d)
2272 +{
2273 + unsigned int gpio = d->irq - AR231X_GPIO_IRQ_BASE;
2274 +
2275 + /* Disable interrupt */
2276 + gpiointmask &= ~(1 << gpio);
2277 + ar2315_set_gpiointmask(gpio, 0);
2278 +}
2279 +
2280 +static struct irq_chip ar2315_gpio_irq_chip = {
2281 + .name = "AR2315-GPIO",
2282 + .irq_unmask = ar2315_gpio_irq_unmask,
2283 + .irq_mask = ar2315_gpio_irq_mask,
2284 +};
2285 +
2286 +static void
2287 +ar2315_misc_irq_unmask(struct irq_data *d)
2288 +{
2289 + unsigned int imr;
2290 +
2291 + imr = ar231x_read_reg(AR2315_IMR);
2292 + imr |= 1 << (d->irq - AR231X_MISC_IRQ_BASE - 1);
2293 + ar231x_write_reg(AR2315_IMR, imr);
2294 +}
2295 +
2296 +static void
2297 +ar2315_misc_irq_mask(struct irq_data *d)
2298 +{
2299 + unsigned int imr;
2300 +
2301 + imr = ar231x_read_reg(AR2315_IMR);
2302 + imr &= ~(1 << (d->irq - AR231X_MISC_IRQ_BASE - 1));
2303 + ar231x_write_reg(AR2315_IMR, imr);
2304 +}
2305 +
2306 +static struct irq_chip ar2315_misc_irq_chip = {
2307 + .name = "AR2315-MISC",
2308 + .irq_unmask = ar2315_misc_irq_unmask,
2309 + .irq_mask = ar2315_misc_irq_mask,
2310 +};
2311 +
2312 +static irqreturn_t ar2315_ahb_proc_handler(int cpl, void *dev_id)
2313 +{
2314 + ar231x_write_reg(AR2315_AHB_ERR0, AHB_ERROR_DET);
2315 + ar231x_read_reg(AR2315_AHB_ERR1);
2316 +
2317 + pr_emerg("AHB fatal error\n");
2318 + machine_restart("AHB error"); /* Catastrophic failure */
2319 +
2320 + return IRQ_HANDLED;
2321 +}
2322 +
2323 +static struct irqaction ar2315_ahb_proc_interrupt = {
2324 + .handler = ar2315_ahb_proc_handler,
2325 + .name = "ar2315_ahb_proc_interrupt",
2326 +};
2327 +
2328 +void
2329 +ar2315_irq_init(void)
2330 +{
2331 + int i;
2332 +
2333 + if (!is_2315())
2334 + return;
2335 +
2336 + ar231x_irq_dispatch = ar2315_irq_dispatch;
2337 + gpiointval = ar231x_read_reg(AR2315_GPIO_DI);
2338 + for (i = 0; i < AR2315_MISC_IRQ_COUNT; i++) {
2339 + int irq = AR231X_MISC_IRQ_BASE + i;
2340 + irq_set_chip_and_handler(irq, &ar2315_misc_irq_chip,
2341 + handle_level_irq);
2342 + }
2343 + for (i = 0; i < AR2315_NUM_GPIO; i++) {
2344 + int irq = AR231X_GPIO_IRQ_BASE + i;
2345 + irq_set_chip_and_handler(irq, &ar2315_gpio_irq_chip,
2346 + handle_level_irq);
2347 + }
2348 + irq_set_chained_handler(AR2315_MISC_IRQ_GPIO, ar2315_gpio_irq_handler);
2349 + setup_irq(AR2315_MISC_IRQ_AHB, &ar2315_ahb_proc_interrupt);
2350 + irq_set_chained_handler(AR2315_IRQ_MISC_INTRS, ar2315_misc_irq_handler);
2351 +}
2352 +
2353 +/*
2354 + * gpiolib implementation
2355 + */
2356 +static int
2357 +ar2315_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
2358 +{
2359 + return (ar231x_read_reg(AR2315_GPIO_DI) >> gpio) & 1;
2360 +}
2361 +
2362 +static void
2363 +ar2315_gpio_set_value(struct gpio_chip *chip, unsigned gpio, int value)
2364 +{
2365 + u32 reg = ar231x_read_reg(AR2315_GPIO_DO);
2366 + reg = value ? reg | (1 << gpio) : reg & ~(1 << gpio);
2367 + ar231x_write_reg(AR2315_GPIO_DO, reg);
2368 +}
2369 +
2370 +static int
2371 +ar2315_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
2372 +{
2373 + ar231x_mask_reg(AR2315_GPIO_DIR, 1 << gpio, 0);
2374 + return 0;
2375 +}
2376 +
2377 +static int
2378 +ar2315_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, int value)
2379 +{
2380 + ar231x_mask_reg(AR2315_GPIO_DIR, 0, 1 << gpio);
2381 + ar2315_gpio_set_value(chip, gpio, value);
2382 + return 0;
2383 +}
2384 +
2385 +static struct gpio_chip ar2315_gpio_chip = {
2386 + .label = "ar2315-gpio",
2387 + .direction_input = ar2315_gpio_direction_input,
2388 + .direction_output = ar2315_gpio_direction_output,
2389 + .set = ar2315_gpio_set_value,
2390 + .get = ar2315_gpio_get_value,
2391 + .base = 0,
2392 + .ngpio = AR2315_NUM_GPIO, /* 22 */
2393 +};
2394 +
2395 +/* end of gpiolib */
2396 +
2397 +static void ar2315_device_reset_set(u32 mask)
2398 +{
2399 + u32 val;
2400 +
2401 + val = ar231x_read_reg(AR2315_RESET);
2402 + ar231x_write_reg(AR2315_RESET, val | mask);
2403 +}
2404 +
2405 +static void ar2315_device_reset_clear(u32 mask)
2406 +{
2407 + u32 val;
2408 +
2409 + val = ar231x_read_reg(AR2315_RESET);
2410 + ar231x_write_reg(AR2315_RESET, val & ~mask);
2411 +}
2412 +
2413 +static struct ar231x_eth ar2315_eth_data = {
2414 + .reset_set = ar2315_device_reset_set,
2415 + .reset_clear = ar2315_device_reset_clear,
2416 + .reset_mac = AR2315_RESET_ENET0,
2417 + .reset_phy = AR2315_RESET_EPHY0,
2418 + .config = &ar231x_board,
2419 +};
2420 +
2421 +static struct resource ar2315_spiflash_res[] = {
2422 + {
2423 + .name = "spiflash_read",
2424 + .flags = IORESOURCE_MEM,
2425 + .start = AR2315_SPI_READ,
2426 + .end = AR2315_SPI_READ + 0x1000000 - 1,
2427 + },
2428 + {
2429 + .name = "spiflash_mmr",
2430 + .flags = IORESOURCE_MEM,
2431 + .start = AR2315_SPI_MMR,
2432 + .end = AR2315_SPI_MMR + 12 - 1,
2433 + },
2434 +};
2435 +
2436 +static struct platform_device ar2315_spiflash = {
2437 + .id = 0,
2438 + .name = "ar2315-spiflash",
2439 + .resource = ar2315_spiflash_res,
2440 + .num_resources = ARRAY_SIZE(ar2315_spiflash_res)
2441 +};
2442 +
2443 +static struct resource ar2315_wdt_res[] = {
2444 + {
2445 + .flags = IORESOURCE_MEM,
2446 + .start = AR2315_WD,
2447 + .end = AR2315_WD + 8 - 1,
2448 + },
2449 + {
2450 + .flags = IORESOURCE_IRQ,
2451 + .start = AR2315_MISC_IRQ_WATCHDOG,
2452 + .end = AR2315_MISC_IRQ_WATCHDOG,
2453 + }
2454 +};
2455 +
2456 +static struct platform_device ar2315_wdt = {
2457 + .id = 0,
2458 + .name = "ar2315-wdt",
2459 + .resource = ar2315_wdt_res,
2460 + .num_resources = ARRAY_SIZE(ar2315_wdt_res)
2461 +};
2462 +
2463 +/*
2464 + * NB: We use mapping size that is larger than the actual flash size,
2465 + * but this shouldn't be a problem here, because the flash will simply
2466 + * be mapped multiple times.
2467 + */
2468 +static u8 __init *ar2315_flash_limit(void)
2469 +{
2470 + return (u8 *)KSEG1ADDR(ar2315_spiflash_res[0].end + 1);
2471 +}
2472 +
2473 +#ifdef CONFIG_LEDS_GPIO
2474 +static struct gpio_led ar2315_leds[6];
2475 +static struct gpio_led_platform_data ar2315_led_data = {
2476 + .leds = (void *)ar2315_leds,
2477 +};
2478 +
2479 +static struct platform_device ar2315_gpio_leds = {
2480 + .name = "leds-gpio",
2481 + .id = -1,
2482 + .dev = {
2483 + .platform_data = (void *)&ar2315_led_data,
2484 + }
2485 +};
2486 +
2487 +static void __init
2488 +ar2315_init_gpio_leds(void)
2489 +{
2490 + static char led_names[6][6];
2491 + int i, led = 0;
2492 +
2493 + ar2315_led_data.num_leds = 0;
2494 + for (i = 1; i < 8; i++) {
2495 + if ((i == AR2315_RESET_GPIO) ||
2496 + (i == ar231x_board.config->reset_config_gpio))
2497 + continue;
2498 +
2499 + if (i == ar231x_board.config->sys_led_gpio)
2500 + strcpy(led_names[led], "wlan");
2501 + else
2502 + sprintf(led_names[led], "gpio%d", i);
2503 +
2504 + ar2315_leds[led].name = led_names[led];
2505 + ar2315_leds[led].gpio = i;
2506 + ar2315_leds[led].active_low = 0;
2507 + led++;
2508 + }
2509 + ar2315_led_data.num_leds = led;
2510 + platform_device_register(&ar2315_gpio_leds);
2511 +}
2512 +#else
2513 +static inline void ar2315_init_gpio_leds(void)
2514 +{
2515 +}
2516 +#endif
2517 +
2518 +int __init
2519 +ar2315_init_devices(void)
2520 +{
2521 + if (!is_2315())
2522 + return 0;
2523 +
2524 + /* Find board configuration */
2525 + ar231x_find_config(ar2315_flash_limit());
2526 + ar2315_eth_data.macaddr = ar231x_board.config->enet0_mac;
2527 +
2528 + ar2315_init_gpio_leds();
2529 + platform_device_register(&ar2315_wdt);
2530 + platform_device_register(&ar2315_spiflash);
2531 + ar231x_add_ethernet(0, AR2315_ENET0, "eth0_mii", AR2315_ENET0_MII,
2532 + AR2315_IRQ_ENET0_INTRS, &ar2315_eth_data);
2533 + ar231x_add_wmac(0, AR2315_WLAN0, AR2315_IRQ_WLAN0_INTRS);
2534 +
2535 + return 0;
2536 +}
2537 +
2538 +static void
2539 +ar2315_restart(char *command)
2540 +{
2541 + void (*mips_reset_vec)(void) = (void *)0xbfc00000;
2542 +
2543 + local_irq_disable();
2544 +
2545 + /* try reset the system via reset control */
2546 + ar231x_write_reg(AR2315_COLD_RESET, AR2317_RESET_SYSTEM);
2547 +
2548 + /* Cold reset does not work on the AR2315/6, use the GPIO reset bits
2549 + * a workaround. Give it some time to attempt a gpio based hardware
2550 + * reset (atheros reference design workaround) */
2551 + gpio_request_one(AR2315_RESET_GPIO, GPIOF_OUT_INIT_LOW, "Reset");
2552 + mdelay(100);
2553 +
2554 + /* Some boards (e.g. Senao EOC-2610) don't implement the reset logic
2555 + * workaround. Attempt to jump to the mips reset location -
2556 + * the boot loader itself might be able to recover the system */
2557 + mips_reset_vec();
2558 +}
2559 +
2560 +
2561 +/*
2562 + * This table is indexed by bits 5..4 of the CLOCKCTL1 register
2563 + * to determine the predevisor value.
2564 + */
2565 +static int clockctl1_predivide_table[4] __initdata = { 1, 2, 4, 5 };
2566 +static int pllc_divide_table[5] __initdata = { 2, 3, 4, 6, 3 };
2567 +
2568 +static unsigned int __init
2569 +ar2315_sys_clk(unsigned int clock_ctl)
2570 +{
2571 + unsigned int pllc_ctrl, cpu_div;
2572 + unsigned int pllc_out, refdiv, fdiv, divby2;
2573 + unsigned int clk_div;
2574 +
2575 + pllc_ctrl = ar231x_read_reg(AR2315_PLLC_CTL);
2576 + refdiv = (pllc_ctrl & PLLC_REF_DIV_M) >> PLLC_REF_DIV_S;
2577 + refdiv = clockctl1_predivide_table[refdiv];
2578 + fdiv = (pllc_ctrl & PLLC_FDBACK_DIV_M) >> PLLC_FDBACK_DIV_S;
2579 + divby2 = (pllc_ctrl & PLLC_ADD_FDBACK_DIV_M) >> PLLC_ADD_FDBACK_DIV_S;
2580 + divby2 += 1;
2581 + pllc_out = (40000000/refdiv)*(2*divby2)*fdiv;
2582 +
2583 + /* clkm input selected */
2584 + switch (clock_ctl & CPUCLK_CLK_SEL_M) {
2585 + case 0:
2586 + case 1:
2587 + clk_div = pllc_divide_table[(pllc_ctrl & PLLC_CLKM_DIV_M) >>
2588 + PLLC_CLKM_DIV_S];
2589 + break;
2590 + case 2:
2591 + clk_div = pllc_divide_table[(pllc_ctrl & PLLC_CLKC_DIV_M) >>
2592 + PLLC_CLKC_DIV_S];
2593 + break;
2594 + default:
2595 + pllc_out = 40000000;
2596 + clk_div = 1;
2597 + break;
2598 + }
2599 +
2600 + cpu_div = (clock_ctl & CPUCLK_CLK_DIV_M) >> CPUCLK_CLK_DIV_S;
2601 + cpu_div = cpu_div * 2 ?: 1;
2602 +
2603 + return pllc_out / (clk_div * cpu_div);
2604 +}
2605 +
2606 +static inline unsigned int
2607 +ar2315_cpu_frequency(void)
2608 +{
2609 + return ar2315_sys_clk(ar231x_read_reg(AR2315_CPUCLK));
2610 +}
2611 +
2612 +static inline unsigned int
2613 +ar2315_apb_frequency(void)
2614 +{
2615 + return ar2315_sys_clk(ar231x_read_reg(AR2315_AMBACLK));
2616 +}
2617 +
2618 +void __init
2619 +ar2315_time_init(void)
2620 +{
2621 + if (!is_2315())
2622 + return;
2623 +
2624 + mips_hpt_frequency = ar2315_cpu_frequency() / 2;
2625 +}
2626 +
2627 +static int __init
2628 +ar2315_gpio_init(void)
2629 +{
2630 + int ret;
2631 + ret = gpiochip_add(&ar2315_gpio_chip);
2632 + if (ret) {
2633 + pr_err("%s: failed to add gpiochip\n", ar2315_gpio_chip.label);
2634 + return ret;
2635 + }
2636 + pr_info("%s: registered %d GPIOs\n", ar2315_gpio_chip.label,
2637 + ar2315_gpio_chip.ngpio);
2638 + return ret;
2639 +}
2640 +
2641 +
2642 +
2643 +void __init
2644 +ar2315_prom_init(void)
2645 +{
2646 + u32 memsize, memcfg, devid;
2647 +
2648 + if (!is_2315())
2649 + return;
2650 +
2651 + memcfg = ar231x_read_reg(AR2315_MEM_CFG);
2652 + memsize = 1 + ((memcfg & SDRAM_DATA_WIDTH_M) >> SDRAM_DATA_WIDTH_S);
2653 + memsize <<= 1 + ((memcfg & SDRAM_COL_WIDTH_M) >> SDRAM_COL_WIDTH_S);
2654 + memsize <<= 1 + ((memcfg & SDRAM_ROW_WIDTH_M) >> SDRAM_ROW_WIDTH_S);
2655 + memsize <<= 3;
2656 + add_memory_region(0, memsize, BOOT_MEM_RAM);
2657 +
2658 + /* Detect the hardware based on the device ID */
2659 + devid = ar231x_read_reg(AR2315_SREV) & AR2315_REV_CHIP;
2660 + switch (devid) {
2661 + case 0x90:
2662 + case 0x91:
2663 + ar231x_devtype = DEV_TYPE_AR2317;
2664 + break;
2665 + default:
2666 + ar231x_devtype = DEV_TYPE_AR2315;
2667 + break;
2668 + }
2669 + ar2315_gpio_init();
2670 + ar231x_board.devid = devid;
2671 +}
2672 +
2673 +void __init
2674 +ar2315_plat_setup(void)
2675 +{
2676 + u32 config;
2677 +
2678 + if (!is_2315())
2679 + return;
2680 +
2681 + /* Clear any lingering AHB errors */
2682 + config = read_c0_config();
2683 + write_c0_config(config & ~0x3);
2684 + ar231x_write_reg(AR2315_AHB_ERR0, AHB_ERROR_DET);
2685 + ar231x_read_reg(AR2315_AHB_ERR1);
2686 + ar231x_write_reg(AR2315_WDC, AR2315_WDC_IGNORE_EXPIRATION);
2687 +
2688 + _machine_restart = ar2315_restart;
2689 + ar231x_serial_setup(AR2315_UART0, AR2315_MISC_IRQ_UART0,
2690 + ar2315_apb_frequency());
2691 +}
2692 --- /dev/null
2693 +++ b/arch/mips/ar231x/ar2315.h
2694 @@ -0,0 +1,37 @@
2695 +#ifndef __AR2315_H
2696 +#define __AR2315_H
2697 +
2698 +#ifdef CONFIG_ATHEROS_AR2315
2699 +
2700 +extern void ar2315_irq_init(void);
2701 +extern int ar2315_init_devices(void);
2702 +extern void ar2315_prom_init(void);
2703 +extern void ar2315_plat_setup(void);
2704 +extern void ar2315_time_init(void);
2705 +
2706 +#else
2707 +
2708 +static inline void ar2315_irq_init(void)
2709 +{
2710 +}
2711 +
2712 +static inline int ar2315_init_devices(void)
2713 +{
2714 + return 0;
2715 +}
2716 +
2717 +static inline void ar2315_prom_init(void)
2718 +{
2719 +}
2720 +
2721 +static inline void ar2315_plat_setup(void)
2722 +{
2723 +}
2724 +
2725 +static inline void ar2315_time_init(void)
2726 +{
2727 +}
2728 +
2729 +#endif
2730 +
2731 +#endif
2732 --- /dev/null
2733 +++ b/arch/mips/ar231x/ar5312.h
2734 @@ -0,0 +1,38 @@
2735 +#ifndef __AR5312_H
2736 +#define __AR5312_H
2737 +
2738 +#ifdef CONFIG_ATHEROS_AR5312
2739 +
2740 +extern void ar5312_irq_init(void);
2741 +extern int ar5312_init_devices(void);
2742 +extern void ar5312_prom_init(void);
2743 +extern void ar5312_plat_setup(void);
2744 +extern void ar5312_time_init(void);
2745 +extern void ar5312_time_init(void);
2746 +
2747 +#else
2748 +
2749 +static inline void ar5312_irq_init(void)
2750 +{
2751 +}
2752 +
2753 +static inline int ar5312_init_devices(void)
2754 +{
2755 + return 0;
2756 +}
2757 +
2758 +static inline void ar5312_prom_init(void)
2759 +{
2760 +}
2761 +
2762 +static inline void ar5312_plat_setup(void)
2763 +{
2764 +}
2765 +
2766 +static inline void ar5312_time_init(void)
2767 +{
2768 +}
2769 +
2770 +#endif
2771 +
2772 +#endif
2773 --- /dev/null
2774 +++ b/arch/mips/include/asm/mach-ar231x/ar231x.h
2775 @@ -0,0 +1,43 @@
2776 +#ifndef __ASM_MACH_AR231X_H
2777 +#define __ASM_MACH_AR231X_H
2778 +
2779 +#include <linux/types.h>
2780 +#include <linux/io.h>
2781 +
2782 +#define AR231X_MISC_IRQ_BASE 0x20
2783 +#define AR231X_GPIO_IRQ_BASE 0x30
2784 +
2785 +/* Software's idea of interrupts handled by "CPU Interrupt Controller" */
2786 +#define AR231X_IRQ_NONE (MIPS_CPU_IRQ_BASE+0)
2787 +#define AR231X_IRQ_CPU_CLOCK (MIPS_CPU_IRQ_BASE+7) /* C0_CAUSE: 0x8000 */
2788 +
2789 +/* GPIO Interrupts, share ARXXXX_MISC_IRQ_GPIO */
2790 +#define AR231X_GPIO_IRQ_NONE (AR231X_GPIO_IRQ_BASE+0)
2791 +#define AR231X_GPIO_IRQ(n) (AR231X_GPIO_IRQ_BASE+n)
2792 +
2793 +static inline u32
2794 +ar231x_read_reg(u32 reg)
2795 +{
2796 + return __raw_readl((void __iomem *)KSEG1ADDR(reg));
2797 +}
2798 +
2799 +static inline void
2800 +ar231x_write_reg(u32 reg, u32 val)
2801 +{
2802 + __raw_writel(val, (void __iomem *)KSEG1ADDR(reg));
2803 +}
2804 +
2805 +static inline u32
2806 +ar231x_mask_reg(u32 reg, u32 mask, u32 val)
2807 +{
2808 + u32 ret;
2809 +
2810 + ret = ar231x_read_reg(reg);
2811 + ret &= ~mask;
2812 + ret |= val;
2813 + ar231x_write_reg(reg, ret);
2814 +
2815 + return ret;
2816 +}
2817 +
2818 +#endif /* __ASM_MACH_AR231X_H */
2819 --- /dev/null
2820 +++ b/arch/mips/ar231x/devices.h
2821 @@ -0,0 +1,38 @@
2822 +#ifndef __AR231X_DEVICES_H
2823 +#define __AR231X_DEVICES_H
2824 +
2825 +enum {
2826 + /* handled by ar5312.c */
2827 + DEV_TYPE_AR2312,
2828 + DEV_TYPE_AR2313,
2829 + DEV_TYPE_AR5312,
2830 +
2831 + /* handled by ar2315.c */
2832 + DEV_TYPE_AR2315,
2833 + DEV_TYPE_AR2316,
2834 + DEV_TYPE_AR2317,
2835 +
2836 + DEV_TYPE_UNKNOWN
2837 +};
2838 +
2839 +extern int ar231x_devtype;
2840 +extern struct ar231x_board_config ar231x_board;
2841 +extern asmlinkage void (*ar231x_irq_dispatch)(void);
2842 +
2843 +extern int ar231x_find_config(u8 *flash_limit);
2844 +extern void ar231x_serial_setup(u32 mapbase, int irq, unsigned int uartclk);
2845 +extern int ar231x_add_wmac(int nr, u32 base, int irq);
2846 +extern int ar231x_add_ethernet(int nr, u32 base, const char *mii_name,
2847 + u32 mii_base, int irq, void *pdata);
2848 +
2849 +static inline bool is_2315(void)
2850 +{
2851 + return (current_cpu_data.cputype == CPU_4KEC);
2852 +}
2853 +
2854 +static inline bool is_5312(void)
2855 +{
2856 + return !is_2315();
2857 +}
2858 +
2859 +#endif
2860 --- /dev/null
2861 +++ b/arch/mips/ar231x/devices.c
2862 @@ -0,0 +1,180 @@
2863 +#include <linux/kernel.h>
2864 +#include <linux/init.h>
2865 +#include <linux/serial.h>
2866 +#include <linux/serial_core.h>
2867 +#include <linux/serial_8250.h>
2868 +#include <linux/platform_device.h>
2869 +#include <ar231x_platform.h>
2870 +#include <ar231x.h>
2871 +#include "devices.h"
2872 +#include "ar5312.h"
2873 +#include "ar2315.h"
2874 +
2875 +struct ar231x_board_config ar231x_board;
2876 +int ar231x_devtype = DEV_TYPE_UNKNOWN;
2877 +
2878 +static struct resource ar231x_eth0_res[] = {
2879 + {
2880 + .name = "eth0_membase",
2881 + .flags = IORESOURCE_MEM,
2882 + },
2883 + {
2884 + .name = "eth0_mii",
2885 + .flags = IORESOURCE_MEM,
2886 + },
2887 + {
2888 + .name = "eth0_irq",
2889 + .flags = IORESOURCE_IRQ,
2890 + }
2891 +};
2892 +
2893 +static struct resource ar231x_eth1_res[] = {
2894 + {
2895 + .name = "eth1_membase",
2896 + .flags = IORESOURCE_MEM,
2897 + },
2898 + {
2899 + .name = "eth1_mii",
2900 + .flags = IORESOURCE_MEM,
2901 + },
2902 + {
2903 + .name = "eth1_irq",
2904 + .flags = IORESOURCE_IRQ,
2905 + }
2906 +};
2907 +
2908 +static struct platform_device ar231x_eth[] = {
2909 + {
2910 + .id = 0,
2911 + .name = "ar231x-eth",
2912 + .resource = ar231x_eth0_res,
2913 + .num_resources = ARRAY_SIZE(ar231x_eth0_res)
2914 + },
2915 + {
2916 + .id = 1,
2917 + .name = "ar231x-eth",
2918 + .resource = ar231x_eth1_res,
2919 + .num_resources = ARRAY_SIZE(ar231x_eth1_res)
2920 + }
2921 +};
2922 +
2923 +static struct resource ar231x_wmac0_res[] = {
2924 + {
2925 + .name = "wmac0_membase",
2926 + .flags = IORESOURCE_MEM,
2927 + },
2928 + {
2929 + .name = "wmac0_irq",
2930 + .flags = IORESOURCE_IRQ,
2931 + }
2932 +};
2933 +
2934 +static struct resource ar231x_wmac1_res[] = {
2935 + {
2936 + .name = "wmac1_membase",
2937 + .flags = IORESOURCE_MEM,
2938 + },
2939 + {
2940 + .name = "wmac1_irq",
2941 + .flags = IORESOURCE_IRQ,
2942 + }
2943 +};
2944 +
2945 +
2946 +static struct platform_device ar231x_wmac[] = {
2947 + {
2948 + .id = 0,
2949 + .name = "ar231x-wmac",
2950 + .resource = ar231x_wmac0_res,
2951 + .num_resources = ARRAY_SIZE(ar231x_wmac0_res),
2952 + .dev.platform_data = &ar231x_board,
2953 + },
2954 + {
2955 + .id = 1,
2956 + .name = "ar231x-wmac",
2957 + .resource = ar231x_wmac1_res,
2958 + .num_resources = ARRAY_SIZE(ar231x_wmac1_res),
2959 + .dev.platform_data = &ar231x_board,
2960 + },
2961 +};
2962 +
2963 +static const char * const devtype_strings[] = {
2964 + [DEV_TYPE_AR5312] = "Atheros AR5312",
2965 + [DEV_TYPE_AR2312] = "Atheros AR2312",
2966 + [DEV_TYPE_AR2313] = "Atheros AR2313",
2967 + [DEV_TYPE_AR2315] = "Atheros AR2315",
2968 + [DEV_TYPE_AR2316] = "Atheros AR2316",
2969 + [DEV_TYPE_AR2317] = "Atheros AR2317",
2970 + [DEV_TYPE_UNKNOWN] = "Atheros (unknown)",
2971 +};
2972 +
2973 +const char *get_system_type(void)
2974 +{
2975 + if ((ar231x_devtype >= ARRAY_SIZE(devtype_strings)) ||
2976 + !devtype_strings[ar231x_devtype])
2977 + return devtype_strings[DEV_TYPE_UNKNOWN];
2978 + return devtype_strings[ar231x_devtype];
2979 +}
2980 +
2981 +
2982 +int __init
2983 +ar231x_add_ethernet(int nr, u32 base, const char *mii_name, u32 mii_base,
2984 + int irq, void *pdata)
2985 +{
2986 + struct resource *res;
2987 +
2988 + ar231x_eth[nr].dev.platform_data = pdata;
2989 + res = &ar231x_eth[nr].resource[0];
2990 + res->start = base;
2991 + res->end = base + 0x2000 - 1;
2992 + res++;
2993 + res->name = mii_name;
2994 + res->start = mii_base;
2995 + res->end = mii_base + 8 - 1;
2996 + res++;
2997 + res->start = irq;
2998 + res->end = irq;
2999 + return platform_device_register(&ar231x_eth[nr]);
3000 +}
3001 +
3002 +void __init
3003 +ar231x_serial_setup(u32 mapbase, int irq, unsigned int uartclk)
3004 +{
3005 + struct uart_port s;
3006 +
3007 + memset(&s, 0, sizeof(s));
3008 +
3009 + s.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP;
3010 + s.iotype = UPIO_MEM32;
3011 + s.irq = irq;
3012 + s.regshift = 2;
3013 + s.mapbase = mapbase;
3014 + s.uartclk = uartclk;
3015 +
3016 + early_serial_setup(&s);
3017 +}
3018 +
3019 +int __init
3020 +ar231x_add_wmac(int nr, u32 base, int irq)
3021 +{
3022 + struct resource *res;
3023 +
3024 + ar231x_wmac[nr].dev.platform_data = &ar231x_board;
3025 + res = &ar231x_wmac[nr].resource[0];
3026 + res->start = base;
3027 + res->end = base + 0x10000 - 1;
3028 + res++;
3029 + res->start = irq;
3030 + res->end = irq;
3031 + return platform_device_register(&ar231x_wmac[nr]);
3032 +}
3033 +
3034 +static int __init ar231x_register_devices(void)
3035 +{
3036 + ar5312_init_devices();
3037 + ar2315_init_devices();
3038 +
3039 + return 0;
3040 +}
3041 +
3042 +device_initcall(ar231x_register_devices);
OpenWrt SVN history