atheros: copy 3.10 patches to 3.14 and refresh them
[openwrt/svn-archive/archive.git] / target / linux / atheros / patches-3.14 / 105-ar2315_pci.patch
1 --- a/arch/mips/ar231x/Makefile
2 +++ b/arch/mips/ar231x/Makefile
3 @@ -14,3 +14,4 @@ obj-$(CONFIG_EARLY_PRINTK) += early_prin
4
5 obj-$(CONFIG_ATHEROS_AR5312) += ar5312.o
6 obj-$(CONFIG_ATHEROS_AR2315) += ar2315.o
7 +obj-$(CONFIG_ATHEROS_AR2315_PCI) += pci.o
8 --- /dev/null
9 +++ b/arch/mips/ar231x/pci.c
10 @@ -0,0 +1,234 @@
11 +/*
12 + * This program is free software; you can redistribute it and/or
13 + * modify it under the terms of the GNU General Public License
14 + * as published by the Free Software Foundation; either version 2
15 + * of the License, or (at your option) any later version.
16 + *
17 + * This program is distributed in the hope that it will be useful,
18 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 + * GNU General Public License for more details.
21 + *
22 + * You should have received a copy of the GNU General Public License
23 + * along with this program; if not, write to the Free Software
24 + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
25 + */
26 +
27 +#include <linux/types.h>
28 +#include <linux/pci.h>
29 +#include <linux/kernel.h>
30 +#include <linux/init.h>
31 +#include <linux/mm.h>
32 +#include <linux/spinlock.h>
33 +#include <linux/delay.h>
34 +#include <linux/irq.h>
35 +#include <linux/io.h>
36 +#include <asm/paccess.h>
37 +#include <ar231x_platform.h>
38 +#include <ar231x.h>
39 +#include <ar2315_regs.h>
40 +#include "devices.h"
41 +
42 +#define AR2315_MEM_BASE 0x80800000UL
43 +#define AR2315_MEM_SIZE 0x00ffffffUL
44 +#define AR2315_IO_SIZE 0x00007fffUL
45 +
46 +static unsigned long configspace;
47 +
48 +static int config_access(int devfn, int where, int size, u32 *ptr, bool write)
49 +{
50 + unsigned long flags;
51 + int func = PCI_FUNC(devfn);
52 + int dev = PCI_SLOT(devfn);
53 + u32 value = 0;
54 + int err = 0;
55 + u32 addr;
56 +
57 + if (((dev != 0) && (dev != 3)) || (func > 2))
58 + return PCIBIOS_DEVICE_NOT_FOUND;
59 +
60 + /* Select Configuration access */
61 + local_irq_save(flags);
62 + ar231x_mask_reg(AR2315_PCI_MISC_CONFIG, 0, AR2315_PCIMISC_CFG_SEL);
63 + mb();
64 +
65 + addr = (u32) configspace + (1 << (13 + dev)) + (func << 8) + where;
66 + if (size == 1)
67 + addr ^= 0x3;
68 + else if (size == 2)
69 + addr ^= 0x2;
70 +
71 + if (write) {
72 + value = *ptr;
73 + if (size == 1)
74 + err = put_dbe(value, (u8 *)addr);
75 + else if (size == 2)
76 + err = put_dbe(value, (u16 *)addr);
77 + else if (size == 4)
78 + err = put_dbe(value, (u32 *)addr);
79 + } else {
80 + if (size == 1)
81 + err = get_dbe(value, (u8 *)addr);
82 + else if (size == 2)
83 + err = get_dbe(value, (u16 *)addr);
84 + else if (size == 4)
85 + err = get_dbe(value, (u32 *)addr);
86 + if (err)
87 + *ptr = 0xffffffff;
88 + else
89 + *ptr = value;
90 + }
91 +
92 + /* Select Memory access */
93 + ar231x_mask_reg(AR2315_PCI_MISC_CONFIG, AR2315_PCIMISC_CFG_SEL, 0);
94 + local_irq_restore(flags);
95 +
96 + return err ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
97 +}
98 +
99 +static int ar231x_pci_read(struct pci_bus *bus, unsigned int devfn, int where,
100 + int size, u32 *value)
101 +{
102 + return config_access(devfn, where, size, value, 0);
103 +}
104 +
105 +static int ar231x_pci_write(struct pci_bus *bus, unsigned int devfn, int where,
106 + int size, u32 value)
107 +{
108 + return config_access(devfn, where, size, &value, 1);
109 +}
110 +
111 +struct pci_ops ar231x_pci_ops = {
112 + .read = ar231x_pci_read,
113 + .write = ar231x_pci_write,
114 +};
115 +
116 +static struct resource ar231x_mem_resource = {
117 + .name = "AR2315 PCI MEM",
118 + .start = AR2315_MEM_BASE,
119 + .end = AR2315_MEM_BASE + AR2315_MEM_SIZE - AR2315_IO_SIZE - 1 +
120 + 0x4000000,
121 + .flags = IORESOURCE_MEM,
122 +};
123 +
124 +static struct resource ar231x_io_resource = {
125 + .name = "AR2315 PCI I/O",
126 + .start = AR2315_MEM_BASE + AR2315_MEM_SIZE - AR2315_IO_SIZE,
127 + .end = AR2315_MEM_BASE + AR2315_MEM_SIZE - 1,
128 + .flags = IORESOURCE_IO,
129 +};
130 +
131 +struct pci_controller ar231x_pci_controller = {
132 + .pci_ops = &ar231x_pci_ops,
133 + .mem_resource = &ar231x_mem_resource,
134 + .io_resource = &ar231x_io_resource,
135 + .mem_offset = 0x00000000UL,
136 + .io_offset = 0x00000000UL,
137 +};
138 +
139 +int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
140 +{
141 + return AR2315_IRQ_LCBUS_PCI;
142 +}
143 +
144 +int pcibios_plat_dev_init(struct pci_dev *dev)
145 +{
146 + pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 5);
147 + pci_write_config_word(dev, 0x40, 0);
148 +
149 + /* Clear any pending Abort or external Interrupts
150 + * and enable interrupt processing */
151 + ar231x_mask_reg(AR2315_PCI_INTEN_REG, AR2315_PCI_INT_ENABLE, 0);
152 + ar231x_write_reg(AR2315_PCI_INT_STATUS, (AR2315_PCI_ABORT_INT |
153 + AR2315_PCI_EXT_INT));
154 + ar231x_write_reg(AR2315_PCI_INT_MASK, (AR2315_PCI_ABORT_INT |
155 + AR2315_PCI_EXT_INT));
156 + ar231x_mask_reg(AR2315_PCI_INTEN_REG, 0, AR2315_PCI_INT_ENABLE);
157 +
158 + return 0;
159 +}
160 +
161 +static void
162 +ar2315_pci_fixup(struct pci_dev *dev)
163 +{
164 + unsigned int devfn = dev->devfn;
165 +
166 + if (dev->bus->number != 0)
167 + return;
168 +
169 + /* Only fix up the PCI host settings */
170 + if ((PCI_SLOT(devfn) != 3) || (PCI_FUNC(devfn) != 0))
171 + return;
172 +
173 + /* Fix up MBARs */
174 + pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, HOST_PCI_MBAR0);
175 + pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, HOST_PCI_MBAR1);
176 + pci_write_config_dword(dev, PCI_BASE_ADDRESS_2, HOST_PCI_MBAR2);
177 + pci_write_config_dword(dev, PCI_COMMAND, PCI_COMMAND_MEMORY |
178 + PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL |
179 + PCI_COMMAND_INVALIDATE | PCI_COMMAND_PARITY |
180 + PCI_COMMAND_SERR | PCI_COMMAND_FAST_BACK);
181 +}
182 +DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, ar2315_pci_fixup);
183 +
184 +static int __init
185 +ar2315_pci_init(void)
186 +{
187 + u32 reg;
188 +
189 + if (ar231x_devtype != DEV_TYPE_AR2315)
190 + return -ENODEV;
191 +
192 + /* Remap PCI config space */
193 + configspace = (unsigned long) ioremap_nocache(AR2315_PCIEXT,
194 + 1*1024*1024);
195 + ar231x_pci_controller.io_map_base =
196 + (unsigned long) ioremap_nocache(AR2315_MEM_BASE +
197 + AR2315_MEM_SIZE, AR2315_IO_SIZE);
198 + set_io_port_base(ar231x_pci_controller.io_map_base); /* PCI I/O space*/
199 +
200 + reg = ar231x_mask_reg(AR2315_RESET, 0, AR2315_RESET_PCIDMA);
201 + msleep(20);
202 +
203 + reg &= ~AR2315_RESET_PCIDMA;
204 + ar231x_write_reg(AR2315_RESET, reg);
205 + msleep(20);
206 +
207 + ar231x_mask_reg(AR2315_ENDIAN_CTL, 0,
208 + AR2315_CONFIG_PCIAHB | AR2315_CONFIG_PCIAHB_BRIDGE);
209 +
210 + ar231x_write_reg(AR2315_PCICLK, AR2315_PCICLK_PLLC_CLKM |
211 + (AR2315_PCICLK_IN_FREQ_DIV_6 << AR2315_PCICLK_DIV_S));
212 + ar231x_mask_reg(AR2315_AHB_ARB_CTL, 0, AR2315_ARB_PCI);
213 + ar231x_mask_reg(AR2315_IF_CTL, AR2315_IF_PCI_CLK_MASK | AR2315_IF_MASK,
214 + AR2315_IF_PCI | AR2315_IF_PCI_HOST | AR2315_IF_PCI_INTR |
215 + (AR2315_IF_PCI_CLK_OUTPUT_CLK << AR2315_IF_PCI_CLK_SHIFT));
216 +
217 + /* Reset the PCI bus by setting bits 5-4 in PCI_MCFG */
218 + ar231x_mask_reg(AR2315_PCI_MISC_CONFIG, AR2315_PCIMISC_RST_MODE,
219 + AR2315_PCIRST_LOW);
220 + msleep(100);
221 +
222 + /* Bring the PCI out of reset */
223 + ar231x_mask_reg(AR2315_PCI_MISC_CONFIG, AR2315_PCIMISC_RST_MODE,
224 + AR2315_PCIRST_HIGH | AR2315_PCICACHE_DIS | 0x8);
225 +
226 + ar231x_write_reg(AR2315_PCI_UNCACHE_CFG,
227 + 0x1E | /* 1GB uncached */
228 + (1 << 5) | /* Enable uncached */
229 + (0x2 << 30) /* Base: 0x80000000 */
230 + );
231 + ar231x_read_reg(AR2315_PCI_UNCACHE_CFG);
232 +
233 + msleep(500);
234 +
235 + /* dirty hack - anyone with a datasheet that knows the memory map ? */
236 + ioport_resource.start = 0x10000000;
237 + ioport_resource.end = 0xffffffff;
238 +
239 + register_pci_controller(&ar231x_pci_controller);
240 +
241 + return 0;
242 +}
243 +
244 +arch_initcall(ar2315_pci_init);
245 --- a/arch/mips/ar231x/Kconfig
246 +++ b/arch/mips/ar231x/Kconfig
247 @@ -14,3 +14,10 @@ config ATHEROS_AR2315
248 select SYS_SUPPORTS_32BIT_KERNEL
249 select SYS_SUPPORTS_BIG_ENDIAN
250 default y
251 +
252 +config ATHEROS_AR2315_PCI
253 + bool "PCI support"
254 + depends on ATHEROS_AR2315
255 + select HW_HAS_PCI
256 + select PCI
257 + default y
258 --- a/arch/mips/ar231x/ar2315.c
259 +++ b/arch/mips/ar231x/ar2315.c
260 @@ -87,6 +87,28 @@ static void ar2315_misc_irq_handler(unsi
261 do_IRQ(AR2315_MISC_IRQ_NONE);
262 }
263
264 +#ifdef CONFIG_ATHEROS_AR2315_PCI
265 +static inline void pci_abort_irq(void)
266 +{
267 + ar231x_write_reg(AR2315_PCI_INT_STATUS, AR2315_PCI_ABORT_INT);
268 +}
269 +
270 +static inline void pci_ack_irq(void)
271 +{
272 + ar231x_write_reg(AR2315_PCI_INT_STATUS, AR2315_PCI_EXT_INT);
273 +}
274 +
275 +void ar2315_pci_irq(int irq)
276 +{
277 + if (ar231x_read_reg(AR2315_PCI_INT_STATUS) == AR2315_PCI_ABORT_INT)
278 + pci_abort_irq();
279 + else {
280 + do_IRQ(irq);
281 + pci_ack_irq();
282 + }
283 +}
284 +#endif /* CONFIG_ATHEROS_AR2315_PCI */
285 +
286 /*
287 * Called when an interrupt is received, this function
288 * determines exactly which interrupt it was, and it
289 @@ -104,6 +126,10 @@ ar2315_irq_dispatch(void)
290 do_IRQ(AR2315_IRQ_WLAN0_INTRS);
291 else if (pending & CAUSEF_IP4)
292 do_IRQ(AR2315_IRQ_ENET0_INTRS);
293 +#ifdef CONFIG_ATHEROS_AR2315_PCI
294 + else if (pending & CAUSEF_IP5)
295 + ar2315_pci_irq(AR2315_IRQ_LCBUS_PCI);
296 +#endif
297 else if (pending & CAUSEF_IP2)
298 do_IRQ(AR2315_IRQ_MISC_INTRS);
299 else if (pending & CAUSEF_IP7)