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[openwrt/svn-archive/archive.git] / target / linux / atheros / patches-3.18 / 100-board.patch
1 --- a/arch/mips/Kconfig
2 +++ b/arch/mips/Kconfig
3 @@ -96,6 +96,19 @@ config AR7
4 Support for the Texas Instruments AR7 System-on-a-Chip
5 family: TNETD7100, 7200 and 7300.
6
7 +config ATH25
8 + bool "Atheros 231x/531x SoC support"
9 + select CEVT_R4K
10 + select CSRC_R4K
11 + select DMA_NONCOHERENT
12 + select IRQ_CPU
13 + select SYS_HAS_CPU_MIPS32_R1
14 + select SYS_SUPPORTS_BIG_ENDIAN
15 + select SYS_SUPPORTS_32BIT_KERNEL
16 + select ARCH_REQUIRE_GPIOLIB
17 + help
18 + Support for AR231x and AR531x based boards
19 +
20 config ATH79
21 bool "Atheros AR71XX/AR724X/AR913X based boards"
22 select ARCH_REQUIRE_GPIOLIB
23 @@ -834,6 +847,7 @@ config MIPS_PARAVIRT
24
25 endchoice
26
27 +source "arch/mips/ath25/Kconfig"
28 source "arch/mips/alchemy/Kconfig"
29 source "arch/mips/ath79/Kconfig"
30 source "arch/mips/bcm47xx/Kconfig"
31 --- a/arch/mips/Kbuild.platforms
32 +++ b/arch/mips/Kbuild.platforms
33 @@ -2,6 +2,7 @@
34
35 platforms += alchemy
36 platforms += ar7
37 +platforms += ath25
38 platforms += ath79
39 platforms += bcm47xx
40 platforms += bcm63xx
41 --- /dev/null
42 +++ b/arch/mips/ath25/Platform
43 @@ -0,0 +1,6 @@
44 +#
45 +# Atheros AR531X/AR231X WiSoC
46 +#
47 +platform-$(CONFIG_ATH25) += ath25/
48 +cflags-$(CONFIG_ATH25) += -I$(srctree)/arch/mips/include/asm/mach-ath25
49 +load-$(CONFIG_ATH25) += 0xffffffff80041000
50 --- /dev/null
51 +++ b/arch/mips/ath25/Kconfig
52 @@ -0,0 +1,9 @@
53 +config SOC_AR5312
54 + bool "Atheros 5312/2312+ support"
55 + depends on ATH25
56 + default y
57 +
58 +config SOC_AR2315
59 + bool "Atheros 2315+ support"
60 + depends on ATH25
61 + default y
62 --- /dev/null
63 +++ b/arch/mips/ath25/Makefile
64 @@ -0,0 +1,13 @@
65 +#
66 +# This file is subject to the terms and conditions of the GNU General Public
67 +# License. See the file "COPYING" in the main directory of this archive
68 +# for more details.
69 +#
70 +# Copyright (C) 2006 FON Technology, SL.
71 +# Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
72 +# Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
73 +#
74 +
75 +obj-y += board.o prom.o devices.o
76 +obj-$(CONFIG_SOC_AR5312) += ar5312.o
77 +obj-$(CONFIG_SOC_AR2315) += ar2315.o
78 --- /dev/null
79 +++ b/arch/mips/ath25/board.c
80 @@ -0,0 +1,234 @@
81 +/*
82 + * This file is subject to the terms and conditions of the GNU General Public
83 + * License. See the file "COPYING" in the main directory of this archive
84 + * for more details.
85 + *
86 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
87 + * Copyright (C) 2006 FON Technology, SL.
88 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
89 + * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
90 + */
91 +
92 +#include <generated/autoconf.h>
93 +#include <linux/init.h>
94 +#include <linux/module.h>
95 +#include <linux/types.h>
96 +#include <linux/string.h>
97 +#include <linux/platform_device.h>
98 +#include <linux/kernel.h>
99 +#include <linux/random.h>
100 +#include <linux/etherdevice.h>
101 +#include <linux/irq.h>
102 +#include <linux/io.h>
103 +#include <asm/irq_cpu.h>
104 +#include <asm/reboot.h>
105 +#include <asm/bootinfo.h>
106 +#include <asm/time.h>
107 +
108 +#include <ath25_platform.h>
109 +#include "devices.h"
110 +#include "ar5312.h"
111 +#include "ar2315.h"
112 +
113 +void (*ath25_irq_dispatch)(void);
114 +
115 +static inline bool check_radio_magic(u8 *addr)
116 +{
117 + addr += 0x7a; /* offset for flash magic */
118 + return (addr[0] == 0x5a) && (addr[1] == 0xa5);
119 +}
120 +
121 +static inline bool check_notempty(u8 *addr)
122 +{
123 + return *(u32 *)addr != 0xffffffff;
124 +}
125 +
126 +static inline bool check_board_data(u8 *flash_limit, u8 *addr, bool broken)
127 +{
128 + /* config magic found */
129 + if (*((u32 *)addr) == ATH25_BD_MAGIC)
130 + return true;
131 +
132 + if (!broken)
133 + return false;
134 +
135 + if (check_radio_magic(addr + 0xf8))
136 + ath25_board.radio = addr + 0xf8;
137 + if ((addr < flash_limit + 0x10000) &&
138 + check_radio_magic(addr + 0x10000))
139 + ath25_board.radio = addr + 0x10000;
140 +
141 + if (ath25_board.radio) {
142 + /* broken board data detected, use radio data to find the
143 + * offset, user will fix this */
144 + return true;
145 + }
146 +
147 + return false;
148 +}
149 +
150 +static u8 * __init find_board_config(u8 *flash_limit, bool broken)
151 +{
152 + u8 *addr;
153 + u8 *begin = flash_limit - 0x1000;
154 + u8 *end = flash_limit - 0x30000;
155 +
156 + for (addr = begin; addr >= end; addr -= 0x1000)
157 + if (check_board_data(flash_limit, addr, broken))
158 + return addr;
159 +
160 + return NULL;
161 +}
162 +
163 +static u8 * __init find_radio_config(u8 *flash_limit, u8 *bcfg)
164 +{
165 + u8 *rcfg, *begin, *end;
166 +
167 + /*
168 + * Now find the start of Radio Configuration data, using heuristics:
169 + * Search forward from Board Configuration data by 0x1000 bytes
170 + * at a time until we find non-0xffffffff.
171 + */
172 + begin = bcfg + 0x1000;
173 + end = flash_limit;
174 + for (rcfg = begin; rcfg < end; rcfg += 0x1000)
175 + if (check_notempty(rcfg) && check_radio_magic(rcfg))
176 + return rcfg;
177 +
178 + /* AR2316 relocates radio config to new location */
179 + begin = bcfg + 0xf8;
180 + end = flash_limit - 0x1000 + 0xf8;
181 + for (rcfg = begin; rcfg < end; rcfg += 0x1000)
182 + if (check_notempty(rcfg) && check_radio_magic(rcfg))
183 + return rcfg;
184 +
185 + pr_warn("WARNING: Could not find Radio Configuration data\n");
186 +
187 + return NULL;
188 +}
189 +
190 +int __init ath25_find_config(u8 *flash_limit)
191 +{
192 + struct ath25_boarddata *config;
193 + unsigned int rcfg_size;
194 + int broken_boarddata = 0;
195 + u8 *bcfg, *rcfg;
196 + u8 *board_data;
197 + u8 *radio_data;
198 + u8 *mac_addr;
199 + u32 offset;
200 +
201 + ath25_board.config = NULL;
202 + ath25_board.radio = NULL;
203 + /* Copy the board and radio data to RAM, because accessing the mapped
204 + * memory of the flash directly after booting is not safe */
205 +
206 + /* Try to find valid board and radio data */
207 + bcfg = find_board_config(flash_limit, false);
208 +
209 + /* If that fails, try to at least find valid radio data */
210 + if (!bcfg) {
211 + bcfg = find_board_config(flash_limit, true);
212 + broken_boarddata = 1;
213 + }
214 +
215 + if (!bcfg) {
216 + pr_warn("WARNING: No board configuration data found!\n");
217 + return -ENODEV;
218 + }
219 +
220 + board_data = kzalloc(BOARD_CONFIG_BUFSZ, GFP_KERNEL);
221 + ath25_board.config = (struct ath25_boarddata *)board_data;
222 + memcpy(board_data, bcfg, 0x100);
223 + if (broken_boarddata) {
224 + pr_warn("WARNING: broken board data detected\n");
225 + config = ath25_board.config;
226 + if (is_zero_ether_addr(config->enet0_mac)) {
227 + pr_info("Fixing up empty mac addresses\n");
228 + config->reset_config_gpio = 0xffff;
229 + config->sys_led_gpio = 0xffff;
230 + random_ether_addr(config->wlan0_mac);
231 + config->wlan0_mac[0] &= ~0x06;
232 + random_ether_addr(config->enet0_mac);
233 + random_ether_addr(config->enet1_mac);
234 + }
235 + }
236 +
237 + /* Radio config starts 0x100 bytes after board config, regardless
238 + * of what the physical layout on the flash chip looks like */
239 +
240 + if (ath25_board.radio)
241 + rcfg = (u8 *)ath25_board.radio;
242 + else
243 + rcfg = find_radio_config(flash_limit, bcfg);
244 +
245 + if (!rcfg)
246 + return -ENODEV;
247 +
248 + radio_data = board_data + 0x100 + ((rcfg - bcfg) & 0xfff);
249 + ath25_board.radio = radio_data;
250 + offset = radio_data - board_data;
251 + pr_info("Radio config found at offset 0x%x (0x%x)\n", rcfg - bcfg,
252 + offset);
253 + rcfg_size = BOARD_CONFIG_BUFSZ - offset;
254 + memcpy(radio_data, rcfg, rcfg_size);
255 +
256 + mac_addr = &radio_data[0x1d * 2];
257 + if (is_broadcast_ether_addr(mac_addr)) {
258 + pr_info("Radio MAC is blank; using board-data\n");
259 + ether_addr_copy(mac_addr, ath25_board.config->wlan0_mac);
260 + }
261 +
262 + return 0;
263 +}
264 +
265 +static void ath25_halt(void)
266 +{
267 + local_irq_disable();
268 + while (1)
269 + ;
270 +}
271 +
272 +void __init plat_mem_setup(void)
273 +{
274 + _machine_halt = ath25_halt;
275 + pm_power_off = ath25_halt;
276 +
277 + if (is_ar5312())
278 + ar5312_plat_mem_setup();
279 + else
280 + ar2315_plat_mem_setup();
281 +
282 + /* Disable data watchpoints */
283 + write_c0_watchlo0(0);
284 +}
285 +
286 +asmlinkage void plat_irq_dispatch(void)
287 +{
288 + ath25_irq_dispatch();
289 +}
290 +
291 +void __init plat_time_init(void)
292 +{
293 + if (is_ar5312())
294 + ar5312_plat_time_init();
295 + else
296 + ar2315_plat_time_init();
297 +}
298 +
299 +unsigned int __cpuinit get_c0_compare_int(void)
300 +{
301 + return CP0_LEGACY_COMPARE_IRQ;
302 +}
303 +
304 +void __init arch_init_irq(void)
305 +{
306 + clear_c0_status(ST0_IM);
307 + mips_cpu_irq_init();
308 +
309 + /* Initialize interrupt controllers */
310 + if (is_ar5312())
311 + ar5312_arch_init_irq();
312 + else
313 + ar2315_arch_init_irq();
314 +}
315 --- /dev/null
316 +++ b/arch/mips/ath25/prom.c
317 @@ -0,0 +1,26 @@
318 +/*
319 + * This file is subject to the terms and conditions of the GNU General Public
320 + * License. See the file "COPYING" in the main directory of this archive
321 + * for more details.
322 + *
323 + * Copyright MontaVista Software Inc
324 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
325 + * Copyright (C) 2006 FON Technology, SL.
326 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
327 + * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
328 + */
329 +
330 +/*
331 + * Prom setup file for ar231x
332 + */
333 +
334 +#include <linux/init.h>
335 +#include <asm/bootinfo.h>
336 +
337 +void __init prom_init(void)
338 +{
339 +}
340 +
341 +void __init prom_free_prom_memory(void)
342 +{
343 +}
344 --- /dev/null
345 +++ b/arch/mips/include/asm/mach-ath25/ath25_platform.h
346 @@ -0,0 +1,84 @@
347 +#ifndef __ASM_MACH_ATH25_PLATFORM_H
348 +#define __ASM_MACH_ATH25_PLATFORM_H
349 +
350 +#include <linux/etherdevice.h>
351 +
352 +/*
353 + * This is board-specific data that is stored in a "fixed" location in flash.
354 + * It is shared across operating systems, so it should not be changed lightly.
355 + * The main reason we need it is in order to extract the ethernet MAC
356 + * address(es).
357 + */
358 +struct ath25_boarddata {
359 + u32 magic; /* board data is valid */
360 +#define ATH25_BD_MAGIC 0x35333131 /* "5311", for all 531x/231x platforms */
361 + u16 cksum; /* checksum (starting with BD_REV 2) */
362 + u16 rev; /* revision of this struct */
363 +#define BD_REV 4
364 + char board_name[64]; /* Name of board */
365 + u16 major; /* Board major number */
366 + u16 minor; /* Board minor number */
367 + u32 flags; /* Board configuration */
368 +#define BD_ENET0 0x00000001 /* ENET0 is stuffed */
369 +#define BD_ENET1 0x00000002 /* ENET1 is stuffed */
370 +#define BD_UART1 0x00000004 /* UART1 is stuffed */
371 +#define BD_UART0 0x00000008 /* UART0 is stuffed (dma) */
372 +#define BD_RSTFACTORY 0x00000010 /* Reset factory defaults stuffed */
373 +#define BD_SYSLED 0x00000020 /* System LED stuffed */
374 +#define BD_EXTUARTCLK 0x00000040 /* External UART clock */
375 +#define BD_CPUFREQ 0x00000080 /* cpu freq is valid in nvram */
376 +#define BD_SYSFREQ 0x00000100 /* sys freq is set in nvram */
377 +#define BD_WLAN0 0x00000200 /* Enable WLAN0 */
378 +#define BD_MEMCAP 0x00000400 /* CAP SDRAM @ mem_cap for testing */
379 +#define BD_DISWATCHDOG 0x00000800 /* disable system watchdog */
380 +#define BD_WLAN1 0x00001000 /* Enable WLAN1 (ar5212) */
381 +#define BD_ISCASPER 0x00002000 /* FLAG for AR2312 */
382 +#define BD_WLAN0_2G_EN 0x00004000 /* FLAG for radio0_2G */
383 +#define BD_WLAN0_5G_EN 0x00008000 /* FLAG for radio0_2G */
384 +#define BD_WLAN1_2G_EN 0x00020000 /* FLAG for radio0_2G */
385 +#define BD_WLAN1_5G_EN 0x00040000 /* FLAG for radio0_2G */
386 + u16 reset_config_gpio; /* Reset factory GPIO pin */
387 + u16 sys_led_gpio; /* System LED GPIO pin */
388 +
389 + u32 cpu_freq; /* CPU core frequency in Hz */
390 + u32 sys_freq; /* System frequency in Hz */
391 + u32 cnt_freq; /* Calculated C0_COUNT frequency */
392 +
393 + u8 wlan0_mac[ETH_ALEN];
394 + u8 enet0_mac[ETH_ALEN];
395 + u8 enet1_mac[ETH_ALEN];
396 +
397 + u16 pci_id; /* Pseudo PCIID for common code */
398 + u16 mem_cap; /* cap bank1 in MB */
399 +
400 + /* version 3 */
401 + u8 wlan1_mac[ETH_ALEN]; /* (ar5212) */
402 +};
403 +
404 +#define BOARD_CONFIG_BUFSZ 0x1000
405 +
406 +/*
407 + * Platform device information for the Wireless MAC
408 + */
409 +struct ar231x_board_config {
410 + u16 devid;
411 +
412 + /* board config data */
413 + struct ath25_boarddata *config;
414 +
415 + /* radio calibration data */
416 + const char *radio;
417 +};
418 +
419 +/*
420 + * Platform device information for the Ethernet MAC
421 + */
422 +struct ar231x_eth {
423 + void (*reset_set)(u32);
424 + void (*reset_clear)(u32);
425 + u32 reset_mac;
426 + u32 reset_phy;
427 + char *macaddr;
428 +};
429 +
430 +#endif /* __ASM_MACH_ATH25_PLATFORM_H */
431 --- /dev/null
432 +++ b/arch/mips/include/asm/mach-ath25/cpu-feature-overrides.h
433 @@ -0,0 +1,64 @@
434 +/*
435 + * Atheros AR231x/AR531x SoC specific CPU feature overrides
436 + *
437 + * Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
438 + *
439 + * This file was derived from: include/asm-mips/cpu-features.h
440 + * Copyright (C) 2003, 2004 Ralf Baechle
441 + * Copyright (C) 2004 Maciej W. Rozycki
442 + *
443 + * This program is free software; you can redistribute it and/or modify it
444 + * under the terms of the GNU General Public License version 2 as published
445 + * by the Free Software Foundation.
446 + *
447 + */
448 +#ifndef __ASM_MACH_ATH25_CPU_FEATURE_OVERRIDES_H
449 +#define __ASM_MACH_ATH25_CPU_FEATURE_OVERRIDES_H
450 +
451 +/*
452 + * The Atheros AR531x/AR231x SoCs have MIPS 4Kc/4KEc core.
453 + */
454 +#define cpu_has_tlb 1
455 +#define cpu_has_4kex 1
456 +#define cpu_has_3k_cache 0
457 +#define cpu_has_4k_cache 1
458 +#define cpu_has_tx39_cache 0
459 +#define cpu_has_sb1_cache 0
460 +#define cpu_has_fpu 0
461 +#define cpu_has_32fpr 0
462 +#define cpu_has_counter 1
463 +#define cpu_has_ejtag 1
464 +
465 +#if !defined(CONFIG_SOC_AR5312)
466 +# define cpu_has_llsc 1
467 +#else
468 +/*
469 + * The MIPS 4Kc V0.9 core in the AR5312/AR2312 have problems with the
470 + * ll/sc instructions.
471 + */
472 +# define cpu_has_llsc 0
473 +#endif
474 +
475 +#define cpu_has_mips16 0
476 +#define cpu_has_mdmx 0
477 +#define cpu_has_mips3d 0
478 +#define cpu_has_smartmips 0
479 +
480 +#define cpu_has_mips32r1 1
481 +
482 +#if !defined(CONFIG_SOC_AR5312)
483 +# define cpu_has_mips32r2 1
484 +#endif
485 +
486 +#define cpu_has_mips64r1 0
487 +#define cpu_has_mips64r2 0
488 +
489 +#define cpu_has_dsp 0
490 +#define cpu_has_mipsmt 0
491 +
492 +#define cpu_has_64bits 0
493 +#define cpu_has_64bit_zero_reg 0
494 +#define cpu_has_64bit_gp_regs 0
495 +#define cpu_has_64bit_addresses 0
496 +
497 +#endif /* __ASM_MACH_ATH25_CPU_FEATURE_OVERRIDES_H */
498 --- /dev/null
499 +++ b/arch/mips/include/asm/mach-ath25/dma-coherence.h
500 @@ -0,0 +1,82 @@
501 +/*
502 + * This file is subject to the terms and conditions of the GNU General Public
503 + * License. See the file "COPYING" in the main directory of this archive
504 + * for more details.
505 + *
506 + * Copyright (C) 2006 Ralf Baechle <ralf@linux-mips.org>
507 + * Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
508 + *
509 + */
510 +#ifndef __ASM_MACH_ATH25_DMA_COHERENCE_H
511 +#define __ASM_MACH_ATH25_DMA_COHERENCE_H
512 +
513 +#include <linux/device.h>
514 +
515 +/*
516 + * We need some arbitrary non-zero value to be programmed to the BAR1 register
517 + * of PCI host controller to enable DMA. The same value should be used as the
518 + * offset to calculate the physical address of DMA buffer for PCI devices.
519 + */
520 +#define AR2315_PCI_HOST_SDRAM_BASEADDR 0x20000000
521 +
522 +static inline dma_addr_t ath25_dev_offset(struct device *dev)
523 +{
524 +#ifdef CONFIG_PCI
525 + extern struct bus_type pci_bus_type;
526 +
527 + if (dev && dev->bus == &pci_bus_type)
528 + return AR2315_PCI_HOST_SDRAM_BASEADDR;
529 +#endif
530 + return 0;
531 +}
532 +
533 +static inline dma_addr_t
534 +plat_map_dma_mem(struct device *dev, void *addr, size_t size)
535 +{
536 + return virt_to_phys(addr) + ath25_dev_offset(dev);
537 +}
538 +
539 +static inline dma_addr_t
540 +plat_map_dma_mem_page(struct device *dev, struct page *page)
541 +{
542 + return page_to_phys(page) + ath25_dev_offset(dev);
543 +}
544 +
545 +static inline unsigned long
546 +plat_dma_addr_to_phys(struct device *dev, dma_addr_t dma_addr)
547 +{
548 + return dma_addr - ath25_dev_offset(dev);
549 +}
550 +
551 +static inline void
552 +plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr, size_t size,
553 + enum dma_data_direction direction)
554 +{
555 +}
556 +
557 +static inline int plat_dma_supported(struct device *dev, u64 mask)
558 +{
559 + return 1;
560 +}
561 +
562 +static inline void plat_extra_sync_for_device(struct device *dev)
563 +{
564 +}
565 +
566 +static inline int plat_dma_mapping_error(struct device *dev,
567 + dma_addr_t dma_addr)
568 +{
569 + return 0;
570 +}
571 +
572 +static inline int plat_device_is_coherent(struct device *dev)
573 +{
574 +#ifdef CONFIG_DMA_COHERENT
575 + return 1;
576 +#endif
577 +#ifdef CONFIG_DMA_NONCOHERENT
578 + return 0;
579 +#endif
580 +}
581 +
582 +#endif /* __ASM_MACH_ATH25_DMA_COHERENCE_H */
583 --- /dev/null
584 +++ b/arch/mips/include/asm/mach-ath25/gpio.h
585 @@ -0,0 +1,16 @@
586 +#ifndef __ASM_MACH_ATH25_GPIO_H
587 +#define __ASM_MACH_ATH25_GPIO_H
588 +
589 +#include <asm-generic/gpio.h>
590 +
591 +#define gpio_get_value __gpio_get_value
592 +#define gpio_set_value __gpio_set_value
593 +#define gpio_cansleep __gpio_cansleep
594 +#define gpio_to_irq __gpio_to_irq
595 +
596 +static inline int irq_to_gpio(unsigned irq)
597 +{
598 + return -EINVAL;
599 +}
600 +
601 +#endif /* __ASM_MACH_ATH25_GPIO_H */
602 --- /dev/null
603 +++ b/arch/mips/include/asm/mach-ath25/war.h
604 @@ -0,0 +1,25 @@
605 +/*
606 + * This file is subject to the terms and conditions of the GNU General Public
607 + * License. See the file "COPYING" in the main directory of this archive
608 + * for more details.
609 + *
610 + * Copyright (C) 2008 Felix Fietkau <nbd@openwrt.org>
611 + */
612 +#ifndef __ASM_MACH_ATH25_WAR_H
613 +#define __ASM_MACH_ATH25_WAR_H
614 +
615 +#define R4600_V1_INDEX_ICACHEOP_WAR 0
616 +#define R4600_V1_HIT_CACHEOP_WAR 0
617 +#define R4600_V2_HIT_CACHEOP_WAR 0
618 +#define R5432_CP0_INTERRUPT_WAR 0
619 +#define BCM1250_M3_WAR 0
620 +#define SIBYTE_1956_WAR 0
621 +#define MIPS4K_ICACHE_REFILL_WAR 0
622 +#define MIPS_CACHE_SYNC_WAR 0
623 +#define TX49XX_ICACHE_INDEX_INV_WAR 0
624 +#define RM9000_CDEX_SMP_WAR 0
625 +#define ICACHE_REFILLS_WORKAROUND_WAR 0
626 +#define R10000_LLSC_WAR 0
627 +#define MIPS34K_MISSED_ITLB_WAR 0
628 +
629 +#endif /* __ASM_MACH_ATH25_WAR_H */
630 --- /dev/null
631 +++ b/arch/mips/include/asm/mach-ath25/ar2315_regs.h
632 @@ -0,0 +1,480 @@
633 +/*
634 + * Register definitions for AR2315+
635 + *
636 + * This file is subject to the terms and conditions of the GNU General Public
637 + * License. See the file "COPYING" in the main directory of this archive
638 + * for more details.
639 + *
640 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
641 + * Copyright (C) 2006 FON Technology, SL.
642 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
643 + * Copyright (C) 2006-2008 Felix Fietkau <nbd@openwrt.org>
644 + */
645 +
646 +#ifndef __ASM_MACH_ATH25_AR2315_REGS_H
647 +#define __ASM_MACH_ATH25_AR2315_REGS_H
648 +
649 +/*
650 + * IRQs
651 + */
652 +#define AR2315_IRQ_MISC_INTRS (MIPS_CPU_IRQ_BASE+2) /* C0_CAUSE: 0x0400 */
653 +#define AR2315_IRQ_WLAN0_INTRS (MIPS_CPU_IRQ_BASE+3) /* C0_CAUSE: 0x0800 */
654 +#define AR2315_IRQ_ENET0_INTRS (MIPS_CPU_IRQ_BASE+4) /* C0_CAUSE: 0x1000 */
655 +#define AR2315_IRQ_LCBUS_PCI (MIPS_CPU_IRQ_BASE+5) /* C0_CAUSE: 0x2000 */
656 +#define AR2315_IRQ_WLAN0_POLL (MIPS_CPU_IRQ_BASE+6) /* C0_CAUSE: 0x4000 */
657 +
658 +/*
659 + * Miscellaneous interrupts, which share IP2.
660 + */
661 +#define AR2315_MISC_IRQ_UART0 (AR231X_MISC_IRQ_BASE+0)
662 +#define AR2315_MISC_IRQ_I2C_RSVD (AR231X_MISC_IRQ_BASE+1)
663 +#define AR2315_MISC_IRQ_SPI (AR231X_MISC_IRQ_BASE+2)
664 +#define AR2315_MISC_IRQ_AHB (AR231X_MISC_IRQ_BASE+3)
665 +#define AR2315_MISC_IRQ_APB (AR231X_MISC_IRQ_BASE+4)
666 +#define AR2315_MISC_IRQ_TIMER (AR231X_MISC_IRQ_BASE+5)
667 +#define AR2315_MISC_IRQ_GPIO (AR231X_MISC_IRQ_BASE+6)
668 +#define AR2315_MISC_IRQ_WATCHDOG (AR231X_MISC_IRQ_BASE+7)
669 +#define AR2315_MISC_IRQ_IR_RSVD (AR231X_MISC_IRQ_BASE+8)
670 +#define AR2315_MISC_IRQ_COUNT 9
671 +
672 +/*
673 + * Address map
674 + */
675 +#define AR2315_SPI_READ 0x08000000 /* SPI FLASH */
676 +#define AR2315_WLAN0 0x10000000 /* Wireless MMR */
677 +#define AR2315_PCI 0x10100000 /* PCI MMR */
678 +#define AR2315_PCI_SIZE 0x00001000
679 +#define AR2315_SDRAMCTL_BASE 0x10300000 /* SDRAM MMR */
680 +#define AR2315_SDRAMCTL_SIZE 0x00000020
681 +#define AR2315_LOCAL_BASE 0x10400000 /* Local bus MMR */
682 +#define AR2315_ENET0 0x10500000 /* ETHERNET MMR */
683 +#define AR2315_RST_BASE 0x11000000 /* Reset control MMR */
684 +#define AR2315_RST_SIZE 0x00000100
685 +#define AR2315_UART0 0x11100000 /* UART MMR */
686 +#define AR2315_SPI_MMR 0x11300000 /* SPI FLASH MMR */
687 +#define AR2315_PCIEXT 0x80000000 /* pci external */
688 +#define AR2315_PCIEXT_SZ 0x40000000
689 +
690 +/* MII registers offset inside Ethernet MMR region */
691 +#define AR2315_ENET0_MII (AR2315_ENET0 + 0x14)
692 +
693 +/*
694 + * Cold reset register
695 + */
696 +#define AR2315_COLD_RESET 0x0000
697 +
698 +#define AR2315_RESET_COLD_AHB 0x00000001
699 +#define AR2315_RESET_COLD_APB 0x00000002
700 +#define AR2315_RESET_COLD_CPU 0x00000004
701 +#define AR2315_RESET_COLD_CPUWARM 0x00000008
702 +#define AR2315_RESET_SYSTEM \
703 + (RESET_COLD_CPU |\
704 + RESET_COLD_APB |\
705 + RESET_COLD_AHB) /* full system */
706 +#define AR2317_RESET_SYSTEM 0x00000010
707 +
708 +/*
709 + * Reset register
710 + */
711 +#define AR2315_RESET 0x0004
712 +
713 +/* warm reset WLAN0 MAC */
714 +#define AR2315_RESET_WARM_WLAN0_MAC 0x00000001
715 +/* warm reset WLAN0 BaseBand */
716 +#define AR2315_RESET_WARM_WLAN0_BB 0x00000002
717 +/* warm reset MPEG-TS */
718 +#define AR2315_RESET_MPEGTS_RSVD 0x00000004
719 +/* warm reset PCI ahb/dma */
720 +#define AR2315_RESET_PCIDMA 0x00000008
721 +/* warm reset memory controller */
722 +#define AR2315_RESET_MEMCTL 0x00000010
723 +/* warm reset local bus */
724 +#define AR2315_RESET_LOCAL 0x00000020
725 +/* warm reset I2C bus */
726 +#define AR2315_RESET_I2C_RSVD 0x00000040
727 +/* warm reset SPI interface */
728 +#define AR2315_RESET_SPI 0x00000080
729 +/* warm reset UART0 */
730 +#define AR2315_RESET_UART0 0x00000100
731 +/* warm reset IR interface */
732 +#define AR2315_RESET_IR_RSVD 0x00000200
733 +/* cold reset ENET0 phy */
734 +#define AR2315_RESET_EPHY0 0x00000400
735 +/* cold reset ENET0 mac */
736 +#define AR2315_RESET_ENET0 0x00000800
737 +
738 +/*
739 + * AHB master arbitration control
740 + */
741 +#define AR2315_AHB_ARB_CTL 0x0008
742 +
743 +/* CPU, default */
744 +#define AR2315_ARB_CPU 0x00000001
745 +/* WLAN */
746 +#define AR2315_ARB_WLAN 0x00000002
747 +/* MPEG-TS */
748 +#define AR2315_ARB_MPEGTS_RSVD 0x00000004
749 +/* LOCAL */
750 +#define AR2315_ARB_LOCAL 0x00000008
751 +/* PCI */
752 +#define AR2315_ARB_PCI 0x00000010
753 +/* Ethernet */
754 +#define AR2315_ARB_ETHERNET 0x00000020
755 +/* retry policy, debug only */
756 +#define AR2315_ARB_RETRY 0x00000100
757 +
758 +/*
759 + * Config Register
760 + */
761 +#define AR2315_ENDIAN_CTL 0x000c
762 +
763 +/* EC - AHB bridge endianess */
764 +#define AR2315_CONFIG_AHB 0x00000001
765 +/* WLAN byteswap */
766 +#define AR2315_CONFIG_WLAN 0x00000002
767 +/* MPEG-TS byteswap */
768 +#define AR2315_CONFIG_MPEGTS_RSVD 0x00000004
769 +/* PCI byteswap */
770 +#define AR2315_CONFIG_PCI 0x00000008
771 +/* Memory controller endianess */
772 +#define AR2315_CONFIG_MEMCTL 0x00000010
773 +/* Local bus byteswap */
774 +#define AR2315_CONFIG_LOCAL 0x00000020
775 +/* Ethernet byteswap */
776 +#define AR2315_CONFIG_ETHERNET 0x00000040
777 +
778 +/* CPU write buffer merge */
779 +#define AR2315_CONFIG_MERGE 0x00000200
780 +/* CPU big endian */
781 +#define AR2315_CONFIG_CPU 0x00000400
782 +#define AR2315_CONFIG_PCIAHB 0x00000800
783 +#define AR2315_CONFIG_PCIAHB_BRIDGE 0x00001000
784 +/* SPI byteswap */
785 +#define AR2315_CONFIG_SPI 0x00008000
786 +#define AR2315_CONFIG_CPU_DRAM 0x00010000
787 +#define AR2315_CONFIG_CPU_PCI 0x00020000
788 +#define AR2315_CONFIG_CPU_MMR 0x00040000
789 +#define AR2315_CONFIG_BIG 0x00000400
790 +
791 +/*
792 + * NMI control
793 + */
794 +#define AR2315_NMI_CTL 0x0010
795 +
796 +#define AR2315_NMI_EN 1
797 +
798 +/*
799 + * Revision Register - Initial value is 0x3010 (WMAC 3.0, AR231X 1.0).
800 + */
801 +#define AR2315_SREV 0x0014
802 +
803 +#define AR2315_REV_MAJ 0x00f0
804 +#define AR2315_REV_MAJ_S 4
805 +#define AR2315_REV_MIN 0x000f
806 +#define AR2315_REV_MIN_S 0
807 +#define AR2315_REV_CHIP (AR2315_REV_MAJ|AR2315_REV_MIN)
808 +
809 +/*
810 + * Interface Enable
811 + */
812 +#define AR2315_IF_CTL 0x0018
813 +
814 +#define AR2315_IF_MASK 0x00000007
815 +#define AR2315_IF_DISABLED 0
816 +#define AR2315_IF_PCI 1
817 +#define AR2315_IF_TS_LOCAL 2
818 +/* only for emulation with separate pins */
819 +#define AR2315_IF_ALL 3
820 +#define AR2315_IF_LOCAL_HOST 0x00000008
821 +#define AR2315_IF_PCI_HOST 0x00000010
822 +#define AR2315_IF_PCI_INTR 0x00000020
823 +#define AR2315_IF_PCI_CLK_MASK 0x00030000
824 +#define AR2315_IF_PCI_CLK_INPUT 0
825 +#define AR2315_IF_PCI_CLK_OUTPUT_LOW 1
826 +#define AR2315_IF_PCI_CLK_OUTPUT_CLK 2
827 +#define AR2315_IF_PCI_CLK_OUTPUT_HIGH 3
828 +#define AR2315_IF_PCI_CLK_SHIFT 16
829 +
830 +/*
831 + * APB Interrupt control
832 + */
833 +
834 +#define AR2315_ISR 0x0020
835 +#define AR2315_IMR 0x0024
836 +#define AR2315_GISR 0x0028
837 +
838 +#define AR2315_ISR_UART0 0x0001 /* high speed UART */
839 +#define AR2315_ISR_I2C_RSVD 0x0002 /* I2C bus */
840 +#define AR2315_ISR_SPI 0x0004 /* SPI bus */
841 +#define AR2315_ISR_AHB 0x0008 /* AHB error */
842 +#define AR2315_ISR_APB 0x0010 /* APB error */
843 +#define AR2315_ISR_TIMER 0x0020 /* timer */
844 +#define AR2315_ISR_GPIO 0x0040 /* GPIO */
845 +#define AR2315_ISR_WD 0x0080 /* watchdog */
846 +#define AR2315_ISR_IR_RSVD 0x0100 /* IR */
847 +
848 +#define AR2315_GISR_MISC 0x0001
849 +#define AR2315_GISR_WLAN0 0x0002
850 +#define AR2315_GISR_MPEGTS_RSVD 0x0004
851 +#define AR2315_GISR_LOCALPCI 0x0008
852 +#define AR2315_GISR_WMACPOLL 0x0010
853 +#define AR2315_GISR_TIMER 0x0020
854 +#define AR2315_GISR_ETHERNET 0x0040
855 +
856 +/*
857 + * Timers
858 + */
859 +#define AR2315_TIMER 0x0030
860 +#define AR2315_RELOAD 0x0034
861 +
862 +#define AR2315_WD 0x0038
863 +#define AR2315_WDC 0x003c
864 +
865 +#define AR2315_WDC_IGNORE_EXPIRATION 0x00000000
866 +#define AR2315_WDC_NMI 0x00000001 /* NMI on watchdog */
867 +#define AR2315_WDC_RESET 0x00000002 /* reset on watchdog */
868 +
869 +/*
870 + * CPU Performance Counters
871 + */
872 +#define AR2315_PERFCNT0 0x0048
873 +#define AR2315_PERFCNT1 0x004c
874 +
875 +#define AR2315_PERF0_DATAHIT 0x0001 /* Count Data Cache Hits */
876 +#define AR2315_PERF0_DATAMISS 0x0002 /* Count Data Cache Misses */
877 +#define AR2315_PERF0_INSTHIT 0x0004 /* Count Instruction Cache Hits */
878 +#define AR2315_PERF0_INSTMISS 0x0008 /* Count Instruction Cache Misses */
879 +#define AR2315_PERF0_ACTIVE 0x0010 /* Count Active Processor Cycles */
880 +#define AR2315_PERF0_WBHIT 0x0020 /* Count CPU Write Buffer Hits */
881 +#define AR2315_PERF0_WBMISS 0x0040 /* Count CPU Write Buffer Misses */
882 +
883 +#define AR2315_PERF1_EB_ARDY 0x0001 /* Count EB_ARdy signal */
884 +#define AR2315_PERF1_EB_AVALID 0x0002 /* Count EB_AValid signal */
885 +#define AR2315_PERF1_EB_WDRDY 0x0004 /* Count EB_WDRdy signal */
886 +#define AR2315_PERF1_EB_RDVAL 0x0008 /* Count EB_RdVal signal */
887 +#define AR2315_PERF1_VRADDR 0x0010 /* Count valid read address cycles */
888 +#define AR2315_PERF1_VWADDR 0x0020 /* Count valid write address cycles */
889 +#define AR2315_PERF1_VWDATA 0x0040 /* Count valid write data cycles */
890 +
891 +/*
892 + * AHB Error Reporting.
893 + */
894 +#define AR2315_AHB_ERR0 0x0050 /* error */
895 +#define AR2315_AHB_ERR1 0x0054 /* haddr */
896 +#define AR2315_AHB_ERR2 0x0058 /* hwdata */
897 +#define AR2315_AHB_ERR3 0x005c /* hrdata */
898 +#define AR2315_AHB_ERR4 0x0060 /* status */
899 +
900 +#define AHB_ERROR_DET 1 /* AHB Error has been detected, */
901 + /* write 1 to clear all bits in ERR0 */
902 +#define AHB_ERROR_OVR 2 /* AHB Error overflow has been detected */
903 +#define AHB_ERROR_WDT 4 /* AHB Error due to wdt instead of hresp */
904 +
905 +#define AR2315_PROCERR_HMAST 0x0000000f
906 +#define AR2315_PROCERR_HMAST_DFLT 0
907 +#define AR2315_PROCERR_HMAST_WMAC 1
908 +#define AR2315_PROCERR_HMAST_ENET 2
909 +#define AR2315_PROCERR_HMAST_PCIENDPT 3
910 +#define AR2315_PROCERR_HMAST_LOCAL 4
911 +#define AR2315_PROCERR_HMAST_CPU 5
912 +#define AR2315_PROCERR_HMAST_PCITGT 6
913 +
914 +#define AR2315_PROCERR_HMAST_S 0
915 +#define AR2315_PROCERR_HWRITE 0x00000010
916 +#define AR2315_PROCERR_HSIZE 0x00000060
917 +#define AR2315_PROCERR_HSIZE_S 5
918 +#define AR2315_PROCERR_HTRANS 0x00000180
919 +#define AR2315_PROCERR_HTRANS_S 7
920 +#define AR2315_PROCERR_HBURST 0x00000e00
921 +#define AR2315_PROCERR_HBURST_S 9
922 +
923 +/*
924 + * Clock Control
925 + */
926 +#define AR2315_PLLC_CTL 0x0064
927 +#define AR2315_PLLV_CTL 0x0068
928 +#define AR2315_CPUCLK 0x006c
929 +#define AR2315_AMBACLK 0x0070
930 +#define AR2315_SYNCCLK 0x0074
931 +#define AR2315_DSL_SLEEP_CTL 0x0080
932 +#define AR2315_DSL_SLEEP_DUR 0x0084
933 +
934 +/* PLLc Control fields */
935 +#define PLLC_REF_DIV_M 0x00000003
936 +#define PLLC_REF_DIV_S 0
937 +#define PLLC_FDBACK_DIV_M 0x0000007C
938 +#define PLLC_FDBACK_DIV_S 2
939 +#define PLLC_ADD_FDBACK_DIV_M 0x00000080
940 +#define PLLC_ADD_FDBACK_DIV_S 7
941 +#define PLLC_CLKC_DIV_M 0x0001c000
942 +#define PLLC_CLKC_DIV_S 14
943 +#define PLLC_CLKM_DIV_M 0x00700000
944 +#define PLLC_CLKM_DIV_S 20
945 +
946 +/* CPU CLK Control fields */
947 +#define CPUCLK_CLK_SEL_M 0x00000003
948 +#define CPUCLK_CLK_SEL_S 0
949 +#define CPUCLK_CLK_DIV_M 0x0000000c
950 +#define CPUCLK_CLK_DIV_S 2
951 +
952 +/* AMBA CLK Control fields */
953 +#define AMBACLK_CLK_SEL_M 0x00000003
954 +#define AMBACLK_CLK_SEL_S 0
955 +#define AMBACLK_CLK_DIV_M 0x0000000c
956 +#define AMBACLK_CLK_DIV_S 2
957 +
958 +/* GPIO MMR base address */
959 +#define AR2315_GPIO 0x0088
960 +
961 +#define AR2315_RESET_GPIO 5
962 +
963 +/*
964 + * PCI Clock Control
965 + */
966 +#define AR2315_PCICLK 0x00a4
967 +
968 +#define AR2315_PCICLK_INPUT_M 0x3
969 +#define AR2315_PCICLK_INPUT_S 0
970 +
971 +#define AR2315_PCICLK_PLLC_CLKM 0
972 +#define AR2315_PCICLK_PLLC_CLKM1 1
973 +#define AR2315_PCICLK_PLLC_CLKC 2
974 +#define AR2315_PCICLK_REF_CLK 3
975 +
976 +#define AR2315_PCICLK_DIV_M 0xc
977 +#define AR2315_PCICLK_DIV_S 2
978 +
979 +#define AR2315_PCICLK_IN_FREQ 0
980 +#define AR2315_PCICLK_IN_FREQ_DIV_6 1
981 +#define AR2315_PCICLK_IN_FREQ_DIV_8 2
982 +#define AR2315_PCICLK_IN_FREQ_DIV_10 3
983 +
984 +/*
985 + * Observation Control Register
986 + */
987 +#define AR2315_OCR 0x00b0
988 +
989 +#define OCR_GPIO0_IRIN 0x0040
990 +#define OCR_GPIO1_IROUT 0x0080
991 +#define OCR_GPIO3_RXCLR 0x0200
992 +
993 +/*
994 + * General Clock Control
995 + */
996 +#define AR2315_MISCCLK 0x00b4
997 +
998 +#define MISCCLK_PLLBYPASS_EN 0x00000001
999 +#define MISCCLK_PROCREFCLK 0x00000002
1000 +
1001 +/*
1002 + * SDRAM Controller
1003 + * - No read or write buffers are included.
1004 + */
1005 +#define AR2315_MEM_CFG 0x0000
1006 +#define AR2315_MEM_CTRL 0x000c
1007 +#define AR2315_MEM_REF 0x0010
1008 +
1009 +#define SDRAM_DATA_WIDTH_M 0x00006000
1010 +#define SDRAM_DATA_WIDTH_S 13
1011 +
1012 +#define SDRAM_COL_WIDTH_M 0x00001E00
1013 +#define SDRAM_COL_WIDTH_S 9
1014 +
1015 +#define SDRAM_ROW_WIDTH_M 0x000001E0
1016 +#define SDRAM_ROW_WIDTH_S 5
1017 +
1018 +#define SDRAM_BANKADDR_BITS_M 0x00000018
1019 +#define SDRAM_BANKADDR_BITS_S 3
1020 +
1021 +/*
1022 + * Local Bus Interface Registers
1023 + */
1024 +#define AR2315_LB_CONFIG 0x0000
1025 +
1026 +#define AR2315_LBCONF_OE 0x00000001 /* =1 OE is low-true */
1027 +#define AR2315_LBCONF_CS0 0x00000002 /* =1 first CS is low-true */
1028 +#define AR2315_LBCONF_CS1 0x00000004 /* =1 2nd CS is low-true */
1029 +#define AR2315_LBCONF_RDY 0x00000008 /* =1 RDY is low-true */
1030 +#define AR2315_LBCONF_WE 0x00000010 /* =1 Write En is low-true */
1031 +#define AR2315_LBCONF_WAIT 0x00000020 /* =1 WAIT is low-true */
1032 +#define AR2315_LBCONF_ADS 0x00000040 /* =1 Adr Strobe is low-true */
1033 +#define AR2315_LBCONF_MOT 0x00000080 /* =0 Intel, =1 Motorola */
1034 +#define AR2315_LBCONF_8CS 0x00000100 /* =1 8 bits CS, 0= 16bits */
1035 +#define AR2315_LBCONF_8DS 0x00000200 /* =1 8 bits Data S, 0=16bits */
1036 +#define AR2315_LBCONF_ADS_EN 0x00000400 /* =1 Enable ADS */
1037 +#define AR2315_LBCONF_ADR_OE 0x00000800 /* =1 Adr cap on OE, WE or DS */
1038 +#define AR2315_LBCONF_ADDT_MUX 0x00001000 /* =1 Adr and Data share bus */
1039 +#define AR2315_LBCONF_DATA_OE 0x00002000 /* =1 Data cap on OE, WE, DS */
1040 +#define AR2315_LBCONF_16DATA 0x00004000 /* =1 Data is 16 bits wide */
1041 +#define AR2315_LBCONF_SWAPDT 0x00008000 /* =1 Byte swap data */
1042 +#define AR2315_LBCONF_SYNC 0x00010000 /* =1 Bus synchronous to clk */
1043 +#define AR2315_LBCONF_INT 0x00020000 /* =1 Intr is low true */
1044 +#define AR2315_LBCONF_INT_CTR0 0x00000000 /* GND high-Z, Vdd is high-Z */
1045 +#define AR2315_LBCONF_INT_CTR1 0x00040000 /* GND drive, Vdd is high-Z */
1046 +#define AR2315_LBCONF_INT_CTR2 0x00080000 /* GND high-Z, Vdd drive */
1047 +#define AR2315_LBCONF_INT_CTR3 0x000C0000 /* GND drive, Vdd drive */
1048 +#define AR2315_LBCONF_RDY_WAIT 0x00100000 /* =1 RDY is negative of WAIT */
1049 +#define AR2315_LBCONF_INT_PULSE 0x00200000 /* =1 Interrupt is a pulse */
1050 +#define AR2315_LBCONF_ENABLE 0x00400000 /* =1 Falcon respond to LB */
1051 +
1052 +#define AR2315_LB_CLKSEL 0x0004
1053 +
1054 +#define AR2315_LBCLK_EXT 0x0001 /* use external clk for lb */
1055 +
1056 +#define AR2315_LB_1MS 0x0008
1057 +
1058 +#define AR2315_LB1MS_MASK 0x3FFFF /* # of AHB clk cycles in 1ms */
1059 +
1060 +#define AR2315_LB_MISCCFG 0x000c
1061 +#define AR2315_LBM_TXD_EN 0x00000001 /* Enable TXD for fragments */
1062 +#define AR2315_LBM_RX_INTEN 0x00000002 /* Enable LB ints on RX ready */
1063 +#define AR2315_LBM_MBOXWR_INTEN 0x00000004 /* Enable LB ints on mbox wr */
1064 +#define AR2315_LBM_MBOXRD_INTEN 0x00000008 /* Enable LB ints on mbox rd */
1065 +#define AR2315_LMB_DESCSWAP_EN 0x00000010 /* Byte swap desc enable */
1066 +#define AR2315_LBM_TIMEOUT_MASK 0x00FFFF80
1067 +#define AR2315_LBM_TIMEOUT_SHFT 7
1068 +#define AR2315_LBM_PORTMUX 0x07000000
1069 +
1070 +#define AR2315_LB_RXTSOFF 0x0010
1071 +
1072 +#define AR2315_LB_TX_CHAIN_EN 0x0100
1073 +
1074 +#define AR2315_LB_TXEN_0 0x01
1075 +#define AR2315_LB_TXEN_1 0x02
1076 +#define AR2315_LB_TXEN_2 0x04
1077 +#define AR2315_LB_TXEN_3 0x08
1078 +
1079 +#define AR2315_LB_TX_CHAIN_DIS 0x0104
1080 +#define AR2315_LB_TX_DESC_PTR 0x0200
1081 +
1082 +#define AR2315_LB_RX_CHAIN_EN 0x0400
1083 +
1084 +#define AR2315_LB_RXEN 0x01
1085 +
1086 +#define AR2315_LB_RX_CHAIN_DIS 0x0404
1087 +#define AR2315_LB_RX_DESC_PTR 0x0408
1088 +
1089 +#define AR2315_LB_INT_STATUS 0x0500
1090 +
1091 +#define AR2315_INT_TX_DESC 0x0001
1092 +#define AR2315_INT_TX_OK 0x0002
1093 +#define AR2315_INT_TX_ERR 0x0004
1094 +#define AR2315_INT_TX_EOF 0x0008
1095 +#define AR2315_INT_RX_DESC 0x0010
1096 +#define AR2315_INT_RX_OK 0x0020
1097 +#define AR2315_INT_RX_ERR 0x0040
1098 +#define AR2315_INT_RX_EOF 0x0080
1099 +#define AR2315_INT_TX_TRUNC 0x0100
1100 +#define AR2315_INT_TX_STARVE 0x0200
1101 +#define AR2315_INT_LB_TIMEOUT 0x0400
1102 +#define AR2315_INT_LB_ERR 0x0800
1103 +#define AR2315_INT_MBOX_WR 0x1000
1104 +#define AR2315_INT_MBOX_RD 0x2000
1105 +
1106 +/* Bit definitions for INT MASK are the same as INT_STATUS */
1107 +#define AR2315_LB_INT_MASK 0x0504
1108 +
1109 +#define AR2315_LB_INT_EN 0x0508
1110 +#define AR2315_LB_MBOX 0x0600
1111 +
1112 +#endif /* __ASM_MACH_ATH25_AR2315_REGS_H */
1113 --- /dev/null
1114 +++ b/arch/mips/include/asm/mach-ath25/ar5312_regs.h
1115 @@ -0,0 +1,227 @@
1116 +/*
1117 + * This file is subject to the terms and conditions of the GNU General Public
1118 + * License. See the file "COPYING" in the main directory of this archive
1119 + * for more details.
1120 + *
1121 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
1122 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
1123 + * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
1124 + */
1125 +
1126 +#ifndef __ASM_MACH_ATH25_AR5312_REGS_H
1127 +#define __ASM_MACH_ATH25_AR5312_REGS_H
1128 +
1129 +#include <asm/addrspace.h>
1130 +
1131 +/*
1132 + * IRQs
1133 + */
1134 +#define AR5312_IRQ_WLAN0_INTRS (MIPS_CPU_IRQ_BASE+2) /* C0_CAUSE: 0x0400 */
1135 +#define AR5312_IRQ_ENET0_INTRS (MIPS_CPU_IRQ_BASE+3) /* C0_CAUSE: 0x0800 */
1136 +#define AR5312_IRQ_ENET1_INTRS (MIPS_CPU_IRQ_BASE+4) /* C0_CAUSE: 0x1000 */
1137 +#define AR5312_IRQ_WLAN1_INTRS (MIPS_CPU_IRQ_BASE+5) /* C0_CAUSE: 0x2000 */
1138 +#define AR5312_IRQ_MISC_INTRS (MIPS_CPU_IRQ_BASE+6) /* C0_CAUSE: 0x4000 */
1139 +
1140 +/*
1141 + * Miscellaneous interrupts, which share IP6.
1142 + */
1143 +#define AR5312_MISC_IRQ_TIMER (AR231X_MISC_IRQ_BASE+0)
1144 +#define AR5312_MISC_IRQ_AHB_PROC (AR231X_MISC_IRQ_BASE+1)
1145 +#define AR5312_MISC_IRQ_AHB_DMA (AR231X_MISC_IRQ_BASE+2)
1146 +#define AR5312_MISC_IRQ_GPIO (AR231X_MISC_IRQ_BASE+3)
1147 +#define AR5312_MISC_IRQ_UART0 (AR231X_MISC_IRQ_BASE+4)
1148 +#define AR5312_MISC_IRQ_UART0_DMA (AR231X_MISC_IRQ_BASE+5)
1149 +#define AR5312_MISC_IRQ_WATCHDOG (AR231X_MISC_IRQ_BASE+6)
1150 +#define AR5312_MISC_IRQ_LOCAL (AR231X_MISC_IRQ_BASE+7)
1151 +#define AR5312_MISC_IRQ_SPI (AR231X_MISC_IRQ_BASE+8)
1152 +#define AR5312_MISC_IRQ_COUNT 9
1153 +
1154 +/*
1155 + * Address Map
1156 + *
1157 + * The AR5312 supports 2 enet MACS, even though many reference boards only
1158 + * actually use 1 of them (i.e. Only MAC 0 is actually connected to an enet
1159 + * PHY or PHY switch. The AR2312 supports 1 enet MAC.
1160 + */
1161 +#define AR5312_WLAN0 0x18000000
1162 +#define AR5312_WLAN1 0x18500000
1163 +#define AR5312_ENET0 0x18100000
1164 +#define AR5312_ENET1 0x18200000
1165 +#define AR5312_SDRAMCTL_BASE 0x18300000
1166 +#define AR5312_SDRAMCTL_SIZE 0x00000010
1167 +#define AR5312_FLASHCTL_BASE 0x18400000
1168 +#define AR5312_FLASHCTL_SIZE 0x00000010
1169 +#define AR5312_UART0 0x1c000000 /* UART MMR */
1170 +#define AR5312_GPIO_BASE 0x1c002000
1171 +#define AR5312_RST_BASE 0x1c003000
1172 +#define AR5312_RST_SIZE 0x00000100
1173 +#define AR5312_FLASH 0x1e000000
1174 +
1175 +/*
1176 + * Need these defines to determine true number of ethernet MACs
1177 + */
1178 +#define AR5312_AR5312_REV2 0x0052 /* AR5312 WMAC (AP31) */
1179 +#define AR5312_AR5312_REV7 0x0057 /* AR5312 WMAC (AP30-040) */
1180 +#define AR5312_AR2313_REV8 0x0058 /* AR2313 WMAC (AP43-030) */
1181 +
1182 +/* MII registers offset inside Ethernet MMR region */
1183 +#define AR5312_ENET0_MII (AR5312_ENET0 + 0x14)
1184 +#define AR5312_ENET1_MII (AR5312_ENET1 + 0x14)
1185 +
1186 +/* Reset/Timer Block Address Map */
1187 +#define AR5312_TIMER 0x0000 /* countdown timer */
1188 +#define AR5312_RELOAD 0x0004 /* timer reload value */
1189 +#define AR5312_WD_CTRL 0x0008 /* watchdog cntrl */
1190 +#define AR5312_WD_TIMER 0x000c /* watchdog timer */
1191 +#define AR5312_ISR 0x0010 /* Intr Status Reg */
1192 +#define AR5312_IMR 0x0014 /* Intr Mask Reg */
1193 +#define AR5312_RESET 0x0020
1194 +#define AR5312_CLOCKCTL1 0x0064
1195 +#define AR5312_SCRATCH 0x006c
1196 +#define AR5312_PROCADDR 0x0070
1197 +#define AR5312_PROC1 0x0074
1198 +#define AR5312_DMAADDR 0x0078
1199 +#define AR5312_DMA1 0x007c
1200 +#define AR5312_ENABLE 0x0080 /* interface enb */
1201 +#define AR5312_REV 0x0090 /* revision */
1202 +
1203 +/* AR5312_WD_CTRL register bit field definitions */
1204 +#define AR5312_WD_CTRL_IGNORE_EXPIRATION 0x0000
1205 +#define AR5312_WD_CTRL_NMI 0x0001
1206 +#define AR5312_WD_CTRL_RESET 0x0002
1207 +
1208 +/* AR5312_ISR register bit field definitions */
1209 +#define AR5312_ISR_TIMER 0x0001
1210 +#define AR5312_ISR_AHBPROC 0x0002
1211 +#define AR5312_ISR_AHBDMA 0x0004
1212 +#define AR5312_ISR_GPIO 0x0008
1213 +#define AR5312_ISR_UART0 0x0010
1214 +#define AR5312_ISR_UART0DMA 0x0020
1215 +#define AR5312_ISR_WD 0x0040
1216 +#define AR5312_ISR_LOCAL 0x0080
1217 +
1218 +/* AR5312_RESET register bit field definitions */
1219 +#define AR5312_RESET_SYSTEM 0x00000001 /* cold reset full system */
1220 +#define AR5312_RESET_PROC 0x00000002 /* cold reset MIPS core */
1221 +#define AR5312_RESET_WLAN0 0x00000004 /* cold reset WLAN MAC and BB */
1222 +#define AR5312_RESET_EPHY0 0x00000008 /* cold reset ENET0 phy */
1223 +#define AR5312_RESET_EPHY1 0x00000010 /* cold reset ENET1 phy */
1224 +#define AR5312_RESET_ENET0 0x00000020 /* cold reset ENET0 mac */
1225 +#define AR5312_RESET_ENET1 0x00000040 /* cold reset ENET1 mac */
1226 +#define AR5312_RESET_UART0 0x00000100 /* cold reset UART0 (high speed) */
1227 +#define AR5312_RESET_WLAN1 0x00000200 /* cold reset WLAN MAC/BB */
1228 +#define AR5312_RESET_APB 0x00000400 /* cold reset APB (ar5312) */
1229 +#define AR5312_RESET_WARM_PROC 0x00001000 /* warm reset MIPS core */
1230 +#define AR5312_RESET_WARM_WLAN0_MAC 0x00002000 /* warm reset WLAN0 MAC */
1231 +#define AR5312_RESET_WARM_WLAN0_BB 0x00004000 /* warm reset WLAN0 BaseBand */
1232 +#define AR5312_RESET_NMI 0x00010000 /* send an NMI to the processor */
1233 +#define AR5312_RESET_WARM_WLAN1_MAC 0x00020000 /* warm reset WLAN1 mac */
1234 +#define AR5312_RESET_WARM_WLAN1_BB 0x00040000 /* warm reset WLAN1 baseband */
1235 +#define AR5312_RESET_LOCAL_BUS 0x00080000 /* reset local bus */
1236 +#define AR5312_RESET_WDOG 0x00100000 /* last reset was a watchdog */
1237 +
1238 +#define AR5312_RESET_WMAC0_BITS \
1239 + (AR5312_RESET_WLAN0 |\
1240 + AR5312_RESET_WARM_WLAN0_MAC |\
1241 + AR5312_RESET_WARM_WLAN0_BB)
1242 +
1243 +#define AR5312_RESET_WMAC1_BITS \
1244 + (AR5312_RESET_WLAN1 |\
1245 + AR5312_RESET_WARM_WLAN1_MAC |\
1246 + AR5312_RESET_WARM_WLAN1_BB)
1247 +
1248 +/* AR5312_CLOCKCTL1 register bit field definitions */
1249 +#define AR5312_CLOCKCTL1_PREDIVIDE_MASK 0x00000030
1250 +#define AR5312_CLOCKCTL1_PREDIVIDE_SHIFT 4
1251 +#define AR5312_CLOCKCTL1_MULTIPLIER_MASK 0x00001f00
1252 +#define AR5312_CLOCKCTL1_MULTIPLIER_SHIFT 8
1253 +#define AR5312_CLOCKCTL1_DOUBLER_MASK 0x00010000
1254 +
1255 +/* Valid for AR5312 and AR2312 */
1256 +#define AR5312_CLOCKCTL1_PREDIVIDE_MASK 0x00000030
1257 +#define AR5312_CLOCKCTL1_PREDIVIDE_SHIFT 4
1258 +#define AR5312_CLOCKCTL1_MULTIPLIER_MASK 0x00001f00
1259 +#define AR5312_CLOCKCTL1_MULTIPLIER_SHIFT 8
1260 +#define AR5312_CLOCKCTL1_DOUBLER_MASK 0x00010000
1261 +
1262 +/* Valid for AR2313 */
1263 +#define AR2313_CLOCKCTL1_PREDIVIDE_MASK 0x00003000
1264 +#define AR2313_CLOCKCTL1_PREDIVIDE_SHIFT 12
1265 +#define AR2313_CLOCKCTL1_MULTIPLIER_MASK 0x001f0000
1266 +#define AR2313_CLOCKCTL1_MULTIPLIER_SHIFT 16
1267 +#define AR2313_CLOCKCTL1_DOUBLER_MASK 0x00000000
1268 +
1269 +/* AR5312_ENABLE register bit field definitions */
1270 +#define AR5312_ENABLE_WLAN0 0x0001
1271 +#define AR5312_ENABLE_ENET0 0x0002
1272 +#define AR5312_ENABLE_ENET1 0x0004
1273 +#define AR5312_ENABLE_UART_AND_WLAN1_PIO 0x0008 /* UART, and WLAN1 PIOs */
1274 +#define AR5312_ENABLE_WLAN1_DMA 0x0010 /* WLAN1 DMAs */
1275 +#define AR5312_ENABLE_WLAN1 \
1276 + (AR5312_ENABLE_UART_AND_WLAN1_PIO |\
1277 + AR5312_ENABLE_WLAN1_DMA)
1278 +
1279 +/* AR5312_REV register bit field definitions */
1280 +#define AR5312_REV_WMAC_MAJ 0xf000
1281 +#define AR5312_REV_WMAC_MAJ_S 12
1282 +#define AR5312_REV_WMAC_MIN 0x0f00
1283 +#define AR5312_REV_WMAC_MIN_S 8
1284 +#define AR5312_REV_MAJ 0x00f0
1285 +#define AR5312_REV_MAJ_S 4
1286 +#define AR5312_REV_MIN 0x000f
1287 +#define AR5312_REV_MIN_S 0
1288 +#define AR5312_REV_CHIP (AR5312_REV_MAJ|AR5312_REV_MIN)
1289 +
1290 +/* Major revision numbers, bits 7..4 of Revision ID register */
1291 +#define AR5312_REV_MAJ_AR5312 0x4
1292 +#define AR5312_REV_MAJ_AR2313 0x5
1293 +
1294 +/* Minor revision numbers, bits 3..0 of Revision ID register */
1295 +#define AR5312_REV_MIN_DUAL 0x0 /* Dual WLAN version */
1296 +#define AR5312_REV_MIN_SINGLE 0x1 /* Single WLAN version */
1297 +
1298 +/* ARM Flash Controller -- 3 flash banks with either x8 or x16 devices. */
1299 +#define AR5312_FLASHCTL0 0x0000
1300 +#define AR5312_FLASHCTL1 0x0004
1301 +#define AR5312_FLASHCTL2 0x0008
1302 +
1303 +/* AR5312_FLASHCTL register bit field definitions */
1304 +#define FLASHCTL_IDCY 0x0000000f /* Idle cycle turn around time */
1305 +#define FLASHCTL_IDCY_S 0
1306 +#define FLASHCTL_WST1 0x000003e0 /* Wait state 1 */
1307 +#define FLASHCTL_WST1_S 5
1308 +#define FLASHCTL_RBLE 0x00000400 /* Read byte lane enable */
1309 +#define FLASHCTL_WST2 0x0000f800 /* Wait state 2 */
1310 +#define FLASHCTL_WST2_S 11
1311 +#define FLASHCTL_AC 0x00070000 /* Flash address check (added) */
1312 +#define FLASHCTL_AC_S 16
1313 +#define FLASHCTL_AC_128K 0x00000000
1314 +#define FLASHCTL_AC_256K 0x00010000
1315 +#define FLASHCTL_AC_512K 0x00020000
1316 +#define FLASHCTL_AC_1M 0x00030000
1317 +#define FLASHCTL_AC_2M 0x00040000
1318 +#define FLASHCTL_AC_4M 0x00050000
1319 +#define FLASHCTL_AC_8M 0x00060000
1320 +#define FLASHCTL_AC_RES 0x00070000 /* 16MB is not supported */
1321 +#define FLASHCTL_E 0x00080000 /* Flash bank enable (added) */
1322 +#define FLASHCTL_BUSERR 0x01000000 /* Bus transfer error status flag */
1323 +#define FLASHCTL_WPERR 0x02000000 /* Write protect error status flag */
1324 +#define FLASHCTL_WP 0x04000000 /* Write protect */
1325 +#define FLASHCTL_BM 0x08000000 /* Burst mode */
1326 +#define FLASHCTL_MW 0x30000000 /* Memory width */
1327 +#define FLASHCTL_MW8 0x00000000 /* Memory width x8 */
1328 +#define FLASHCTL_MW16 0x10000000 /* Memory width x16 */
1329 +#define FLASHCTL_MW32 0x20000000 /* Memory width x32 (not supported) */
1330 +#define FLASHCTL_ATNR 0x00000000 /* Access type == no retry */
1331 +#define FLASHCTL_ATR 0x80000000 /* Access type == retry every */
1332 +#define FLASHCTL_ATR4 0xc0000000 /* Access type == retry every 4 */
1333 +
1334 +/* ARM SDRAM Controller -- just enough to determine memory size */
1335 +#define AR5312_MEM_CFG1 0x0004
1336 +
1337 +#define MEM_CFG1_AC0 0x00000700 /* bank 0: SDRAM addr check (added) */
1338 +#define MEM_CFG1_AC0_S 8
1339 +#define MEM_CFG1_AC1 0x00007000 /* bank 1: SDRAM addr check (added) */
1340 +#define MEM_CFG1_AC1_S 12
1341 +
1342 +#endif /* __ASM_MACH_ATH25_AR5312_REGS_H */
1343 --- /dev/null
1344 +++ b/arch/mips/ath25/ar5312.c
1345 @@ -0,0 +1,483 @@
1346 +/*
1347 + * This file is subject to the terms and conditions of the GNU General Public
1348 + * License. See the file "COPYING" in the main directory of this archive
1349 + * for more details.
1350 + *
1351 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
1352 + * Copyright (C) 2006 FON Technology, SL.
1353 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
1354 + * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
1355 + * Copyright (C) 2012 Alexandros C. Couloumbis <alex@ozo.com>
1356 + */
1357 +
1358 +/*
1359 + * Platform devices for Atheros SoCs
1360 + */
1361 +
1362 +#include <generated/autoconf.h>
1363 +#include <linux/init.h>
1364 +#include <linux/module.h>
1365 +#include <linux/types.h>
1366 +#include <linux/string.h>
1367 +#include <linux/mtd/physmap.h>
1368 +#include <linux/platform_device.h>
1369 +#include <linux/kernel.h>
1370 +#include <linux/reboot.h>
1371 +#include <linux/leds.h>
1372 +#include <linux/gpio.h>
1373 +#include <asm/bootinfo.h>
1374 +#include <asm/reboot.h>
1375 +#include <asm/time.h>
1376 +#include <linux/irq.h>
1377 +#include <linux/io.h>
1378 +
1379 +#include <ath25_platform.h>
1380 +#include <ar5312_regs.h>
1381 +#include <ar231x.h>
1382 +#include "devices.h"
1383 +#include "ar5312.h"
1384 +
1385 +static void __iomem *ar5312_rst_base;
1386 +
1387 +static inline u32 ar5312_rst_reg_read(u32 reg)
1388 +{
1389 + return __raw_readl(ar5312_rst_base + reg);
1390 +}
1391 +
1392 +static inline void ar5312_rst_reg_write(u32 reg, u32 val)
1393 +{
1394 + __raw_writel(val, ar5312_rst_base + reg);
1395 +}
1396 +
1397 +static inline void ar5312_rst_reg_mask(u32 reg, u32 mask, u32 val)
1398 +{
1399 + u32 ret = ar5312_rst_reg_read(reg);
1400 +
1401 + ret &= ~mask;
1402 + ret |= val;
1403 + ar5312_rst_reg_write(reg, ret);
1404 +}
1405 +
1406 +static irqreturn_t ar5312_ahb_err_handler(int cpl, void *dev_id)
1407 +{
1408 + u32 proc1 = ar5312_rst_reg_read(AR5312_PROC1);
1409 + u32 proc_addr = ar5312_rst_reg_read(AR5312_PROCADDR); /* clears error */
1410 + u32 dma1 = ar5312_rst_reg_read(AR5312_DMA1);
1411 + u32 dma_addr = ar5312_rst_reg_read(AR5312_DMAADDR); /* clears error */
1412 +
1413 + pr_emerg("AHB interrupt: PROCADDR=0x%8.8x PROC1=0x%8.8x DMAADDR=0x%8.8x DMA1=0x%8.8x\n",
1414 + proc_addr, proc1, dma_addr, dma1);
1415 +
1416 + machine_restart("AHB error"); /* Catastrophic failure */
1417 + return IRQ_HANDLED;
1418 +}
1419 +
1420 +static struct irqaction ar5312_ahb_err_interrupt = {
1421 + .handler = ar5312_ahb_err_handler,
1422 + .name = "ar5312-ahb-error",
1423 +};
1424 +
1425 +static void ar5312_misc_irq_handler(unsigned irq, struct irq_desc *desc)
1426 +{
1427 + unsigned int ar231x_misc_intrs = ar5312_rst_reg_read(AR5312_ISR) &
1428 + ar5312_rst_reg_read(AR5312_IMR);
1429 +
1430 + if (ar231x_misc_intrs & AR5312_ISR_TIMER) {
1431 + generic_handle_irq(AR5312_MISC_IRQ_TIMER);
1432 + (void)ar5312_rst_reg_read(AR5312_TIMER);
1433 + } else if (ar231x_misc_intrs & AR5312_ISR_AHBPROC)
1434 + generic_handle_irq(AR5312_MISC_IRQ_AHB_PROC);
1435 + else if ((ar231x_misc_intrs & AR5312_ISR_UART0))
1436 + generic_handle_irq(AR5312_MISC_IRQ_UART0);
1437 + else if (ar231x_misc_intrs & AR5312_ISR_WD)
1438 + generic_handle_irq(AR5312_MISC_IRQ_WATCHDOG);
1439 + else
1440 + spurious_interrupt();
1441 +}
1442 +
1443 +/* Enable the specified AR5312_MISC_IRQ interrupt */
1444 +static void ar5312_misc_irq_unmask(struct irq_data *d)
1445 +{
1446 + unsigned int imr;
1447 +
1448 + imr = ar5312_rst_reg_read(AR5312_IMR);
1449 + imr |= 1 << (d->irq - AR231X_MISC_IRQ_BASE);
1450 + ar5312_rst_reg_write(AR5312_IMR, imr);
1451 +}
1452 +
1453 +/* Disable the specified AR5312_MISC_IRQ interrupt */
1454 +static void ar5312_misc_irq_mask(struct irq_data *d)
1455 +{
1456 + unsigned int imr;
1457 +
1458 + imr = ar5312_rst_reg_read(AR5312_IMR);
1459 + imr &= ~(1 << (d->irq - AR231X_MISC_IRQ_BASE));
1460 + ar5312_rst_reg_write(AR5312_IMR, imr);
1461 + ar5312_rst_reg_read(AR5312_IMR); /* flush write buffer */
1462 +}
1463 +
1464 +static struct irq_chip ar5312_misc_irq_chip = {
1465 + .name = "ar5312-misc",
1466 + .irq_unmask = ar5312_misc_irq_unmask,
1467 + .irq_mask = ar5312_misc_irq_mask,
1468 +};
1469 +
1470 +static void ar5312_irq_dispatch(void)
1471 +{
1472 + int pending = read_c0_status() & read_c0_cause();
1473 +
1474 + if (pending & CAUSEF_IP2)
1475 + do_IRQ(AR5312_IRQ_WLAN0_INTRS);
1476 + else if (pending & CAUSEF_IP3)
1477 + do_IRQ(AR5312_IRQ_ENET0_INTRS);
1478 + else if (pending & CAUSEF_IP4)
1479 + do_IRQ(AR5312_IRQ_ENET1_INTRS);
1480 + else if (pending & CAUSEF_IP5)
1481 + do_IRQ(AR5312_IRQ_WLAN1_INTRS);
1482 + else if (pending & CAUSEF_IP6)
1483 + do_IRQ(AR5312_IRQ_MISC_INTRS);
1484 + else if (pending & CAUSEF_IP7)
1485 + do_IRQ(AR231X_IRQ_CPU_CLOCK);
1486 + else
1487 + spurious_interrupt();
1488 +}
1489 +
1490 +void __init ar5312_arch_init_irq(void)
1491 +{
1492 + int i;
1493 +
1494 + ath25_irq_dispatch = ar5312_irq_dispatch;
1495 + for (i = 0; i < AR5312_MISC_IRQ_COUNT; i++) {
1496 + int irq = AR231X_MISC_IRQ_BASE + i;
1497 +
1498 + irq_set_chip_and_handler(irq, &ar5312_misc_irq_chip,
1499 + handle_level_irq);
1500 + }
1501 + setup_irq(AR5312_MISC_IRQ_AHB_PROC, &ar5312_ahb_err_interrupt);
1502 + irq_set_chained_handler(AR5312_IRQ_MISC_INTRS, ar5312_misc_irq_handler);
1503 +}
1504 +
1505 +static void ar5312_device_reset_set(u32 mask)
1506 +{
1507 + u32 val;
1508 +
1509 + val = ar5312_rst_reg_read(AR5312_RESET);
1510 + ar5312_rst_reg_write(AR5312_RESET, val | mask);
1511 +}
1512 +
1513 +static void ar5312_device_reset_clear(u32 mask)
1514 +{
1515 + u32 val;
1516 +
1517 + val = ar5312_rst_reg_read(AR5312_RESET);
1518 + ar5312_rst_reg_write(AR5312_RESET, val & ~mask);
1519 +}
1520 +
1521 +static struct physmap_flash_data ar5312_flash_data = {
1522 + .width = 2,
1523 +};
1524 +
1525 +static struct resource ar5312_flash_resource = {
1526 + .start = AR5312_FLASH,
1527 + .end = AR5312_FLASH + 0x800000 - 1,
1528 + .flags = IORESOURCE_MEM,
1529 +};
1530 +
1531 +static struct ar231x_eth ar5312_eth0_data = {
1532 + .reset_set = ar5312_device_reset_set,
1533 + .reset_clear = ar5312_device_reset_clear,
1534 + .reset_mac = AR5312_RESET_ENET0,
1535 + .reset_phy = AR5312_RESET_EPHY0,
1536 +};
1537 +
1538 +static struct ar231x_eth ar5312_eth1_data = {
1539 + .reset_set = ar5312_device_reset_set,
1540 + .reset_clear = ar5312_device_reset_clear,
1541 + .reset_mac = AR5312_RESET_ENET1,
1542 + .reset_phy = AR5312_RESET_EPHY1,
1543 +};
1544 +
1545 +static struct platform_device ar5312_physmap_flash = {
1546 + .name = "physmap-flash",
1547 + .id = 0,
1548 + .dev.platform_data = &ar5312_flash_data,
1549 + .resource = &ar5312_flash_resource,
1550 + .num_resources = 1,
1551 +};
1552 +
1553 +#ifdef CONFIG_LEDS_GPIO
1554 +static struct gpio_led ar5312_leds[] = {
1555 + { .name = "wlan", .gpio = 0, .active_low = 1, },
1556 +};
1557 +
1558 +static const struct gpio_led_platform_data ar5312_led_data = {
1559 + .num_leds = ARRAY_SIZE(ar5312_leds),
1560 + .leds = (void *)ar5312_leds,
1561 +};
1562 +
1563 +static struct platform_device ar5312_gpio_leds = {
1564 + .name = "leds-gpio",
1565 + .id = -1,
1566 + .dev.platform_data = (void *)&ar5312_led_data,
1567 +};
1568 +#endif
1569 +
1570 +/*
1571 + * NB: This mapping size is larger than the actual flash size,
1572 + * but this shouldn't be a problem here, because the flash
1573 + * will simply be mapped multiple times.
1574 + */
1575 +static char __init *ar5312_flash_limit(void)
1576 +{
1577 + void __iomem *flashctl_base;
1578 + u32 ctl;
1579 +
1580 + flashctl_base = ioremap_nocache(AR5312_FLASHCTL_BASE,
1581 + AR5312_FLASHCTL_SIZE);
1582 +
1583 + ctl = __raw_readl(flashctl_base + AR5312_FLASHCTL0);
1584 + ctl &= FLASHCTL_MW;
1585 +
1586 + /* fixup flash width */
1587 + switch (ctl) {
1588 + case FLASHCTL_MW16:
1589 + ar5312_flash_data.width = 2;
1590 + break;
1591 + case FLASHCTL_MW8:
1592 + default:
1593 + ar5312_flash_data.width = 1;
1594 + break;
1595 + }
1596 +
1597 + /*
1598 + * Configure flash bank 0.
1599 + * Assume 8M window size. Flash will be aliased if it's smaller
1600 + */
1601 + ctl = FLASHCTL_E |
1602 + FLASHCTL_AC_8M |
1603 + FLASHCTL_RBLE |
1604 + (0x01 << FLASHCTL_IDCY_S) |
1605 + (0x07 << FLASHCTL_WST1_S) |
1606 + (0x07 << FLASHCTL_WST2_S) |
1607 + ctl;
1608 +
1609 + __raw_writel(ctl, flashctl_base + AR5312_FLASHCTL0);
1610 +
1611 + /* Disable other flash banks */
1612 + ctl = __raw_readl(flashctl_base + AR5312_FLASHCTL1);
1613 + ctl &= ~(FLASHCTL_E | FLASHCTL_AC);
1614 + __raw_writel(ctl, flashctl_base + AR5312_FLASHCTL1);
1615 + ctl = __raw_readl(flashctl_base + AR5312_FLASHCTL2);
1616 + ctl &= ~(FLASHCTL_E | FLASHCTL_AC);
1617 + __raw_writel(ctl, flashctl_base + AR5312_FLASHCTL2);
1618 +
1619 + iounmap(flashctl_base);
1620 +
1621 + return (char *)KSEG1ADDR(AR5312_FLASH + 0x800000);
1622 +}
1623 +
1624 +void __init ar5312_init_devices(void)
1625 +{
1626 + struct ath25_boarddata *config;
1627 + u8 *c;
1628 +
1629 + /* Locate board/radio config data */
1630 + ath25_find_config(ar5312_flash_limit());
1631 + config = ath25_board.config;
1632 +
1633 + /* AR2313 has CPU minor rev. 10 */
1634 + if ((current_cpu_data.processor_id & 0xff) == 0x0a)
1635 + ath25_soc = ATH25_SOC_AR2313;
1636 +
1637 + /* AR2312 shares the same Silicon ID as AR5312 */
1638 + else if (config->flags & BD_ISCASPER)
1639 + ath25_soc = ATH25_SOC_AR2312;
1640 +
1641 + /* Everything else is probably AR5312 or compatible */
1642 + else
1643 + ath25_soc = ATH25_SOC_AR5312;
1644 +
1645 + platform_device_register(&ar5312_physmap_flash);
1646 +
1647 +#ifdef CONFIG_LEDS_GPIO
1648 + ar5312_leds[0].gpio = config->sys_led_gpio;
1649 + platform_device_register(&ar5312_gpio_leds);
1650 +#endif
1651 +
1652 + /* Fix up MAC addresses if necessary */
1653 + if (is_broadcast_ether_addr(config->enet0_mac))
1654 + ether_addr_copy(config->enet0_mac, config->enet1_mac);
1655 +
1656 + /* If ENET0 and ENET1 have the same mac address,
1657 + * increment the one from ENET1 */
1658 + if (ether_addr_equal(config->enet0_mac, config->enet1_mac)) {
1659 + c = config->enet1_mac + 5;
1660 + while ((c >= config->enet1_mac) && !(++(*c)))
1661 + c--;
1662 + }
1663 +
1664 + switch (ath25_soc) {
1665 + case ATH25_SOC_AR5312:
1666 + ar5312_eth0_data.macaddr = config->enet0_mac;
1667 + ath25_add_ethernet(0, AR5312_ENET0, "eth0_mii",
1668 + AR5312_ENET0_MII, AR5312_IRQ_ENET0_INTRS,
1669 + &ar5312_eth0_data);
1670 +
1671 + ar5312_eth1_data.macaddr = config->enet1_mac;
1672 + ath25_add_ethernet(1, AR5312_ENET1, "eth1_mii",
1673 + AR5312_ENET1_MII, AR5312_IRQ_ENET1_INTRS,
1674 + &ar5312_eth1_data);
1675 +
1676 + if (!ath25_board.radio)
1677 + return;
1678 +
1679 + if (!(config->flags & BD_WLAN0))
1680 + break;
1681 +
1682 + ath25_add_wmac(0, AR5312_WLAN0, AR5312_IRQ_WLAN0_INTRS);
1683 + break;
1684 + /*
1685 + * AR2312/3 ethernet uses the PHY of ENET0, but the MAC
1686 + * of ENET1. Atheros calls it 'twisted' for a reason :)
1687 + */
1688 + case ATH25_SOC_AR2312:
1689 + case ATH25_SOC_AR2313:
1690 + ar5312_eth1_data.reset_phy = ar5312_eth0_data.reset_phy;
1691 + ar5312_eth1_data.macaddr = config->enet0_mac;
1692 + ath25_add_ethernet(1, AR5312_ENET1, "eth0_mii",
1693 + AR5312_ENET0_MII, AR5312_IRQ_ENET1_INTRS,
1694 + &ar5312_eth1_data);
1695 +
1696 + if (!ath25_board.radio)
1697 + return;
1698 + break;
1699 + default:
1700 + break;
1701 + }
1702 +
1703 + if (config->flags & BD_WLAN1)
1704 + ath25_add_wmac(1, AR5312_WLAN1, AR5312_IRQ_WLAN1_INTRS);
1705 +}
1706 +
1707 +static void ar5312_restart(char *command)
1708 +{
1709 + /* reset the system */
1710 + local_irq_disable();
1711 + while (1)
1712 + ar5312_rst_reg_write(AR5312_RESET, AR5312_RESET_SYSTEM);
1713 +}
1714 +
1715 +/*
1716 + * This table is indexed by bits 5..4 of the CLOCKCTL1 register
1717 + * to determine the predevisor value.
1718 + */
1719 +static unsigned clockctl1_predivide_table[4] __initdata = { 1, 2, 4, 5 };
1720 +
1721 +static unsigned __init ar5312_cpu_frequency(void)
1722 +{
1723 + unsigned int scratch;
1724 + unsigned int predivide_mask, predivide_shift;
1725 + unsigned int multiplier_mask, multiplier_shift;
1726 + unsigned int clock_ctl1, predivide_select, predivisor, multiplier;
1727 + unsigned int doubler_mask;
1728 + u16 devid;
1729 +
1730 + /* Trust the bootrom's idea of cpu frequency. */
1731 + scratch = ar5312_rst_reg_read(AR5312_SCRATCH);
1732 + if (scratch)
1733 + return scratch;
1734 +
1735 + devid = ar5312_rst_reg_read(AR5312_REV);
1736 + devid &= AR5312_REV_MAJ;
1737 + devid >>= AR5312_REV_MAJ_S;
1738 + if (devid == AR5312_REV_MAJ_AR2313) {
1739 + predivide_mask = AR2313_CLOCKCTL1_PREDIVIDE_MASK;
1740 + predivide_shift = AR2313_CLOCKCTL1_PREDIVIDE_SHIFT;
1741 + multiplier_mask = AR2313_CLOCKCTL1_MULTIPLIER_MASK;
1742 + multiplier_shift = AR2313_CLOCKCTL1_MULTIPLIER_SHIFT;
1743 + doubler_mask = AR2313_CLOCKCTL1_DOUBLER_MASK;
1744 + } else { /* AR5312 and AR2312 */
1745 + predivide_mask = AR5312_CLOCKCTL1_PREDIVIDE_MASK;
1746 + predivide_shift = AR5312_CLOCKCTL1_PREDIVIDE_SHIFT;
1747 + multiplier_mask = AR5312_CLOCKCTL1_MULTIPLIER_MASK;
1748 + multiplier_shift = AR5312_CLOCKCTL1_MULTIPLIER_SHIFT;
1749 + doubler_mask = AR5312_CLOCKCTL1_DOUBLER_MASK;
1750 + }
1751 +
1752 + /*
1753 + * Clocking is derived from a fixed 40MHz input clock.
1754 + *
1755 + * cpu_freq = input_clock * MULT (where MULT is PLL multiplier)
1756 + * sys_freq = cpu_freq / 4 (used for APB clock, serial,
1757 + * flash, Timer, Watchdog Timer)
1758 + *
1759 + * cnt_freq = cpu_freq / 2 (use for CPU count/compare)
1760 + *
1761 + * So, for example, with a PLL multiplier of 5, we have
1762 + *
1763 + * cpu_freq = 200MHz
1764 + * sys_freq = 50MHz
1765 + * cnt_freq = 100MHz
1766 + *
1767 + * We compute the CPU frequency, based on PLL settings.
1768 + */
1769 +
1770 + clock_ctl1 = ar5312_rst_reg_read(AR5312_CLOCKCTL1);
1771 + predivide_select = (clock_ctl1 & predivide_mask) >> predivide_shift;
1772 + predivisor = clockctl1_predivide_table[predivide_select];
1773 + multiplier = (clock_ctl1 & multiplier_mask) >> multiplier_shift;
1774 +
1775 + if (clock_ctl1 & doubler_mask)
1776 + multiplier = multiplier << 1;
1777 +
1778 + return (40000000 / predivisor) * multiplier;
1779 +}
1780 +
1781 +static inline unsigned ar5312_sys_frequency(void)
1782 +{
1783 + return ar5312_cpu_frequency() / 4;
1784 +}
1785 +
1786 +void __init ar5312_plat_time_init(void)
1787 +{
1788 + mips_hpt_frequency = ar5312_cpu_frequency() / 2;
1789 +}
1790 +
1791 +void __init ar5312_plat_mem_setup(void)
1792 +{
1793 + void __iomem *sdram_base;
1794 + u32 memsize, memcfg, bank0AC, bank1AC;
1795 + u32 devid;
1796 +
1797 + /* Detect memory size */
1798 + sdram_base = ioremap_nocache(AR5312_SDRAMCTL_BASE,
1799 + AR5312_SDRAMCTL_SIZE);
1800 + memcfg = __raw_readl(sdram_base + AR5312_MEM_CFG1);
1801 + bank0AC = (memcfg & MEM_CFG1_AC0) >> MEM_CFG1_AC0_S;
1802 + bank1AC = (memcfg & MEM_CFG1_AC1) >> MEM_CFG1_AC1_S;
1803 + memsize = (bank0AC ? (1 << (bank0AC+1)) : 0) +
1804 + (bank1AC ? (1 << (bank1AC+1)) : 0);
1805 + memsize <<= 20;
1806 + add_memory_region(0, memsize, BOOT_MEM_RAM);
1807 + iounmap(sdram_base);
1808 +
1809 + ar5312_rst_base = ioremap_nocache(AR5312_RST_BASE, AR5312_RST_SIZE);
1810 +
1811 + devid = ar5312_rst_reg_read(AR5312_REV);
1812 + devid >>= AR5312_REV_WMAC_MIN_S;
1813 + devid &= AR5312_REV_CHIP;
1814 + ath25_board.devid = (u16)devid;
1815 +
1816 + /* Clear any lingering AHB errors */
1817 + ar5312_rst_reg_read(AR5312_PROCADDR);
1818 + ar5312_rst_reg_read(AR5312_DMAADDR);
1819 + ar5312_rst_reg_write(AR5312_WD_CTRL, AR5312_WD_CTRL_IGNORE_EXPIRATION);
1820 +
1821 + _machine_restart = ar5312_restart;
1822 +}
1823 +
1824 +void __init ar5312_arch_init(void)
1825 +{
1826 + ath25_serial_setup(AR5312_UART0, AR5312_MISC_IRQ_UART0,
1827 + ar5312_sys_frequency());
1828 +}
1829 --- /dev/null
1830 +++ b/arch/mips/ath25/ar2315.c
1831 @@ -0,0 +1,428 @@
1832 +/*
1833 + * This file is subject to the terms and conditions of the GNU General Public
1834 + * License. See the file "COPYING" in the main directory of this archive
1835 + * for more details.
1836 + *
1837 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
1838 + * Copyright (C) 2006 FON Technology, SL.
1839 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
1840 + * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
1841 + * Copyright (C) 2012 Alexandros C. Couloumbis <alex@ozo.com>
1842 + */
1843 +
1844 +/*
1845 + * Platform devices for Atheros SoCs
1846 + */
1847 +
1848 +#include <generated/autoconf.h>
1849 +#include <linux/init.h>
1850 +#include <linux/module.h>
1851 +#include <linux/types.h>
1852 +#include <linux/string.h>
1853 +#include <linux/platform_device.h>
1854 +#include <linux/kernel.h>
1855 +#include <linux/reboot.h>
1856 +#include <linux/delay.h>
1857 +#include <linux/leds.h>
1858 +#include <linux/gpio.h>
1859 +#include <asm/bootinfo.h>
1860 +#include <asm/reboot.h>
1861 +#include <asm/time.h>
1862 +#include <linux/irq.h>
1863 +#include <linux/io.h>
1864 +
1865 +#include <ath25_platform.h>
1866 +#include <ar2315_regs.h>
1867 +#include <ar231x.h>
1868 +#include "devices.h"
1869 +#include "ar2315.h"
1870 +
1871 +static void __iomem *ar2315_rst_base;
1872 +
1873 +static inline u32 ar2315_rst_reg_read(u32 reg)
1874 +{
1875 + return __raw_readl(ar2315_rst_base + reg);
1876 +}
1877 +
1878 +static inline void ar2315_rst_reg_write(u32 reg, u32 val)
1879 +{
1880 + __raw_writel(val, ar2315_rst_base + reg);
1881 +}
1882 +
1883 +static inline void ar2315_rst_reg_mask(u32 reg, u32 mask, u32 val)
1884 +{
1885 + u32 ret = ar2315_rst_reg_read(reg);
1886 +
1887 + ret &= ~mask;
1888 + ret |= val;
1889 + ar2315_rst_reg_write(reg, ret);
1890 +}
1891 +
1892 +static irqreturn_t ar2315_ahb_err_handler(int cpl, void *dev_id)
1893 +{
1894 + ar2315_rst_reg_write(AR2315_AHB_ERR0, AHB_ERROR_DET);
1895 + ar2315_rst_reg_read(AR2315_AHB_ERR1);
1896 +
1897 + pr_emerg("AHB fatal error\n");
1898 + machine_restart("AHB error"); /* Catastrophic failure */
1899 +
1900 + return IRQ_HANDLED;
1901 +}
1902 +
1903 +static struct irqaction ar2315_ahb_err_interrupt = {
1904 + .handler = ar2315_ahb_err_handler,
1905 + .name = "ar2315-ahb-error",
1906 +};
1907 +
1908 +static void ar2315_misc_irq_handler(unsigned irq, struct irq_desc *desc)
1909 +{
1910 + unsigned int misc_intr = ar2315_rst_reg_read(AR2315_ISR) &
1911 + ar2315_rst_reg_read(AR2315_IMR);
1912 +
1913 + if (misc_intr & AR2315_ISR_SPI)
1914 + generic_handle_irq(AR2315_MISC_IRQ_SPI);
1915 + else if (misc_intr & AR2315_ISR_TIMER)
1916 + generic_handle_irq(AR2315_MISC_IRQ_TIMER);
1917 + else if (misc_intr & AR2315_ISR_AHB)
1918 + generic_handle_irq(AR2315_MISC_IRQ_AHB);
1919 + else if (misc_intr & AR2315_ISR_GPIO) {
1920 + ar2315_rst_reg_write(AR2315_ISR, AR2315_ISR_GPIO);
1921 + generic_handle_irq(AR2315_MISC_IRQ_GPIO);
1922 + } else if (misc_intr & AR2315_ISR_UART0)
1923 + generic_handle_irq(AR2315_MISC_IRQ_UART0);
1924 + else if (misc_intr & AR2315_ISR_WD) {
1925 + ar2315_rst_reg_write(AR2315_ISR, AR2315_ISR_WD);
1926 + generic_handle_irq(AR2315_MISC_IRQ_WATCHDOG);
1927 + } else
1928 + spurious_interrupt();
1929 +}
1930 +
1931 +static void ar2315_misc_irq_unmask(struct irq_data *d)
1932 +{
1933 + unsigned int imr;
1934 +
1935 + imr = ar2315_rst_reg_read(AR2315_IMR);
1936 + imr |= 1 << (d->irq - AR231X_MISC_IRQ_BASE);
1937 + ar2315_rst_reg_write(AR2315_IMR, imr);
1938 +}
1939 +
1940 +static void ar2315_misc_irq_mask(struct irq_data *d)
1941 +{
1942 + unsigned int imr;
1943 +
1944 + imr = ar2315_rst_reg_read(AR2315_IMR);
1945 + imr &= ~(1 << (d->irq - AR231X_MISC_IRQ_BASE));
1946 + ar2315_rst_reg_write(AR2315_IMR, imr);
1947 +}
1948 +
1949 +static struct irq_chip ar2315_misc_irq_chip = {
1950 + .name = "ar2315-misc",
1951 + .irq_unmask = ar2315_misc_irq_unmask,
1952 + .irq_mask = ar2315_misc_irq_mask,
1953 +};
1954 +
1955 +/*
1956 + * Called when an interrupt is received, this function
1957 + * determines exactly which interrupt it was, and it
1958 + * invokes the appropriate handler.
1959 + *
1960 + * Implicitly, we also define interrupt priority by
1961 + * choosing which to dispatch first.
1962 + */
1963 +static void ar2315_irq_dispatch(void)
1964 +{
1965 + int pending = read_c0_status() & read_c0_cause();
1966 +
1967 + if (pending & CAUSEF_IP3)
1968 + do_IRQ(AR2315_IRQ_WLAN0_INTRS);
1969 + else if (pending & CAUSEF_IP4)
1970 + do_IRQ(AR2315_IRQ_ENET0_INTRS);
1971 + else if (pending & CAUSEF_IP2)
1972 + do_IRQ(AR2315_IRQ_MISC_INTRS);
1973 + else if (pending & CAUSEF_IP7)
1974 + do_IRQ(AR231X_IRQ_CPU_CLOCK);
1975 + else
1976 + spurious_interrupt();
1977 +}
1978 +
1979 +void __init ar2315_arch_init_irq(void)
1980 +{
1981 + int i;
1982 +
1983 + ath25_irq_dispatch = ar2315_irq_dispatch;
1984 + for (i = 0; i < AR2315_MISC_IRQ_COUNT; i++) {
1985 + int irq = AR231X_MISC_IRQ_BASE + i;
1986 +
1987 + irq_set_chip_and_handler(irq, &ar2315_misc_irq_chip,
1988 + handle_level_irq);
1989 + }
1990 + setup_irq(AR2315_MISC_IRQ_AHB, &ar2315_ahb_err_interrupt);
1991 + irq_set_chained_handler(AR2315_IRQ_MISC_INTRS, ar2315_misc_irq_handler);
1992 +}
1993 +
1994 +static void ar2315_device_reset_set(u32 mask)
1995 +{
1996 + u32 val;
1997 +
1998 + val = ar2315_rst_reg_read(AR2315_RESET);
1999 + ar2315_rst_reg_write(AR2315_RESET, val | mask);
2000 +}
2001 +
2002 +static void ar2315_device_reset_clear(u32 mask)
2003 +{
2004 + u32 val;
2005 +
2006 + val = ar2315_rst_reg_read(AR2315_RESET);
2007 + ar2315_rst_reg_write(AR2315_RESET, val & ~mask);
2008 +}
2009 +
2010 +static struct ar231x_eth ar2315_eth_data = {
2011 + .reset_set = ar2315_device_reset_set,
2012 + .reset_clear = ar2315_device_reset_clear,
2013 + .reset_mac = AR2315_RESET_ENET0,
2014 + .reset_phy = AR2315_RESET_EPHY0,
2015 +};
2016 +
2017 +static struct resource ar2315_spiflash_res[] = {
2018 + {
2019 + .name = "spiflash_read",
2020 + .flags = IORESOURCE_MEM,
2021 + .start = AR2315_SPI_READ,
2022 + .end = AR2315_SPI_READ + 0x1000000 - 1,
2023 + },
2024 + {
2025 + .name = "spiflash_mmr",
2026 + .flags = IORESOURCE_MEM,
2027 + .start = AR2315_SPI_MMR,
2028 + .end = AR2315_SPI_MMR + 12 - 1,
2029 + },
2030 +};
2031 +
2032 +static struct platform_device ar2315_spiflash = {
2033 + .id = 0,
2034 + .name = "ar2315-spiflash",
2035 + .resource = ar2315_spiflash_res,
2036 + .num_resources = ARRAY_SIZE(ar2315_spiflash_res)
2037 +};
2038 +
2039 +static struct resource ar2315_wdt_res[] = {
2040 + {
2041 + .flags = IORESOURCE_MEM,
2042 + .start = AR2315_RST_BASE + AR2315_WD,
2043 + .end = AR2315_RST_BASE + AR2315_WD + 8 - 1,
2044 + },
2045 + {
2046 + .flags = IORESOURCE_IRQ,
2047 + .start = AR2315_MISC_IRQ_WATCHDOG,
2048 + .end = AR2315_MISC_IRQ_WATCHDOG,
2049 + }
2050 +};
2051 +
2052 +static struct platform_device ar2315_wdt = {
2053 + .id = 0,
2054 + .name = "ar2315-wdt",
2055 + .resource = ar2315_wdt_res,
2056 + .num_resources = ARRAY_SIZE(ar2315_wdt_res)
2057 +};
2058 +
2059 +/*
2060 + * NB: We use mapping size that is larger than the actual flash size,
2061 + * but this shouldn't be a problem here, because the flash will simply
2062 + * be mapped multiple times.
2063 + */
2064 +static u8 __init *ar2315_flash_limit(void)
2065 +{
2066 + return (u8 *)KSEG1ADDR(ar2315_spiflash_res[0].end + 1);
2067 +}
2068 +
2069 +#ifdef CONFIG_LEDS_GPIO
2070 +static struct gpio_led ar2315_leds[6];
2071 +static struct gpio_led_platform_data ar2315_led_data = {
2072 + .leds = (void *)ar2315_leds,
2073 +};
2074 +
2075 +static struct platform_device ar2315_gpio_leds = {
2076 + .name = "leds-gpio",
2077 + .id = -1,
2078 + .dev = {
2079 + .platform_data = (void *)&ar2315_led_data,
2080 + }
2081 +};
2082 +
2083 +static void __init ar2315_init_gpio_leds(void)
2084 +{
2085 + static char led_names[6][6];
2086 + int i, led = 0;
2087 +
2088 + ar2315_led_data.num_leds = 0;
2089 + for (i = 1; i < 8; i++) {
2090 + if ((i == AR2315_RESET_GPIO) ||
2091 + (i == ath25_board.config->reset_config_gpio))
2092 + continue;
2093 +
2094 + if (i == ath25_board.config->sys_led_gpio)
2095 + strcpy(led_names[led], "wlan");
2096 + else
2097 + sprintf(led_names[led], "gpio%d", i);
2098 +
2099 + ar2315_leds[led].name = led_names[led];
2100 + ar2315_leds[led].gpio = i;
2101 + ar2315_leds[led].active_low = 0;
2102 + led++;
2103 + }
2104 + ar2315_led_data.num_leds = led;
2105 + platform_device_register(&ar2315_gpio_leds);
2106 +}
2107 +#else
2108 +static inline void ar2315_init_gpio_leds(void)
2109 +{
2110 +}
2111 +#endif
2112 +
2113 +void __init ar2315_init_devices(void)
2114 +{
2115 + /* Find board configuration */
2116 + ath25_find_config(ar2315_flash_limit());
2117 + ar2315_eth_data.macaddr = ath25_board.config->enet0_mac;
2118 +
2119 + ar2315_init_gpio_leds();
2120 + platform_device_register(&ar2315_wdt);
2121 + platform_device_register(&ar2315_spiflash);
2122 + ath25_add_ethernet(0, AR2315_ENET0, "eth0_mii", AR2315_ENET0_MII,
2123 + AR2315_IRQ_ENET0_INTRS, &ar2315_eth_data);
2124 + ath25_add_wmac(0, AR2315_WLAN0, AR2315_IRQ_WLAN0_INTRS);
2125 +}
2126 +
2127 +static void ar2315_restart(char *command)
2128 +{
2129 + void (*mips_reset_vec)(void) = (void *)0xbfc00000;
2130 +
2131 + local_irq_disable();
2132 +
2133 + /* try reset the system via reset control */
2134 + ar2315_rst_reg_write(AR2315_COLD_RESET, AR2317_RESET_SYSTEM);
2135 +
2136 + /* Cold reset does not work on the AR2315/6, use the GPIO reset bits
2137 + * a workaround. Give it some time to attempt a gpio based hardware
2138 + * reset (atheros reference design workaround) */
2139 + gpio_request_one(AR2315_RESET_GPIO, GPIOF_OUT_INIT_LOW, "Reset");
2140 + mdelay(100);
2141 +
2142 + /* Some boards (e.g. Senao EOC-2610) don't implement the reset logic
2143 + * workaround. Attempt to jump to the mips reset location -
2144 + * the boot loader itself might be able to recover the system */
2145 + mips_reset_vec();
2146 +}
2147 +
2148 +/*
2149 + * This table is indexed by bits 5..4 of the CLOCKCTL1 register
2150 + * to determine the predevisor value.
2151 + */
2152 +static int clockctl1_predivide_table[4] __initdata = { 1, 2, 4, 5 };
2153 +static int pllc_divide_table[5] __initdata = { 2, 3, 4, 6, 3 };
2154 +
2155 +static unsigned __init ar2315_sys_clk(u32 clock_ctl)
2156 +{
2157 + unsigned int pllc_ctrl, cpu_div;
2158 + unsigned int pllc_out, refdiv, fdiv, divby2;
2159 + unsigned int clk_div;
2160 +
2161 + pllc_ctrl = ar2315_rst_reg_read(AR2315_PLLC_CTL);
2162 + refdiv = (pllc_ctrl & PLLC_REF_DIV_M) >> PLLC_REF_DIV_S;
2163 + refdiv = clockctl1_predivide_table[refdiv];
2164 + fdiv = (pllc_ctrl & PLLC_FDBACK_DIV_M) >> PLLC_FDBACK_DIV_S;
2165 + divby2 = (pllc_ctrl & PLLC_ADD_FDBACK_DIV_M) >> PLLC_ADD_FDBACK_DIV_S;
2166 + divby2 += 1;
2167 + pllc_out = (40000000/refdiv)*(2*divby2)*fdiv;
2168 +
2169 + /* clkm input selected */
2170 + switch (clock_ctl & CPUCLK_CLK_SEL_M) {
2171 + case 0:
2172 + case 1:
2173 + clk_div = pllc_divide_table[(pllc_ctrl & PLLC_CLKM_DIV_M) >>
2174 + PLLC_CLKM_DIV_S];
2175 + break;
2176 + case 2:
2177 + clk_div = pllc_divide_table[(pllc_ctrl & PLLC_CLKC_DIV_M) >>
2178 + PLLC_CLKC_DIV_S];
2179 + break;
2180 + default:
2181 + pllc_out = 40000000;
2182 + clk_div = 1;
2183 + break;
2184 + }
2185 +
2186 + cpu_div = (clock_ctl & CPUCLK_CLK_DIV_M) >> CPUCLK_CLK_DIV_S;
2187 + cpu_div = cpu_div * 2 ?: 1;
2188 +
2189 + return pllc_out / (clk_div * cpu_div);
2190 +}
2191 +
2192 +static inline unsigned ar2315_cpu_frequency(void)
2193 +{
2194 + return ar2315_sys_clk(ar2315_rst_reg_read(AR2315_CPUCLK));
2195 +}
2196 +
2197 +static inline unsigned ar2315_apb_frequency(void)
2198 +{
2199 + return ar2315_sys_clk(ar2315_rst_reg_read(AR2315_AMBACLK));
2200 +}
2201 +
2202 +void __init ar2315_plat_time_init(void)
2203 +{
2204 + mips_hpt_frequency = ar2315_cpu_frequency() / 2;
2205 +}
2206 +
2207 +void __init ar2315_plat_mem_setup(void)
2208 +{
2209 + void __iomem *sdram_base;
2210 + u32 memsize, memcfg;
2211 + u32 devid;
2212 + u32 config;
2213 +
2214 + sdram_base = ioremap_nocache(AR2315_SDRAMCTL_BASE,
2215 + AR2315_SDRAMCTL_SIZE);
2216 + memcfg = __raw_readl(sdram_base + AR2315_MEM_CFG);
2217 + memsize = 1 + ((memcfg & SDRAM_DATA_WIDTH_M) >> SDRAM_DATA_WIDTH_S);
2218 + memsize <<= 1 + ((memcfg & SDRAM_COL_WIDTH_M) >> SDRAM_COL_WIDTH_S);
2219 + memsize <<= 1 + ((memcfg & SDRAM_ROW_WIDTH_M) >> SDRAM_ROW_WIDTH_S);
2220 + memsize <<= 3;
2221 + add_memory_region(0, memsize, BOOT_MEM_RAM);
2222 + iounmap(sdram_base);
2223 +
2224 + ar2315_rst_base = ioremap_nocache(AR2315_RST_BASE, AR2315_RST_SIZE);
2225 +
2226 + /* Detect the hardware based on the device ID */
2227 + devid = ar2315_rst_reg_read(AR2315_SREV) & AR2315_REV_CHIP;
2228 + switch (devid) {
2229 + case 0x91: /* Need to check */
2230 + ath25_soc = ATH25_SOC_AR2318;
2231 + break;
2232 + case 0x90:
2233 + ath25_soc = ATH25_SOC_AR2317;
2234 + break;
2235 + case 0x87:
2236 + ath25_soc = ATH25_SOC_AR2316;
2237 + break;
2238 + case 0x86:
2239 + default:
2240 + ath25_soc = ATH25_SOC_AR2315;
2241 + break;
2242 + }
2243 + ath25_board.devid = devid;
2244 +
2245 + /* Clear any lingering AHB errors */
2246 + config = read_c0_config();
2247 + write_c0_config(config & ~0x3);
2248 + ar2315_rst_reg_write(AR2315_AHB_ERR0, AHB_ERROR_DET);
2249 + ar2315_rst_reg_read(AR2315_AHB_ERR1);
2250 + ar2315_rst_reg_write(AR2315_WDC, AR2315_WDC_IGNORE_EXPIRATION);
2251 +
2252 + _machine_restart = ar2315_restart;
2253 +}
2254 +
2255 +void __init ar2315_arch_init(void)
2256 +{
2257 + ath25_serial_setup(AR2315_UART0, AR2315_MISC_IRQ_UART0,
2258 + ar2315_apb_frequency());
2259 +}
2260 --- /dev/null
2261 +++ b/arch/mips/ath25/ar2315.h
2262 @@ -0,0 +1,36 @@
2263 +#ifndef __AR2315_H
2264 +#define __AR2315_H
2265 +
2266 +#ifdef CONFIG_SOC_AR2315
2267 +
2268 +void ar2315_arch_init_irq(void);
2269 +void ar2315_init_devices(void);
2270 +void ar2315_plat_time_init(void);
2271 +void ar2315_plat_mem_setup(void);
2272 +void ar2315_arch_init(void);
2273 +
2274 +#else
2275 +
2276 +static inline void ar2315_arch_init_irq(void)
2277 +{
2278 +}
2279 +
2280 +static inline void ar2315_init_devices(void)
2281 +{
2282 +}
2283 +
2284 +static inline void ar2315_plat_time_init(void)
2285 +{
2286 +}
2287 +
2288 +static inline void ar2315_plat_mem_setup(void)
2289 +{
2290 +}
2291 +
2292 +static inline void ar2315_arch_init(void)
2293 +{
2294 +}
2295 +
2296 +#endif
2297 +
2298 +#endif
2299 --- /dev/null
2300 +++ b/arch/mips/ath25/ar5312.h
2301 @@ -0,0 +1,36 @@
2302 +#ifndef __AR5312_H
2303 +#define __AR5312_H
2304 +
2305 +#ifdef CONFIG_SOC_AR5312
2306 +
2307 +void ar5312_arch_init_irq(void);
2308 +void ar5312_init_devices(void);
2309 +void ar5312_plat_time_init(void);
2310 +void ar5312_plat_mem_setup(void);
2311 +void ar5312_arch_init(void);
2312 +
2313 +#else
2314 +
2315 +static inline void ar5312_arch_init_irq(void)
2316 +{
2317 +}
2318 +
2319 +static inline void ar5312_init_devices(void)
2320 +{
2321 +}
2322 +
2323 +static inline void ar5312_plat_time_init(void)
2324 +{
2325 +}
2326 +
2327 +static inline void ar5312_plat_mem_setup(void)
2328 +{
2329 +}
2330 +
2331 +static inline void ar5312_arch_init(void)
2332 +{
2333 +}
2334 +
2335 +#endif
2336 +
2337 +#endif
2338 --- /dev/null
2339 +++ b/arch/mips/include/asm/mach-ath25/ar231x.h
2340 @@ -0,0 +1,13 @@
2341 +#ifndef __ASM_MACH_ATH25_AR231X_H
2342 +#define __ASM_MACH_ATH25_AR231X_H
2343 +
2344 +#include <linux/types.h>
2345 +#include <linux/io.h>
2346 +
2347 +#define AR231X_MISC_IRQ_BASE 0x20
2348 +#define AR231X_GPIO_IRQ_BASE 0x30
2349 +
2350 +/* Software's idea of interrupts handled by "CPU Interrupt Controller" */
2351 +#define AR231X_IRQ_CPU_CLOCK (MIPS_CPU_IRQ_BASE+7) /* C0_CAUSE: 0x8000 */
2352 +
2353 +#endif /* __ASM_MACH_ATH25_AR231X_H */
2354 --- /dev/null
2355 +++ b/arch/mips/ath25/devices.h
2356 @@ -0,0 +1,39 @@
2357 +#ifndef __ATH25_DEVICES_H
2358 +#define __ATH25_DEVICES_H
2359 +
2360 +enum ath25_soc_type {
2361 + /* handled by ar5312.c */
2362 + ATH25_SOC_AR2312,
2363 + ATH25_SOC_AR2313,
2364 + ATH25_SOC_AR5312,
2365 +
2366 + /* handled by ar2315.c */
2367 + ATH25_SOC_AR2315,
2368 + ATH25_SOC_AR2316,
2369 + ATH25_SOC_AR2317,
2370 + ATH25_SOC_AR2318,
2371 +
2372 + ATH25_SOC_UNKNOWN
2373 +};
2374 +
2375 +extern enum ath25_soc_type ath25_soc;
2376 +extern struct ar231x_board_config ath25_board;
2377 +extern void (*ath25_irq_dispatch)(void);
2378 +
2379 +int ath25_find_config(u8 *flash_limit);
2380 +int ath25_add_ethernet(int nr, u32 base, const char *mii_name, u32 mii_base,
2381 + int irq, void *pdata);
2382 +void ath25_serial_setup(u32 mapbase, int irq, unsigned int uartclk);
2383 +int ath25_add_wmac(int nr, u32 base, int irq);
2384 +
2385 +static inline bool is_ar2315(void)
2386 +{
2387 + return (current_cpu_data.cputype == CPU_4KEC);
2388 +}
2389 +
2390 +static inline bool is_ar5312(void)
2391 +{
2392 + return !is_ar2315();
2393 +}
2394 +
2395 +#endif
2396 --- /dev/null
2397 +++ b/arch/mips/ath25/devices.c
2398 @@ -0,0 +1,192 @@
2399 +#include <linux/kernel.h>
2400 +#include <linux/init.h>
2401 +#include <linux/serial.h>
2402 +#include <linux/serial_core.h>
2403 +#include <linux/serial_8250.h>
2404 +#include <linux/platform_device.h>
2405 +#include <asm/bootinfo.h>
2406 +
2407 +#include <ath25_platform.h>
2408 +#include <ar231x.h>
2409 +#include "devices.h"
2410 +#include "ar5312.h"
2411 +#include "ar2315.h"
2412 +
2413 +struct ar231x_board_config ath25_board;
2414 +enum ath25_soc_type ath25_soc = ATH25_SOC_UNKNOWN;
2415 +
2416 +static struct resource ath25_eth0_res[] = {
2417 + {
2418 + .name = "eth0_membase",
2419 + .flags = IORESOURCE_MEM,
2420 + },
2421 + {
2422 + .name = "eth0_mii",
2423 + .flags = IORESOURCE_MEM,
2424 + },
2425 + {
2426 + .name = "eth0_irq",
2427 + .flags = IORESOURCE_IRQ,
2428 + }
2429 +};
2430 +
2431 +static struct resource ath25_eth1_res[] = {
2432 + {
2433 + .name = "eth1_membase",
2434 + .flags = IORESOURCE_MEM,
2435 + },
2436 + {
2437 + .name = "eth1_mii",
2438 + .flags = IORESOURCE_MEM,
2439 + },
2440 + {
2441 + .name = "eth1_irq",
2442 + .flags = IORESOURCE_IRQ,
2443 + }
2444 +};
2445 +
2446 +static struct platform_device ath25_eth[] = {
2447 + {
2448 + .id = 0,
2449 + .name = "ar231x-eth",
2450 + .resource = ath25_eth0_res,
2451 + .num_resources = ARRAY_SIZE(ath25_eth0_res)
2452 + },
2453 + {
2454 + .id = 1,
2455 + .name = "ar231x-eth",
2456 + .resource = ath25_eth1_res,
2457 + .num_resources = ARRAY_SIZE(ath25_eth1_res)
2458 + }
2459 +};
2460 +
2461 +static struct resource ath25_wmac0_res[] = {
2462 + {
2463 + .name = "wmac0_membase",
2464 + .flags = IORESOURCE_MEM,
2465 + },
2466 + {
2467 + .name = "wmac0_irq",
2468 + .flags = IORESOURCE_IRQ,
2469 + }
2470 +};
2471 +
2472 +static struct resource ath25_wmac1_res[] = {
2473 + {
2474 + .name = "wmac1_membase",
2475 + .flags = IORESOURCE_MEM,
2476 + },
2477 + {
2478 + .name = "wmac1_irq",
2479 + .flags = IORESOURCE_IRQ,
2480 + }
2481 +};
2482 +
2483 +static struct platform_device ath25_wmac[] = {
2484 + {
2485 + .id = 0,
2486 + .name = "ar231x-wmac",
2487 + .resource = ath25_wmac0_res,
2488 + .num_resources = ARRAY_SIZE(ath25_wmac0_res),
2489 + .dev.platform_data = &ath25_board,
2490 + },
2491 + {
2492 + .id = 1,
2493 + .name = "ar231x-wmac",
2494 + .resource = ath25_wmac1_res,
2495 + .num_resources = ARRAY_SIZE(ath25_wmac1_res),
2496 + .dev.platform_data = &ath25_board,
2497 + },
2498 +};
2499 +
2500 +static const char * const soc_type_strings[] = {
2501 + [ATH25_SOC_AR5312] = "Atheros AR5312",
2502 + [ATH25_SOC_AR2312] = "Atheros AR2312",
2503 + [ATH25_SOC_AR2313] = "Atheros AR2313",
2504 + [ATH25_SOC_AR2315] = "Atheros AR2315",
2505 + [ATH25_SOC_AR2316] = "Atheros AR2316",
2506 + [ATH25_SOC_AR2317] = "Atheros AR2317",
2507 + [ATH25_SOC_AR2318] = "Atheros AR2318",
2508 + [ATH25_SOC_UNKNOWN] = "Atheros (unknown)",
2509 +};
2510 +
2511 +const char *get_system_type(void)
2512 +{
2513 + if ((ath25_soc >= ARRAY_SIZE(soc_type_strings)) ||
2514 + !soc_type_strings[ath25_soc])
2515 + return soc_type_strings[ATH25_SOC_UNKNOWN];
2516 + return soc_type_strings[ath25_soc];
2517 +}
2518 +
2519 +int __init ath25_add_ethernet(int nr, u32 base, const char *mii_name,
2520 + u32 mii_base, int irq, void *pdata)
2521 +{
2522 + struct resource *res;
2523 +
2524 + ath25_eth[nr].dev.platform_data = pdata;
2525 + res = &ath25_eth[nr].resource[0];
2526 + res->start = base;
2527 + res->end = base + 0x2000 - 1;
2528 + res++;
2529 + res->name = mii_name;
2530 + res->start = mii_base;
2531 + res->end = mii_base + 8 - 1;
2532 + res++;
2533 + res->start = irq;
2534 + res->end = irq;
2535 + return platform_device_register(&ath25_eth[nr]);
2536 +}
2537 +
2538 +void __init ath25_serial_setup(u32 mapbase, int irq, unsigned int uartclk)
2539 +{
2540 + struct uart_port s;
2541 +
2542 + memset(&s, 0, sizeof(s));
2543 +
2544 + s.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP;
2545 + s.iotype = UPIO_MEM32;
2546 + s.irq = irq;
2547 + s.regshift = 2;
2548 + s.mapbase = mapbase;
2549 + s.uartclk = uartclk;
2550 +
2551 + early_serial_setup(&s);
2552 +}
2553 +
2554 +int __init ath25_add_wmac(int nr, u32 base, int irq)
2555 +{
2556 + struct resource *res;
2557 +
2558 + ath25_wmac[nr].dev.platform_data = &ath25_board;
2559 + res = &ath25_wmac[nr].resource[0];
2560 + res->start = base;
2561 + res->end = base + 0x10000 - 1;
2562 + res++;
2563 + res->start = irq;
2564 + res->end = irq;
2565 + return platform_device_register(&ath25_wmac[nr]);
2566 +}
2567 +
2568 +static int __init ath25_register_devices(void)
2569 +{
2570 + if (is_ar5312())
2571 + ar5312_init_devices();
2572 + else
2573 + ar2315_init_devices();
2574 +
2575 + return 0;
2576 +}
2577 +
2578 +device_initcall(ath25_register_devices);
2579 +
2580 +static int __init ath25_arch_init(void)
2581 +{
2582 + if (is_ar5312())
2583 + ar5312_arch_init();
2584 + else
2585 + ar2315_arch_init();
2586 +
2587 + return 0;
2588 +}
2589 +
2590 +arch_initcall(ath25_arch_init);
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