target/linux/atheros/patches-3.18/103-ar2315_gpio.patch

   1 --- a/arch/mips/ath25/Kconfig
   2 +++ b/arch/mips/ath25/Kconfig
   3 @@ -7,4 +7,5 @@ config SOC_AR5312
   4  config SOC_AR2315
   5         bool "Atheros 2315+ support"
   6         depends on ATH25
   7 +       select GPIO_AR2315
   8         default y
   9 --- a/arch/mips/ath25/ar2315.c
  10 +++ b/arch/mips/ath25/ar2315.c
  11 @@ -204,6 +204,34 @@ static struct platform_device ar2315_wdt
  12         .num_resources = ARRAY_SIZE(ar2315_wdt_res)
  13  };
  14
  15 +static struct resource ar2315_gpio_res[] = {
  16 +       {
  17 +               .name = "ar2315-gpio",
  18 +               .flags = IORESOURCE_MEM,
  19 +               .start = AR2315_GPIO,
  20 +               .end = AR2315_GPIO + 0x10 - 1,
  21 +       },
  22 +       {
  23 +               .name = "ar2315-gpio",
  24 +               .flags = IORESOURCE_IRQ,
  25 +               .start = AR2315_MISC_IRQ_GPIO,
  26 +               .end = AR2315_MISC_IRQ_GPIO,
  27 +       },
  28 +       {
  29 +               .name = "ar2315-gpio-irq-base",
  30 +               .flags = IORESOURCE_IRQ,
  31 +               .start = AR231X_GPIO_IRQ_BASE,
  32 +               .end = AR231X_GPIO_IRQ_BASE,
  33 +       }
  34 +};
  35 +
  36 +static struct platform_device ar2315_gpio = {
  37 +       .id = -1,
  38 +       .name = "ar2315-gpio",
  39 +       .resource = ar2315_gpio_res,
  40 +       .num_resources = ARRAY_SIZE(ar2315_gpio_res)
  41 +};
  42 +
  43  /*
  44   * NB: We use mapping size that is larger than the actual flash size,
  45   * but this shouldn't be a problem here, because the flash will simply
  46 @@ -264,6 +292,7 @@ void __init ar2315_init_devices(void)
  47         ath25_find_config(ar2315_flash_limit());
  48         ar2315_eth_data.macaddr = ath25_board.config->enet0_mac;
  49
  50 +       platform_device_register(&ar2315_gpio);
  51         ar2315_init_gpio_leds();
  52         platform_device_register(&ar2315_wdt);
  53         platform_device_register(&ar2315_spiflash);
  54 --- a/drivers/gpio/Kconfig
  55 +++ b/drivers/gpio/Kconfig
  56 @@ -112,6 +112,13 @@ config GPIO_MAX730X
  57
  58  comment "Memory mapped GPIO drivers:"
  59
  60 +config GPIO_AR2315
  61 +       bool "AR2315 SoC GPIO support"
  62 +       default y if SOC_AR2315
  63 +       depends on SOC_AR2315
  64 +       help
  65 +         Say yes here to enable GPIO support for Atheros AR2315+ SoCs.
  66 +
  67  config GPIO_AR5312
  68         bool "AR5312 SoC GPIO support"
  69         default y if SOC_AR5312
  70 --- a/drivers/gpio/Makefile
  71 +++ b/drivers/gpio/Makefile
  72 @@ -17,6 +17,7 @@ obj-$(CONFIG_GPIO_ADNP)               += gpio-adnp.o
  73  obj-$(CONFIG_GPIO_ADP5520)     += gpio-adp5520.o
  74  obj-$(CONFIG_GPIO_ADP5588)     += gpio-adp5588.o
  75  obj-$(CONFIG_GPIO_AMD8111)     += gpio-amd8111.o
  76 +obj-$(CONFIG_GPIO_AR2315)      += gpio-ar2315.o
  77  obj-$(CONFIG_GPIO_AR5312)      += gpio-ar5312.o
  78  obj-$(CONFIG_GPIO_ARIZONA)     += gpio-arizona.o
  79  obj-$(CONFIG_GPIO_BCM_KONA)    += gpio-bcm-kona.o
  80 --- /dev/null
  81 +++ b/drivers/gpio/gpio-ar2315.c
  82 @@ -0,0 +1,233 @@
  83 +/*
  84 + * This file is subject to the terms and conditions of the GNU General Public
  85 + * License.  See the file "COPYING" in the main directory of this archive
  86 + * for more details.
  87 + *
  88 + * Copyright (C) 2003 Atheros Communications, Inc.,  All Rights Reserved.
  89 + * Copyright (C) 2006 FON Technology, SL.
  90 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
  91 + * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
  92 + * Copyright (C) 2012 Alexandros C. Couloumbis <alex@ozo.com>
  93 + */
  94 +
  95 +#include <linux/kernel.h>
  96 +#include <linux/init.h>
  97 +#include <linux/platform_device.h>
  98 +#include <linux/gpio.h>
  99 +#include <linux/irq.h>
 100 +
 101 +#define DRIVER_NAME    "ar2315-gpio"
 102 +
 103 +#define AR2315_GPIO_DI                 0x0000
 104 +#define AR2315_GPIO_DO                 0x0008
 105 +#define AR2315_GPIO_DIR                        0x0010
 106 +#define AR2315_GPIO_INT                        0x0018
 107 +
 108 +#define AR2315_GPIO_DIR_M(x)           (1 << (x))      /* mask for i/o */
 109 +#define AR2315_GPIO_DIR_O(x)           (1 << (x))      /* output */
 110 +#define AR2315_GPIO_DIR_I(x)           (0)             /* input */
 111 +
 112 +#define AR2315_GPIO_INT_NUM_M          0x3F            /* mask for GPIO num */
 113 +#define AR2315_GPIO_INT_TRIG(x)                ((x) << 6)      /* interrupt trigger */
 114 +#define AR2315_GPIO_INT_TRIG_M         (0x3 << 6)      /* mask for int trig */
 115 +
 116 +#define AR2315_GPIO_INT_TRIG_OFF       0       /* Triggerring off */
 117 +#define AR2315_GPIO_INT_TRIG_LOW       1       /* Low Level Triggered */
 118 +#define AR2315_GPIO_INT_TRIG_HIGH      2       /* High Level Triggered */
 119 +#define AR2315_GPIO_INT_TRIG_EDGE      3       /* Edge Triggered */
 120 +
 121 +#define AR2315_GPIO_NUM                22
 122 +
 123 +static u32 ar2315_gpio_intmask;
 124 +static u32 ar2315_gpio_intval;
 125 +static unsigned ar2315_gpio_irq_base;
 126 +static void __iomem *ar2315_mem;
 127 +
 128 +static inline u32 ar2315_gpio_reg_read(unsigned reg)
 129 +{
 130 +       return __raw_readl(ar2315_mem + reg);
 131 +}
 132 +
 133 +static inline void ar2315_gpio_reg_write(unsigned reg, u32 val)
 134 +{
 135 +       __raw_writel(val, ar2315_mem + reg);
 136 +}
 137 +
 138 +static inline void ar2315_gpio_reg_mask(unsigned reg, u32 mask, u32 val)
 139 +{
 140 +       ar2315_gpio_reg_write(reg, (ar2315_gpio_reg_read(reg) & ~mask) | val);
 141 +}
 142 +
 143 +static void ar2315_gpio_irq_handler(unsigned irq, struct irq_desc *desc)
 144 +{
 145 +       u32 pend;
 146 +       int bit = -1;
 147 +
 148 +       /* only do one gpio interrupt at a time */
 149 +       pend = ar2315_gpio_reg_read(AR2315_GPIO_DI);
 150 +       pend ^= ar2315_gpio_intval;
 151 +       pend &= ar2315_gpio_intmask;
 152 +
 153 +       if (pend) {
 154 +               bit = fls(pend) - 1;
 155 +               pend &= ~(1 << bit);
 156 +               ar2315_gpio_intval ^= (1 << bit);
 157 +       }
 158 +
 159 +       /* Enable interrupt with edge detection */
 160 +       if ((ar2315_gpio_reg_read(AR2315_GPIO_DIR) & AR2315_GPIO_DIR_M(bit)) !=
 161 +           AR2315_GPIO_DIR_I(bit))
 162 +               return;
 163 +
 164 +       if (bit >= 0)
 165 +               generic_handle_irq(ar2315_gpio_irq_base + bit);
 166 +}
 167 +
 168 +static void ar2315_gpio_int_setup(unsigned gpio, int trig)
 169 +{
 170 +       u32 reg = ar2315_gpio_reg_read(AR2315_GPIO_INT);
 171 +
 172 +       reg &= ~(AR2315_GPIO_INT_NUM_M | AR2315_GPIO_INT_TRIG_M);
 173 +       reg |= gpio | AR2315_GPIO_INT_TRIG(trig);
 174 +       ar2315_gpio_reg_write(AR2315_GPIO_INT, reg);
 175 +}
 176 +
 177 +static void ar2315_gpio_irq_unmask(struct irq_data *d)
 178 +{
 179 +       unsigned gpio = d->irq - ar2315_gpio_irq_base;
 180 +       u32 dir = ar2315_gpio_reg_read(AR2315_GPIO_DIR);
 181 +
 182 +       /* Enable interrupt with edge detection */
 183 +       if ((dir & AR2315_GPIO_DIR_M(gpio)) != AR2315_GPIO_DIR_I(gpio))
 184 +               return;
 185 +
 186 +       ar2315_gpio_intmask |= (1 << gpio);
 187 +       ar2315_gpio_int_setup(gpio, AR2315_GPIO_INT_TRIG_EDGE);
 188 +}
 189 +
 190 +static void ar2315_gpio_irq_mask(struct irq_data *d)
 191 +{
 192 +       unsigned gpio = d->irq - ar2315_gpio_irq_base;
 193 +
 194 +       /* Disable interrupt */
 195 +       ar2315_gpio_intmask &= ~(1 << gpio);
 196 +       ar2315_gpio_int_setup(gpio, AR2315_GPIO_INT_TRIG_OFF);
 197 +}
 198 +
 199 +static struct irq_chip ar2315_gpio_irq_chip = {
 200 +       .name           = DRIVER_NAME,
 201 +       .irq_unmask     = ar2315_gpio_irq_unmask,
 202 +       .irq_mask       = ar2315_gpio_irq_mask,
 203 +};
 204 +
 205 +static void ar2315_gpio_irq_init(unsigned irq)
 206 +{
 207 +       unsigned i;
 208 +
 209 +       ar2315_gpio_intval = ar2315_gpio_reg_read(AR2315_GPIO_DI);
 210 +       for (i = 0; i < AR2315_GPIO_NUM; i++) {
 211 +               unsigned _irq = ar2315_gpio_irq_base + i;
 212 +
 213 +               irq_set_chip_and_handler(_irq, &ar2315_gpio_irq_chip,
 214 +                                        handle_level_irq);
 215 +       }
 216 +       irq_set_chained_handler(irq, ar2315_gpio_irq_handler);
 217 +}
 218 +
 219 +static int ar2315_gpio_get_val(struct gpio_chip *chip, unsigned gpio)
 220 +{
 221 +       return (ar2315_gpio_reg_read(AR2315_GPIO_DI) >> gpio) & 1;
 222 +}
 223 +
 224 +static void ar2315_gpio_set_val(struct gpio_chip *chip, unsigned gpio, int val)
 225 +{
 226 +       u32 reg = ar2315_gpio_reg_read(AR2315_GPIO_DO);
 227 +
 228 +       reg = val ? reg | (1 << gpio) : reg & ~(1 << gpio);
 229 +       ar2315_gpio_reg_write(AR2315_GPIO_DO, reg);
 230 +}
 231 +
 232 +static int ar2315_gpio_dir_in(struct gpio_chip *chip, unsigned gpio)
 233 +{
 234 +       ar2315_gpio_reg_mask(AR2315_GPIO_DIR, 1 << gpio, 0);
 235 +       return 0;
 236 +}
 237 +
 238 +static int ar2315_gpio_dir_out(struct gpio_chip *chip, unsigned gpio, int val)
 239 +{
 240 +       ar2315_gpio_reg_mask(AR2315_GPIO_DIR, 0, 1 << gpio);
 241 +       ar2315_gpio_set_val(chip, gpio, val);
 242 +       return 0;
 243 +}
 244 +
 245 +static int ar2315_gpio_to_irq(struct gpio_chip *chip, unsigned gpio)
 246 +{
 247 +       return ar2315_gpio_irq_base + gpio;
 248 +}
 249 +
 250 +static struct gpio_chip ar2315_gpio_chip = {
 251 +       .label                  = DRIVER_NAME,
 252 +       .direction_input        = ar2315_gpio_dir_in,
 253 +       .direction_output       = ar2315_gpio_dir_out,
 254 +       .set                    = ar2315_gpio_set_val,
 255 +       .get                    = ar2315_gpio_get_val,
 256 +       .to_irq                 = ar2315_gpio_to_irq,
 257 +       .base                   = 0,
 258 +       .ngpio                  = AR2315_GPIO_NUM,
 259 +};
 260 +
 261 +static int ar2315_gpio_probe(struct platform_device *pdev)
 262 +{
 263 +       struct device *dev = &pdev->dev;
 264 +       struct resource *res;
 265 +       unsigned irq;
 266 +       int ret;
 267 +
 268 +       if (ar2315_mem)
 269 +               return -EBUSY;
 270 +
 271 +       res = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
 272 +                                          "ar2315-gpio-irq-base");
 273 +       if (!res) {
 274 +               dev_err(dev, "not found GPIO IRQ base\n");
 275 +               return -ENXIO;
 276 +       }
 277 +       ar2315_gpio_irq_base = res->start;
 278 +
 279 +       res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, DRIVER_NAME);
 280 +       if (!res) {
 281 +               dev_err(dev, "not found IRQ number\n");
 282 +               return -ENXIO;
 283 +       }
 284 +       irq = res->start;
 285 +
 286 +       res = platform_get_resource_byname(pdev, IORESOURCE_MEM, DRIVER_NAME);
 287 +       ar2315_mem = devm_ioremap_resource(dev, res);
 288 +       if (IS_ERR(ar2315_mem))
 289 +               return PTR_ERR(ar2315_mem);
 290 +
 291 +       ar2315_gpio_chip.dev = dev;
 292 +       ret = gpiochip_add(&ar2315_gpio_chip);
 293 +       if (ret) {
 294 +               dev_err(dev, "failed to add gpiochip\n");
 295 +               return ret;
 296 +       }
 297 +
 298 +       ar2315_gpio_irq_init(irq);
 299 +
 300 +       return 0;
 301 +}
 302 +
 303 +static struct platform_driver ar2315_gpio_driver = {
 304 +       .probe = ar2315_gpio_probe,
 305 +       .driver = {
 306 +               .name = DRIVER_NAME,
 307 +               .owner = THIS_MODULE,
 308 +       }
 309 +};
 310 +
 311 +static int __init ar2315_gpio_init(void)
 312 +{
 313 +       return platform_driver_register(&ar2315_gpio_driver);
 314 +}
 315 +subsys_initcall(ar2315_gpio_init);