target/linux/atheros/patches-3.18/105-ar2315_pci.patch

   1 --- a/arch/mips/pci/Makefile
   2 +++ b/arch/mips/pci/Makefile
   3 @@ -19,6 +19,7 @@ obj-$(CONFIG_BCM47XX)         += pci-bcm47xx.o
   4  obj-$(CONFIG_BCM63XX)          += pci-bcm63xx.o fixup-bcm63xx.o \
   5                                         ops-bcm63xx.o
   6  obj-$(CONFIG_MIPS_ALCHEMY)     += pci-alchemy.o
   7 +obj-$(CONFIG_PCI_AR2315)       += pci-ar2315.o
   8  obj-$(CONFIG_SOC_AR71XX)       += pci-ar71xx.o
   9  obj-$(CONFIG_PCI_AR724X)       += pci-ar724x.o
  10  obj-$(CONFIG_MIPS_PCI_VIRTIO)  += pci-virtio-guest.o
  11 --- /dev/null
  12 +++ b/arch/mips/pci/pci-ar2315.c
  13 @@ -0,0 +1,482 @@
  14 +/*
  15 + * This program is free software; you can redistribute it and/or
  16 + * modify it under the terms of the GNU General Public License
  17 + * as published by the Free Software Foundation; either version 2
  18 + * of the License, or (at your option) any later version.
  19 + *
  20 + * This program is distributed in the hope that it will be useful,
  21 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  23 + * GNU General Public License for more details.
  24 + *
  25 + * You should have received a copy of the GNU General Public License
  26 + * along with this program; if not, see <http://www.gnu.org/licenses/>.
  27 + */
  28 +
  29 +/**
  30 + * Both AR2315 and AR2316 chips have PCI interface unit, which supports DMA
  31 + * and interrupt. PCI interface supports MMIO access method, but does not
  32 + * seem to support I/O ports.
  33 + *
  34 + * Read/write operation in the region 0x80000000-0xBFFFFFFF causes
  35 + * a memory read/write command on the PCI bus. 30 LSBs of address on
  36 + * the bus are taken from memory read/write request and 2 MSBs are
  37 + * determined by PCI unit configuration.
  38 + *
  39 + * To work with the configuration space instead of memory is necessary set
  40 + * the CFG_SEL bit in the PCI_MISC_CONFIG register.
  41 + *
  42 + * Devices on the bus can perform DMA requests via chip BAR1. PCI host
  43 + * controller BARs are programmend as if an external device is programmed.
  44 + * Which means that during configuration, IDSEL pin of the chip should be
  45 + * asserted.
  46 + *
  47 + * We know (and support) only one board that uses the PCI interface -
  48 + * Fonera 2.0g (FON2202). It has a USB EHCI controller connected to the
  49 + * AR2315 PCI bus. IDSEL pin of USB controller is connected to AD[13] line
  50 + * and IDSEL pin of AR125 is connected to AD[16] line.
  51 + */
  52 +
  53 +#include <linux/types.h>
  54 +#include <linux/pci.h>
  55 +#include <linux/platform_device.h>
  56 +#include <linux/kernel.h>
  57 +#include <linux/init.h>
  58 +#include <linux/mm.h>
  59 +#include <linux/delay.h>
  60 +#include <linux/irq.h>
  61 +#include <linux/io.h>
  62 +#include <asm/paccess.h>
  63 +#include <ath25_platform.h>
  64 +#include <ar231x.h>
  65 +#include <ar2315_regs.h>
  66 +
  67 +/*
  68 + * PCI Bus Interface Registers
  69 + */
  70 +#define AR2315_PCI_1MS_REG             0x0008
  71 +
  72 +#define AR2315_PCI_1MS_MASK            0x3FFFF /* # of AHB clk cycles in 1ms */
  73 +
  74 +#define AR2315_PCI_MISC_CONFIG         0x000c
  75 +
  76 +#define AR2315_PCIMISC_TXD_EN  0x00000001      /* Enable TXD for fragments */
  77 +#define AR2315_PCIMISC_CFG_SEL 0x00000002      /* Mem or Config cycles */
  78 +#define AR2315_PCIMISC_GIG_MASK        0x0000000C      /* bits 31-30 for pci req */
  79 +#define AR2315_PCIMISC_RST_MODE        0x00000030
  80 +#define AR2315_PCIRST_INPUT    0x00000000      /* 4:5=0 rst is input */
  81 +#define AR2315_PCIRST_LOW      0x00000010      /* 4:5=1 rst to GND */
  82 +#define AR2315_PCIRST_HIGH     0x00000020      /* 4:5=2 rst to VDD */
  83 +#define AR2315_PCIGRANT_EN     0x00000000      /* 6:7=0 early grant en */
  84 +#define AR2315_PCIGRANT_FRAME  0x00000040      /* 6:7=1 grant waits 4 frame */
  85 +#define AR2315_PCIGRANT_IDLE   0x00000080      /* 6:7=2 grant waits 4 idle */
  86 +#define AR2315_PCIGRANT_GAP    0x00000000      /* 6:7=2 grant waits 4 idle */
  87 +#define AR2315_PCICACHE_DIS    0x00001000      /* PCI external access cache
  88 +                                                * disable */
  89 +
  90 +#define AR2315_PCI_OUT_TSTAMP          0x0010
  91 +
  92 +#define AR2315_PCI_UNCACHE_CFG         0x0014
  93 +
  94 +#define AR2315_PCI_IN_EN               0x0100
  95 +
  96 +#define AR2315_PCI_IN_EN0      0x01    /* Enable chain 0 */
  97 +#define AR2315_PCI_IN_EN1      0x02    /* Enable chain 1 */
  98 +#define AR2315_PCI_IN_EN2      0x04    /* Enable chain 2 */
  99 +#define AR2315_PCI_IN_EN3      0x08    /* Enable chain 3 */
 100 +
 101 +#define AR2315_PCI_IN_DIS              0x0104
 102 +
 103 +#define AR2315_PCI_IN_DIS0     0x01    /* Disable chain 0 */
 104 +#define AR2315_PCI_IN_DIS1     0x02    /* Disable chain 1 */
 105 +#define AR2315_PCI_IN_DIS2     0x04    /* Disable chain 2 */
 106 +#define AR2315_PCI_IN_DIS3     0x08    /* Disable chain 3 */
 107 +
 108 +#define AR2315_PCI_IN_PTR              0x0200
 109 +
 110 +#define AR2315_PCI_OUT_EN              0x0400
 111 +
 112 +#define AR2315_PCI_OUT_EN0     0x01    /* Enable chain 0 */
 113 +
 114 +#define AR2315_PCI_OUT_DIS             0x0404
 115 +
 116 +#define AR2315_PCI_OUT_DIS0    0x01    /* Disable chain 0 */
 117 +
 118 +#define AR2315_PCI_OUT_PTR             0x0408
 119 +
 120 +/* PCI interrupt status (write one to clear) */
 121 +#define AR2315_PCI_ISR                 0x0500
 122 +
 123 +#define AR2315_PCI_INT_TX      0x00000001      /* Desc In Completed */
 124 +#define AR2315_PCI_INT_TXOK    0x00000002      /* Desc In OK */
 125 +#define AR2315_PCI_INT_TXERR   0x00000004      /* Desc In ERR */
 126 +#define AR2315_PCI_INT_TXEOL   0x00000008      /* Desc In End-of-List */
 127 +#define AR2315_PCI_INT_RX      0x00000010      /* Desc Out Completed */
 128 +#define AR2315_PCI_INT_RXOK    0x00000020      /* Desc Out OK */
 129 +#define AR2315_PCI_INT_RXERR   0x00000040      /* Desc Out ERR */
 130 +#define AR2315_PCI_INT_RXEOL   0x00000080      /* Desc Out EOL */
 131 +#define AR2315_PCI_INT_TXOOD   0x00000200      /* Desc In Out-of-Desc */
 132 +#define AR2315_PCI_INT_DESCMASK        0x0000FFFF      /* Desc Mask */
 133 +#define AR2315_PCI_INT_EXT     0x02000000      /* Extern PCI INTA */
 134 +#define AR2315_PCI_INT_ABORT   0x04000000      /* PCI bus abort event */
 135 +
 136 +/* PCI interrupt mask */
 137 +#define AR2315_PCI_IMR                 0x0504
 138 +
 139 +/* Global PCI interrupt enable */
 140 +#define AR2315_PCI_IER                 0x0508
 141 +
 142 +#define AR2315_PCI_IER_DISABLE         0x00    /* disable pci interrupts */
 143 +#define AR2315_PCI_IER_ENABLE          0x01    /* enable pci interrupts */
 144 +
 145 +#define AR2315_PCI_HOST_IN_EN          0x0800
 146 +#define AR2315_PCI_HOST_IN_DIS         0x0804
 147 +#define AR2315_PCI_HOST_IN_PTR         0x0810
 148 +#define AR2315_PCI_HOST_OUT_EN         0x0900
 149 +#define AR2315_PCI_HOST_OUT_DIS                0x0904
 150 +#define AR2315_PCI_HOST_OUT_PTR                0x0908
 151 +
 152 +/*
 153 + * PCI interrupts, which share IP5
 154 + * Keep ordered according to AR2315_PCI_INT_XXX bits
 155 + */
 156 +#define AR2315_PCI_IRQ_BASE            0x50
 157 +#define AR2315_PCI_IRQ_EXT             (AR2315_PCI_IRQ_BASE+0)
 158 +#define AR2315_PCI_IRQ_ABORT           (AR2315_PCI_IRQ_BASE+1)
 159 +#define AR2315_PCI_IRQ_COUNT           2
 160 +#define AR2315_PCI_IRQ_SHIFT           25      /* in AR2315_PCI_INT_STATUS */
 161 +
 162 +/* Arbitrary size of memory region to access the configuration space */
 163 +#define AR2315_PCI_CFG_SIZE    0x00100000
 164 +
 165 +#define AR2315_PCI_HOST_SLOT   3
 166 +#define AR2315_PCI_HOST_DEVID  ((0xff18 << 16) | PCI_VENDOR_ID_ATHEROS)
 167 +
 168 +/* ??? access BAR */
 169 +#define AR2315_PCI_HOST_MBAR0          0x10000000
 170 +/* RAM access BAR */
 171 +#define AR2315_PCI_HOST_MBAR1          AR2315_PCI_HOST_SDRAM_BASEADDR
 172 +/* ??? access BAR */
 173 +#define AR2315_PCI_HOST_MBAR2          0x30000000
 174 +
 175 +struct ar2315_pci_ctrl {
 176 +       void __iomem *cfg_mem;
 177 +       void __iomem *mmr_mem;
 178 +       struct pci_controller pci_ctrl;
 179 +       struct resource mem_res;
 180 +       struct resource io_res;
 181 +};
 182 +
 183 +static inline struct ar2315_pci_ctrl *ar2315_pci_bus_to_apc(struct pci_bus *bus)
 184 +{
 185 +       struct pci_controller *hose = bus->sysdata;
 186 +
 187 +       return container_of(hose, struct ar2315_pci_ctrl, pci_ctrl);
 188 +}
 189 +
 190 +static inline u32 ar2315_pci_reg_read(struct ar2315_pci_ctrl *apc, u32 reg)
 191 +{
 192 +       return __raw_readl(apc->mmr_mem + reg);
 193 +}
 194 +
 195 +static inline void ar2315_pci_reg_write(struct ar2315_pci_ctrl *apc, u32 reg,
 196 +                                       u32 val)
 197 +{
 198 +       __raw_writel(val, apc->mmr_mem + reg);
 199 +}
 200 +
 201 +static inline void ar2315_pci_reg_mask(struct ar2315_pci_ctrl *apc, u32 reg,
 202 +                                      u32 mask, u32 val)
 203 +{
 204 +       u32 ret = ar2315_pci_reg_read(apc, reg);
 205 +
 206 +       ret &= ~mask;
 207 +       ret |= val;
 208 +       ar2315_pci_reg_write(apc, reg, ret);
 209 +}
 210 +
 211 +static int ar2315_pci_cfg_access(struct ar2315_pci_ctrl *apc, unsigned devfn,
 212 +                                int where, int size, u32 *ptr, bool write)
 213 +{
 214 +       int func = PCI_FUNC(devfn);
 215 +       int dev = PCI_SLOT(devfn);
 216 +       u32 addr = (1 << (13 + dev)) | (func << 8) | (where & ~3);
 217 +       u32 mask = 0xffffffff >> 8 * (4 - size);
 218 +       u32 sh = (where & 3) * 8;
 219 +       u32 value, isr;
 220 +
 221 +       /* Prevent access past the remapped area */
 222 +       if (addr >= AR2315_PCI_CFG_SIZE || dev > 18)
 223 +               return PCIBIOS_DEVICE_NOT_FOUND;
 224 +
 225 +       /* Clear pending errors */
 226 +       ar2315_pci_reg_write(apc, AR2315_PCI_ISR, AR2315_PCI_INT_ABORT);
 227 +       /* Select Configuration access */
 228 +       ar2315_pci_reg_mask(apc, AR2315_PCI_MISC_CONFIG, 0,
 229 +                           AR2315_PCIMISC_CFG_SEL);
 230 +
 231 +       mb();   /* PCI must see space change before we begin */
 232 +
 233 +       value = __raw_readl(apc->cfg_mem + addr);
 234 +
 235 +       isr = ar2315_pci_reg_read(apc, AR2315_PCI_ISR);
 236 +
 237 +       if (isr & AR2315_PCI_INT_ABORT)
 238 +               goto exit_err;
 239 +
 240 +       if (write) {
 241 +               value = (value & ~(mask << sh)) | *ptr << sh;
 242 +               __raw_writel(value, apc->cfg_mem + addr);
 243 +               isr = ar2315_pci_reg_read(apc, AR2315_PCI_ISR);
 244 +               if (isr & AR2315_PCI_INT_ABORT)
 245 +                       goto exit_err;
 246 +       } else {
 247 +               *ptr = (value >> sh) & mask;
 248 +       }
 249 +
 250 +       goto exit;
 251 +
 252 +exit_err:
 253 +       ar2315_pci_reg_write(apc, AR2315_PCI_ISR, AR2315_PCI_INT_ABORT);
 254 +       if (!write)
 255 +               *ptr = 0xffffffff;
 256 +
 257 +exit:
 258 +       /* Select Memory access */
 259 +       ar2315_pci_reg_mask(apc, AR2315_PCI_MISC_CONFIG, AR2315_PCIMISC_CFG_SEL,
 260 +                           0);
 261 +
 262 +       return isr & AR2315_PCI_INT_ABORT ? PCIBIOS_DEVICE_NOT_FOUND :
 263 +                                           PCIBIOS_SUCCESSFUL;
 264 +}
 265 +
 266 +static inline int ar2315_pci_local_cfg_rd(struct ar2315_pci_ctrl *apc,
 267 +                                         unsigned devfn, int where, u32 *val)
 268 +{
 269 +       return ar2315_pci_cfg_access(apc, devfn, where, sizeof(u32), val,
 270 +                                    false);
 271 +}
 272 +
 273 +static inline int ar2315_pci_local_cfg_wr(struct ar2315_pci_ctrl *apc,
 274 +                                         unsigned devfn, int where, u32 val)
 275 +{
 276 +       return ar2315_pci_cfg_access(apc, devfn, where, sizeof(u32), &val,
 277 +                                    true);
 278 +}
 279 +
 280 +static int ar2315_pci_cfg_read(struct pci_bus *bus, unsigned devfn, int where,
 281 +                              int size, u32 *value)
 282 +{
 283 +       struct ar2315_pci_ctrl *apc = ar2315_pci_bus_to_apc(bus);
 284 +
 285 +       if (PCI_SLOT(devfn) == AR2315_PCI_HOST_SLOT)
 286 +               return PCIBIOS_DEVICE_NOT_FOUND;
 287 +
 288 +       return ar2315_pci_cfg_access(apc, devfn, where, size, value, false);
 289 +}
 290 +
 291 +static int ar2315_pci_cfg_write(struct pci_bus *bus, unsigned devfn, int where,
 292 +                               int size, u32 value)
 293 +{
 294 +       struct ar2315_pci_ctrl *apc = ar2315_pci_bus_to_apc(bus);
 295 +
 296 +       if (PCI_SLOT(devfn) == AR2315_PCI_HOST_SLOT)
 297 +               return PCIBIOS_DEVICE_NOT_FOUND;
 298 +
 299 +       return ar2315_pci_cfg_access(apc, devfn, where, size, &value, true);
 300 +}
 301 +
 302 +static struct pci_ops ar2315_pci_ops = {
 303 +       .read   = ar2315_pci_cfg_read,
 304 +       .write  = ar2315_pci_cfg_write,
 305 +};
 306 +
 307 +static int ar2315_pci_host_setup(struct ar2315_pci_ctrl *apc)
 308 +{
 309 +       unsigned devfn = PCI_DEVFN(AR2315_PCI_HOST_SLOT, 0);
 310 +       int res;
 311 +       u32 id;
 312 +
 313 +       res = ar2315_pci_local_cfg_rd(apc, devfn, PCI_VENDOR_ID, &id);
 314 +       if (res != PCIBIOS_SUCCESSFUL || id != AR2315_PCI_HOST_DEVID)
 315 +               return -ENODEV;
 316 +
 317 +       /* Program MBARs */
 318 +       ar2315_pci_local_cfg_wr(apc, devfn, PCI_BASE_ADDRESS_0,
 319 +                               AR2315_PCI_HOST_MBAR0);
 320 +       ar2315_pci_local_cfg_wr(apc, devfn, PCI_BASE_ADDRESS_1,
 321 +                               AR2315_PCI_HOST_MBAR1);
 322 +       ar2315_pci_local_cfg_wr(apc, devfn, PCI_BASE_ADDRESS_2,
 323 +                               AR2315_PCI_HOST_MBAR2);
 324 +
 325 +       /* Run */
 326 +       ar2315_pci_local_cfg_wr(apc, devfn, PCI_COMMAND, PCI_COMMAND_MEMORY |
 327 +                               PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL |
 328 +                               PCI_COMMAND_INVALIDATE | PCI_COMMAND_PARITY |
 329 +                               PCI_COMMAND_SERR | PCI_COMMAND_FAST_BACK);
 330 +
 331 +       return 0;
 332 +}
 333 +
 334 +static void ar2315_pci_irq_handler(unsigned irq, struct irq_desc *desc)
 335 +{
 336 +       struct ar2315_pci_ctrl *apc = irq_get_handler_data(irq);
 337 +       u32 pending = ar2315_pci_reg_read(apc, AR2315_PCI_ISR) &
 338 +                     ar2315_pci_reg_read(apc, AR2315_PCI_IMR);
 339 +
 340 +       if (pending & AR2315_PCI_INT_EXT)
 341 +               generic_handle_irq(AR2315_PCI_IRQ_EXT);
 342 +       else if (pending & AR2315_PCI_INT_ABORT)
 343 +               generic_handle_irq(AR2315_PCI_IRQ_ABORT);
 344 +       else
 345 +               spurious_interrupt();
 346 +}
 347 +
 348 +static void ar2315_pci_irq_mask(struct irq_data *d)
 349 +{
 350 +       struct ar2315_pci_ctrl *apc = irq_data_get_irq_chip_data(d);
 351 +       u32 m = 1 << (d->irq - AR2315_PCI_IRQ_BASE + AR2315_PCI_IRQ_SHIFT);
 352 +
 353 +       ar2315_pci_reg_mask(apc, AR2315_PCI_IMR, m, 0);
 354 +}
 355 +
 356 +static void ar2315_pci_irq_mask_ack(struct irq_data *d)
 357 +{
 358 +       struct ar2315_pci_ctrl *apc = irq_data_get_irq_chip_data(d);
 359 +       u32 m = 1 << (d->irq - AR2315_PCI_IRQ_BASE + AR2315_PCI_IRQ_SHIFT);
 360 +
 361 +       ar2315_pci_reg_mask(apc, AR2315_PCI_IMR, m, 0);
 362 +       ar2315_pci_reg_write(apc, AR2315_PCI_ISR, m);
 363 +}
 364 +
 365 +static void ar2315_pci_irq_unmask(struct irq_data *d)
 366 +{
 367 +       struct ar2315_pci_ctrl *apc = irq_data_get_irq_chip_data(d);
 368 +       u32 m = 1 << (d->irq - AR2315_PCI_IRQ_BASE + AR2315_PCI_IRQ_SHIFT);
 369 +
 370 +       ar2315_pci_reg_mask(apc, AR2315_PCI_IMR, 0, m);
 371 +}
 372 +
 373 +static struct irq_chip ar2315_pci_irq_chip = {
 374 +       .name = "AR2315-PCI",
 375 +       .irq_mask = ar2315_pci_irq_mask,
 376 +       .irq_mask_ack = ar2315_pci_irq_mask_ack,
 377 +       .irq_unmask = ar2315_pci_irq_unmask,
 378 +};
 379 +
 380 +static void ar2315_pci_irq_init(struct ar2315_pci_ctrl *apc)
 381 +{
 382 +       int i;
 383 +
 384 +       ar2315_pci_reg_mask(apc, AR2315_PCI_IER, AR2315_PCI_IER_ENABLE, 0);
 385 +       ar2315_pci_reg_mask(apc, AR2315_PCI_IMR, (AR2315_PCI_INT_ABORT |
 386 +                           AR2315_PCI_INT_EXT), 0);
 387 +
 388 +       for (i = 0; i < AR2315_PCI_IRQ_COUNT; ++i) {
 389 +               int irq = AR2315_PCI_IRQ_BASE + i;
 390 +
 391 +               irq_set_chip_and_handler(irq, &ar2315_pci_irq_chip,
 392 +                                        handle_level_irq);
 393 +               irq_set_chip_data(irq, apc);
 394 +       }
 395 +
 396 +       irq_set_chained_handler(AR2315_IRQ_LCBUS_PCI, ar2315_pci_irq_handler);
 397 +       irq_set_handler_data(AR2315_IRQ_LCBUS_PCI, apc);
 398 +
 399 +       /* Clear any pending Abort or external Interrupts
 400 +        * and enable interrupt processing */
 401 +       ar2315_pci_reg_write(apc, AR2315_PCI_ISR, AR2315_PCI_INT_ABORT |
 402 +                                                 AR2315_PCI_INT_EXT);
 403 +       ar2315_pci_reg_mask(apc, AR2315_PCI_IER, 0, AR2315_PCI_IER_ENABLE);
 404 +}
 405 +
 406 +static int ar2315_pci_probe(struct platform_device *pdev)
 407 +{
 408 +       struct ar2315_pci_ctrl *apc;
 409 +       struct device *dev = &pdev->dev;
 410 +       int err;
 411 +
 412 +       apc = devm_kzalloc(dev, sizeof(*apc), GFP_KERNEL);
 413 +       if (!apc)
 414 +               return -ENOMEM;
 415 +
 416 +       apc->mmr_mem = devm_ioremap_nocache(dev, AR2315_PCI, AR2315_PCI_SIZE);
 417 +       if (!apc->mmr_mem)
 418 +               return -ENOMEM;
 419 +
 420 +       apc->mem_res.name = "AR2315 PCI mem space";
 421 +       apc->mem_res.start = AR2315_PCIEXT;
 422 +       apc->mem_res.end = AR2315_PCIEXT + AR2315_PCIEXT_SZ - 1;
 423 +       apc->mem_res.flags = IORESOURCE_MEM;
 424 +
 425 +       /* Remap PCI config space */
 426 +       apc->cfg_mem = devm_ioremap_nocache(dev, AR2315_PCIEXT,
 427 +                                           AR2315_PCI_CFG_SIZE);
 428 +       if (!apc->cfg_mem) {
 429 +               dev_err(dev, "failed to remap PCI config space\n");
 430 +               return -ENOMEM;
 431 +       }
 432 +
 433 +       /* Reset the PCI bus by setting bits 5-4 in PCI_MCFG */
 434 +       ar2315_pci_reg_mask(apc, AR2315_PCI_MISC_CONFIG,
 435 +                           AR2315_PCIMISC_RST_MODE,
 436 +                           AR2315_PCIRST_LOW);
 437 +       msleep(100);
 438 +
 439 +       /* Bring the PCI out of reset */
 440 +       ar2315_pci_reg_mask(apc, AR2315_PCI_MISC_CONFIG,
 441 +                           AR2315_PCIMISC_RST_MODE,
 442 +                           AR2315_PCIRST_HIGH | AR2315_PCICACHE_DIS | 0x8);
 443 +
 444 +       ar2315_pci_reg_write(apc, AR2315_PCI_UNCACHE_CFG,
 445 +                            0x1E | /* 1GB uncached */
 446 +                            (1 << 5) | /* Enable uncached */
 447 +                            (0x2 << 30) /* Base: 0x80000000 */);
 448 +       ar2315_pci_reg_read(apc, AR2315_PCI_UNCACHE_CFG);
 449 +
 450 +       msleep(500);
 451 +
 452 +       err = ar2315_pci_host_setup(apc);
 453 +       if (err)
 454 +               return err;
 455 +
 456 +       ar2315_pci_irq_init(apc);
 457 +
 458 +       /* PCI controller does not support I/O ports */
 459 +       apc->io_res.name = "AR2315 IO space";
 460 +       apc->io_res.start = 0;
 461 +       apc->io_res.end = 0;
 462 +       apc->io_res.flags = IORESOURCE_IO,
 463 +
 464 +       apc->pci_ctrl.pci_ops = &ar2315_pci_ops;
 465 +       apc->pci_ctrl.mem_resource = &apc->mem_res,
 466 +       apc->pci_ctrl.io_resource = &apc->io_res,
 467 +
 468 +       register_pci_controller(&apc->pci_ctrl);
 469 +
 470 +       return 0;
 471 +}
 472 +
 473 +static struct platform_driver ar2315_pci_driver = {
 474 +       .probe = ar2315_pci_probe,
 475 +       .driver = {
 476 +               .name = "ar2315-pci",
 477 +               .owner = THIS_MODULE,
 478 +       },
 479 +};
 480 +
 481 +static int __init ar2315_pci_init(void)
 482 +{
 483 +       return platform_driver_register(&ar2315_pci_driver);
 484 +}
 485 +arch_initcall(ar2315_pci_init);
 486 +
 487 +int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 488 +{
 489 +       return AR2315_PCI_IRQ_EXT;
 490 +}
 491 +
 492 +int pcibios_plat_dev_init(struct pci_dev *dev)
 493 +{
 494 +       return 0;
 495 +}
 496 --- a/arch/mips/ath25/Kconfig
 497 +++ b/arch/mips/ath25/Kconfig
 498 @@ -9,3 +9,10 @@ config SOC_AR2315
 499         depends on ATH25
 500         select GPIO_AR2315
 501         default y
 502 +
 503 +config PCI_AR2315
 504 +       bool "AR2315 PCI controller support"
 505 +       depends on SOC_AR2315
 506 +       select HW_HAS_PCI
 507 +       select PCI
 508 +       default y
 509 --- a/arch/mips/ath25/ar2315.c
 510 +++ b/arch/mips/ath25/ar2315.c
 511 @@ -116,6 +116,10 @@ static void ar2315_irq_dispatch(void)
 512                 do_IRQ(AR2315_IRQ_WLAN0_INTRS);
 513         else if (pending & CAUSEF_IP4)
 514                 do_IRQ(AR2315_IRQ_ENET0_INTRS);
 515 +#ifdef CONFIG_PCI_AR2315
 516 +       else if (pending & CAUSEF_IP5)
 517 +               do_IRQ(AR2315_IRQ_LCBUS_PCI);
 518 +#endif
 519         else if (pending & CAUSEF_IP2)
 520                 do_IRQ(AR2315_IRQ_MISC_INTRS);
 521         else if (pending & CAUSEF_IP7)
 522 @@ -427,4 +431,31 @@ void __init ar2315_arch_init(void)
 523  {
 524         ath25_serial_setup(AR2315_UART0, AR2315_MISC_IRQ_UART0,
 525                            ar2315_apb_frequency());
 526 +
 527 +#ifdef CONFIG_PCI_AR2315
 528 +       if (ath25_soc == ATH25_SOC_AR2315) {
 529 +               /* Reset PCI DMA logic */
 530 +               ar231x_mask_reg(AR2315_RESET, 0, AR2315_RESET_PCIDMA);
 531 +               msleep(20);
 532 +               ar231x_mask_reg(AR2315_RESET, AR2315_RESET_PCIDMA, 0);
 533 +               msleep(20);
 534 +
 535 +               /* Configure endians */
 536 +               ar231x_mask_reg(AR2315_ENDIAN_CTL, 0, AR2315_CONFIG_PCIAHB |
 537 +                               AR2315_CONFIG_PCIAHB_BRIDGE);
 538 +
 539 +               /* Configure as PCI host with DMA */
 540 +               ar231x_write_reg(AR2315_PCICLK, AR2315_PCICLK_PLLC_CLKM |
 541 +                                (AR2315_PCICLK_IN_FREQ_DIV_6 <<
 542 +                                 AR2315_PCICLK_DIV_S));
 543 +               ar231x_mask_reg(AR2315_AHB_ARB_CTL, 0, AR2315_ARB_PCI);
 544 +               ar231x_mask_reg(AR2315_IF_CTL, AR2315_IF_PCI_CLK_MASK |
 545 +                               AR2315_IF_MASK, AR2315_IF_PCI |
 546 +                               AR2315_IF_PCI_HOST | AR2315_IF_PCI_INTR |
 547 +                               (AR2315_IF_PCI_CLK_OUTPUT_CLK <<
 548 +                                AR2315_IF_PCI_CLK_SHIFT));
 549 +
 550 +               platform_device_register_simple("ar2315-pci", -1, NULL, 0);
 551 +       }
 552 +#endif
 553  }