atheros: update to 3.3.4 (based on work by acoul), fix mvswitch driver for newer...
[openwrt/svn-archive/archive.git] / target / linux / atheros / patches-3.3 / 120-spiflash.patch
1 --- a/drivers/mtd/devices/Kconfig
2 +++ b/drivers/mtd/devices/Kconfig
3 @@ -120,6 +120,10 @@ config MTD_SST25L
4 Set up your spi devices with the right board-specific platform data,
5 if you want to specify device partitioning.
6
7 +config MTD_AR2315
8 + tristate "Atheros AR2315+ SPI Flash support"
9 + depends on ATHEROS_AR2315
10 +
11 config MTD_SLRAM
12 tristate "Uncached system RAM"
13 help
14 --- a/drivers/mtd/devices/Makefile
15 +++ b/drivers/mtd/devices/Makefile
16 @@ -18,5 +18,6 @@ obj-$(CONFIG_MTD_BLOCK2MTD) += block2mtd
17 obj-$(CONFIG_MTD_DATAFLASH) += mtd_dataflash.o
18 obj-$(CONFIG_MTD_M25P80) += m25p80.o
19 obj-$(CONFIG_MTD_SST25L) += sst25l.o
20 +obj-$(CONFIG_MTD_AR2315) += ar2315.o
21
22 -CFLAGS_docg3.o += -I$(src)
23 \ No newline at end of file
24 +CFLAGS_docg3.o += -I$(src)
25 --- /dev/null
26 +++ b/drivers/mtd/devices/ar2315.c
27 @@ -0,0 +1,515 @@
28 +
29 +/*
30 + * MTD driver for the SPI Flash Memory support on Atheros AR2315
31 + *
32 + * Copyright (c) 2005-2006 Atheros Communications Inc.
33 + * Copyright (C) 2006-2007 FON Technology, SL.
34 + * Copyright (C) 2006-2007 Imre Kaloz <kaloz@openwrt.org>
35 + * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
36 + * Copyright (C) 2012 Alexandros C. Couloumbis <alex@ozo.com>
37 + *
38 + * This code is free software; you can redistribute it and/or modify
39 + * it under the terms of the GNU General Public License version 2 as
40 + * published by the Free Software Foundation.
41 + *
42 + */
43 +
44 +#include <linux/kernel.h>
45 +#include <linux/module.h>
46 +#include <linux/types.h>
47 +#include <linux/version.h>
48 +#include <linux/errno.h>
49 +#include <linux/slab.h>
50 +#include <linux/mtd/mtd.h>
51 +#include <linux/mtd/partitions.h>
52 +#include <linux/platform_device.h>
53 +#include <linux/sched.h>
54 +#include <linux/root_dev.h>
55 +#include <linux/delay.h>
56 +#include <asm/delay.h>
57 +#include <asm/io.h>
58 +
59 +#include <ar2315_spiflash.h>
60 +#include <ar231x_platform.h>
61 +#include <ar231x.h>
62 +
63 +
64 +#define SPIFLASH "spiflash: "
65 +#define busy_wait(_priv, _condition, _wait) do { \
66 + while (_condition) { \
67 + spin_unlock_bh(&_priv->lock); \
68 + if (_wait > 1) \
69 + msleep(_wait); \
70 + else if ((_wait == 1) && need_resched()) \
71 + schedule(); \
72 + else \
73 + udelay(1); \
74 + spin_lock_bh(&_priv->lock); \
75 + } \
76 +} while (0)
77 +
78 +enum {
79 + FLASH_NONE,
80 + FLASH_1MB,
81 + FLASH_2MB,
82 + FLASH_4MB,
83 + FLASH_8MB,
84 + FLASH_16MB,
85 +};
86 +
87 +/* Flash configuration table */
88 +struct flashconfig {
89 + u32 byte_cnt;
90 + u32 sector_cnt;
91 + u32 sector_size;
92 +};
93 +
94 +const struct flashconfig flashconfig_tbl[] = {
95 + [FLASH_NONE] = { 0, 0, 0},
96 + [FLASH_1MB] = { STM_1MB_BYTE_COUNT, STM_1MB_SECTOR_COUNT, STM_1MB_SECTOR_SIZE},
97 + [FLASH_2MB] = { STM_2MB_BYTE_COUNT, STM_2MB_SECTOR_COUNT, STM_2MB_SECTOR_SIZE},
98 + [FLASH_4MB] = { STM_4MB_BYTE_COUNT, STM_4MB_SECTOR_COUNT, STM_4MB_SECTOR_SIZE},
99 + [FLASH_8MB] = { STM_8MB_BYTE_COUNT, STM_8MB_SECTOR_COUNT, STM_8MB_SECTOR_SIZE},
100 + [FLASH_16MB] = { STM_16MB_BYTE_COUNT, STM_16MB_SECTOR_COUNT, STM_16MB_SECTOR_SIZE}
101 +};
102 +
103 +/* Mapping of generic opcodes to STM serial flash opcodes */
104 +enum {
105 + SPI_WRITE_ENABLE,
106 + SPI_WRITE_DISABLE,
107 + SPI_RD_STATUS,
108 + SPI_WR_STATUS,
109 + SPI_RD_DATA,
110 + SPI_FAST_RD_DATA,
111 + SPI_PAGE_PROGRAM,
112 + SPI_SECTOR_ERASE,
113 + SPI_BULK_ERASE,
114 + SPI_DEEP_PWRDOWN,
115 + SPI_RD_SIG,
116 +};
117 +
118 +struct opcodes {
119 + __u16 code;
120 + __s8 tx_cnt;
121 + __s8 rx_cnt;
122 +};
123 +const struct opcodes stm_opcodes[] = {
124 + [SPI_WRITE_ENABLE] = {STM_OP_WR_ENABLE, 1, 0},
125 + [SPI_WRITE_DISABLE] = {STM_OP_WR_DISABLE, 1, 0},
126 + [SPI_RD_STATUS] = {STM_OP_RD_STATUS, 1, 1},
127 + [SPI_WR_STATUS] = {STM_OP_WR_STATUS, 1, 0},
128 + [SPI_RD_DATA] = {STM_OP_RD_DATA, 4, 4},
129 + [SPI_FAST_RD_DATA] = {STM_OP_FAST_RD_DATA, 5, 0},
130 + [SPI_PAGE_PROGRAM] = {STM_OP_PAGE_PGRM, 8, 0},
131 + [SPI_SECTOR_ERASE] = {STM_OP_SECTOR_ERASE, 4, 0},
132 + [SPI_BULK_ERASE] = {STM_OP_BULK_ERASE, 1, 0},
133 + [SPI_DEEP_PWRDOWN] = {STM_OP_DEEP_PWRDOWN, 1, 0},
134 + [SPI_RD_SIG] = {STM_OP_RD_SIG, 4, 1},
135 +};
136 +
137 +/* Driver private data structure */
138 +struct spiflash_priv {
139 + struct mtd_info mtd;
140 + void *readaddr; /* memory mapped data for read */
141 + void *mmraddr; /* memory mapped register space */
142 + wait_queue_head_t wq;
143 + spinlock_t lock;
144 + int state;
145 +};
146 +
147 +#define to_spiflash(_mtd) container_of(_mtd, struct spiflash_priv, mtd)
148 +
149 +enum {
150 + FL_READY,
151 + FL_READING,
152 + FL_ERASING,
153 + FL_WRITING
154 +};
155 +
156 +/***************************************************************************************************/
157 +
158 +static u32
159 +spiflash_read_reg(struct spiflash_priv *priv, int reg)
160 +{
161 + return ar231x_read_reg((u32) priv->mmraddr + reg);
162 +}
163 +
164 +static void
165 +spiflash_write_reg(struct spiflash_priv *priv, int reg, u32 data)
166 +{
167 + ar231x_write_reg((u32) priv->mmraddr + reg, data);
168 +}
169 +
170 +static u32
171 +spiflash_wait_busy(struct spiflash_priv *priv)
172 +{
173 + u32 reg;
174 +
175 + busy_wait(priv, (reg = spiflash_read_reg(priv, SPI_FLASH_CTL)) &
176 + SPI_CTL_BUSY, 0);
177 + return reg;
178 +}
179 +
180 +static u32
181 +spiflash_sendcmd (struct spiflash_priv *priv, int opcode, u32 addr)
182 +{
183 + const struct opcodes *op;
184 + u32 reg, mask;
185 +
186 + op = &stm_opcodes[opcode];
187 + reg = spiflash_wait_busy(priv);
188 + spiflash_write_reg(priv, SPI_FLASH_OPCODE,
189 + ((u32) op->code) | (addr << 8));
190 +
191 + reg &= ~SPI_CTL_TX_RX_CNT_MASK;
192 + reg |= SPI_CTL_START | op->tx_cnt | (op->rx_cnt << 4);
193 +
194 + spiflash_write_reg(priv, SPI_FLASH_CTL, reg);
195 + spiflash_wait_busy(priv);
196 +
197 + if (!op->rx_cnt)
198 + return 0;
199 +
200 + reg = spiflash_read_reg(priv, SPI_FLASH_DATA);
201 +
202 + switch (op->rx_cnt) {
203 + case 1:
204 + mask = 0x000000ff;
205 + break;
206 + case 2:
207 + mask = 0x0000ffff;
208 + break;
209 + case 3:
210 + mask = 0x00ffffff;
211 + break;
212 + default:
213 + mask = 0xffffffff;
214 + break;
215 + }
216 + reg &= mask;
217 +
218 + return reg;
219 +}
220 +
221 +
222 +/*
223 + * Probe SPI flash device
224 + * Function returns 0 for failure.
225 + * and flashconfig_tbl array index for success.
226 + */
227 +static int
228 +spiflash_probe_chip (struct spiflash_priv *priv)
229 +{
230 + u32 sig;
231 + int flash_size;
232 +
233 + /* Read the signature on the flash device */
234 + spin_lock_bh(&priv->lock);
235 + sig = spiflash_sendcmd(priv, SPI_RD_SIG, 0);
236 + spin_unlock_bh(&priv->lock);
237 +
238 + switch (sig) {
239 + case STM_8MBIT_SIGNATURE:
240 + flash_size = FLASH_1MB;
241 + break;
242 + case STM_16MBIT_SIGNATURE:
243 + flash_size = FLASH_2MB;
244 + break;
245 + case STM_32MBIT_SIGNATURE:
246 + flash_size = FLASH_4MB;
247 + break;
248 + case STM_64MBIT_SIGNATURE:
249 + flash_size = FLASH_8MB;
250 + break;
251 + case STM_128MBIT_SIGNATURE:
252 + flash_size = FLASH_16MB;
253 + break;
254 + default:
255 + printk (KERN_WARNING SPIFLASH "Read of flash device signature failed!\n");
256 + return 0;
257 + }
258 +
259 + return flash_size;
260 +}
261 +
262 +
263 +/* wait until the flash chip is ready and grab a lock */
264 +static int spiflash_wait_ready(struct spiflash_priv *priv, int state)
265 +{
266 + DECLARE_WAITQUEUE(wait, current);
267 +
268 +retry:
269 + spin_lock_bh(&priv->lock);
270 + if (priv->state != FL_READY) {
271 + set_current_state(TASK_UNINTERRUPTIBLE);
272 + add_wait_queue(&priv->wq, &wait);
273 + spin_unlock_bh(&priv->lock);
274 + schedule();
275 + remove_wait_queue(&priv->wq, &wait);
276 +
277 + if(signal_pending(current))
278 + return 0;
279 +
280 + goto retry;
281 + }
282 + priv->state = state;
283 +
284 + return 1;
285 +}
286 +
287 +static inline void spiflash_done(struct spiflash_priv *priv)
288 +{
289 + priv->state = FL_READY;
290 + spin_unlock_bh(&priv->lock);
291 + wake_up(&priv->wq);
292 +}
293 +
294 +static void
295 +spiflash_wait_complete(struct spiflash_priv *priv, unsigned int timeout)
296 +{
297 + busy_wait(priv, spiflash_sendcmd(priv, SPI_RD_STATUS, 0) &
298 + SPI_STATUS_WIP, timeout);
299 + spiflash_done(priv);
300 +}
301 +
302 +
303 +
304 +static int
305 +spiflash_erase (struct mtd_info *mtd, struct erase_info *instr)
306 +{
307 + struct spiflash_priv *priv = to_spiflash(mtd);
308 + const struct opcodes *op;
309 + u32 temp, reg;
310 +
311 + if (instr->addr + instr->len > mtd->size)
312 + return -EINVAL;
313 +
314 + if (!spiflash_wait_ready(priv, FL_ERASING))
315 + return -EINTR;
316 +
317 + spiflash_sendcmd(priv, SPI_WRITE_ENABLE, 0);
318 + reg = spiflash_wait_busy(priv);
319 +
320 + op = &stm_opcodes[SPI_SECTOR_ERASE];
321 + temp = ((u32)instr->addr << 8) | (u32)(op->code);
322 + spiflash_write_reg(priv, SPI_FLASH_OPCODE, temp);
323 +
324 + reg &= ~SPI_CTL_TX_RX_CNT_MASK;
325 + reg |= op->tx_cnt | SPI_CTL_START;
326 + spiflash_write_reg(priv, SPI_FLASH_CTL, reg);
327 +
328 + spiflash_wait_complete(priv, 20);
329 +
330 + instr->state = MTD_ERASE_DONE;
331 + mtd_erase_callback(instr);
332 +
333 + return 0;
334 +}
335 +
336 +static int
337 +spiflash_read (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf)
338 +{
339 + struct spiflash_priv *priv = to_spiflash(mtd);
340 + u8 *read_addr;
341 +
342 + if (!len)
343 + return 0;
344 +
345 + if (from + len > mtd->size)
346 + return -EINVAL;
347 +
348 + *retlen = len;
349 +
350 + if (!spiflash_wait_ready(priv, FL_READING))
351 + return -EINTR;
352 +
353 + read_addr = (u8 *)(priv->readaddr + from);
354 + memcpy_fromio(buf, read_addr, len);
355 + spiflash_done(priv);
356 +
357 + return 0;
358 +}
359 +
360 +static int
361 +spiflash_write (struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen, const u8 *buf)
362 +{
363 + struct spiflash_priv *priv = to_spiflash(mtd);
364 + u32 opcode, bytes_left;
365 +
366 + *retlen = 0;
367 +
368 + if (!len)
369 + return 0;
370 +
371 + if (to + len > mtd->size)
372 + return -EINVAL;
373 +
374 + bytes_left = len;
375 +
376 + do {
377 + u32 read_len, reg, page_offset, spi_data = 0;
378 +
379 + read_len = min(bytes_left, sizeof(u32));
380 +
381 + /* 32-bit writes cannot span across a page boundary
382 + * (256 bytes). This types of writes require two page
383 + * program operations to handle it correctly. The STM part
384 + * will write the overflow data to the beginning of the
385 + * current page as opposed to the subsequent page.
386 + */
387 + page_offset = (to & (STM_PAGE_SIZE - 1)) + read_len;
388 +
389 + if (page_offset > STM_PAGE_SIZE)
390 + read_len -= (page_offset - STM_PAGE_SIZE);
391 +
392 + if (!spiflash_wait_ready(priv, FL_WRITING))
393 + return -EINTR;
394 +
395 + spiflash_sendcmd(priv, SPI_WRITE_ENABLE, 0);
396 + spi_data = 0;
397 + switch (read_len) {
398 + case 4:
399 + spi_data |= buf[3] << 24;
400 + /* fall through */
401 + case 3:
402 + spi_data |= buf[2] << 16;
403 + /* fall through */
404 + case 2:
405 + spi_data |= buf[1] << 8;
406 + /* fall through */
407 + case 1:
408 + spi_data |= buf[0] & 0xff;
409 + break;
410 + default:
411 + break;
412 + }
413 +
414 + spiflash_write_reg(priv, SPI_FLASH_DATA, spi_data);
415 + opcode = stm_opcodes[SPI_PAGE_PROGRAM].code |
416 + (to & 0x00ffffff) << 8;
417 + spiflash_write_reg(priv, SPI_FLASH_OPCODE, opcode);
418 +
419 + reg = spiflash_read_reg(priv, SPI_FLASH_CTL);
420 + reg &= ~SPI_CTL_TX_RX_CNT_MASK;
421 + reg |= (read_len + 4) | SPI_CTL_START;
422 + spiflash_write_reg(priv, SPI_FLASH_CTL, reg);
423 +
424 + spiflash_wait_complete(priv, 1);
425 +
426 + bytes_left -= read_len;
427 + to += read_len;
428 + buf += read_len;
429 +
430 + *retlen += read_len;
431 + } while (bytes_left != 0);
432 +
433 + return 0;
434 +}
435 +
436 +
437 +#if defined CONFIG_MTD_REDBOOT_PARTS || CONFIG_MTD_MYLOADER_PARTS
438 +static const char *part_probe_types[] = { "cmdlinepart", "RedBoot", "MyLoader", NULL };
439 +#endif
440 +
441 +
442 +static int
443 +spiflash_probe(struct platform_device *pdev)
444 +{
445 + struct spiflash_priv *priv;
446 + struct mtd_info *mtd;
447 + int index;
448 + int result = 0;
449 +
450 + priv = kzalloc(sizeof(struct spiflash_priv), GFP_KERNEL);
451 + spin_lock_init(&priv->lock);
452 + init_waitqueue_head(&priv->wq);
453 + priv->state = FL_READY;
454 + mtd = &priv->mtd;
455 +
456 + priv->mmraddr = ioremap_nocache(SPI_FLASH_MMR, SPI_FLASH_MMR_SIZE);
457 + if (!priv->mmraddr) {
458 + printk(KERN_WARNING SPIFLASH "Failed to map flash device\n");
459 + goto error;
460 + }
461 +
462 + index = spiflash_probe_chip(priv);
463 + if (!index) {
464 + printk (KERN_WARNING SPIFLASH "Found no serial flash device\n");
465 + goto error;
466 + }
467 +
468 + priv->readaddr = ioremap_nocache(SPI_FLASH_READ, flashconfig_tbl[index].byte_cnt);
469 + if (!priv->readaddr) {
470 + printk (KERN_WARNING SPIFLASH "Failed to map flash device\n");
471 + goto error;
472 + }
473 +
474 + platform_set_drvdata(pdev, priv);
475 + mtd->name = "spiflash";
476 + mtd->type = MTD_NORFLASH;
477 + mtd->flags = (MTD_CAP_NORFLASH|MTD_WRITEABLE);
478 + mtd->size = flashconfig_tbl[index].byte_cnt;
479 + mtd->erasesize = flashconfig_tbl[index].sector_size;
480 + mtd->writesize = 1;
481 + mtd->numeraseregions = 0;
482 + mtd->eraseregions = NULL;
483 + mtd->erase = spiflash_erase;
484 + mtd->read = spiflash_read;
485 + mtd->write = spiflash_write;
486 + mtd->owner = THIS_MODULE;
487 +
488 +#if defined CONFIG_MTD_REDBOOT_PARTS || CONFIG_MTD_MYLOADER_PARTS
489 + /* parse redboot partitions */
490 +
491 + result = mtd_device_parse_register(mtd, part_probe_types,
492 + NULL, NULL, 0);
493 +#endif
494 +
495 + return result;
496 +
497 +error:
498 + if (priv->mmraddr)
499 + iounmap(priv->mmraddr);
500 + kfree(priv);
501 + return -ENXIO;
502 +}
503 +
504 +static int
505 +spiflash_remove (struct platform_device *pdev)
506 +{
507 + struct spiflash_priv *priv = platform_get_drvdata(pdev);
508 + struct mtd_info *mtd = &priv->mtd;
509 +
510 + mtd_device_unregister(mtd);
511 + iounmap(priv->mmraddr);
512 + iounmap(priv->readaddr);
513 + kfree(priv);
514 +
515 + return 0;
516 +}
517 +
518 +struct platform_driver spiflash_driver = {
519 + .driver.name = "spiflash",
520 + .probe = spiflash_probe,
521 + .remove = spiflash_remove,
522 +};
523 +
524 +int __init
525 +spiflash_init (void)
526 +{
527 + return platform_driver_register(&spiflash_driver);
528 +}
529 +
530 +void __exit
531 +spiflash_exit (void)
532 +{
533 + return platform_driver_unregister(&spiflash_driver);
534 +}
535 +
536 +module_init (spiflash_init);
537 +module_exit (spiflash_exit);
538 +
539 +MODULE_LICENSE("GPL");
540 +MODULE_AUTHOR("OpenWrt.org, Atheros Communications Inc");
541 +MODULE_DESCRIPTION("MTD driver for SPI Flash on Atheros SOC");
542 +
543 --- /dev/null
544 +++ b/arch/mips/include/asm/mach-ar231x/ar2315_spiflash.h
545 @@ -0,0 +1,116 @@
546 +/*
547 + * SPI Flash Memory support header file.
548 + *
549 + * Copyright (c) 2005, Atheros Communications Inc.
550 + * Copyright (C) 2006 FON Technology, SL.
551 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
552 + * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
553 + *
554 + * This code is free software; you can redistribute it and/or modify
555 + * it under the terms of the GNU General Public License version 2 as
556 + * published by the Free Software Foundation.
557 + *
558 + */
559 +#ifndef __AR2315_SPIFLASH_H
560 +#define __AR2315_SPIFLASH_H
561 +
562 +#define STM_PAGE_SIZE 256
563 +
564 +#define SFI_WRITE_BUFFER_SIZE 4
565 +#define SFI_FLASH_ADDR_MASK 0x00ffffff
566 +
567 +#define STM_8MBIT_SIGNATURE 0x13
568 +#define STM_M25P80_BYTE_COUNT 1048576
569 +#define STM_M25P80_SECTOR_COUNT 16
570 +#define STM_M25P80_SECTOR_SIZE 0x10000
571 +
572 +#define STM_16MBIT_SIGNATURE 0x14
573 +#define STM_M25P16_BYTE_COUNT 2097152
574 +#define STM_M25P16_SECTOR_COUNT 32
575 +#define STM_M25P16_SECTOR_SIZE 0x10000
576 +
577 +#define STM_32MBIT_SIGNATURE 0x15
578 +#define STM_M25P32_BYTE_COUNT 4194304
579 +#define STM_M25P32_SECTOR_COUNT 64
580 +#define STM_M25P32_SECTOR_SIZE 0x10000
581 +
582 +#define STM_64MBIT_SIGNATURE 0x16
583 +#define STM_M25P64_BYTE_COUNT 8388608
584 +#define STM_M25P64_SECTOR_COUNT 128
585 +#define STM_M25P64_SECTOR_SIZE 0x10000
586 +
587 +#define STM_128MBIT_SIGNATURE 0x17
588 +#define STM_M25P128_BYTE_COUNT 16777216
589 +#define STM_M25P128_SECTOR_COUNT 256
590 +#define STM_M25P128_SECTOR_SIZE 0x10000
591 +
592 +#define STM_1MB_BYTE_COUNT STM_M25P80_BYTE_COUNT
593 +#define STM_1MB_SECTOR_COUNT STM_M25P80_SECTOR_COUNT
594 +#define STM_1MB_SECTOR_SIZE STM_M25P80_SECTOR_SIZE
595 +#define STM_2MB_BYTE_COUNT STM_M25P16_BYTE_COUNT
596 +#define STM_2MB_SECTOR_COUNT STM_M25P16_SECTOR_COUNT
597 +#define STM_2MB_SECTOR_SIZE STM_M25P16_SECTOR_SIZE
598 +#define STM_4MB_BYTE_COUNT STM_M25P32_BYTE_COUNT
599 +#define STM_4MB_SECTOR_COUNT STM_M25P32_SECTOR_COUNT
600 +#define STM_4MB_SECTOR_SIZE STM_M25P32_SECTOR_SIZE
601 +#define STM_8MB_BYTE_COUNT STM_M25P64_BYTE_COUNT
602 +#define STM_8MB_SECTOR_COUNT STM_M25P64_SECTOR_COUNT
603 +#define STM_8MB_SECTOR_SIZE STM_M25P64_SECTOR_SIZE
604 +#define STM_16MB_BYTE_COUNT STM_M25P128_BYTE_COUNT
605 +#define STM_16MB_SECTOR_COUNT STM_M25P128_SECTOR_COUNT
606 +#define STM_16MB_SECTOR_SIZE STM_M25P128_SECTOR_SIZE
607 +
608 +/*
609 + * ST Microelectronics Opcodes for Serial Flash
610 + */
611 +
612 +#define STM_OP_WR_ENABLE 0x06 /* Write Enable */
613 +#define STM_OP_WR_DISABLE 0x04 /* Write Disable */
614 +#define STM_OP_RD_STATUS 0x05 /* Read Status */
615 +#define STM_OP_WR_STATUS 0x01 /* Write Status */
616 +#define STM_OP_RD_DATA 0x03 /* Read Data */
617 +#define STM_OP_FAST_RD_DATA 0x0b /* Fast Read Data */
618 +#define STM_OP_PAGE_PGRM 0x02 /* Page Program */
619 +#define STM_OP_SECTOR_ERASE 0xd8 /* Sector Erase */
620 +#define STM_OP_BULK_ERASE 0xc7 /* Bulk Erase */
621 +#define STM_OP_DEEP_PWRDOWN 0xb9 /* Deep Power-Down Mode */
622 +#define STM_OP_RD_SIG 0xab /* Read Electronic Signature */
623 +
624 +#define STM_STATUS_WIP 0x01 /* Write-In-Progress */
625 +#define STM_STATUS_WEL 0x02 /* Write Enable Latch */
626 +#define STM_STATUS_BP0 0x04 /* Block Protect 0 */
627 +#define STM_STATUS_BP1 0x08 /* Block Protect 1 */
628 +#define STM_STATUS_BP2 0x10 /* Block Protect 2 */
629 +#define STM_STATUS_SRWD 0x80 /* Status Register Write Disable */
630 +
631 +/*
632 + * SPI Flash Interface Registers
633 + */
634 +#define AR531XPLUS_SPI_READ 0x08000000
635 +#define AR531XPLUS_SPI_MMR 0x11300000
636 +#define AR531XPLUS_SPI_MMR_SIZE 12
637 +
638 +#define AR531XPLUS_SPI_CTL 0x00
639 +#define AR531XPLUS_SPI_OPCODE 0x04
640 +#define AR531XPLUS_SPI_DATA 0x08
641 +
642 +#define SPI_FLASH_READ AR531XPLUS_SPI_READ
643 +#define SPI_FLASH_MMR AR531XPLUS_SPI_MMR
644 +#define SPI_FLASH_MMR_SIZE AR531XPLUS_SPI_MMR_SIZE
645 +#define SPI_FLASH_CTL AR531XPLUS_SPI_CTL
646 +#define SPI_FLASH_OPCODE AR531XPLUS_SPI_OPCODE
647 +#define SPI_FLASH_DATA AR531XPLUS_SPI_DATA
648 +
649 +#define SPI_CTL_START 0x00000100
650 +#define SPI_CTL_BUSY 0x00010000
651 +#define SPI_CTL_TXCNT_MASK 0x0000000f
652 +#define SPI_CTL_RXCNT_MASK 0x000000f0
653 +#define SPI_CTL_TX_RX_CNT_MASK 0x000000ff
654 +#define SPI_CTL_SIZE_MASK 0x00060000
655 +
656 +#define SPI_CTL_CLK_SEL_MASK 0x03000000
657 +#define SPI_OPCODE_MASK 0x000000ff
658 +
659 +#define SPI_STATUS_WIP STM_STATUS_WIP
660 +
661 +#endif