atheros: add support for linux kernel v3.8
[openwrt/svn-archive/archive.git] / target / linux / atheros / patches-3.8 / 100-board.patch
1 --- a/arch/mips/Kconfig
2 +++ b/arch/mips/Kconfig
3 @@ -120,6 +120,19 @@ config BCM63XX
4 help
5 Support for BCM63XX based boards
6
7 +config ATHEROS_AR231X
8 + bool "Atheros 231x/531x SoC support"
9 + select CEVT_R4K
10 + select CSRC_R4K
11 + select DMA_NONCOHERENT
12 + select IRQ_CPU
13 + select SYS_HAS_CPU_MIPS32_R1
14 + select SYS_SUPPORTS_BIG_ENDIAN
15 + select SYS_SUPPORTS_32BIT_KERNEL
16 + select ARCH_REQUIRE_GPIOLIB
17 + help
18 + Support for AR231x and AR531x based boards
19 +
20 config MIPS_COBALT
21 bool "Cobalt Server"
22 select CEVT_R4K
23 @@ -813,6 +826,7 @@ config NLM_XLP_BOARD
24
25 endchoice
26
27 +source "arch/mips/ar231x/Kconfig"
28 source "arch/mips/alchemy/Kconfig"
29 source "arch/mips/ath79/Kconfig"
30 source "arch/mips/bcm47xx/Kconfig"
31 --- a/arch/mips/Kbuild.platforms
32 +++ b/arch/mips/Kbuild.platforms
33 @@ -6,6 +6,7 @@ platforms += ath79
34 platforms += bcm47xx
35 platforms += bcm63xx
36 platforms += cavium-octeon
37 +platforms += ar231x
38 platforms += cobalt
39 platforms += dec
40 platforms += emma
41 --- /dev/null
42 +++ b/arch/mips/ar231x/Platform
43 @@ -0,0 +1,6 @@
44 +#
45 +# Atheros AR5312/AR2312 WiSoC
46 +#
47 +platform-$(CONFIG_ATHEROS_AR231X) += ar231x/
48 +cflags-$(CONFIG_ATHEROS_AR231X) += -I$(srctree)/arch/mips/include/asm/mach-ar231x
49 +load-$(CONFIG_ATHEROS_AR231X) += 0xffffffff80041000
50 --- /dev/null
51 +++ b/arch/mips/ar231x/Kconfig
52 @@ -0,0 +1,16 @@
53 +config ATHEROS_AR5312
54 + bool "Atheros 5312/2312+ support"
55 + depends on ATHEROS_AR231X
56 + default y
57 +
58 +config ATHEROS_AR2315
59 + bool "Atheros 2315+ support"
60 + depends on ATHEROS_AR231X
61 + select DMA_NONCOHERENT
62 + select CEVT_R4K
63 + select CSRC_R4K
64 + select IRQ_CPU
65 + select SYS_HAS_CPU_MIPS32_R1
66 + select SYS_SUPPORTS_32BIT_KERNEL
67 + select SYS_SUPPORTS_BIG_ENDIAN
68 + default y
69 --- /dev/null
70 +++ b/arch/mips/ar231x/Makefile
71 @@ -0,0 +1,13 @@
72 +#
73 +# This file is subject to the terms and conditions of the GNU General Public
74 +# License. See the file "COPYING" in the main directory of this archive
75 +# for more details.
76 +#
77 +# Copyright (C) 2006 FON Technology, SL.
78 +# Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
79 +# Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
80 +#
81 +
82 +obj-y += board.o prom.o devices.o
83 +obj-$(CONFIG_ATHEROS_AR5312) += ar5312.o
84 +obj-$(CONFIG_ATHEROS_AR2315) += ar2315.o
85 --- /dev/null
86 +++ b/arch/mips/ar231x/board.c
87 @@ -0,0 +1,259 @@
88 +/*
89 + * This file is subject to the terms and conditions of the GNU General Public
90 + * License. See the file "COPYING" in the main directory of this archive
91 + * for more details.
92 + *
93 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
94 + * Copyright (C) 2006 FON Technology, SL.
95 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
96 + * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
97 + */
98 +
99 +#include <generated/autoconf.h>
100 +#include <linux/init.h>
101 +#include <linux/module.h>
102 +#include <linux/types.h>
103 +#include <linux/string.h>
104 +#include <linux/platform_device.h>
105 +#include <linux/kernel.h>
106 +#include <linux/random.h>
107 +#include <linux/etherdevice.h>
108 +#include <linux/irq.h>
109 +#include <asm/irq_cpu.h>
110 +#include <asm/reboot.h>
111 +#include <asm/io.h>
112 +
113 +#include <ar231x_platform.h>
114 +#include "devices.h"
115 +#include "ar5312.h"
116 +#include "ar2315.h"
117 +
118 +void (*ar231x_irq_dispatch)(void);
119 +
120 +static inline bool
121 +check_radio_magic(u8 *addr)
122 +{
123 + addr += 0x7a; /* offset for flash magic */
124 + if ((addr[0] == 0x5a) && (addr[1] == 0xa5)) {
125 + return 1;
126 + }
127 + return 0;
128 +}
129 +
130 +static inline bool
131 +check_board_data(u8 *flash_limit, u8 *addr, bool broken)
132 +{
133 + /* config magic found */
134 + if (*((u32 *)addr) == AR531X_BD_MAGIC)
135 + return 1;
136 +
137 + if (!broken)
138 + return 0;
139 +
140 + if (check_radio_magic(addr + 0xf8))
141 + ar231x_board.radio = addr + 0xf8;
142 + if ((addr < flash_limit + 0x10000) &&
143 + check_radio_magic(addr + 0x10000))
144 + ar231x_board.radio = addr + 0x10000;
145 +
146 + if (ar231x_board.radio) {
147 + /* broken board data detected, use radio data to find the offset,
148 + * user will fix this */
149 + return 1;
150 + }
151 + return 0;
152 +}
153 +
154 +static u8 *
155 +find_board_config(u8 *flash_limit, bool broken)
156 +{
157 + u8 *addr;
158 + int found = 0;
159 +
160 + for (addr = flash_limit - 0x1000;
161 + addr >= flash_limit - 0x30000;
162 + addr -= 0x1000) {
163 +
164 + if (check_board_data(flash_limit, addr, broken)) {
165 + found = 1;
166 + break;
167 + }
168 + }
169 +
170 + if (!found)
171 + addr = NULL;
172 +
173 + return addr;
174 +}
175 +
176 +static u8 *
177 +find_radio_config(u8 *flash_limit, u8 *board_config)
178 +{
179 + int found;
180 + u8 *radio_config;
181 +
182 + /*
183 + * Now find the start of Radio Configuration data, using heuristics:
184 + * Search forward from Board Configuration data by 0x1000 bytes
185 + * at a time until we find non-0xffffffff.
186 + */
187 + found = 0;
188 + for (radio_config = board_config + 0x1000;
189 + (radio_config < flash_limit);
190 + radio_config += 0x1000) {
191 + if ((*(u32 *)radio_config != 0xffffffff) &&
192 + check_radio_magic(radio_config)) {
193 + found = 1;
194 + break;
195 + }
196 + }
197 +
198 + /* AR2316 relocates radio config to new location */
199 + if (!found) {
200 + for (radio_config = board_config + 0xf8;
201 + (radio_config < flash_limit - 0x1000 + 0xf8);
202 + radio_config += 0x1000) {
203 + if ((*(u32 *)radio_config != 0xffffffff) &&
204 + check_radio_magic(radio_config)) {
205 + found = 1;
206 + break;
207 + }
208 + }
209 + }
210 +
211 + if (!found) {
212 + printk("Could not find Radio Configuration data\n");
213 + radio_config = 0;
214 + }
215 +
216 + return (u8 *) radio_config;
217 +}
218 +
219 +int __init
220 +ar231x_find_config(u8 *flash_limit)
221 +{
222 + struct ar231x_boarddata *config;
223 + unsigned int rcfg_size;
224 + int broken_boarddata = 0;
225 + u8 *bcfg, *rcfg;
226 + u8 *board_data;
227 + u8 *radio_data;
228 + u8 *mac_addr;
229 + u32 offset;
230 +
231 + ar231x_board.config = NULL;
232 + ar231x_board.radio = NULL;
233 + /* Copy the board and radio data to RAM, because accessing the mapped
234 + * memory of the flash directly after booting is not safe */
235 +
236 + /* Try to find valid board and radio data */
237 + bcfg = find_board_config(flash_limit, false);
238 +
239 + /* If that fails, try to at least find valid radio data */
240 + if (!bcfg) {
241 + bcfg = find_board_config(flash_limit, true);
242 + broken_boarddata = 1;
243 + }
244 +
245 + if (!bcfg) {
246 + printk(KERN_WARNING "WARNING: No board configuration data found!\n");
247 + return -ENODEV;
248 + }
249 +
250 + board_data = kzalloc(BOARD_CONFIG_BUFSZ, GFP_KERNEL);
251 + ar231x_board.config = (struct ar231x_boarddata *) board_data;
252 + memcpy(board_data, bcfg, 0x100);
253 + if (broken_boarddata) {
254 + printk(KERN_WARNING "WARNING: broken board data detected\n");
255 + config = ar231x_board.config;
256 + if (!memcmp(config->enet0_mac, "\x00\x00\x00\x00\x00\x00", 6)) {
257 + printk(KERN_INFO "Fixing up empty mac addresses\n");
258 + config->resetConfigGpio = 0xffff;
259 + config->sysLedGpio = 0xffff;
260 + random_ether_addr(config->wlan0_mac);
261 + config->wlan0_mac[0] &= ~0x06;
262 + random_ether_addr(config->enet0_mac);
263 + random_ether_addr(config->enet1_mac);
264 + }
265 + }
266 +
267 +
268 + /* Radio config starts 0x100 bytes after board config, regardless
269 + * of what the physical layout on the flash chip looks like */
270 +
271 + if (ar231x_board.radio)
272 + rcfg = (u8 *) ar231x_board.radio;
273 + else
274 + rcfg = find_radio_config(flash_limit, bcfg);
275 +
276 + if (!rcfg)
277 + return -ENODEV;
278 +
279 + radio_data = board_data + 0x100 + ((rcfg - bcfg) & 0xfff);
280 + ar231x_board.radio = radio_data;
281 + offset = radio_data - board_data;
282 + printk(KERN_INFO "Radio config found at offset 0x%x(0x%x)\n", rcfg - bcfg, offset);
283 + rcfg_size = BOARD_CONFIG_BUFSZ - offset;
284 + memcpy(radio_data, rcfg, rcfg_size);
285 +
286 + mac_addr = &radio_data[0x1d * 2];
287 + if (is_broadcast_ether_addr(mac_addr)) {
288 + printk(KERN_INFO "Radio MAC is blank; using board-data\n");
289 + memcpy(mac_addr, ar231x_board.config->wlan0_mac, ETH_ALEN);
290 + }
291 +
292 + return 0;
293 +}
294 +
295 +static void
296 +ar231x_halt(void)
297 +{
298 + local_irq_disable();
299 + while (1);
300 +}
301 +
302 +void __init
303 +plat_mem_setup(void)
304 +{
305 + _machine_halt = ar231x_halt;
306 + pm_power_off = ar231x_halt;
307 +
308 + ar5312_plat_setup();
309 + ar2315_plat_setup();
310 +
311 + /* Disable data watchpoints */
312 + write_c0_watchlo0(0);
313 +}
314 +
315 +
316 +asmlinkage void
317 +plat_irq_dispatch(void)
318 +{
319 + ar231x_irq_dispatch();
320 +}
321 +
322 +void __init
323 +plat_time_init(void)
324 +{
325 + ar5312_time_init();
326 + ar2315_time_init();
327 +}
328 +
329 +unsigned int __cpuinit
330 +get_c0_compare_int(void)
331 +{
332 + return CP0_LEGACY_COMPARE_IRQ;
333 +}
334 +
335 +void __init
336 +arch_init_irq(void)
337 +{
338 + clear_c0_status(ST0_IM);
339 + mips_cpu_irq_init();
340 +
341 + /* Initialize interrupt controllers */
342 + ar5312_irq_init();
343 + ar2315_irq_init();
344 +}
345 +
346 +
347 --- /dev/null
348 +++ b/arch/mips/ar231x/prom.c
349 @@ -0,0 +1,37 @@
350 +/*
351 + * This file is subject to the terms and conditions of the GNU General Public
352 + * License. See the file "COPYING" in the main directory of this archive
353 + * for more details.
354 + *
355 + * Copyright MontaVista Software Inc
356 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
357 + * Copyright (C) 2006 FON Technology, SL.
358 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
359 + * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
360 + */
361 +
362 +/*
363 + * Prom setup file for ar531x
364 + */
365 +
366 +#include <linux/init.h>
367 +#include <generated/autoconf.h>
368 +#include <linux/kernel.h>
369 +#include <linux/string.h>
370 +#include <linux/mm.h>
371 +#include <linux/bootmem.h>
372 +
373 +#include <asm/bootinfo.h>
374 +#include <asm/addrspace.h>
375 +#include "ar5312.h"
376 +#include "ar2315.h"
377 +
378 +void __init prom_init(void)
379 +{
380 + ar5312_prom_init();
381 + ar2315_prom_init();
382 +}
383 +
384 +void __init prom_free_prom_memory(void)
385 +{
386 +}
387 --- /dev/null
388 +++ b/arch/mips/include/asm/mach-ar231x/ar231x_platform.h
389 @@ -0,0 +1,83 @@
390 +#ifndef __AR531X_PLATFORM_H
391 +#define __AR531X_PLATFORM_H
392 +
393 +/*
394 + * This is board-specific data that is stored in a "fixed" location in flash.
395 + * It is shared across operating systems, so it should not be changed lightly.
396 + * The main reason we need it is in order to extract the ethernet MAC
397 + * address(es).
398 + */
399 +struct ar231x_boarddata {
400 + u32 magic; /* board data is valid */
401 +#define AR531X_BD_MAGIC 0x35333131 /* "5311", for all 531x platforms */
402 + u16 cksum; /* checksum (starting with BD_REV 2) */
403 + u16 rev; /* revision of this struct */
404 +#define BD_REV 4
405 + char boardName[64]; /* Name of board */
406 + u16 major; /* Board major number */
407 + u16 minor; /* Board minor number */
408 + u32 flags; /* Board configuration */
409 +#define BD_ENET0 0x00000001 /* ENET0 is stuffed */
410 +#define BD_ENET1 0x00000002 /* ENET1 is stuffed */
411 +#define BD_UART1 0x00000004 /* UART1 is stuffed */
412 +#define BD_UART0 0x00000008 /* UART0 is stuffed (dma) */
413 +#define BD_RSTFACTORY 0x00000010 /* Reset factory defaults stuffed */
414 +#define BD_SYSLED 0x00000020 /* System LED stuffed */
415 +#define BD_EXTUARTCLK 0x00000040 /* External UART clock */
416 +#define BD_CPUFREQ 0x00000080 /* cpu freq is valid in nvram */
417 +#define BD_SYSFREQ 0x00000100 /* sys freq is set in nvram */
418 +#define BD_WLAN0 0x00000200 /* Enable WLAN0 */
419 +#define BD_MEMCAP 0x00000400 /* CAP SDRAM @ memCap for testing */
420 +#define BD_DISWATCHDOG 0x00000800 /* disable system watchdog */
421 +#define BD_WLAN1 0x00001000 /* Enable WLAN1 (ar5212) */
422 +#define BD_ISCASPER 0x00002000 /* FLAG for AR2312 */
423 +#define BD_WLAN0_2G_EN 0x00004000 /* FLAG for radio0_2G */
424 +#define BD_WLAN0_5G_EN 0x00008000 /* FLAG for radio0_2G */
425 +#define BD_WLAN1_2G_EN 0x00020000 /* FLAG for radio0_2G */
426 +#define BD_WLAN1_5G_EN 0x00040000 /* FLAG for radio0_2G */
427 + u16 resetConfigGpio; /* Reset factory GPIO pin */
428 + u16 sysLedGpio; /* System LED GPIO pin */
429 +
430 + u32 cpuFreq; /* CPU core frequency in Hz */
431 + u32 sysFreq; /* System frequency in Hz */
432 + u32 cntFreq; /* Calculated C0_COUNT frequency */
433 +
434 + u8 wlan0_mac[6];
435 + u8 enet0_mac[6];
436 + u8 enet1_mac[6];
437 +
438 + u16 pciId; /* Pseudo PCIID for common code */
439 + u16 memCap; /* cap bank1 in MB */
440 +
441 + /* version 3 */
442 + u8 wlan1_mac[6]; /* (ar5212) */
443 +};
444 +
445 +#define BOARD_CONFIG_BUFSZ 0x1000
446 +
447 +/*
448 + * Platform device information for the Wireless MAC
449 + */
450 +struct ar231x_board_config {
451 + u16 devid;
452 +
453 + /* board config data */
454 + struct ar231x_boarddata *config;
455 +
456 + /* radio calibration data */
457 + const char *radio;
458 +};
459 +
460 +/*
461 + * Platform device information for the Ethernet MAC
462 + */
463 +struct ar231x_eth {
464 + u32 reset_base;
465 + u32 reset_mac;
466 + u32 reset_phy;
467 + u32 phy_base;
468 + struct ar231x_board_config *config;
469 + char *macaddr;
470 +};
471 +
472 +#endif /* __AR531X_PLATFORM_H */
473 --- /dev/null
474 +++ b/arch/mips/include/asm/mach-ar231x/cpu-feature-overrides.h
475 @@ -0,0 +1,84 @@
476 +/*
477 + * Atheros SoC specific CPU feature overrides
478 + *
479 + * Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
480 + *
481 + * This file was derived from: include/asm-mips/cpu-features.h
482 + * Copyright (C) 2003, 2004 Ralf Baechle
483 + * Copyright (C) 2004 Maciej W. Rozycki
484 + *
485 + * This program is free software; you can redistribute it and/or modify it
486 + * under the terms of the GNU General Public License version 2 as published
487 + * by the Free Software Foundation.
488 + *
489 + */
490 +#ifndef __ASM_MACH_ATHEROS_CPU_FEATURE_OVERRIDES_H
491 +#define __ASM_MACH_ATHEROS_CPU_FEATURE_OVERRIDES_H
492 +
493 +/*
494 + * The ATHEROS SoCs have MIPS 4Kc/4KEc core.
495 + */
496 +#define cpu_has_tlb 1
497 +#define cpu_has_4kex 1
498 +#define cpu_has_3k_cache 0
499 +#define cpu_has_4k_cache 1
500 +#define cpu_has_tx39_cache 0
501 +#define cpu_has_sb1_cache 0
502 +#define cpu_has_fpu 0
503 +#define cpu_has_32fpr 0
504 +#define cpu_has_counter 1
505 +/* #define cpu_has_watch ? */
506 +/* #define cpu_has_divec ? */
507 +/* #define cpu_has_vce ? */
508 +/* #define cpu_has_cache_cdex_p ? */
509 +/* #define cpu_has_cache_cdex_s ? */
510 +/* #define cpu_has_prefetch ? */
511 +/* #define cpu_has_mcheck ? */
512 +#define cpu_has_ejtag 1
513 +
514 +#if !defined(CONFIG_ATHEROS_AR5312)
515 +# define cpu_has_llsc 1
516 +#else
517 +/*
518 + * The MIPS 4Kc V0.9 core in the AR5312/AR2312 have problems with the
519 + * ll/sc instructions.
520 + */
521 +# define cpu_has_llsc 0
522 +#endif
523 +
524 +#define cpu_has_mips16 0
525 +#define cpu_has_mdmx 0
526 +#define cpu_has_mips3d 0
527 +#define cpu_has_smartmips 0
528 +
529 +/* #define cpu_has_vtag_icache ? */
530 +/* #define cpu_has_dc_aliases ? */
531 +/* #define cpu_has_ic_fills_f_dc ? */
532 +/* #define cpu_has_pindexed_dcache ? */
533 +
534 +/* #define cpu_icache_snoops_remote_store ? */
535 +
536 +#define cpu_has_mips32r1 1
537 +
538 +#if !defined(CONFIG_ATHEROS_AR5312)
539 +# define cpu_has_mips32r2 1
540 +#endif
541 +
542 +#define cpu_has_mips64r1 0
543 +#define cpu_has_mips64r2 0
544 +
545 +#define cpu_has_dsp 0
546 +#define cpu_has_mipsmt 0
547 +
548 +/* #define cpu_has_nofpuex ? */
549 +#define cpu_has_64bits 0
550 +#define cpu_has_64bit_zero_reg 0
551 +#define cpu_has_64bit_gp_regs 0
552 +#define cpu_has_64bit_addresses 0
553 +
554 +/* #define cpu_has_inclusive_pcaches ? */
555 +
556 +/* #define cpu_dcache_line_size() ? */
557 +/* #define cpu_icache_line_size() ? */
558 +
559 +#endif /* __ASM_MACH_ATHEROS_CPU_FEATURE_OVERRIDES_H */
560 --- /dev/null
561 +++ b/arch/mips/include/asm/mach-ar231x/dma-coherence.h
562 @@ -0,0 +1,76 @@
563 +/*
564 + * This file is subject to the terms and conditions of the GNU General Public
565 + * License. See the file "COPYING" in the main directory of this archive
566 + * for more details.
567 + *
568 + * Copyright (C) 2006 Ralf Baechle <ralf@linux-mips.org>
569 + * Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
570 + *
571 + */
572 +#ifndef __ASM_MACH_GENERIC_DMA_COHERENCE_H
573 +#define __ASM_MACH_GENERIC_DMA_COHERENCE_H
574 +
575 +#define PCI_DMA_OFFSET 0x20000000
576 +
577 +#include <linux/device.h>
578 +
579 +static inline dma_addr_t ar231x_dev_offset(struct device *dev)
580 +{
581 +#ifdef CONFIG_PCI
582 + extern struct bus_type pci_bus_type;
583 +
584 + if (dev && dev->bus == &pci_bus_type)
585 + return PCI_DMA_OFFSET;
586 + else
587 +#endif
588 + return 0;
589 +}
590 +
591 +static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr, size_t size)
592 +{
593 + return virt_to_phys(addr) + ar231x_dev_offset(dev);
594 +}
595 +
596 +static inline dma_addr_t plat_map_dma_mem_page(struct device *dev, struct page *page)
597 +{
598 + return page_to_phys(page) + ar231x_dev_offset(dev);
599 +}
600 +
601 +static inline unsigned long plat_dma_addr_to_phys(struct device *dev,
602 + dma_addr_t dma_addr)
603 +{
604 + return dma_addr - ar231x_dev_offset(dev);
605 +}
606 +
607 +static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr,
608 + size_t size, enum dma_data_direction direction)
609 +{
610 +}
611 +
612 +static inline int plat_dma_supported(struct device *dev, u64 mask)
613 +{
614 + return 1;
615 +}
616 +
617 +static inline void plat_extra_sync_for_device(struct device *dev)
618 +{
619 + return;
620 +}
621 +
622 +static inline int plat_dma_mapping_error(struct device *dev,
623 + dma_addr_t dma_addr)
624 +{
625 + return 0;
626 +}
627 +
628 +static inline int plat_device_is_coherent(struct device *dev)
629 +{
630 +#ifdef CONFIG_DMA_COHERENT
631 + return 1;
632 +#endif
633 +#ifdef CONFIG_DMA_NONCOHERENT
634 + return 0;
635 +#endif
636 +}
637 +
638 +#endif /* __ASM_MACH_GENERIC_DMA_COHERENCE_H */
639 --- /dev/null
640 +++ b/arch/mips/include/asm/mach-ar231x/gpio.h
641 @@ -0,0 +1,28 @@
642 +#ifndef _ATHEROS_GPIO_H_
643 +#define _ATHEROS_GPIO_H_
644 +
645 +#include <ar231x.h>
646 +
647 +#define gpio_get_value __gpio_get_value
648 +#define gpio_set_value __gpio_set_value
649 +#define gpio_cansleep __gpio_cansleep
650 +
651 +/*
652 + * Wrappers for the generic GPIO layer
653 + */
654 +
655 +/* not sure if these are used? */
656 +
657 +/* Returns IRQ to attach for gpio. Unchecked function */
658 +static inline int gpio_to_irq(unsigned gpio) {
659 + return AR531X_GPIO_IRQ(gpio);
660 +}
661 +
662 +/* Returns gpio for IRQ attached. Unchecked function */
663 +static inline int irq_to_gpio(unsigned irq) {
664 + return (irq - (AR531X_GPIO_IRQ(0)));
665 +}
666 +
667 +#include <asm-generic/gpio.h> /* cansleep wrappers */
668 +
669 +#endif
670 --- /dev/null
671 +++ b/arch/mips/include/asm/mach-ar231x/reset.h
672 @@ -0,0 +1,6 @@
673 +#ifndef __AR531X_RESET_H
674 +#define __AR531X_RESET_H
675 +
676 +void ar531x_disable_reset_button(void);
677 +
678 +#endif /* __AR531X_RESET_H */
679 --- /dev/null
680 +++ b/arch/mips/include/asm/mach-ar231x/war.h
681 @@ -0,0 +1,25 @@
682 +/*
683 + * This file is subject to the terms and conditions of the GNU General Public
684 + * License. See the file "COPYING" in the main directory of this archive
685 + * for more details.
686 + *
687 + * Copyright (C) 2008 Felix Fietkau <nbd@openwrt.org>
688 + */
689 +#ifndef __ASM_MIPS_MACH_ATHEROS_WAR_H
690 +#define __ASM_MIPS_MACH_ATHEROS_WAR_H
691 +
692 +#define R4600_V1_INDEX_ICACHEOP_WAR 0
693 +#define R4600_V1_HIT_CACHEOP_WAR 0
694 +#define R4600_V2_HIT_CACHEOP_WAR 0
695 +#define R5432_CP0_INTERRUPT_WAR 0
696 +#define BCM1250_M3_WAR 0
697 +#define SIBYTE_1956_WAR 0
698 +#define MIPS4K_ICACHE_REFILL_WAR 0
699 +#define MIPS_CACHE_SYNC_WAR 0
700 +#define TX49XX_ICACHE_INDEX_INV_WAR 0
701 +#define RM9000_CDEX_SMP_WAR 0
702 +#define ICACHE_REFILLS_WORKAROUND_WAR 0
703 +#define R10000_LLSC_WAR 0
704 +#define MIPS34K_MISSED_ITLB_WAR 0
705 +
706 +#endif /* __ASM_MIPS_MACH_ATHEROS_WAR_H */
707 --- /dev/null
708 +++ b/arch/mips/include/asm/mach-ar231x/ar2315_regs.h
709 @@ -0,0 +1,580 @@
710 +/*
711 + * Register definitions for AR2315+
712 + *
713 + * This file is subject to the terms and conditions of the GNU General Public
714 + * License. See the file "COPYING" in the main directory of this archive
715 + * for more details.
716 + *
717 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
718 + * Copyright (C) 2006 FON Technology, SL.
719 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
720 + * Copyright (C) 2006-2008 Felix Fietkau <nbd@openwrt.org>
721 + */
722 +
723 +#ifndef __AR2315_REG_H
724 +#define __AR2315_REG_H
725 +
726 +/*
727 + * IRQs
728 + */
729 +#define AR2315_IRQ_MISC_INTRS MIPS_CPU_IRQ_BASE+2 /* C0_CAUSE: 0x0400 */
730 +#define AR2315_IRQ_WLAN0_INTRS MIPS_CPU_IRQ_BASE+3 /* C0_CAUSE: 0x0800 */
731 +#define AR2315_IRQ_ENET0_INTRS MIPS_CPU_IRQ_BASE+4 /* C0_CAUSE: 0x1000 */
732 +#define AR2315_IRQ_LCBUS_PCI MIPS_CPU_IRQ_BASE+5 /* C0_CAUSE: 0x2000 */
733 +#define AR2315_IRQ_WLAN0_POLL MIPS_CPU_IRQ_BASE+6 /* C0_CAUSE: 0x4000 */
734 +
735 +/*
736 + * Address map
737 + */
738 +#define AR2315_SPI_READ 0x08000000 /* SPI FLASH */
739 +#define AR2315_WLAN0 0x10000000 /* Wireless MMR */
740 +#define AR2315_PCI 0x10100000 /* PCI MMR */
741 +#define AR2315_SDRAMCTL 0x10300000 /* SDRAM MMR */
742 +#define AR2315_LOCAL 0x10400000 /* LOCAL BUS MMR */
743 +#define AR2315_ENET0 0x10500000 /* ETHERNET MMR */
744 +#define AR2315_DSLBASE 0x11000000 /* RESET CONTROL MMR */
745 +#define AR2315_UART0 0x11100003 /* UART MMR */
746 +#define AR2315_SPI 0x11300000 /* SPI FLASH MMR */
747 +#define AR2315_PCIEXT 0x80000000 /* pci external */
748 +
749 +/*
750 + * Reset Register
751 + */
752 +#define AR2315_COLD_RESET (AR2315_DSLBASE + 0x0000)
753 +
754 +#define AR2315_RESET_COLD_AHB 0x00000001
755 +#define AR2315_RESET_COLD_APB 0x00000002
756 +#define AR2315_RESET_COLD_CPU 0x00000004
757 +#define AR2315_RESET_COLD_CPUWARM 0x00000008
758 +#define AR2315_RESET_SYSTEM (RESET_COLD_CPU | RESET_COLD_APB | RESET_COLD_AHB) /* full system */
759 +#define AR2317_RESET_SYSTEM 0x00000010
760 +
761 +
762 +#define AR2315_RESET (AR2315_DSLBASE + 0x0004)
763 +
764 +#define AR2315_RESET_WARM_WLAN0_MAC 0x00000001 /* warm reset WLAN0 MAC */
765 +#define AR2315_RESET_WARM_WLAN0_BB 0x00000002 /* warm reset WLAN0 BaseBand */
766 +#define AR2315_RESET_MPEGTS_RSVD 0x00000004 /* warm reset MPEG-TS */
767 +#define AR2315_RESET_PCIDMA 0x00000008 /* warm reset PCI ahb/dma */
768 +#define AR2315_RESET_MEMCTL 0x00000010 /* warm reset memory controller */
769 +#define AR2315_RESET_LOCAL 0x00000020 /* warm reset local bus */
770 +#define AR2315_RESET_I2C_RSVD 0x00000040 /* warm reset I2C bus */
771 +#define AR2315_RESET_SPI 0x00000080 /* warm reset SPI interface */
772 +#define AR2315_RESET_UART0 0x00000100 /* warm reset UART0 */
773 +#define AR2315_RESET_IR_RSVD 0x00000200 /* warm reset IR interface */
774 +#define AR2315_RESET_EPHY0 0x00000400 /* cold reset ENET0 phy */
775 +#define AR2315_RESET_ENET0 0x00000800 /* cold reset ENET0 mac */
776 +
777 +/*
778 + * AHB master arbitration control
779 + */
780 +#define AR2315_AHB_ARB_CTL (AR2315_DSLBASE + 0x0008)
781 +
782 +#define AR2315_ARB_CPU 0x00000001 /* CPU, default */
783 +#define AR2315_ARB_WLAN 0x00000002 /* WLAN */
784 +#define AR2315_ARB_MPEGTS_RSVD 0x00000004 /* MPEG-TS */
785 +#define AR2315_ARB_LOCAL 0x00000008 /* LOCAL */
786 +#define AR2315_ARB_PCI 0x00000010 /* PCI */
787 +#define AR2315_ARB_ETHERNET 0x00000020 /* Ethernet */
788 +#define AR2315_ARB_RETRY 0x00000100 /* retry policy, debug only */
789 +
790 +/*
791 + * Config Register
792 + */
793 +#define AR2315_ENDIAN_CTL (AR2315_DSLBASE + 0x000c)
794 +
795 +#define AR2315_CONFIG_AHB 0x00000001 /* EC - AHB bridge endianess */
796 +#define AR2315_CONFIG_WLAN 0x00000002 /* WLAN byteswap */
797 +#define AR2315_CONFIG_MPEGTS_RSVD 0x00000004 /* MPEG-TS byteswap */
798 +#define AR2315_CONFIG_PCI 0x00000008 /* PCI byteswap */
799 +#define AR2315_CONFIG_MEMCTL 0x00000010 /* Memory controller endianess */
800 +#define AR2315_CONFIG_LOCAL 0x00000020 /* Local bus byteswap */
801 +#define AR2315_CONFIG_ETHERNET 0x00000040 /* Ethernet byteswap */
802 +
803 +#define AR2315_CONFIG_MERGE 0x00000200 /* CPU write buffer merge */
804 +#define AR2315_CONFIG_CPU 0x00000400 /* CPU big endian */
805 +#define AR2315_CONFIG_PCIAHB 0x00000800
806 +#define AR2315_CONFIG_PCIAHB_BRIDGE 0x00001000
807 +#define AR2315_CONFIG_SPI 0x00008000 /* SPI byteswap */
808 +#define AR2315_CONFIG_CPU_DRAM 0x00010000
809 +#define AR2315_CONFIG_CPU_PCI 0x00020000
810 +#define AR2315_CONFIG_CPU_MMR 0x00040000
811 +#define AR2315_CONFIG_BIG 0x00000400
812 +
813 +
814 +/*
815 + * NMI control
816 + */
817 +#define AR2315_NMI_CTL (AR2315_DSLBASE + 0x0010)
818 +
819 +#define AR2315_NMI_EN 1
820 +
821 +/*
822 + * Revision Register - Initial value is 0x3010 (WMAC 3.0, AR531X 1.0).
823 + */
824 +#define AR2315_SREV (AR2315_DSLBASE + 0x0014)
825 +
826 +#define AR2315_REV_MAJ 0x00f0
827 +#define AR2315_REV_MAJ_S 4
828 +#define AR2315_REV_MIN 0x000f
829 +#define AR2315_REV_MIN_S 0
830 +#define AR2315_REV_CHIP (AR2315_REV_MAJ|AR2315_REV_MIN)
831 +
832 +/*
833 + * Interface Enable
834 + */
835 +#define AR2315_IF_CTL (AR2315_DSLBASE + 0x0018)
836 +
837 +#define AR2315_IF_MASK 0x00000007
838 +#define AR2315_IF_DISABLED 0
839 +#define AR2315_IF_PCI 1
840 +#define AR2315_IF_TS_LOCAL 2
841 +#define AR2315_IF_ALL 3 /* only for emulation with separate pins */
842 +#define AR2315_IF_LOCAL_HOST 0x00000008
843 +#define AR2315_IF_PCI_HOST 0x00000010
844 +#define AR2315_IF_PCI_INTR 0x00000020
845 +#define AR2315_IF_PCI_CLK_MASK 0x00030000
846 +#define AR2315_IF_PCI_CLK_INPUT 0
847 +#define AR2315_IF_PCI_CLK_OUTPUT_LOW 1
848 +#define AR2315_IF_PCI_CLK_OUTPUT_CLK 2
849 +#define AR2315_IF_PCI_CLK_OUTPUT_HIGH 3
850 +#define AR2315_IF_PCI_CLK_SHIFT 16
851 +
852 +/*
853 + * APB Interrupt control
854 + */
855 +
856 +#define AR2315_ISR (AR2315_DSLBASE + 0x0020)
857 +#define AR2315_IMR (AR2315_DSLBASE + 0x0024)
858 +#define AR2315_GISR (AR2315_DSLBASE + 0x0028)
859 +
860 +#define AR2315_ISR_UART0 0x0001 /* high speed UART */
861 +#define AR2315_ISR_I2C_RSVD 0x0002 /* I2C bus */
862 +#define AR2315_ISR_SPI 0x0004 /* SPI bus */
863 +#define AR2315_ISR_AHB 0x0008 /* AHB error */
864 +#define AR2315_ISR_APB 0x0010 /* APB error */
865 +#define AR2315_ISR_TIMER 0x0020 /* timer */
866 +#define AR2315_ISR_GPIO 0x0040 /* GPIO */
867 +#define AR2315_ISR_WD 0x0080 /* watchdog */
868 +#define AR2315_ISR_IR_RSVD 0x0100 /* IR */
869 +
870 +#define AR2315_GISR_MISC 0x0001
871 +#define AR2315_GISR_WLAN0 0x0002
872 +#define AR2315_GISR_MPEGTS_RSVD 0x0004
873 +#define AR2315_GISR_LOCALPCI 0x0008
874 +#define AR2315_GISR_WMACPOLL 0x0010
875 +#define AR2315_GISR_TIMER 0x0020
876 +#define AR2315_GISR_ETHERNET 0x0040
877 +
878 +/*
879 + * Interrupt routing from IO to the processor IP bits
880 + * Define our inter mask and level
881 + */
882 +#define AR2315_INTR_MISCIO SR_IBIT3
883 +#define AR2315_INTR_WLAN0 SR_IBIT4
884 +#define AR2315_INTR_ENET0 SR_IBIT5
885 +#define AR2315_INTR_LOCALPCI SR_IBIT6
886 +#define AR2315_INTR_WMACPOLL SR_IBIT7
887 +#define AR2315_INTR_COMPARE SR_IBIT8
888 +
889 +/*
890 + * Timers
891 + */
892 +#define AR2315_TIMER (AR2315_DSLBASE + 0x0030)
893 +#define AR2315_RELOAD (AR2315_DSLBASE + 0x0034)
894 +#define AR2315_WD (AR2315_DSLBASE + 0x0038)
895 +#define AR2315_WDC (AR2315_DSLBASE + 0x003c)
896 +
897 +#define AR2315_WDC_IGNORE_EXPIRATION 0x00000000
898 +#define AR2315_WDC_NMI 0x00000001 /* NMI on watchdog */
899 +#define AR2315_WDC_RESET 0x00000002 /* reset on watchdog */
900 +
901 +/*
902 + * CPU Performance Counters
903 + */
904 +#define AR2315_PERFCNT0 (AR2315_DSLBASE + 0x0048)
905 +#define AR2315_PERFCNT1 (AR2315_DSLBASE + 0x004c)
906 +
907 +#define AR2315_PERF0_DATAHIT 0x0001 /* Count Data Cache Hits */
908 +#define AR2315_PERF0_DATAMISS 0x0002 /* Count Data Cache Misses */
909 +#define AR2315_PERF0_INSTHIT 0x0004 /* Count Instruction Cache Hits */
910 +#define AR2315_PERF0_INSTMISS 0x0008 /* Count Instruction Cache Misses */
911 +#define AR2315_PERF0_ACTIVE 0x0010 /* Count Active Processor Cycles */
912 +#define AR2315_PERF0_WBHIT 0x0020 /* Count CPU Write Buffer Hits */
913 +#define AR2315_PERF0_WBMISS 0x0040 /* Count CPU Write Buffer Misses */
914 +
915 +#define AR2315_PERF1_EB_ARDY 0x0001 /* Count EB_ARdy signal */
916 +#define AR2315_PERF1_EB_AVALID 0x0002 /* Count EB_AValid signal */
917 +#define AR2315_PERF1_EB_WDRDY 0x0004 /* Count EB_WDRdy signal */
918 +#define AR2315_PERF1_EB_RDVAL 0x0008 /* Count EB_RdVal signal */
919 +#define AR2315_PERF1_VRADDR 0x0010 /* Count valid read address cycles */
920 +#define AR2315_PERF1_VWADDR 0x0020 /* Count valid write address cycles */
921 +#define AR2315_PERF1_VWDATA 0x0040 /* Count valid write data cycles */
922 +
923 +/*
924 + * AHB Error Reporting.
925 + */
926 +#define AR2315_AHB_ERR0 (AR2315_DSLBASE + 0x0050) /* error */
927 +#define AR2315_AHB_ERR1 (AR2315_DSLBASE + 0x0054) /* haddr */
928 +#define AR2315_AHB_ERR2 (AR2315_DSLBASE + 0x0058) /* hwdata */
929 +#define AR2315_AHB_ERR3 (AR2315_DSLBASE + 0x005c) /* hrdata */
930 +#define AR2315_AHB_ERR4 (AR2315_DSLBASE + 0x0060) /* status */
931 +
932 +#define AHB_ERROR_DET 1 /* AHB Error has been detected, */
933 + /* write 1 to clear all bits in ERR0 */
934 +#define AHB_ERROR_OVR 2 /* AHB Error overflow has been detected */
935 +#define AHB_ERROR_WDT 4 /* AHB Error due to wdt instead of hresp */
936 +
937 +#define AR2315_PROCERR_HMAST 0x0000000f
938 +#define AR2315_PROCERR_HMAST_DFLT 0
939 +#define AR2315_PROCERR_HMAST_WMAC 1
940 +#define AR2315_PROCERR_HMAST_ENET 2
941 +#define AR2315_PROCERR_HMAST_PCIENDPT 3
942 +#define AR2315_PROCERR_HMAST_LOCAL 4
943 +#define AR2315_PROCERR_HMAST_CPU 5
944 +#define AR2315_PROCERR_HMAST_PCITGT 6
945 +
946 +#define AR2315_PROCERR_HMAST_S 0
947 +#define AR2315_PROCERR_HWRITE 0x00000010
948 +#define AR2315_PROCERR_HSIZE 0x00000060
949 +#define AR2315_PROCERR_HSIZE_S 5
950 +#define AR2315_PROCERR_HTRANS 0x00000180
951 +#define AR2315_PROCERR_HTRANS_S 7
952 +#define AR2315_PROCERR_HBURST 0x00000e00
953 +#define AR2315_PROCERR_HBURST_S 9
954 +
955 +/*
956 + * Clock Control
957 + */
958 +#define AR2315_PLLC_CTL (AR2315_DSLBASE + 0x0064)
959 +#define AR2315_PLLV_CTL (AR2315_DSLBASE + 0x0068)
960 +#define AR2315_CPUCLK (AR2315_DSLBASE + 0x006c)
961 +#define AR2315_AMBACLK (AR2315_DSLBASE + 0x0070)
962 +#define AR2315_SYNCCLK (AR2315_DSLBASE + 0x0074)
963 +#define AR2315_DSL_SLEEP_CTL (AR2315_DSLBASE + 0x0080)
964 +#define AR2315_DSL_SLEEP_DUR (AR2315_DSLBASE + 0x0084)
965 +
966 +/* PLLc Control fields */
967 +#define PLLC_REF_DIV_M 0x00000003
968 +#define PLLC_REF_DIV_S 0
969 +#define PLLC_FDBACK_DIV_M 0x0000007C
970 +#define PLLC_FDBACK_DIV_S 2
971 +#define PLLC_ADD_FDBACK_DIV_M 0x00000080
972 +#define PLLC_ADD_FDBACK_DIV_S 7
973 +#define PLLC_CLKC_DIV_M 0x0001c000
974 +#define PLLC_CLKC_DIV_S 14
975 +#define PLLC_CLKM_DIV_M 0x00700000
976 +#define PLLC_CLKM_DIV_S 20
977 +
978 +/* CPU CLK Control fields */
979 +#define CPUCLK_CLK_SEL_M 0x00000003
980 +#define CPUCLK_CLK_SEL_S 0
981 +#define CPUCLK_CLK_DIV_M 0x0000000c
982 +#define CPUCLK_CLK_DIV_S 2
983 +
984 +/* AMBA CLK Control fields */
985 +#define AMBACLK_CLK_SEL_M 0x00000003
986 +#define AMBACLK_CLK_SEL_S 0
987 +#define AMBACLK_CLK_DIV_M 0x0000000c
988 +#define AMBACLK_CLK_DIV_S 2
989 +
990 +/*
991 + * GPIO
992 + */
993 +#define AR2315_GPIO_DI (AR2315_DSLBASE + 0x0088)
994 +#define AR2315_GPIO_DO (AR2315_DSLBASE + 0x0090)
995 +#define AR2315_GPIO_CR (AR2315_DSLBASE + 0x0098)
996 +#define AR2315_GPIO_INT (AR2315_DSLBASE + 0x00a0)
997 +
998 +#define AR2315_GPIO_CR_M(x) (1 << (x)) /* mask for i/o */
999 +#define AR2315_GPIO_CR_O(x) (1 << (x)) /* output */
1000 +#define AR2315_GPIO_CR_I(x) (0) /* input */
1001 +
1002 +#define AR2315_GPIO_INT_S(x) (x) /* interrupt enable */
1003 +#define AR2315_GPIO_INT_M (0x3F) /* mask for int */
1004 +#define AR2315_GPIO_INT_LVL(x) ((x) << 6) /* interrupt level */
1005 +#define AR2315_GPIO_INT_LVL_M ((0x3) << 6) /* mask for int level */
1006 +
1007 +#define AR2315_GPIO_INT_MAX_Y 1 /* Maximum value of Y for AR5313_GPIO_INT_* macros */
1008 +#define AR2315_GPIO_INT_LVL_OFF 0 /* Triggerring off */
1009 +#define AR2315_GPIO_INT_LVL_LOW 1 /* Low Level Triggered */
1010 +#define AR2315_GPIO_INT_LVL_HIGH 2 /* High Level Triggered */
1011 +#define AR2315_GPIO_INT_LVL_EDGE 3 /* Edge Triggered */
1012 +
1013 +#define AR2315_RESET_GPIO 5
1014 +#define AR2315_NUM_GPIO 22
1015 +
1016 +/*
1017 + * PCI Clock Control
1018 + */
1019 +#define AR2315_PCICLK (AR2315_DSLBASE + 0x00a4)
1020 +
1021 +#define AR2315_PCICLK_INPUT_M 0x3
1022 +#define AR2315_PCICLK_INPUT_S 0
1023 +
1024 +#define AR2315_PCICLK_PLLC_CLKM 0
1025 +#define AR2315_PCICLK_PLLC_CLKM1 1
1026 +#define AR2315_PCICLK_PLLC_CLKC 2
1027 +#define AR2315_PCICLK_REF_CLK 3
1028 +
1029 +#define AR2315_PCICLK_DIV_M 0xc
1030 +#define AR2315_PCICLK_DIV_S 2
1031 +
1032 +#define AR2315_PCICLK_IN_FREQ 0
1033 +#define AR2315_PCICLK_IN_FREQ_DIV_6 1
1034 +#define AR2315_PCICLK_IN_FREQ_DIV_8 2
1035 +#define AR2315_PCICLK_IN_FREQ_DIV_10 3
1036 +
1037 +/*
1038 + * Observation Control Register
1039 + */
1040 +#define AR2315_OCR (AR2315_DSLBASE + 0x00b0)
1041 +#define OCR_GPIO0_IRIN 0x0040
1042 +#define OCR_GPIO1_IROUT 0x0080
1043 +#define OCR_GPIO3_RXCLR 0x0200
1044 +
1045 +/*
1046 + * General Clock Control
1047 + */
1048 +
1049 +#define AR2315_MISCCLK (AR2315_DSLBASE + 0x00b4)
1050 +#define MISCCLK_PLLBYPASS_EN 0x00000001
1051 +#define MISCCLK_PROCREFCLK 0x00000002
1052 +
1053 +/*
1054 + * SDRAM Controller
1055 + * - No read or write buffers are included.
1056 + */
1057 +#define AR2315_MEM_CFG (AR2315_SDRAMCTL + 0x00)
1058 +#define AR2315_MEM_CTRL (AR2315_SDRAMCTL + 0x0c)
1059 +#define AR2315_MEM_REF (AR2315_SDRAMCTL + 0x10)
1060 +
1061 +#define SDRAM_DATA_WIDTH_M 0x00006000
1062 +#define SDRAM_DATA_WIDTH_S 13
1063 +
1064 +#define SDRAM_COL_WIDTH_M 0x00001E00
1065 +#define SDRAM_COL_WIDTH_S 9
1066 +
1067 +#define SDRAM_ROW_WIDTH_M 0x000001E0
1068 +#define SDRAM_ROW_WIDTH_S 5
1069 +
1070 +#define SDRAM_BANKADDR_BITS_M 0x00000018
1071 +#define SDRAM_BANKADDR_BITS_S 3
1072 +
1073 +/*
1074 + * SPI Flash Interface Registers
1075 + */
1076 +
1077 +#define AR2315_SPI_CTL (AR2315_SPI + 0x00)
1078 +#define AR2315_SPI_OPCODE (AR2315_SPI + 0x04)
1079 +#define AR2315_SPI_DATA (AR2315_SPI + 0x08)
1080 +
1081 +#define SPI_CTL_START 0x00000100
1082 +#define SPI_CTL_BUSY 0x00010000
1083 +#define SPI_CTL_TXCNT_MASK 0x0000000f
1084 +#define SPI_CTL_RXCNT_MASK 0x000000f0
1085 +#define SPI_CTL_TX_RX_CNT_MASK 0x000000ff
1086 +#define SPI_CTL_SIZE_MASK 0x00060000
1087 +
1088 +#define SPI_CTL_CLK_SEL_MASK 0x03000000
1089 +#define SPI_OPCODE_MASK 0x000000ff
1090 +
1091 +/*
1092 + * PCI Bus Interface Registers
1093 + */
1094 +#define AR2315_PCI_1MS_REG (AR2315_PCI + 0x0008)
1095 +#define AR2315_PCI_1MS_MASK 0x3FFFF /* # of AHB clk cycles in 1ms */
1096 +
1097 +#define AR2315_PCI_MISC_CONFIG (AR2315_PCI + 0x000c)
1098 +#define AR2315_PCIMISC_TXD_EN 0x00000001 /* Enable TXD for fragments */
1099 +#define AR2315_PCIMISC_CFG_SEL 0x00000002 /* mem or config cycles */
1100 +#define AR2315_PCIMISC_GIG_MASK 0x0000000C /* bits 31-30 for pci req */
1101 +#define AR2315_PCIMISC_RST_MODE 0x00000030
1102 +#define AR2315_PCIRST_INPUT 0x00000000 /* 4:5=0 rst is input */
1103 +#define AR2315_PCIRST_LOW 0x00000010 /* 4:5=1 rst to GND */
1104 +#define AR2315_PCIRST_HIGH 0x00000020 /* 4:5=2 rst to VDD */
1105 +#define AR2315_PCIGRANT_EN 0x00000000 /* 6:7=0 early grant en */
1106 +#define AR2315_PCIGRANT_FRAME 0x00000040 /* 6:7=1 grant waits 4 frame */
1107 +#define AR2315_PCIGRANT_IDLE 0x00000080 /* 6:7=2 grant waits 4 idle */
1108 +#define AR2315_PCIGRANT_GAP 0x00000000 /* 6:7=2 grant waits 4 idle */
1109 +#define AR2315_PCICACHE_DIS 0x00001000 /* PCI external access cache disable */
1110 +
1111 +#define AR2315_PCI_OUT_TSTAMP (AR2315_PCI + 0x0010)
1112 +
1113 +#define AR2315_PCI_UNCACHE_CFG (AR2315_PCI + 0x0014)
1114 +
1115 +#define AR2315_PCI_IN_EN (AR2315_PCI + 0x0100)
1116 +#define AR2315_PCI_IN_EN0 0x01 /* Enable chain 0 */
1117 +#define AR2315_PCI_IN_EN1 0x02 /* Enable chain 1 */
1118 +#define AR2315_PCI_IN_EN2 0x04 /* Enable chain 2 */
1119 +#define AR2315_PCI_IN_EN3 0x08 /* Enable chain 3 */
1120 +
1121 +#define AR2315_PCI_IN_DIS (AR2315_PCI + 0x0104)
1122 +#define AR2315_PCI_IN_DIS0 0x01 /* Disable chain 0 */
1123 +#define AR2315_PCI_IN_DIS1 0x02 /* Disable chain 1 */
1124 +#define AR2315_PCI_IN_DIS2 0x04 /* Disable chain 2 */
1125 +#define AR2315_PCI_IN_DIS3 0x08 /* Disable chain 3 */
1126 +
1127 +#define AR2315_PCI_IN_PTR (AR2315_PCI + 0x0200)
1128 +
1129 +#define AR2315_PCI_OUT_EN (AR2315_PCI + 0x0400)
1130 +#define AR2315_PCI_OUT_EN0 0x01 /* Enable chain 0 */
1131 +
1132 +#define AR2315_PCI_OUT_DIS (AR2315_PCI + 0x0404)
1133 +#define AR2315_PCI_OUT_DIS0 0x01 /* Disable chain 0 */
1134 +
1135 +#define AR2315_PCI_OUT_PTR (AR2315_PCI + 0x0408)
1136 +
1137 +#define AR2315_PCI_INT_STATUS (AR2315_PCI + 0x0500) /* write one to clr */
1138 +#define AR2315_PCI_TXINT 0x00000001 /* Desc In Completed */
1139 +#define AR2315_PCI_TXOK 0x00000002 /* Desc In OK */
1140 +#define AR2315_PCI_TXERR 0x00000004 /* Desc In ERR */
1141 +#define AR2315_PCI_TXEOL 0x00000008 /* Desc In End-of-List */
1142 +#define AR2315_PCI_RXINT 0x00000010 /* Desc Out Completed */
1143 +#define AR2315_PCI_RXOK 0x00000020 /* Desc Out OK */
1144 +#define AR2315_PCI_RXERR 0x00000040 /* Desc Out ERR */
1145 +#define AR2315_PCI_RXEOL 0x00000080 /* Desc Out EOL */
1146 +#define AR2315_PCI_TXOOD 0x00000200 /* Desc In Out-of-Desc */
1147 +#define AR2315_PCI_MASK 0x0000FFFF /* Desc Mask */
1148 +#define AR2315_PCI_EXT_INT 0x02000000
1149 +#define AR2315_PCI_ABORT_INT 0x04000000
1150 +
1151 +#define AR2315_PCI_INT_MASK (AR2315_PCI + 0x0504) /* same as INT_STATUS */
1152 +
1153 +#define AR2315_PCI_INTEN_REG (AR2315_PCI + 0x0508)
1154 +#define AR2315_PCI_INT_DISABLE 0x00 /* disable pci interrupts */
1155 +#define AR2315_PCI_INT_ENABLE 0x01 /* enable pci interrupts */
1156 +
1157 +#define AR2315_PCI_HOST_IN_EN (AR2315_PCI + 0x0800)
1158 +#define AR2315_PCI_HOST_IN_DIS (AR2315_PCI + 0x0804)
1159 +#define AR2315_PCI_HOST_IN_PTR (AR2315_PCI + 0x0810)
1160 +#define AR2315_PCI_HOST_OUT_EN (AR2315_PCI + 0x0900)
1161 +#define AR2315_PCI_HOST_OUT_DIS (AR2315_PCI + 0x0904)
1162 +#define AR2315_PCI_HOST_OUT_PTR (AR2315_PCI + 0x0908)
1163 +
1164 +
1165 +/*
1166 + * Local Bus Interface Registers
1167 + */
1168 +#define AR2315_LB_CONFIG (AR2315_LOCAL + 0x0000)
1169 +#define AR2315_LBCONF_OE 0x00000001 /* =1 OE is low-true */
1170 +#define AR2315_LBCONF_CS0 0x00000002 /* =1 first CS is low-true */
1171 +#define AR2315_LBCONF_CS1 0x00000004 /* =1 2nd CS is low-true */
1172 +#define AR2315_LBCONF_RDY 0x00000008 /* =1 RDY is low-true */
1173 +#define AR2315_LBCONF_WE 0x00000010 /* =1 Write En is low-true */
1174 +#define AR2315_LBCONF_WAIT 0x00000020 /* =1 WAIT is low-true */
1175 +#define AR2315_LBCONF_ADS 0x00000040 /* =1 Adr Strobe is low-true */
1176 +#define AR2315_LBCONF_MOT 0x00000080 /* =0 Intel, =1 Motorola */
1177 +#define AR2315_LBCONF_8CS 0x00000100 /* =1 8 bits CS, 0= 16bits */
1178 +#define AR2315_LBCONF_8DS 0x00000200 /* =1 8 bits Data S, 0=16bits */
1179 +#define AR2315_LBCONF_ADS_EN 0x00000400 /* =1 Enable ADS */
1180 +#define AR2315_LBCONF_ADR_OE 0x00000800 /* =1 Adr cap on OE, WE or DS */
1181 +#define AR2315_LBCONF_ADDT_MUX 0x00001000 /* =1 Adr and Data share bus */
1182 +#define AR2315_LBCONF_DATA_OE 0x00002000 /* =1 Data cap on OE, WE, DS */
1183 +#define AR2315_LBCONF_16DATA 0x00004000 /* =1 Data is 16 bits wide */
1184 +#define AR2315_LBCONF_SWAPDT 0x00008000 /* =1 Byte swap data */
1185 +#define AR2315_LBCONF_SYNC 0x00010000 /* =1 Bus synchronous to clk */
1186 +#define AR2315_LBCONF_INT 0x00020000 /* =1 Intr is low true */
1187 +#define AR2315_LBCONF_INT_CTR0 0x00000000 /* GND high-Z, Vdd is high-Z */
1188 +#define AR2315_LBCONF_INT_CTR1 0x00040000 /* GND drive, Vdd is high-Z */
1189 +#define AR2315_LBCONF_INT_CTR2 0x00080000 /* GND high-Z, Vdd drive */
1190 +#define AR2315_LBCONF_INT_CTR3 0x000C0000 /* GND drive, Vdd drive */
1191 +#define AR2315_LBCONF_RDY_WAIT 0x00100000 /* =1 RDY is negative of WAIT */
1192 +#define AR2315_LBCONF_INT_PULSE 0x00200000 /* =1 Interrupt is a pulse */
1193 +#define AR2315_LBCONF_ENABLE 0x00400000 /* =1 Falcon respond to LB */
1194 +
1195 +#define AR2315_LB_CLKSEL (AR2315_LOCAL + 0x0004)
1196 +#define AR2315_LBCLK_EXT 0x0001 /* use external clk for lb */
1197 +
1198 +#define AR2315_LB_1MS (AR2315_LOCAL + 0x0008)
1199 +#define AR2315_LB1MS_MASK 0x3FFFF /* # of AHB clk cycles in 1ms */
1200 +
1201 +#define AR2315_LB_MISCCFG (AR2315_LOCAL + 0x000C)
1202 +#define AR2315_LBM_TXD_EN 0x00000001 /* Enable TXD for fragments */
1203 +#define AR2315_LBM_RX_INTEN 0x00000002 /* Enable LB ints on RX ready */
1204 +#define AR2315_LBM_MBOXWR_INTEN 0x00000004 /* Enable LB ints on mbox wr */
1205 +#define AR2315_LBM_MBOXRD_INTEN 0x00000008 /* Enable LB ints on mbox rd */
1206 +#define AR2315_LMB_DESCSWAP_EN 0x00000010 /* Byte swap desc enable */
1207 +#define AR2315_LBM_TIMEOUT_MASK 0x00FFFF80
1208 +#define AR2315_LBM_TIMEOUT_SHFT 7
1209 +#define AR2315_LBM_PORTMUX 0x07000000
1210 +
1211 +
1212 +#define AR2315_LB_RXTSOFF (AR2315_LOCAL + 0x0010)
1213 +
1214 +#define AR2315_LB_TX_CHAIN_EN (AR2315_LOCAL + 0x0100)
1215 +#define AR2315_LB_TXEN_0 0x01
1216 +#define AR2315_LB_TXEN_1 0x02
1217 +#define AR2315_LB_TXEN_2 0x04
1218 +#define AR2315_LB_TXEN_3 0x08
1219 +
1220 +#define AR2315_LB_TX_CHAIN_DIS (AR2315_LOCAL + 0x0104)
1221 +#define AR2315_LB_TX_DESC_PTR (AR2315_LOCAL + 0x0200)
1222 +
1223 +#define AR2315_LB_RX_CHAIN_EN (AR2315_LOCAL + 0x0400)
1224 +#define AR2315_LB_RXEN 0x01
1225 +
1226 +#define AR2315_LB_RX_CHAIN_DIS (AR2315_LOCAL + 0x0404)
1227 +#define AR2315_LB_RX_DESC_PTR (AR2315_LOCAL + 0x0408)
1228 +
1229 +#define AR2315_LB_INT_STATUS (AR2315_LOCAL + 0x0500)
1230 +#define AR2315_INT_TX_DESC 0x0001
1231 +#define AR2315_INT_TX_OK 0x0002
1232 +#define AR2315_INT_TX_ERR 0x0004
1233 +#define AR2315_INT_TX_EOF 0x0008
1234 +#define AR2315_INT_RX_DESC 0x0010
1235 +#define AR2315_INT_RX_OK 0x0020
1236 +#define AR2315_INT_RX_ERR 0x0040
1237 +#define AR2315_INT_RX_EOF 0x0080
1238 +#define AR2315_INT_TX_TRUNC 0x0100
1239 +#define AR2315_INT_TX_STARVE 0x0200
1240 +#define AR2315_INT_LB_TIMEOUT 0x0400
1241 +#define AR2315_INT_LB_ERR 0x0800
1242 +#define AR2315_INT_MBOX_WR 0x1000
1243 +#define AR2315_INT_MBOX_RD 0x2000
1244 +
1245 +/* Bit definitions for INT MASK are the same as INT_STATUS */
1246 +#define AR2315_LB_INT_MASK (AR2315_LOCAL + 0x0504)
1247 +
1248 +#define AR2315_LB_INT_EN (AR2315_LOCAL + 0x0508)
1249 +#define AR2315_LB_MBOX (AR2315_LOCAL + 0x0600)
1250 +
1251 +/*
1252 + * IR Interface Registers
1253 + */
1254 +#define AR2315_IR_PKTDATA (AR2315_IR + 0x0000)
1255 +
1256 +#define AR2315_IR_PKTLEN (AR2315_IR + 0x07fc) /* 0 - 63 */
1257 +
1258 +#define AR2315_IR_CONTROL (AR2315_IR + 0x0800)
1259 +#define AR2315_IRCTL_TX 0x00000000 /* use as tranmitter */
1260 +#define AR2315_IRCTL_RX 0x00000001 /* use as receiver */
1261 +#define AR2315_IRCTL_SAMPLECLK_MASK 0x00003ffe /* Sample clk divisor mask */
1262 +#define AR2315_IRCTL_SAMPLECLK_SHFT 1
1263 +#define AR2315_IRCTL_OUTPUTCLK_MASK 0x03ffc000 /* Output clk divisor mask */
1264 +#define AR2315_IRCTL_OUTPUTCLK_SHFT 14
1265 +
1266 +#define AR2315_IR_STATUS (AR2315_IR + 0x0804)
1267 +#define AR2315_IRSTS_RX 0x00000001 /* receive in progress */
1268 +#define AR2315_IRSTS_TX 0x00000002 /* transmit in progress */
1269 +
1270 +#define AR2315_IR_CONFIG (AR2315_IR + 0x0808)
1271 +#define AR2315_IRCFG_INVIN 0x00000001 /* invert input polarity */
1272 +#define AR2315_IRCFG_INVOUT 0x00000002 /* invert output polarity */
1273 +#define AR2315_IRCFG_SEQ_START_WIN_SEL 0x00000004 /* 1 => 28, 0 => 7 */
1274 +#define AR2315_IRCFG_SEQ_START_THRESH 0x000000f0 /* */
1275 +#define AR2315_IRCFG_SEQ_END_UNIT_SEL 0x00000100 /* */
1276 +#define AR2315_IRCFG_SEQ_END_UNIT_THRESH 0x00007e00 /* */
1277 +#define AR2315_IRCFG_SEQ_END_WIN_SEL 0x00008000 /* */
1278 +#define AR2315_IRCFG_SEQ_END_WIN_THRESH 0x001f0000 /* */
1279 +#define AR2315_IRCFG_NUM_BACKOFF_WORDS 0x01e00000 /* */
1280 +
1281 +#define HOST_PCI_DEV_ID 3
1282 +#define HOST_PCI_MBAR0 0x10000000
1283 +#define HOST_PCI_MBAR1 0x20000000
1284 +#define HOST_PCI_MBAR2 0x30000000
1285 +
1286 +#define HOST_PCI_SDRAM_BASEADDR HOST_PCI_MBAR1
1287 +#define PCI_DEVICE_MEM_SPACE 0x800000
1288 +
1289 +#endif /* __AR2315_REG_H */
1290 --- /dev/null
1291 +++ b/arch/mips/include/asm/mach-ar231x/ar5312_regs.h
1292 @@ -0,0 +1,232 @@
1293 +/*
1294 + * This file is subject to the terms and conditions of the GNU General Public
1295 + * License. See the file "COPYING" in the main directory of this archive
1296 + * for more details.
1297 + *
1298 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
1299 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
1300 + * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
1301 + */
1302 +
1303 +#ifndef AR5312_H
1304 +#define AR5312_H
1305 +
1306 +#include <asm/addrspace.h>
1307 +
1308 +/*
1309 + * IRQs
1310 + */
1311 +
1312 +#define AR5312_IRQ_WLAN0_INTRS MIPS_CPU_IRQ_BASE+2 /* C0_CAUSE: 0x0400 */
1313 +#define AR5312_IRQ_ENET0_INTRS MIPS_CPU_IRQ_BASE+3 /* C0_CAUSE: 0x0800 */
1314 +#define AR5312_IRQ_ENET1_INTRS MIPS_CPU_IRQ_BASE+4 /* C0_CAUSE: 0x1000 */
1315 +#define AR5312_IRQ_WLAN1_INTRS MIPS_CPU_IRQ_BASE+5 /* C0_CAUSE: 0x2000 */
1316 +#define AR5312_IRQ_MISC_INTRS MIPS_CPU_IRQ_BASE+6 /* C0_CAUSE: 0x4000 */
1317 +
1318 +
1319 +/* Address Map */
1320 +#define AR531X_WLAN0 0x18000000
1321 +#define AR531X_WLAN1 0x18500000
1322 +#define AR531X_ENET0 0x18100000
1323 +#define AR531X_ENET1 0x18200000
1324 +#define AR531X_SDRAMCTL 0x18300000
1325 +#define AR531X_FLASHCTL 0x18400000
1326 +#define AR531X_APBBASE 0x1c000000
1327 +#define AR531X_FLASH 0x1e000000
1328 +#define AR531X_UART0 0xbc000003 /* UART MMR */
1329 +
1330 +/*
1331 + * AR531X_NUM_ENET_MAC defines the number of ethernet MACs that
1332 + * should be considered available. The AR5312 supports 2 enet MACS,
1333 + * even though many reference boards only actually use 1 of them
1334 + * (i.e. Only MAC 0 is actually connected to an enet PHY or PHY switch.
1335 + * The AR2312 supports 1 enet MAC.
1336 + */
1337 +#define AR531X_NUM_ENET_MAC 2
1338 +
1339 +/*
1340 + * Need these defines to determine true number of ethernet MACs
1341 + */
1342 +#define AR5212_AR5312_REV2 0x0052 /* AR5312 WMAC (AP31) */
1343 +#define AR5212_AR5312_REV7 0x0057 /* AR5312 WMAC (AP30-040) */
1344 +#define AR5212_AR2313_REV8 0x0058 /* AR2313 WMAC (AP43-030) */
1345 +
1346 +/*
1347 + * AR531X_NUM_WMAC defines the number of Wireless MACs that\
1348 + * should be considered available.
1349 + */
1350 +#define AR531X_NUM_WMAC 2
1351 +
1352 +/* Reset/Timer Block Address Map */
1353 +#define AR531X_RESETTMR (AR531X_APBBASE + 0x3000)
1354 +#define AR531X_TIMER (AR531X_RESETTMR + 0x0000) /* countdown timer */
1355 +#define AR531X_WD_CTRL (AR531X_RESETTMR + 0x0008) /* watchdog cntrl */
1356 +#define AR531X_WD_TIMER (AR531X_RESETTMR + 0x000c) /* watchdog timer */
1357 +#define AR531X_ISR (AR531X_RESETTMR + 0x0010) /* Intr Status Reg */
1358 +#define AR531X_IMR (AR531X_RESETTMR + 0x0014) /* Intr Mask Reg */
1359 +#define AR531X_RESET (AR531X_RESETTMR + 0x0020)
1360 +#define AR5312_CLOCKCTL1 (AR531X_RESETTMR + 0x0064)
1361 +#define AR5312_SCRATCH (AR531X_RESETTMR + 0x006c)
1362 +#define AR531X_PROCADDR (AR531X_RESETTMR + 0x0070)
1363 +#define AR531X_PROC1 (AR531X_RESETTMR + 0x0074)
1364 +#define AR531X_DMAADDR (AR531X_RESETTMR + 0x0078)
1365 +#define AR531X_DMA1 (AR531X_RESETTMR + 0x007c)
1366 +#define AR531X_ENABLE (AR531X_RESETTMR + 0x0080) /* interface enb */
1367 +#define AR531X_REV (AR531X_RESETTMR + 0x0090) /* revision */
1368 +
1369 +/* AR531X_WD_CTRL register bit field definitions */
1370 +#define AR531X_WD_CTRL_IGNORE_EXPIRATION 0x0000
1371 +#define AR531X_WD_CTRL_NMI 0x0001
1372 +#define AR531X_WD_CTRL_RESET 0x0002
1373 +
1374 +/* AR531X_ISR register bit field definitions */
1375 +#define AR531X_ISR_NONE 0x0000
1376 +#define AR531X_ISR_TIMER 0x0001
1377 +#define AR531X_ISR_AHBPROC 0x0002
1378 +#define AR531X_ISR_AHBDMA 0x0004
1379 +#define AR531X_ISR_GPIO 0x0008
1380 +#define AR531X_ISR_UART0 0x0010
1381 +#define AR531X_ISR_UART0DMA 0x0020
1382 +#define AR531X_ISR_WD 0x0040
1383 +#define AR531X_ISR_LOCAL 0x0080
1384 +
1385 +/* AR531X_RESET register bit field definitions */
1386 +#define AR531X_RESET_SYSTEM 0x00000001 /* cold reset full system */
1387 +#define AR531X_RESET_PROC 0x00000002 /* cold reset MIPS core */
1388 +#define AR531X_RESET_WLAN0 0x00000004 /* cold reset WLAN MAC and BB */
1389 +#define AR531X_RESET_EPHY0 0x00000008 /* cold reset ENET0 phy */
1390 +#define AR531X_RESET_EPHY1 0x00000010 /* cold reset ENET1 phy */
1391 +#define AR531X_RESET_ENET0 0x00000020 /* cold reset ENET0 mac */
1392 +#define AR531X_RESET_ENET1 0x00000040 /* cold reset ENET1 mac */
1393 +#define AR531X_RESET_UART0 0x00000100 /* cold reset UART0 (high speed) */
1394 +#define AR531X_RESET_WLAN1 0x00000200 /* cold reset WLAN MAC/BB */
1395 +#define AR531X_RESET_APB 0x00000400 /* cold reset APB (ar5312) */
1396 +#define AR531X_RESET_WARM_PROC 0x00001000 /* warm reset MIPS core */
1397 +#define AR531X_RESET_WARM_WLAN0_MAC 0x00002000 /* warm reset WLAN0 MAC */
1398 +#define AR531X_RESET_WARM_WLAN0_BB 0x00004000 /* warm reset WLAN0 BaseBand */
1399 +#define AR531X_RESET_NMI 0x00010000 /* send an NMI to the processor */
1400 +#define AR531X_RESET_WARM_WLAN1_MAC 0x00020000 /* warm reset WLAN1 mac */
1401 +#define AR531X_RESET_WARM_WLAN1_BB 0x00040000 /* warm reset WLAN1 baseband */
1402 +#define AR531X_RESET_LOCAL_BUS 0x00080000 /* reset local bus */
1403 +#define AR531X_RESET_WDOG 0x00100000 /* last reset was a watchdog */
1404 +
1405 +#define AR531X_RESET_WMAC0_BITS \
1406 + AR531X_RESET_WLAN0 |\
1407 + AR531X_RESET_WARM_WLAN0_MAC |\
1408 + AR531X_RESET_WARM_WLAN0_BB
1409 +
1410 +#define AR531X_RESERT_WMAC1_BITS \
1411 + AR531X_RESET_WLAN1 |\
1412 + AR531X_RESET_WARM_WLAN1_MAC |\
1413 + AR531X_RESET_WARM_WLAN1_BB
1414 +
1415 +/* AR5312_CLOCKCTL1 register bit field definitions */
1416 +#define AR5312_CLOCKCTL1_PREDIVIDE_MASK 0x00000030
1417 +#define AR5312_CLOCKCTL1_PREDIVIDE_SHIFT 4
1418 +#define AR5312_CLOCKCTL1_MULTIPLIER_MASK 0x00001f00
1419 +#define AR5312_CLOCKCTL1_MULTIPLIER_SHIFT 8
1420 +#define AR5312_CLOCKCTL1_DOUBLER_MASK 0x00010000
1421 +
1422 +/* Valid for AR5312 and AR2312 */
1423 +#define AR5312_CLOCKCTL1_PREDIVIDE_MASK 0x00000030
1424 +#define AR5312_CLOCKCTL1_PREDIVIDE_SHIFT 4
1425 +#define AR5312_CLOCKCTL1_MULTIPLIER_MASK 0x00001f00
1426 +#define AR5312_CLOCKCTL1_MULTIPLIER_SHIFT 8
1427 +#define AR5312_CLOCKCTL1_DOUBLER_MASK 0x00010000
1428 +
1429 +/* Valid for AR2313 */
1430 +#define AR2313_CLOCKCTL1_PREDIVIDE_MASK 0x00003000
1431 +#define AR2313_CLOCKCTL1_PREDIVIDE_SHIFT 12
1432 +#define AR2313_CLOCKCTL1_MULTIPLIER_MASK 0x001f0000
1433 +#define AR2313_CLOCKCTL1_MULTIPLIER_SHIFT 16
1434 +#define AR2313_CLOCKCTL1_DOUBLER_MASK 0x00000000
1435 +
1436 +
1437 +/* AR531X_ENABLE register bit field definitions */
1438 +#define AR531X_ENABLE_WLAN0 0x0001
1439 +#define AR531X_ENABLE_ENET0 0x0002
1440 +#define AR531X_ENABLE_ENET1 0x0004
1441 +#define AR531X_ENABLE_UART_AND_WLAN1_PIO 0x0008 /* UART, and WLAN1 PIOs */
1442 +#define AR531X_ENABLE_WLAN1_DMA 0x0010 /* WLAN1 DMAs */
1443 +#define AR531X_ENABLE_WLAN1 \
1444 + (AR531X_ENABLE_UART_AND_WLAN1_PIO | AR531X_ENABLE_WLAN1_DMA)
1445 +
1446 +/* AR531X_REV register bit field definitions */
1447 +#define AR531X_REV_WMAC_MAJ 0xf000
1448 +#define AR531X_REV_WMAC_MAJ_S 12
1449 +#define AR531X_REV_WMAC_MIN 0x0f00
1450 +#define AR531X_REV_WMAC_MIN_S 8
1451 +#define AR531X_REV_MAJ 0x00f0
1452 +#define AR531X_REV_MAJ_S 4
1453 +#define AR531X_REV_MIN 0x000f
1454 +#define AR531X_REV_MIN_S 0
1455 +#define AR531X_REV_CHIP (AR531X_REV_MAJ|AR531X_REV_MIN)
1456 +
1457 +/* Major revision numbers, bits 7..4 of Revision ID register */
1458 +#define AR531X_REV_MAJ_AR5312 0x4
1459 +#define AR531X_REV_MAJ_AR2313 0x5
1460 +
1461 +/* Minor revision numbers, bits 3..0 of Revision ID register */
1462 +#define AR5312_REV_MIN_DUAL 0x0 /* Dual WLAN version */
1463 +#define AR5312_REV_MIN_SINGLE 0x1 /* Single WLAN version */
1464 +
1465 +/* AR531X_FLASHCTL register bit field definitions */
1466 +#define FLASHCTL_IDCY 0x0000000f /* Idle cycle turn around time */
1467 +#define FLASHCTL_IDCY_S 0
1468 +#define FLASHCTL_WST1 0x000003e0 /* Wait state 1 */
1469 +#define FLASHCTL_WST1_S 5
1470 +#define FLASHCTL_RBLE 0x00000400 /* Read byte lane enable */
1471 +#define FLASHCTL_WST2 0x0000f800 /* Wait state 2 */
1472 +#define FLASHCTL_WST2_S 11
1473 +#define FLASHCTL_AC 0x00070000 /* Flash address check (added) */
1474 +#define FLASHCTL_AC_S 16
1475 +#define FLASHCTL_AC_128K 0x00000000
1476 +#define FLASHCTL_AC_256K 0x00010000
1477 +#define FLASHCTL_AC_512K 0x00020000
1478 +#define FLASHCTL_AC_1M 0x00030000
1479 +#define FLASHCTL_AC_2M 0x00040000
1480 +#define FLASHCTL_AC_4M 0x00050000
1481 +#define FLASHCTL_AC_8M 0x00060000
1482 +#define FLASHCTL_AC_RES 0x00070000 /* 16MB is not supported */
1483 +#define FLASHCTL_E 0x00080000 /* Flash bank enable (added) */
1484 +#define FLASHCTL_BUSERR 0x01000000 /* Bus transfer error status flag */
1485 +#define FLASHCTL_WPERR 0x02000000 /* Write protect error status flag */
1486 +#define FLASHCTL_WP 0x04000000 /* Write protect */
1487 +#define FLASHCTL_BM 0x08000000 /* Burst mode */
1488 +#define FLASHCTL_MW 0x30000000 /* Memory width */
1489 +#define FLASHCTL_MWx8 0x00000000 /* Memory width x8 */
1490 +#define FLASHCTL_MWx16 0x10000000 /* Memory width x16 */
1491 +#define FLASHCTL_MWx32 0x20000000 /* Memory width x32 (not supported) */
1492 +#define FLASHCTL_ATNR 0x00000000 /* Access type == no retry */
1493 +#define FLASHCTL_ATR 0x80000000 /* Access type == retry every */
1494 +#define FLASHCTL_ATR4 0xc0000000 /* Access type == retry every 4 */
1495 +
1496 +/* ARM Flash Controller -- 3 flash banks with either x8 or x16 devices. */
1497 +#define AR531X_FLASHCTL0 (AR531X_FLASHCTL + 0x00)
1498 +#define AR531X_FLASHCTL1 (AR531X_FLASHCTL + 0x04)
1499 +#define AR531X_FLASHCTL2 (AR531X_FLASHCTL + 0x08)
1500 +
1501 +/* ARM SDRAM Controller -- just enough to determine memory size */
1502 +#define AR531X_MEM_CFG1 (AR531X_SDRAMCTL + 0x04)
1503 +#define MEM_CFG1_AC0 0x00000700 /* bank 0: SDRAM addr check (added) */
1504 +#define MEM_CFG1_AC0_S 8
1505 +#define MEM_CFG1_AC1 0x00007000 /* bank 1: SDRAM addr check (added) */
1506 +#define MEM_CFG1_AC1_S 12
1507 +
1508 +/* GPIO Address Map */
1509 +#define AR531X_GPIO (AR531X_APBBASE + 0x2000)
1510 +#define AR531X_GPIO_DO (AR531X_GPIO + 0x00) /* output register */
1511 +#define AR531X_GPIO_DI (AR531X_GPIO + 0x04) /* intput register */
1512 +#define AR531X_GPIO_CR (AR531X_GPIO + 0x08) /* control register */
1513 +
1514 +/* GPIO Control Register bit field definitions */
1515 +#define AR531X_GPIO_CR_M(x) (1 << (x)) /* mask for i/o */
1516 +#define AR531X_GPIO_CR_O(x) (0 << (x)) /* mask for output */
1517 +#define AR531X_GPIO_CR_I(x) (1 << (x)) /* mask for input */
1518 +#define AR531X_GPIO_CR_INT(x) (1 << ((x)+8)) /* mask for interrupt */
1519 +#define AR531X_GPIO_CR_UART(x) (1 << ((x)+16)) /* uart multiplex */
1520 +#define AR531X_NUM_GPIO 8
1521 +
1522 +
1523 +#endif
1524 +
1525 --- /dev/null
1526 +++ b/arch/mips/ar231x/ar5312.c
1527 @@ -0,0 +1,579 @@
1528 +/*
1529 + * This file is subject to the terms and conditions of the GNU General Public
1530 + * License. See the file "COPYING" in the main directory of this archive
1531 + * for more details.
1532 + *
1533 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
1534 + * Copyright (C) 2006 FON Technology, SL.
1535 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
1536 + * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
1537 + * Copyright (C) 2012 Alexandros C. Couloumbis <alex@ozo.com>
1538 + */
1539 +
1540 +/*
1541 + * Platform devices for Atheros SoCs
1542 + */
1543 +
1544 +#include <generated/autoconf.h>
1545 +#include <linux/init.h>
1546 +#include <linux/module.h>
1547 +#include <linux/types.h>
1548 +#include <linux/string.h>
1549 +#include <linux/mtd/physmap.h>
1550 +#include <linux/platform_device.h>
1551 +#include <linux/kernel.h>
1552 +#include <linux/reboot.h>
1553 +#include <linux/leds.h>
1554 +#include <linux/gpio.h>
1555 +#include <asm/bootinfo.h>
1556 +#include <asm/reboot.h>
1557 +#include <asm/time.h>
1558 +#include <linux/irq.h>
1559 +#include <asm/io.h>
1560 +
1561 +#include <ar231x_platform.h>
1562 +#include <ar5312_regs.h>
1563 +#include <ar231x.h>
1564 +#include "devices.h"
1565 +#include "ar5312.h"
1566 +
1567 +static void
1568 +ar5312_misc_irq_dispatch(void)
1569 +{
1570 + unsigned int ar231x_misc_intrs = ar231x_read_reg(AR531X_ISR) & ar231x_read_reg(AR531X_IMR);
1571 +
1572 + if (ar231x_misc_intrs & AR531X_ISR_TIMER) {
1573 + do_IRQ(AR531X_MISC_IRQ_TIMER);
1574 + (void)ar231x_read_reg(AR531X_TIMER);
1575 + } else if (ar231x_misc_intrs & AR531X_ISR_AHBPROC)
1576 + do_IRQ(AR531X_MISC_IRQ_AHB_PROC);
1577 + else if ((ar231x_misc_intrs & AR531X_ISR_UART0))
1578 + do_IRQ(AR531X_MISC_IRQ_UART0);
1579 + else if (ar231x_misc_intrs & AR531X_ISR_WD)
1580 + do_IRQ(AR531X_MISC_IRQ_WATCHDOG);
1581 + else
1582 + do_IRQ(AR531X_MISC_IRQ_NONE);
1583 +}
1584 +
1585 +static asmlinkage void
1586 +ar5312_irq_dispatch(void)
1587 +{
1588 + int pending = read_c0_status() & read_c0_cause();
1589 +
1590 + if (pending & CAUSEF_IP2)
1591 + do_IRQ(AR5312_IRQ_WLAN0_INTRS);
1592 + else if (pending & CAUSEF_IP3)
1593 + do_IRQ(AR5312_IRQ_ENET0_INTRS);
1594 + else if (pending & CAUSEF_IP4)
1595 + do_IRQ(AR5312_IRQ_ENET1_INTRS);
1596 + else if (pending & CAUSEF_IP5)
1597 + do_IRQ(AR5312_IRQ_WLAN1_INTRS);
1598 + else if (pending & CAUSEF_IP6)
1599 + ar5312_misc_irq_dispatch();
1600 + else if (pending & CAUSEF_IP7)
1601 + do_IRQ(AR531X_IRQ_CPU_CLOCK);
1602 +}
1603 +
1604 +
1605 +/* Enable the specified AR531X_MISC_IRQ interrupt */
1606 +static void
1607 +ar5312_misc_intr_enable(struct irq_data *d)
1608 +{
1609 + unsigned int imr;
1610 +
1611 + imr = ar231x_read_reg(AR531X_IMR);
1612 + imr |= (1 << (d->irq - AR531X_MISC_IRQ_BASE - 1));
1613 + ar231x_write_reg(AR531X_IMR, imr);
1614 +}
1615 +
1616 +/* Disable the specified AR531X_MISC_IRQ interrupt */
1617 +static void
1618 +ar5312_misc_intr_disable(struct irq_data *d)
1619 +{
1620 + unsigned int imr;
1621 +
1622 + imr = ar231x_read_reg(AR531X_IMR);
1623 + imr &= ~(1 << (d->irq - AR531X_MISC_IRQ_BASE - 1));
1624 + ar231x_write_reg(AR531X_IMR, imr);
1625 + ar231x_read_reg(AR531X_IMR); /* flush write buffer */
1626 +}
1627 +
1628 +static struct irq_chip ar5312_misc_intr_controller = {
1629 + .irq_mask = ar5312_misc_intr_disable,
1630 + .irq_unmask = ar5312_misc_intr_enable,
1631 +};
1632 +
1633 +
1634 +static irqreturn_t ar5312_ahb_proc_handler(int cpl, void *dev_id)
1635 +{
1636 + u32 proc1 = ar231x_read_reg(AR531X_PROC1);
1637 + u32 procAddr = ar231x_read_reg(AR531X_PROCADDR); /* clears error state */
1638 + u32 dma1 = ar231x_read_reg(AR531X_DMA1);
1639 + u32 dmaAddr = ar231x_read_reg(AR531X_DMAADDR); /* clears error state */
1640 +
1641 + printk("AHB interrupt: PROCADDR=0x%8.8x PROC1=0x%8.8x DMAADDR=0x%8.8x DMA1=0x%8.8x\n",
1642 + procAddr, proc1, dmaAddr, dma1);
1643 +
1644 + machine_restart("AHB error"); /* Catastrophic failure */
1645 + return IRQ_HANDLED;
1646 +}
1647 +
1648 +
1649 +static struct irqaction ar5312_ahb_proc_interrupt = {
1650 + .handler = ar5312_ahb_proc_handler,
1651 + .name = "ar5312_ahb_proc_interrupt",
1652 +};
1653 +
1654 +
1655 +static struct irqaction cascade = {
1656 + .handler = no_action,
1657 + .name = "cascade",
1658 +};
1659 +
1660 +void __init ar5312_irq_init(void)
1661 +{
1662 + int i;
1663 +
1664 + if (!is_5312())
1665 + return;
1666 +
1667 + ar231x_irq_dispatch = ar5312_irq_dispatch;
1668 + for (i = 0; i < AR531X_MISC_IRQ_COUNT; i++) {
1669 + int irq = AR531X_MISC_IRQ_BASE + i;
1670 + irq_set_chip_and_handler(irq, &ar5312_misc_intr_controller,
1671 + handle_level_irq);
1672 + }
1673 + setup_irq(AR531X_MISC_IRQ_AHB_PROC, &ar5312_ahb_proc_interrupt);
1674 + setup_irq(AR5312_IRQ_MISC_INTRS, &cascade);
1675 +}
1676 +
1677 +static u32
1678 +ar5312_gpio_set_output(u32 mask, u32 val)
1679 +{
1680 + u32 reg;
1681 +
1682 + reg = ar231x_read_reg(AR531X_GPIO_CR);
1683 + reg |= mask;
1684 + reg &= ~val;
1685 + ar231x_write_reg(AR531X_GPIO_CR, reg);
1686 + return reg;
1687 +}
1688 +
1689 +static u32
1690 +ar5312_gpio_get(u32 valid_mask)
1691 +{
1692 + u32 reg;
1693 + reg = ar231x_read_reg(AR531X_GPIO_DI);
1694 + reg &= valid_mask;
1695 + return reg;
1696 +}
1697 +
1698 +static u32
1699 +ar5312_gpio_set(u32 mask, u32 value)
1700 +{
1701 + u32 reg;
1702 + reg = ar231x_read_reg(AR531X_GPIO_DO);
1703 + reg &= ~mask;
1704 + reg |= value;
1705 + ar231x_write_reg(AR531X_GPIO_DO, reg);
1706 + return reg;
1707 +}
1708 +
1709 +/*
1710 + * gpiolib implementations. Original mask based methods preserved
1711 + */
1712 +static int
1713 +ar5312_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
1714 +{
1715 + struct ar231x_gpio_chip *gpch =
1716 + container_of(chip, struct ar231x_gpio_chip, chip);
1717 + u32 mask = 1 << gpio;
1718 + u32 rett;
1719 + if (!(gpch->valid_mask & mask))
1720 + return 0;
1721 + rett = ar5312_gpio_get(gpch->valid_mask);
1722 + return !!(rett & mask);
1723 +}
1724 +
1725 +static void
1726 +ar5312_gpio_set_value(struct gpio_chip *chip, unsigned gpio, int value)
1727 +{
1728 + struct ar231x_gpio_chip *gpch =
1729 + container_of(chip, struct ar231x_gpio_chip, chip);
1730 + u32 mask = 1 << gpio;
1731 + if (!(gpch->valid_mask & mask))
1732 + return;
1733 + ar5312_gpio_set(mask, (!!value) * mask);
1734 +}
1735 +
1736 +static int
1737 +ar5312_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
1738 +{
1739 + struct ar231x_gpio_chip *gpch =
1740 + container_of(chip, struct ar231x_gpio_chip, chip);
1741 + u32 mask = 1 << gpio;
1742 + if (!(gpch->valid_mask & mask))
1743 + return -ENXIO;
1744 + ar5312_gpio_set_output(mask, 0);
1745 + return 0;
1746 +}
1747 +static int
1748 +ar5312_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, int value)
1749 +{
1750 + struct ar231x_gpio_chip *gpch =
1751 + container_of(chip, struct ar231x_gpio_chip, chip);
1752 + u32 mask = 1 << gpio;
1753 + if (!(gpch->valid_mask & mask))
1754 + return -ENXIO;
1755 + ar5312_gpio_set_output(mask, mask);
1756 + ar5312_gpio_set(mask, (!!value) * mask);
1757 + return 0;
1758 +}
1759 +
1760 +static struct ar231x_gpio_chip ar5312_gpio_chip = {
1761 + .valid_mask = (1 << 22) - 1,
1762 + .chip = {
1763 + .label = "ar5312-gpio",
1764 + .direction_input = ar5312_gpio_direction_input,
1765 + .direction_output = ar5312_gpio_direction_output,
1766 + .set = ar5312_gpio_set_value,
1767 + .get = ar5312_gpio_get_value,
1768 + .base = 0,
1769 + .ngpio = AR531X_GPIO_IRQ_COUNT, // 22
1770 + }
1771 +};
1772 +
1773 +// end of gpiolib
1774 +
1775 +static struct physmap_flash_data ar5312_flash_data = {
1776 + .width = 2,
1777 +};
1778 +
1779 +static struct resource ar5312_flash_resource = {
1780 + .start = AR531X_FLASH,
1781 + .end = AR531X_FLASH + 0x800000 - 1,
1782 + .flags = IORESOURCE_MEM,
1783 +};
1784 +
1785 +static struct ar231x_eth ar5312_eth0_data = {
1786 + .reset_base = AR531X_RESET,
1787 + .reset_mac = AR531X_RESET_ENET0,
1788 + .reset_phy = AR531X_RESET_EPHY0,
1789 + .phy_base = KSEG1ADDR(AR531X_ENET0),
1790 + .config = &ar231x_board,
1791 +};
1792 +
1793 +static struct ar231x_eth ar5312_eth1_data = {
1794 + .reset_base = AR531X_RESET,
1795 + .reset_mac = AR531X_RESET_ENET1,
1796 + .reset_phy = AR531X_RESET_EPHY1,
1797 + .phy_base = KSEG1ADDR(AR531X_ENET1),
1798 + .config = &ar231x_board,
1799 +};
1800 +
1801 +static struct platform_device ar5312_physmap_flash = {
1802 + .name = "physmap-flash",
1803 + .id = 0,
1804 + .dev.platform_data = &ar5312_flash_data,
1805 + .resource = &ar5312_flash_resource,
1806 + .num_resources = 1,
1807 +};
1808 +
1809 +#ifdef CONFIG_LEDS_GPIO
1810 +static struct gpio_led ar5312_leds[] = {
1811 + { .name = "wlan", .gpio = 0, .active_low = 1, },
1812 +};
1813 +
1814 +static const struct gpio_led_platform_data ar5312_led_data = {
1815 + .num_leds = ARRAY_SIZE(ar5312_leds),
1816 + .leds = (void *) ar5312_leds,
1817 +};
1818 +
1819 +static struct platform_device ar5312_gpio_leds = {
1820 + .name = "leds-gpio",
1821 + .id = -1,
1822 + .dev.platform_data = (void *) &ar5312_led_data,
1823 +};
1824 +#endif
1825 +
1826 +/*
1827 + * NB: This mapping size is larger than the actual flash size,
1828 + * but this shouldn't be a problem here, because the flash
1829 + * will simply be mapped multiple times.
1830 + */
1831 +static char __init *ar5312_flash_limit(void)
1832 +{
1833 + u32 ctl;
1834 + /*
1835 + * Configure flash bank 0.
1836 + * Assume 8M window size. Flash will be aliased if it's smaller
1837 + */
1838 + ctl = FLASHCTL_E |
1839 + FLASHCTL_AC_8M |
1840 + FLASHCTL_RBLE |
1841 + (0x01 << FLASHCTL_IDCY_S) |
1842 + (0x07 << FLASHCTL_WST1_S) |
1843 + (0x07 << FLASHCTL_WST2_S) |
1844 + (ar231x_read_reg(AR531X_FLASHCTL0) & FLASHCTL_MW);
1845 +
1846 + ar231x_write_reg(AR531X_FLASHCTL0, ctl);
1847 +
1848 + /* Disable other flash banks */
1849 + ar231x_write_reg(AR531X_FLASHCTL1,
1850 + ar231x_read_reg(AR531X_FLASHCTL1) & ~(FLASHCTL_E | FLASHCTL_AC));
1851 +
1852 + ar231x_write_reg(AR531X_FLASHCTL2,
1853 + ar231x_read_reg(AR531X_FLASHCTL2) & ~(FLASHCTL_E | FLASHCTL_AC));
1854 +
1855 + return (char *) KSEG1ADDR(AR531X_FLASH + 0x800000);
1856 +}
1857 +
1858 +int __init ar5312_init_devices(void)
1859 +{
1860 + struct ar231x_boarddata *config;
1861 + u32 fctl = 0;
1862 + u8 *c;
1863 +
1864 + if (!is_5312())
1865 + return 0;
1866 +
1867 + /* Locate board/radio config data */
1868 + ar231x_find_config(ar5312_flash_limit());
1869 + config = ar231x_board.config;
1870 +
1871 + /* AR2313 has CPU minor rev. 10 */
1872 + if ((current_cpu_data.processor_id & 0xff) == 0x0a)
1873 + ar231x_devtype = DEV_TYPE_AR2313;
1874 +
1875 + /* AR2312 shares the same Silicon ID as AR5312 */
1876 + else if (config->flags & BD_ISCASPER)
1877 + ar231x_devtype = DEV_TYPE_AR2312;
1878 +
1879 + /* Everything else is probably AR5312 or compatible */
1880 + else
1881 + ar231x_devtype = DEV_TYPE_AR5312;
1882 +
1883 + /* fixup flash width */
1884 + fctl = ar231x_read_reg(AR531X_FLASHCTL) & FLASHCTL_MW;
1885 + switch (fctl) {
1886 + case FLASHCTL_MWx16:
1887 + ar5312_flash_data.width = 2;
1888 + break;
1889 + case FLASHCTL_MWx8:
1890 + default:
1891 + ar5312_flash_data.width = 1;
1892 + break;
1893 + }
1894 +
1895 + platform_device_register(&ar5312_physmap_flash);
1896 +
1897 +#ifdef CONFIG_LEDS_GPIO
1898 + ar5312_leds[0].gpio = config->sysLedGpio;
1899 + platform_device_register(&ar5312_gpio_leds);
1900 +#endif
1901 +
1902 + /* Fix up MAC addresses if necessary */
1903 + if (!memcmp(config->enet0_mac, "\xff\xff\xff\xff\xff\xff", 6))
1904 + memcpy(config->enet0_mac, config->enet1_mac, 6);
1905 +
1906 + /* If ENET0 and ENET1 have the same mac address,
1907 + * increment the one from ENET1 */
1908 + if (memcmp(config->enet0_mac, config->enet1_mac, 6) == 0) {
1909 + c = config->enet1_mac + 5;
1910 + while ((c >= config->enet1_mac) && !(++(*c)))
1911 + c--;
1912 + }
1913 +
1914 + switch(ar231x_devtype) {
1915 + case DEV_TYPE_AR5312:
1916 + ar5312_eth0_data.macaddr = config->enet0_mac;
1917 + ar231x_add_ethernet(0, KSEG1ADDR(AR531X_ENET0),
1918 + AR5312_IRQ_ENET0_INTRS, &ar5312_eth0_data);
1919 +
1920 + ar5312_eth1_data.macaddr = config->enet1_mac;
1921 + ar231x_add_ethernet(1, KSEG1ADDR(AR531X_ENET1),
1922 + AR5312_IRQ_ENET1_INTRS, &ar5312_eth1_data);
1923 +
1924 + if (!ar231x_board.radio)
1925 + return 0;
1926 +
1927 + if (!(config->flags & BD_WLAN0))
1928 + break;
1929 +
1930 + ar231x_add_wmac(0, AR531X_WLAN0, AR5312_IRQ_WLAN0_INTRS);
1931 + break;
1932 + /*
1933 + * AR2312/3 ethernet uses the PHY of ENET0, but the MAC
1934 + * of ENET1. Atheros calls it 'twisted' for a reason :)
1935 + */
1936 + case DEV_TYPE_AR2312:
1937 + case DEV_TYPE_AR2313:
1938 + ar5312_eth1_data.phy_base = ar5312_eth0_data.phy_base;
1939 + ar5312_eth1_data.reset_phy = ar5312_eth0_data.reset_phy;
1940 + ar5312_eth1_data.macaddr = config->enet0_mac;
1941 + ar231x_add_ethernet(0, KSEG1ADDR(AR531X_ENET1),
1942 + AR5312_IRQ_ENET1_INTRS, &ar5312_eth1_data);
1943 +
1944 + if (!ar231x_board.radio)
1945 + return 0;
1946 + break;
1947 + default:
1948 + break;
1949 + }
1950 +
1951 + if (config->flags & BD_WLAN1)
1952 + ar231x_add_wmac(1, AR531X_WLAN1, AR5312_IRQ_WLAN1_INTRS);
1953 +
1954 + return 0;
1955 +}
1956 +
1957 +
1958 +static void ar5312_restart(char *command)
1959 +{
1960 + /* reset the system */
1961 + local_irq_disable();
1962 + while(1) {
1963 + ar231x_write_reg(AR531X_RESET, AR531X_RESET_SYSTEM);
1964 + }
1965 +}
1966 +
1967 +
1968 +/*
1969 + * This table is indexed by bits 5..4 of the CLOCKCTL1 register
1970 + * to determine the predevisor value.
1971 + */
1972 +static int __initdata CLOCKCTL1_PREDIVIDE_TABLE[4] = { 1, 2, 4, 5 };
1973 +
1974 +
1975 +static int __init
1976 +ar5312_cpu_frequency(void)
1977 +{
1978 + unsigned int result;
1979 + unsigned int predivide_mask, predivide_shift;
1980 + unsigned int multiplier_mask, multiplier_shift;
1981 + unsigned int clockCtl1, preDivideSelect, preDivisor, multiplier;
1982 + unsigned int doubler_mask;
1983 + u16 devid;
1984 +
1985 + /* Trust the bootrom's idea of cpu frequency. */
1986 + if ((result = ar231x_read_reg(AR5312_SCRATCH)))
1987 + return result;
1988 +
1989 + devid = ar231x_read_reg(AR531X_REV);
1990 + devid &= AR531X_REV_MAJ;
1991 + devid >>= AR531X_REV_MAJ_S;
1992 + if (devid == AR531X_REV_MAJ_AR2313) {
1993 + predivide_mask = AR2313_CLOCKCTL1_PREDIVIDE_MASK;
1994 + predivide_shift = AR2313_CLOCKCTL1_PREDIVIDE_SHIFT;
1995 + multiplier_mask = AR2313_CLOCKCTL1_MULTIPLIER_MASK;
1996 + multiplier_shift = AR2313_CLOCKCTL1_MULTIPLIER_SHIFT;
1997 + doubler_mask = AR2313_CLOCKCTL1_DOUBLER_MASK;
1998 + } else { /* AR5312 and AR2312 */
1999 + predivide_mask = AR5312_CLOCKCTL1_PREDIVIDE_MASK;
2000 + predivide_shift = AR5312_CLOCKCTL1_PREDIVIDE_SHIFT;
2001 + multiplier_mask = AR5312_CLOCKCTL1_MULTIPLIER_MASK;
2002 + multiplier_shift = AR5312_CLOCKCTL1_MULTIPLIER_SHIFT;
2003 + doubler_mask = AR5312_CLOCKCTL1_DOUBLER_MASK;
2004 + }
2005 +
2006 + /*
2007 + * Clocking is derived from a fixed 40MHz input clock.
2008 + *
2009 + * cpuFreq = InputClock * MULT (where MULT is PLL multiplier)
2010 + * sysFreq = cpuFreq / 4 (used for APB clock, serial,
2011 + * flash, Timer, Watchdog Timer)
2012 + *
2013 + * cntFreq = cpuFreq / 2 (use for CPU count/compare)
2014 + *
2015 + * So, for example, with a PLL multiplier of 5, we have
2016 + *
2017 + * cpuFreq = 200MHz
2018 + * sysFreq = 50MHz
2019 + * cntFreq = 100MHz
2020 + *
2021 + * We compute the CPU frequency, based on PLL settings.
2022 + */
2023 +
2024 + clockCtl1 = ar231x_read_reg(AR5312_CLOCKCTL1);
2025 + preDivideSelect = (clockCtl1 & predivide_mask) >> predivide_shift;
2026 + preDivisor = CLOCKCTL1_PREDIVIDE_TABLE[preDivideSelect];
2027 + multiplier = (clockCtl1 & multiplier_mask) >> multiplier_shift;
2028 +
2029 + if (clockCtl1 & doubler_mask) {
2030 + multiplier = multiplier << 1;
2031 + }
2032 + return (40000000 / preDivisor) * multiplier;
2033 +}
2034 +
2035 +static inline int
2036 +ar5312_sys_frequency(void)
2037 +{
2038 + return ar5312_cpu_frequency() / 4;
2039 +}
2040 +
2041 +void __init
2042 +ar5312_time_init(void)
2043 +{
2044 + if (!is_5312())
2045 + return;
2046 +
2047 + mips_hpt_frequency = ar5312_cpu_frequency() / 2;
2048 +}
2049 +
2050 +int __init
2051 +ar5312_gpio_init(void)
2052 +{
2053 + int ret;
2054 + struct ar231x_gpio_chip *gpch;
2055 + gpch = &ar5312_gpio_chip;
2056 + ret = gpiochip_add(&gpch->chip);
2057 + if (ret) {
2058 + printk(KERN_ERR "%s: failed to add gpiochip\n",
2059 + gpch->chip.label);
2060 + return ret;
2061 + }
2062 + printk(KERN_INFO "%s: registered %d GPIOs\n",
2063 + gpch->chip.label, gpch->chip.ngpio);
2064 + return ret;
2065 +}
2066 +
2067 +void __init
2068 +ar5312_prom_init(void)
2069 +{
2070 + u32 memsize, memcfg, bank0AC, bank1AC;
2071 + u32 devid;
2072 +
2073 + if (!is_5312())
2074 + return;
2075 +
2076 + /* Detect memory size */
2077 + memcfg = ar231x_read_reg(AR531X_MEM_CFG1);
2078 + bank0AC = (memcfg & MEM_CFG1_AC0) >> MEM_CFG1_AC0_S;
2079 + bank1AC = (memcfg & MEM_CFG1_AC1) >> MEM_CFG1_AC1_S;
2080 + memsize = (bank0AC ? (1 << (bank0AC+1)) : 0)
2081 + + (bank1AC ? (1 << (bank1AC+1)) : 0);
2082 + memsize <<= 20;
2083 + add_memory_region(0, memsize, BOOT_MEM_RAM);
2084 +
2085 + devid = ar231x_read_reg(AR531X_REV);
2086 + devid >>= AR531X_REV_WMAC_MIN_S;
2087 + devid &= AR531X_REV_CHIP;
2088 + ar231x_board.devid = (u16) devid;
2089 + ar5312_gpio_init();
2090 +}
2091 +
2092 +void __init
2093 +ar5312_plat_setup(void)
2094 +{
2095 + if (!is_5312())
2096 + return;
2097 +
2098 + /* Clear any lingering AHB errors */
2099 + ar231x_read_reg(AR531X_PROCADDR);
2100 + ar231x_read_reg(AR531X_DMAADDR);
2101 + ar231x_write_reg(AR531X_WD_CTRL, AR531X_WD_CTRL_IGNORE_EXPIRATION);
2102 +
2103 + _machine_restart = ar5312_restart;
2104 + ar231x_serial_setup(KSEG1ADDR(AR531X_UART0), ar5312_sys_frequency());
2105 +}
2106 +
2107 --- /dev/null
2108 +++ b/arch/mips/ar231x/ar2315.c
2109 @@ -0,0 +1,694 @@
2110 +/*
2111 + * This file is subject to the terms and conditions of the GNU General Public
2112 + * License. See the file "COPYING" in the main directory of this archive
2113 + * for more details.
2114 + *
2115 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
2116 + * Copyright (C) 2006 FON Technology, SL.
2117 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
2118 + * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
2119 + * Copyright (C) 2012 Alexandros C. Couloumbis <alex@ozo.com>
2120 + */
2121 +
2122 +/*
2123 + * Platform devices for Atheros SoCs
2124 + */
2125 +
2126 +#include <generated/autoconf.h>
2127 +#include <linux/init.h>
2128 +#include <linux/module.h>
2129 +#include <linux/types.h>
2130 +#include <linux/string.h>
2131 +#include <linux/platform_device.h>
2132 +#include <linux/kernel.h>
2133 +#include <linux/reboot.h>
2134 +#include <linux/delay.h>
2135 +#include <linux/leds.h>
2136 +#include <linux/gpio.h>
2137 +#include <asm/bootinfo.h>
2138 +#include <asm/reboot.h>
2139 +#include <asm/time.h>
2140 +#include <linux/irq.h>
2141 +#include <asm/io.h>
2142 +
2143 +#include <ar231x_platform.h>
2144 +#include <ar2315_regs.h>
2145 +#include <ar231x.h>
2146 +#include "devices.h"
2147 +#include "ar2315.h"
2148 +
2149 +static u32 gpiointmask = 0, gpiointval = 0;
2150 +
2151 +static inline void ar2315_gpio_irq(void)
2152 +{
2153 + u32 pend;
2154 + int bit = -1;
2155 +
2156 + /* only do one gpio interrupt at a time */
2157 + pend = (ar231x_read_reg(AR2315_GPIO_DI) ^ gpiointval) & gpiointmask;
2158 +
2159 + if (pend) {
2160 + bit = fls(pend) - 1;
2161 + pend &= ~(1 << bit);
2162 + gpiointval ^= (1 << bit);
2163 + }
2164 +
2165 + if (!pend)
2166 + ar231x_write_reg(AR2315_ISR, AR2315_ISR_GPIO);
2167 +
2168 + /* Enable interrupt with edge detection */
2169 + if ((ar231x_read_reg(AR2315_GPIO_CR) & AR2315_GPIO_CR_M(bit)) != AR2315_GPIO_CR_I(bit))
2170 + return;
2171 +
2172 + if (bit >= 0)
2173 + do_IRQ(AR531X_GPIO_IRQ_BASE + bit);
2174 +}
2175 +
2176 +
2177 +/*
2178 + * Called when an interrupt is received, this function
2179 + * determines exactly which interrupt it was, and it
2180 + * invokes the appropriate handler.
2181 + *
2182 + * Implicitly, we also define interrupt priority by
2183 + * choosing which to dispatch first.
2184 + */
2185 +static asmlinkage void
2186 +ar2315_irq_dispatch(void)
2187 +{
2188 + int pending = read_c0_status() & read_c0_cause();
2189 +
2190 + if (pending & CAUSEF_IP3)
2191 + do_IRQ(AR2315_IRQ_WLAN0_INTRS);
2192 + else if (pending & CAUSEF_IP4)
2193 + do_IRQ(AR2315_IRQ_ENET0_INTRS);
2194 + else if (pending & CAUSEF_IP2) {
2195 + unsigned int misc_intr = ar231x_read_reg(AR2315_ISR) & ar231x_read_reg(AR2315_IMR);
2196 +
2197 + if (misc_intr & AR2315_ISR_SPI)
2198 + do_IRQ(AR531X_MISC_IRQ_SPI);
2199 + else if (misc_intr & AR2315_ISR_TIMER)
2200 + do_IRQ(AR531X_MISC_IRQ_TIMER);
2201 + else if (misc_intr & AR2315_ISR_AHB)
2202 + do_IRQ(AR531X_MISC_IRQ_AHB_PROC);
2203 + else if (misc_intr & AR2315_ISR_GPIO)
2204 + ar2315_gpio_irq();
2205 + else if (misc_intr & AR2315_ISR_UART0)
2206 + do_IRQ(AR531X_MISC_IRQ_UART0);
2207 + else if (misc_intr & AR2315_ISR_WD)
2208 + do_IRQ(AR531X_MISC_IRQ_WATCHDOG);
2209 + else
2210 + do_IRQ(AR531X_MISC_IRQ_NONE);
2211 + } else if (pending & CAUSEF_IP7)
2212 + do_IRQ(AR531X_IRQ_CPU_CLOCK);
2213 +}
2214 +
2215 +static void ar2315_set_gpiointmask(int gpio, int level)
2216 +{
2217 + u32 reg;
2218 +
2219 + reg = ar231x_read_reg(AR2315_GPIO_INT);
2220 + reg &= ~(AR2315_GPIO_INT_M | AR2315_GPIO_INT_LVL_M);
2221 + reg |= gpio | AR2315_GPIO_INT_LVL(level);
2222 + ar231x_write_reg(AR2315_GPIO_INT, reg);
2223 +}
2224 +
2225 +static void ar2315_gpio_intr_enable(struct irq_data *d)
2226 +{
2227 + unsigned int gpio = d->irq - AR531X_GPIO_IRQ_BASE;
2228 +
2229 + /* Enable interrupt with edge detection */
2230 + if ((ar231x_read_reg(AR2315_GPIO_CR) & AR2315_GPIO_CR_M(gpio)) != AR2315_GPIO_CR_I(gpio))
2231 + return;
2232 +
2233 + gpiointmask |= (1 << gpio);
2234 + ar2315_set_gpiointmask(gpio, 3);
2235 +}
2236 +
2237 +static void ar2315_gpio_intr_disable(struct irq_data *d)
2238 +{
2239 + unsigned int gpio = d->irq - AR531X_GPIO_IRQ_BASE;
2240 +
2241 + /* Disable interrupt */
2242 + gpiointmask &= ~(1 << gpio);
2243 + ar2315_set_gpiointmask(gpio, 0);
2244 +}
2245 +
2246 +static struct irq_chip ar2315_gpio_intr_controller = {
2247 + .irq_mask = ar2315_gpio_intr_disable,
2248 + .irq_unmask = ar2315_gpio_intr_enable,
2249 +};
2250 +
2251 +static void
2252 +ar2315_misc_intr_enable(struct irq_data *d)
2253 +{
2254 + unsigned int imr;
2255 +
2256 + imr = ar231x_read_reg(AR2315_IMR);
2257 + switch(d->irq) {
2258 + case AR531X_MISC_IRQ_SPI:
2259 + imr |= AR2315_ISR_SPI;
2260 + break;
2261 + case AR531X_MISC_IRQ_TIMER:
2262 + imr |= AR2315_ISR_TIMER;
2263 + break;
2264 + case AR531X_MISC_IRQ_AHB_PROC:
2265 + imr |= AR2315_ISR_AHB;
2266 + break;
2267 + case AR531X_MISC_IRQ_GPIO:
2268 + imr |= AR2315_ISR_GPIO;
2269 + break;
2270 + case AR531X_MISC_IRQ_UART0:
2271 + imr |= AR2315_ISR_UART0;
2272 + break;
2273 + case AR531X_MISC_IRQ_WATCHDOG:
2274 + imr |= AR2315_ISR_WD;
2275 + break;
2276 + default:
2277 + break;
2278 + }
2279 + ar231x_write_reg(AR2315_IMR, imr);
2280 +}
2281 +
2282 +static void
2283 +ar2315_misc_intr_disable(struct irq_data *d)
2284 +{
2285 + unsigned int imr;
2286 +
2287 + imr = ar231x_read_reg(AR2315_IMR);
2288 + switch(d->irq) {
2289 + case AR531X_MISC_IRQ_SPI:
2290 + imr &= ~AR2315_ISR_SPI;
2291 + break;
2292 + case AR531X_MISC_IRQ_TIMER:
2293 + imr &= ~AR2315_ISR_TIMER;
2294 + break;
2295 + case AR531X_MISC_IRQ_AHB_PROC:
2296 + imr &= ~AR2315_ISR_AHB;
2297 + break;
2298 + case AR531X_MISC_IRQ_GPIO:
2299 + imr &= ~AR2315_ISR_GPIO;
2300 + break;
2301 + case AR531X_MISC_IRQ_UART0:
2302 + imr &= ~AR2315_ISR_UART0;
2303 + break;
2304 + case AR531X_MISC_IRQ_WATCHDOG:
2305 + imr &= ~AR2315_ISR_WD;
2306 + break;
2307 + default:
2308 + break;
2309 + }
2310 + ar231x_write_reg(AR2315_IMR, imr);
2311 +}
2312 +
2313 +static struct irq_chip ar2315_misc_intr_controller = {
2314 + .irq_mask = ar2315_misc_intr_disable,
2315 + .irq_unmask = ar2315_misc_intr_enable,
2316 +};
2317 +
2318 +static irqreturn_t ar2315_ahb_proc_handler(int cpl, void *dev_id)
2319 +{
2320 + ar231x_write_reg(AR2315_AHB_ERR0, AHB_ERROR_DET);
2321 + ar231x_read_reg(AR2315_AHB_ERR1);
2322 +
2323 + printk(KERN_ERR "AHB fatal error\n");
2324 + machine_restart("AHB error"); /* Catastrophic failure */
2325 +
2326 + return IRQ_HANDLED;
2327 +}
2328 +
2329 +static struct irqaction ar2315_ahb_proc_interrupt = {
2330 + .handler = ar2315_ahb_proc_handler,
2331 + .name = "ar2315_ahb_proc_interrupt",
2332 +};
2333 +
2334 +static struct irqaction cascade = {
2335 + .handler = no_action,
2336 + .name = "cascade",
2337 +};
2338 +
2339 +void
2340 +ar2315_irq_init(void)
2341 +{
2342 + int i;
2343 +
2344 + if (!is_2315())
2345 + return;
2346 +
2347 + ar231x_irq_dispatch = ar2315_irq_dispatch;
2348 + gpiointval = ar231x_read_reg(AR2315_GPIO_DI);
2349 + for (i = 0; i < AR531X_MISC_IRQ_COUNT; i++) {
2350 + int irq = AR531X_MISC_IRQ_BASE + i;
2351 + irq_set_chip_and_handler(irq, &ar2315_misc_intr_controller,
2352 + handle_level_irq);
2353 + }
2354 + for (i = 0; i < AR531X_GPIO_IRQ_COUNT; i++) {
2355 + int irq = AR531X_GPIO_IRQ_BASE + i;
2356 + irq_set_chip_and_handler(irq, &ar2315_gpio_intr_controller,
2357 + handle_level_irq);
2358 + }
2359 + setup_irq(AR531X_MISC_IRQ_GPIO, &cascade);
2360 + setup_irq(AR531X_MISC_IRQ_AHB_PROC, &ar2315_ahb_proc_interrupt);
2361 + setup_irq(AR2315_IRQ_MISC_INTRS, &cascade);
2362 +}
2363 +
2364 +static u32
2365 +ar2315_gpio_set_output(u32 mask, u32 val)
2366 +{
2367 + u32 reg;
2368 +
2369 + reg = ar231x_read_reg(AR2315_GPIO_CR);
2370 + reg &= ~mask;
2371 + reg |= val;
2372 + ar231x_write_reg(AR2315_GPIO_CR, reg);
2373 + return reg;
2374 +}
2375 +
2376 +static u32
2377 +ar2315_gpio_get(u32 valid_mask)
2378 +{
2379 + u32 reg;
2380 + reg = ar231x_read_reg(AR2315_GPIO_DI);
2381 + reg &= valid_mask;
2382 + return reg;
2383 +}
2384 +
2385 +static u32
2386 +ar2315_gpio_set(u32 mask, u32 value)
2387 +{
2388 + u32 reg;
2389 + reg = ar231x_read_reg(AR2315_GPIO_DO);
2390 + reg &= ~mask;
2391 + reg |= value;
2392 + ar231x_write_reg(AR2315_GPIO_DO, reg);
2393 + return reg;
2394 +}
2395 +
2396 +/*
2397 + * gpiolib implementation. Original legacy mask based methods
2398 + * preserved for now.
2399 + */
2400 +static int
2401 +ar2315_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
2402 +{
2403 + struct ar231x_gpio_chip *gpch =
2404 + container_of(chip, struct ar231x_gpio_chip, chip);
2405 + u32 mask = 1 << gpio;
2406 + u32 rett;
2407 + if (!(gpch->valid_mask & mask))
2408 + return 0;
2409 + rett = ar2315_gpio_get(gpch->valid_mask); // legacy code
2410 + return !!(rett & mask);
2411 +}
2412 +
2413 +static void
2414 +ar2315_gpio_set_value(struct gpio_chip *chip, unsigned gpio, int value)
2415 +{
2416 + struct ar231x_gpio_chip *gpch =
2417 + container_of(chip, struct ar231x_gpio_chip, chip);
2418 + u32 mask = 1 << gpio;
2419 + if (!(gpch->valid_mask & mask))
2420 + return;
2421 + ar2315_gpio_set(mask, (!!value) * mask); // legacy
2422 +}
2423 +
2424 +static int
2425 +ar2315_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
2426 +{
2427 + struct ar231x_gpio_chip *gpch =
2428 + container_of(chip, struct ar231x_gpio_chip, chip);
2429 + u32 mask = 1 << gpio;
2430 + if (!(gpch->valid_mask & mask))
2431 + return -ENXIO;
2432 + ar2315_gpio_set_output(mask, 0); // legacy
2433 + return 0;
2434 +}
2435 +
2436 +static int
2437 +ar2315_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, int value)
2438 +{
2439 + struct ar231x_gpio_chip *gpch =
2440 + container_of(chip, struct ar231x_gpio_chip, chip);
2441 + u32 mask = 1 << gpio;
2442 + if (!(gpch->valid_mask & mask))
2443 + return -ENXIO;
2444 + ar2315_gpio_set_output(mask, mask); // both legacy
2445 + ar2315_gpio_set(mask, (!!value) * mask);
2446 + return 0;
2447 +}
2448 +
2449 +static struct ar231x_gpio_chip ar2315_gpio_chip = {
2450 + .valid_mask = (1 << 22) - 1,
2451 + .chip = {
2452 + .label = "ar2315-gpio",
2453 + .direction_input = ar2315_gpio_direction_input,
2454 + .direction_output = ar2315_gpio_direction_output,
2455 + .set = ar2315_gpio_set_value,
2456 + .get = ar2315_gpio_get_value,
2457 + .base = 0,
2458 + .ngpio = AR531X_GPIO_IRQ_COUNT, // 22
2459 + }
2460 +};
2461 +
2462 +// end of gpiolib
2463 +
2464 +
2465 +static struct ar231x_eth ar2315_eth_data = {
2466 + .reset_base = AR2315_RESET,
2467 + .reset_mac = AR2315_RESET_ENET0,
2468 + .reset_phy = AR2315_RESET_EPHY0,
2469 + .phy_base = KSEG1ADDR(AR2315_ENET0),
2470 + .config = &ar231x_board,
2471 +};
2472 +
2473 +static struct resource ar2315_spiflash_res[] = {
2474 + {
2475 + .name = "flash_base",
2476 + .flags = IORESOURCE_MEM,
2477 + .start = KSEG1ADDR(AR2315_SPI_READ),
2478 + .end = KSEG1ADDR(AR2315_SPI_READ) + 0x1000000 - 1,
2479 + },
2480 + {
2481 + .name = "flash_regs",
2482 + .flags = IORESOURCE_MEM,
2483 + .start = 0x11300000,
2484 + .end = 0x11300012,
2485 + },
2486 +};
2487 +
2488 +static struct platform_device ar2315_spiflash = {
2489 + .id = 0,
2490 + .name = "spiflash",
2491 + .resource = ar2315_spiflash_res,
2492 + .num_resources = ARRAY_SIZE(ar2315_spiflash_res)
2493 +};
2494 +
2495 +static struct platform_device ar2315_wdt = {
2496 + .id = 0,
2497 + .name = "ar2315_wdt",
2498 +};
2499 +
2500 +#define SPI_FLASH_CTL 0x00
2501 +#define SPI_FLASH_OPCODE 0x04
2502 +#define SPI_FLASH_DATA 0x08
2503 +
2504 +static inline u32
2505 +spiflash_read_reg(int reg)
2506 +{
2507 + return ar231x_read_reg(AR2315_SPI + reg);
2508 +}
2509 +
2510 +static inline void
2511 +spiflash_write_reg(int reg, u32 data)
2512 +{
2513 + ar231x_write_reg(AR2315_SPI + reg, data);
2514 +}
2515 +
2516 +static u32
2517 +spiflash_wait_status(void)
2518 +{
2519 + u32 reg;
2520 +
2521 + do {
2522 + reg = spiflash_read_reg(SPI_FLASH_CTL);
2523 + } while (reg & SPI_CTL_BUSY);
2524 +
2525 + return reg;
2526 +}
2527 +
2528 +static u8
2529 +spiflash_probe(void)
2530 +{
2531 + u32 reg;
2532 +
2533 + reg = spiflash_wait_status();
2534 + reg &= ~SPI_CTL_TX_RX_CNT_MASK;
2535 + reg |= (1 << 4) | 4 | SPI_CTL_START;
2536 +
2537 + spiflash_write_reg(SPI_FLASH_OPCODE, 0xab);
2538 + spiflash_write_reg(SPI_FLASH_CTL, reg);
2539 +
2540 + reg = spiflash_wait_status();
2541 + reg = spiflash_read_reg(SPI_FLASH_DATA);
2542 + reg &= 0xff;
2543 +
2544 + return (u8) reg;
2545 +}
2546 +
2547 +
2548 +#define STM_8MBIT_SIGNATURE 0x13
2549 +#define STM_16MBIT_SIGNATURE 0x14
2550 +#define STM_32MBIT_SIGNATURE 0x15
2551 +#define STM_64MBIT_SIGNATURE 0x16
2552 +#define STM_128MBIT_SIGNATURE 0x17
2553 +
2554 +static u8 __init *
2555 +ar2315_flash_limit(void)
2556 +{
2557 + u32 flash_size = 0;
2558 +
2559 + /* probe the flash chip size */
2560 + switch(spiflash_probe()) {
2561 + case STM_8MBIT_SIGNATURE:
2562 + flash_size = 0x00100000;
2563 + break;
2564 + case STM_16MBIT_SIGNATURE:
2565 + flash_size = 0x00200000;
2566 + break;
2567 + case STM_32MBIT_SIGNATURE:
2568 + flash_size = 0x00400000;
2569 + break;
2570 + case STM_64MBIT_SIGNATURE:
2571 + flash_size = 0x00800000;
2572 + break;
2573 + case STM_128MBIT_SIGNATURE:
2574 + flash_size = 0x01000000;
2575 + break;
2576 + }
2577 +
2578 + ar2315_spiflash_res[0].end = ar2315_spiflash_res[0].start +
2579 + flash_size - 1;
2580 + return (u8 *) ar2315_spiflash_res[0].end + 1;
2581 +}
2582 +
2583 +#ifdef CONFIG_LEDS_GPIO
2584 +static struct gpio_led ar2315_leds[6];
2585 +static struct gpio_led_platform_data ar2315_led_data = {
2586 + .leds = (void *) ar2315_leds,
2587 +};
2588 +
2589 +static struct platform_device ar2315_gpio_leds = {
2590 + .name = "leds-gpio",
2591 + .id = -1,
2592 + .dev = {
2593 + .platform_data = (void *) &ar2315_led_data,
2594 + }
2595 +};
2596 +
2597 +static void __init
2598 +ar2315_init_gpio_leds(void)
2599 +{
2600 + static char led_names[6][6];
2601 + int i, led = 0;
2602 +
2603 + ar2315_led_data.num_leds = 0;
2604 + for(i = 1; i < 8; i++)
2605 + {
2606 + if((i == AR2315_RESET_GPIO) ||
2607 + (i == ar231x_board.config->resetConfigGpio))
2608 + continue;
2609 +
2610 + if(i == ar231x_board.config->sysLedGpio)
2611 + strcpy(led_names[led], "wlan");
2612 + else
2613 + sprintf(led_names[led], "gpio%d", i);
2614 +
2615 + ar2315_leds[led].name = led_names[led];
2616 + ar2315_leds[led].gpio = i;
2617 + ar2315_leds[led].active_low = 0;
2618 + led++;
2619 + }
2620 + ar2315_led_data.num_leds = led;
2621 + platform_device_register(&ar2315_gpio_leds);
2622 +}
2623 +#else
2624 +static inline void ar2315_init_gpio_leds(void)
2625 +{
2626 +}
2627 +#endif
2628 +
2629 +int __init
2630 +ar2315_init_devices(void)
2631 +{
2632 + if (!is_2315())
2633 + return 0;
2634 +
2635 + /* Find board configuration */
2636 + ar231x_find_config(ar2315_flash_limit());
2637 + ar2315_eth_data.macaddr = ar231x_board.config->enet0_mac;
2638 +
2639 + ar2315_init_gpio_leds();
2640 + platform_device_register(&ar2315_wdt);
2641 + platform_device_register(&ar2315_spiflash);
2642 + ar231x_add_ethernet(0, KSEG1ADDR(AR2315_ENET0), AR2315_IRQ_ENET0_INTRS,
2643 + &ar2315_eth_data);
2644 + ar231x_add_wmac(0, AR2315_WLAN0, AR2315_IRQ_WLAN0_INTRS);
2645 +
2646 + return 0;
2647 +}
2648 +
2649 +static void
2650 +ar2315_restart(char *command)
2651 +{
2652 + void (*mips_reset_vec)(void) = (void *) 0xbfc00000;
2653 +
2654 + local_irq_disable();
2655 +
2656 + /* try reset the system via reset control */
2657 + ar231x_write_reg(AR2315_COLD_RESET,AR2317_RESET_SYSTEM);
2658 +
2659 + /* Cold reset does not work on the AR2315/6, use the GPIO reset bits a workaround.
2660 + * give it some time to attempt a gpio based hardware reset
2661 + * (atheros reference design workaround) */
2662 + gpio_direction_output(AR2315_RESET_GPIO, 0);
2663 + mdelay(100);
2664 +
2665 + /* Some boards (e.g. Senao EOC-2610) don't implement the reset logic
2666 + * workaround. Attempt to jump to the mips reset location -
2667 + * the boot loader itself might be able to recover the system */
2668 + mips_reset_vec();
2669 +}
2670 +
2671 +
2672 +/*
2673 + * This table is indexed by bits 5..4 of the CLOCKCTL1 register
2674 + * to determine the predevisor value.
2675 + */
2676 +static int __initdata CLOCKCTL1_PREDIVIDE_TABLE[4] = { 1, 2, 4, 5 };
2677 +static int __initdata PLLC_DIVIDE_TABLE[5] = { 2, 3, 4, 6, 3 };
2678 +
2679 +static unsigned int __init
2680 +ar2315_sys_clk(unsigned int clockCtl)
2681 +{
2682 + unsigned int pllcCtrl,cpuDiv;
2683 + unsigned int pllcOut,refdiv,fdiv,divby2;
2684 + unsigned int clkDiv;
2685 +
2686 + pllcCtrl = ar231x_read_reg(AR2315_PLLC_CTL);
2687 + refdiv = (pllcCtrl & PLLC_REF_DIV_M) >> PLLC_REF_DIV_S;
2688 + refdiv = CLOCKCTL1_PREDIVIDE_TABLE[refdiv];
2689 + fdiv = (pllcCtrl & PLLC_FDBACK_DIV_M) >> PLLC_FDBACK_DIV_S;
2690 + divby2 = (pllcCtrl & PLLC_ADD_FDBACK_DIV_M) >> PLLC_ADD_FDBACK_DIV_S;
2691 + divby2 += 1;
2692 + pllcOut = (40000000/refdiv)*(2*divby2)*fdiv;
2693 +
2694 +
2695 + /* clkm input selected */
2696 + switch(clockCtl & CPUCLK_CLK_SEL_M) {
2697 + case 0:
2698 + case 1:
2699 + clkDiv = PLLC_DIVIDE_TABLE[(pllcCtrl & PLLC_CLKM_DIV_M) >> PLLC_CLKM_DIV_S];
2700 + break;
2701 + case 2:
2702 + clkDiv = PLLC_DIVIDE_TABLE[(pllcCtrl & PLLC_CLKC_DIV_M) >> PLLC_CLKC_DIV_S];
2703 + break;
2704 + default:
2705 + pllcOut = 40000000;
2706 + clkDiv = 1;
2707 + break;
2708 + }
2709 + cpuDiv = (clockCtl & CPUCLK_CLK_DIV_M) >> CPUCLK_CLK_DIV_S;
2710 + cpuDiv = cpuDiv * 2 ?: 1;
2711 + return (pllcOut/(clkDiv * cpuDiv));
2712 +}
2713 +
2714 +static inline unsigned int
2715 +ar2315_cpu_frequency(void)
2716 +{
2717 + return ar2315_sys_clk(ar231x_read_reg(AR2315_CPUCLK));
2718 +}
2719 +
2720 +static inline unsigned int
2721 +ar2315_apb_frequency(void)
2722 +{
2723 + return ar2315_sys_clk(ar231x_read_reg(AR2315_AMBACLK));
2724 +}
2725 +
2726 +void __init
2727 +ar2315_time_init(void)
2728 +{
2729 + if (!is_2315())
2730 + return;
2731 +
2732 + mips_hpt_frequency = ar2315_cpu_frequency() / 2;
2733 +}
2734 +
2735 +int __init
2736 +ar2315_gpio_init(void)
2737 +{
2738 + int ret;
2739 + struct ar231x_gpio_chip *gpch;
2740 + gpch = &ar2315_gpio_chip;
2741 + ret = gpiochip_add(&gpch->chip);
2742 + if (ret) {
2743 + printk(KERN_ERR "%s: failed to add gpiochip\n",
2744 + gpch->chip.label);
2745 + return ret;
2746 + }
2747 + printk(KERN_INFO "%s: registered %d GPIOs\n",
2748 + gpch->chip.label, gpch->chip.ngpio);
2749 + return ret;
2750 +}
2751 +
2752 +
2753 +
2754 +void __init
2755 +ar2315_prom_init(void)
2756 +{
2757 + u32 memsize, memcfg, devid;
2758 +
2759 + if (!is_2315())
2760 + return;
2761 +
2762 + memcfg = ar231x_read_reg(AR2315_MEM_CFG);
2763 + memsize = 1 + ((memcfg & SDRAM_DATA_WIDTH_M) >> SDRAM_DATA_WIDTH_S);
2764 + memsize <<= 1 + ((memcfg & SDRAM_COL_WIDTH_M) >> SDRAM_COL_WIDTH_S);
2765 + memsize <<= 1 + ((memcfg & SDRAM_ROW_WIDTH_M) >> SDRAM_ROW_WIDTH_S);
2766 + memsize <<= 3;
2767 + add_memory_region(0, memsize, BOOT_MEM_RAM);
2768 +
2769 + /* Detect the hardware based on the device ID */
2770 + devid = ar231x_read_reg(AR2315_SREV) & AR2315_REV_CHIP;
2771 + switch(devid) {
2772 + case 0x90:
2773 + case 0x91:
2774 + ar231x_devtype = DEV_TYPE_AR2317;
2775 + break;
2776 + default:
2777 + ar231x_devtype = DEV_TYPE_AR2315;
2778 + break;
2779 + }
2780 + ar2315_gpio_init();
2781 + ar231x_board.devid = devid;
2782 +}
2783 +
2784 +void __init
2785 +ar2315_plat_setup(void)
2786 +{
2787 + u32 config;
2788 +
2789 + if (!is_2315())
2790 + return;
2791 +
2792 + gpio_request(AR2315_RESET_GPIO, "reset");
2793 +
2794 + /* Clear any lingering AHB errors */
2795 + config = read_c0_config();
2796 + write_c0_config(config & ~0x3);
2797 + ar231x_write_reg(AR2315_AHB_ERR0,AHB_ERROR_DET);
2798 + ar231x_read_reg(AR2315_AHB_ERR1);
2799 + ar231x_write_reg(AR2315_WDC, AR2315_WDC_IGNORE_EXPIRATION);
2800 +
2801 + _machine_restart = ar2315_restart;
2802 + ar231x_serial_setup(KSEG1ADDR(AR2315_UART0), ar2315_apb_frequency());
2803 +}
2804 --- /dev/null
2805 +++ b/arch/mips/ar231x/ar2315.h
2806 @@ -0,0 +1,37 @@
2807 +#ifndef __AR2315_H
2808 +#define __AR2315_H
2809 +
2810 +#ifdef CONFIG_ATHEROS_AR2315
2811 +
2812 +extern void ar2315_irq_init(void);
2813 +extern int ar2315_init_devices(void);
2814 +extern void ar2315_prom_init(void);
2815 +extern void ar2315_plat_setup(void);
2816 +extern void ar2315_time_init(void);
2817 +
2818 +#else
2819 +
2820 +static inline void ar2315_irq_init(void)
2821 +{
2822 +}
2823 +
2824 +static inline int ar2315_init_devices(void)
2825 +{
2826 + return 0;
2827 +}
2828 +
2829 +static inline void ar2315_prom_init(void)
2830 +{
2831 +}
2832 +
2833 +static inline void ar2315_plat_setup(void)
2834 +{
2835 +}
2836 +
2837 +static inline void ar2315_time_init(void)
2838 +{
2839 +}
2840 +
2841 +#endif
2842 +
2843 +#endif
2844 --- /dev/null
2845 +++ b/arch/mips/ar231x/ar5312.h
2846 @@ -0,0 +1,38 @@
2847 +#ifndef __AR5312_H
2848 +#define __AR5312_H
2849 +
2850 +#ifdef CONFIG_ATHEROS_AR5312
2851 +
2852 +extern void ar5312_irq_init(void);
2853 +extern int ar5312_init_devices(void);
2854 +extern void ar5312_prom_init(void);
2855 +extern void ar5312_plat_setup(void);
2856 +extern void ar5312_time_init(void);
2857 +extern void ar5312_time_init(void);
2858 +
2859 +#else
2860 +
2861 +static inline void ar5312_irq_init(void)
2862 +{
2863 +}
2864 +
2865 +static inline int ar5312_init_devices(void)
2866 +{
2867 + return 0;
2868 +}
2869 +
2870 +static inline void ar5312_prom_init(void)
2871 +{
2872 +}
2873 +
2874 +static inline void ar5312_plat_setup(void)
2875 +{
2876 +}
2877 +
2878 +static inline void ar5312_time_init(void)
2879 +{
2880 +}
2881 +
2882 +#endif
2883 +
2884 +#endif
2885 --- /dev/null
2886 +++ b/arch/mips/include/asm/mach-ar231x/ar231x.h
2887 @@ -0,0 +1,57 @@
2888 +#ifndef __AR531X_H
2889 +#define __AR531X_H
2890 +
2891 +#include <linux/types.h>
2892 +#include <linux/io.h>
2893 +
2894 +#define AR531X_MISC_IRQ_BASE 0x20
2895 +#define AR531X_GPIO_IRQ_BASE 0x30
2896 +
2897 +/* Software's idea of interrupts handled by "CPU Interrupt Controller" */
2898 +#define AR531X_IRQ_NONE MIPS_CPU_IRQ_BASE+0
2899 +#define AR531X_IRQ_CPU_CLOCK MIPS_CPU_IRQ_BASE+7 /* C0_CAUSE: 0x8000 */
2900 +
2901 +/* Miscellaneous interrupts, which share IP6 */
2902 +#define AR531X_MISC_IRQ_NONE AR531X_MISC_IRQ_BASE+0
2903 +#define AR531X_MISC_IRQ_TIMER AR531X_MISC_IRQ_BASE+1
2904 +#define AR531X_MISC_IRQ_AHB_PROC AR531X_MISC_IRQ_BASE+2
2905 +#define AR531X_MISC_IRQ_AHB_DMA AR531X_MISC_IRQ_BASE+3
2906 +#define AR531X_MISC_IRQ_GPIO AR531X_MISC_IRQ_BASE+4
2907 +#define AR531X_MISC_IRQ_UART0 AR531X_MISC_IRQ_BASE+5
2908 +#define AR531X_MISC_IRQ_UART0_DMA AR531X_MISC_IRQ_BASE+6
2909 +#define AR531X_MISC_IRQ_WATCHDOG AR531X_MISC_IRQ_BASE+7
2910 +#define AR531X_MISC_IRQ_LOCAL AR531X_MISC_IRQ_BASE+8
2911 +#define AR531X_MISC_IRQ_SPI AR531X_MISC_IRQ_BASE+9
2912 +#define AR531X_MISC_IRQ_COUNT 10
2913 +
2914 +/* GPIO Interrupts [0..7], share AR531X_MISC_IRQ_GPIO */
2915 +#define AR531X_GPIO_IRQ_NONE AR531X_GPIO_IRQ_BASE+0
2916 +#define AR531X_GPIO_IRQ(n) AR531X_GPIO_IRQ_BASE+n
2917 +#define AR531X_GPIO_IRQ_COUNT 22
2918 +
2919 +static inline u32
2920 +ar231x_read_reg(u32 reg)
2921 +{
2922 + return __raw_readl((u32 *) KSEG1ADDR(reg));
2923 +}
2924 +
2925 +static inline void
2926 +ar231x_write_reg(u32 reg, u32 val)
2927 +{
2928 + __raw_writel(val, (u32 *) KSEG1ADDR(reg));
2929 +}
2930 +
2931 +static inline u32
2932 +ar231x_mask_reg(u32 reg, u32 mask, u32 val)
2933 +{
2934 + u32 ret;
2935 +
2936 + ret = ar231x_read_reg(reg);
2937 + ret &= ~mask;
2938 + ret |= val;
2939 + ar231x_write_reg(reg, ret);
2940 +
2941 + return ret;
2942 +}
2943 +
2944 +#endif
2945 --- /dev/null
2946 +++ b/arch/mips/ar231x/devices.h
2947 @@ -0,0 +1,42 @@
2948 +#ifndef __AR231X_DEVICES_H
2949 +#define __AR231X_DEVICES_H
2950 +#include <linux/gpio.h>
2951 +
2952 +enum {
2953 + /* handled by ar5312.c */
2954 + DEV_TYPE_AR2312,
2955 + DEV_TYPE_AR2313,
2956 + DEV_TYPE_AR5312,
2957 +
2958 + /* handled by ar2315.c */
2959 + DEV_TYPE_AR2315,
2960 + DEV_TYPE_AR2316,
2961 + DEV_TYPE_AR2317,
2962 +
2963 + DEV_TYPE_UNKNOWN
2964 +};
2965 +
2966 +extern int ar231x_devtype;
2967 +extern struct ar231x_board_config ar231x_board;
2968 +extern asmlinkage void (*ar231x_irq_dispatch)(void);
2969 +
2970 +extern int ar231x_find_config(u8 *flash_limit);
2971 +extern void ar231x_serial_setup(u32 mapbase, unsigned int uartclk);
2972 +extern int ar231x_add_wmac(int nr, u32 base, int irq);
2973 +extern int ar231x_add_ethernet(int nr, u32 base, int irq, void *pdata);
2974 +
2975 +static inline bool is_2315(void)
2976 +{
2977 + return (current_cpu_data.cputype == CPU_4KEC);
2978 +}
2979 +
2980 +static inline bool is_5312(void)
2981 +{
2982 + return !is_2315();
2983 +}
2984 +
2985 +struct ar231x_gpio_chip {
2986 + u32 valid_mask;
2987 + struct gpio_chip chip;
2988 +};
2989 +#endif
2990 --- /dev/null
2991 +++ b/arch/mips/ar231x/devices.c
2992 @@ -0,0 +1,168 @@
2993 +#include <linux/kernel.h>
2994 +#include <linux/init.h>
2995 +#include <linux/serial.h>
2996 +#include <linux/serial_core.h>
2997 +#include <linux/serial_8250.h>
2998 +#include <linux/platform_device.h>
2999 +#include <ar231x_platform.h>
3000 +#include <ar231x.h>
3001 +#include "devices.h"
3002 +#include "ar5312.h"
3003 +#include "ar2315.h"
3004 +
3005 +struct ar231x_board_config ar231x_board;
3006 +int ar231x_devtype = DEV_TYPE_UNKNOWN;
3007 +
3008 +static struct resource ar231x_eth0_res[] = {
3009 + {
3010 + .name = "eth0_membase",
3011 + .flags = IORESOURCE_MEM,
3012 + },
3013 + {
3014 + .name = "eth0_irq",
3015 + .flags = IORESOURCE_IRQ,
3016 + }
3017 +};
3018 +
3019 +static struct resource ar231x_eth1_res[] = {
3020 + {
3021 + .name = "eth1_membase",
3022 + .flags = IORESOURCE_MEM,
3023 + },
3024 + {
3025 + .name = "eth1_irq",
3026 + .flags = IORESOURCE_IRQ,
3027 + }
3028 +};
3029 +
3030 +static struct platform_device ar231x_eth[] = {
3031 + {
3032 + .id = 0,
3033 + .name = "ar231x-eth",
3034 + .resource = ar231x_eth0_res,
3035 + .num_resources = ARRAY_SIZE(ar231x_eth0_res)
3036 + },
3037 + {
3038 + .id = 1,
3039 + .name = "ar231x-eth",
3040 + .resource = ar231x_eth1_res,
3041 + .num_resources = ARRAY_SIZE(ar231x_eth1_res)
3042 + }
3043 +};
3044 +
3045 +static struct resource ar231x_wmac0_res[] = {
3046 + {
3047 + .name = "wmac0_membase",
3048 + .flags = IORESOURCE_MEM,
3049 + },
3050 + {
3051 + .name = "wmac0_irq",
3052 + .flags = IORESOURCE_IRQ,
3053 + }
3054 +};
3055 +
3056 +static struct resource ar231x_wmac1_res[] = {
3057 + {
3058 + .name = "wmac1_membase",
3059 + .flags = IORESOURCE_MEM,
3060 + },
3061 + {
3062 + .name = "wmac1_irq",
3063 + .flags = IORESOURCE_IRQ,
3064 + }
3065 +};
3066 +
3067 +
3068 +static struct platform_device ar231x_wmac[] = {
3069 + {
3070 + .id = 0,
3071 + .name = "ar231x-wmac",
3072 + .resource = ar231x_wmac0_res,
3073 + .num_resources = ARRAY_SIZE(ar231x_wmac0_res),
3074 + .dev.platform_data = &ar231x_board,
3075 + },
3076 + {
3077 + .id = 1,
3078 + .name = "ar231x-wmac",
3079 + .resource = ar231x_wmac1_res,
3080 + .num_resources = ARRAY_SIZE(ar231x_wmac1_res),
3081 + .dev.platform_data = &ar231x_board,
3082 + },
3083 +};
3084 +
3085 +static const char *devtype_strings[] = {
3086 + [DEV_TYPE_AR5312] = "Atheros AR5312",
3087 + [DEV_TYPE_AR2312] = "Atheros AR2312",
3088 + [DEV_TYPE_AR2313] = "Atheros AR2313",
3089 + [DEV_TYPE_AR2315] = "Atheros AR2315",
3090 + [DEV_TYPE_AR2316] = "Atheros AR2316",
3091 + [DEV_TYPE_AR2317] = "Atheros AR2317",
3092 + [DEV_TYPE_UNKNOWN] = "Atheros (unknown)",
3093 +};
3094 +
3095 +const char *get_system_type(void)
3096 +{
3097 + if ((ar231x_devtype >= ARRAY_SIZE(devtype_strings)) ||
3098 + !devtype_strings[ar231x_devtype])
3099 + return devtype_strings[DEV_TYPE_UNKNOWN];
3100 + return devtype_strings[ar231x_devtype];
3101 +}
3102 +
3103 +
3104 +int __init
3105 +ar231x_add_ethernet(int nr, u32 base, int irq, void *pdata)
3106 +{
3107 + struct resource *res;
3108 +
3109 + ar231x_eth[nr].dev.platform_data = pdata;
3110 + res = &ar231x_eth[nr].resource[0];
3111 + res->start = base;
3112 + res->end = base + 0x2000 - 1;
3113 + res++;
3114 + res->start = irq;
3115 + res->end = irq;
3116 + return platform_device_register(&ar231x_eth[nr]);
3117 +}
3118 +
3119 +void __init
3120 +ar231x_serial_setup(u32 mapbase, unsigned int uartclk)
3121 +{
3122 + struct uart_port s;
3123 +
3124 + memset(&s, 0, sizeof(s));
3125 +
3126 + s.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
3127 + s.iotype = UPIO_MEM;
3128 + s.irq = AR531X_MISC_IRQ_UART0;
3129 + s.regshift = 2;
3130 + s.mapbase = mapbase;
3131 + s.uartclk = uartclk;
3132 + s.membase = (void __iomem *)s.mapbase;
3133 +
3134 + early_serial_setup(&s);
3135 +}
3136 +
3137 +int __init
3138 +ar231x_add_wmac(int nr, u32 base, int irq)
3139 +{
3140 + struct resource *res;
3141 +
3142 + ar231x_wmac[nr].dev.platform_data = &ar231x_board;
3143 + res = &ar231x_wmac[nr].resource[0];
3144 + res->start = base;
3145 + res->end = base + 0x10000 - 1;
3146 + res++;
3147 + res->start = irq;
3148 + res->end = irq;
3149 + return platform_device_register(&ar231x_wmac[nr]);
3150 +}
3151 +
3152 +static int __init ar231x_register_devices(void)
3153 +{
3154 + ar5312_init_devices();
3155 + ar2315_init_devices();
3156 +
3157 + return 0;
3158 +}
3159 +
3160 +device_initcall(ar231x_register_devices);