bcm53xx: add linux 4.4 support
[openwrt/svn-archive/archive.git] / target / linux / bcm53xx / patches-4.4 / 050-ARM-dts-enable-clock-support-for-BCM5301X.patch
1 From e96ef422d0095fe9ae39b03c0805a0db8ff7e382 Mon Sep 17 00:00:00 2001
2 From: Jon Mason <jonmason@broadcom.com>
3 Date: Tue, 13 Oct 2015 17:22:25 -0400
4 Subject: [PATCH 50/50] ARM: dts: enable clock support for BCM5301X
5
6 Replace current device tree dummy clocks with real clock support for
7 Broadcom Northstar SoCs.
8
9 Signed-off-by: Jon Mason <jonmason@broadcom.com>
10 ---
11 arch/arm/boot/dts/bcm5301x.dtsi | 88 ++++++++++++++++++++++++++++++++---------
12 1 file changed, 69 insertions(+), 19 deletions(-)
13
14 --- a/arch/arm/boot/dts/bcm5301x.dtsi
15 +++ b/arch/arm/boot/dts/bcm5301x.dtsi
16 @@ -8,6 +8,7 @@
17 * Licensed under the GNU/GPL. See COPYING for details.
18 */
19
20 +#include <dt-bindings/clock/bcm-nsp.h>
21 #include <dt-bindings/gpio/gpio.h>
22 #include <dt-bindings/input/input.h>
23 #include <dt-bindings/interrupt-controller/irq.h>
24 @@ -42,41 +43,48 @@
25
26 mpcore {
27 compatible = "simple-bus";
28 - ranges = <0x00000000 0x19020000 0x00003000>;
29 + ranges = <0x00000000 0x19000000 0x00023000>;
30 #address-cells = <1>;
31 #size-cells = <1>;
32
33 - scu@0000 {
34 + a9pll: arm_clk@00000 {
35 + #clock-cells = <0>;
36 + compatible = "brcm,nsp-armpll";
37 + clocks = <&osc>;
38 + reg = <0x00000 0x1000>;
39 + };
40 +
41 + scu@20000 {
42 compatible = "arm,cortex-a9-scu";
43 - reg = <0x0000 0x100>;
44 + reg = <0x20000 0x100>;
45 };
46
47 - timer@0200 {
48 + timer@20200 {
49 compatible = "arm,cortex-a9-global-timer";
50 - reg = <0x0200 0x100>;
51 + reg = <0x20200 0x100>;
52 interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
53 - clocks = <&clk_periph>;
54 + clocks = <&periph_clk>;
55 };
56
57 - local-timer@0600 {
58 + local-timer@20600 {
59 compatible = "arm,cortex-a9-twd-timer";
60 - reg = <0x0600 0x100>;
61 + reg = <0x20600 0x100>;
62 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
63 - clocks = <&clk_periph>;
64 + clocks = <&periph_clk>;
65 };
66
67 - gic: interrupt-controller@1000 {
68 + gic: interrupt-controller@21000 {
69 compatible = "arm,cortex-a9-gic";
70 #interrupt-cells = <3>;
71 #address-cells = <0>;
72 interrupt-controller;
73 - reg = <0x1000 0x1000>,
74 - <0x0100 0x100>;
75 + reg = <0x21000 0x1000>,
76 + <0x20100 0x100>;
77 };
78
79 - L2: cache-controller@2000 {
80 + L2: cache-controller@22000 {
81 compatible = "arm,pl310-cache";
82 - reg = <0x2000 0x1000>;
83 + reg = <0x22000 0x1000>;
84 cache-unified;
85 arm,shared-override;
86 prefetch-data = <1>;
87 @@ -94,14 +102,37 @@
88
89 clocks {
90 #address-cells = <1>;
91 - #size-cells = <0>;
92 + #size-cells = <1>;
93 + ranges;
94
95 - /* As long as we do not have a real clock driver us this
96 - * fixed clock */
97 - clk_periph: periph {
98 + osc: oscillator {
99 + #clock-cells = <0>;
100 compatible = "fixed-clock";
101 + clock-frequency = <25000000>;
102 + };
103 +
104 + iprocmed: iprocmed {
105 #clock-cells = <0>;
106 - clock-frequency = <400000000>;
107 + compatible = "fixed-factor-clock";
108 + clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>;
109 + clock-div = <2>;
110 + clock-mult = <1>;
111 + };
112 +
113 + iprocslow: iprocslow {
114 + #clock-cells = <0>;
115 + compatible = "fixed-factor-clock";
116 + clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>;
117 + clock-div = <4>;
118 + clock-mult = <1>;
119 + };
120 +
121 + periph_clk: periph_clk {
122 + #clock-cells = <0>;
123 + compatible = "fixed-factor-clock";
124 + clocks = <&a9pll>;
125 + clock-div = <2>;
126 + clock-mult = <1>;
127 };
128 };
129
130 @@ -189,4 +220,23 @@
131
132 brcm,nand-has-wp;
133 };
134 +
135 + lcpll0: lcpll0@1800c100 {
136 + #clock-cells = <1>;
137 + compatible = "brcm,nsp-lcpll0";
138 + reg = <0x1800c100 0x14>;
139 + clocks = <&osc>;
140 + clock-output-names = "lcpll0", "pcie_phy", "sdio",
141 + "ddr_phy";
142 + };
143 +
144 + genpll: genpll@1800c140 {
145 + #clock-cells = <1>;
146 + compatible = "brcm,nsp-genpll";
147 + reg = <0x1800c140 0x24>;
148 + clocks = <&osc>;
149 + clock-output-names = "genpll", "phy", "ethernetclk",
150 + "usbclk", "iprocfast", "sata1",
151 + "sata2";
152 + };
153 };