bcm53xx: use backported versiions or R8000 & dt-bindings patches
[openwrt/svn-archive/archive.git] / target / linux / bcm53xx / patches-4.4 / 082-dt-bindings-add-SMP-enable-method-for-Broadcom-NSP.patch
1 From fa20071c74be69a1d84df85e5d1e72a40a156b89 Mon Sep 17 00:00:00 2001
2 From: Kapil Hali <kapilh@broadcom.com>
3 Date: Tue, 1 Dec 2015 11:24:05 -0500
4 Subject: [PATCH] dt-bindings: add SMP enable-method for Broadcom NSP
5
6 Add a compatible string "brcm,bcm-nsp-smp" for Broadcom's
7 Northstar Plus CPU to the 32-bit ARM CPU device tree binding
8 documentation file and create a new binding documentation for
9 Northstar Plus CPU.
10
11 Signed-off-by: Kapil Hali <kapilh@broadcom.com>
12 Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
13 ---
14 .../bindings/arm/bcm/brcm,nsp-cpu-method.txt | 39 ++++++++++++++++++++++
15 Documentation/devicetree/bindings/arm/cpus.txt | 1 +
16 2 files changed, 40 insertions(+)
17 create mode 100644 Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt
18
19 --- /dev/null
20 +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt
21 @@ -0,0 +1,39 @@
22 +Broadcom Northstar Plus SoC CPU Enable Method
23 +---------------------------------------------
24 +This binding defines the enable method used for starting secondary
25 +CPUs in the following Broadcom SoCs:
26 + BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312
27 +
28 +The enable method is specified by defining the following required
29 +properties in the "cpus" device tree node:
30 + - enable-method = "brcm,bcm-nsp-smp";
31 + - secondary-boot-reg = <...>;
32 +
33 +The secondary-boot-reg property is a u32 value that specifies the
34 +physical address of the register which should hold the common
35 +entry point for a secondary CPU. This entry is cpu node specific
36 +and should be added per cpu. E.g., in case of NSP (BCM58625) which
37 +is a dual core CPU SoC, this entry should be added to cpu1 node.
38 +
39 +
40 +Example:
41 + cpus {
42 + #address-cells = <1>;
43 + #size-cells = <0>;
44 + enable-method = "brcm,bcm-nsp-smp";
45 +
46 + cpu0: cpu@0 {
47 + device_type = "cpu";
48 + compatible = "arm,cortex-a9";
49 + next-level-cache = <&L2>;
50 + reg = <0>;
51 + };
52 +
53 + cpu1: cpu@1 {
54 + device_type = "cpu";
55 + compatible = "arm,cortex-a9";
56 + next-level-cache = <&L2>;
57 + reg = <1>;
58 + secondary-boot-reg = <0xffff042c>;
59 + };
60 + };
61 --- a/Documentation/devicetree/bindings/arm/cpus.txt
62 +++ b/Documentation/devicetree/bindings/arm/cpus.txt
63 @@ -190,6 +190,7 @@ nodes to be present and contain the properties described below.
64 "allwinner,sun6i-a31"
65 "allwinner,sun8i-a23"
66 "arm,psci"
67 + "brcm,bcm-nsp-smp"
68 "brcm,brahma-b15"
69 "marvell,armada-375-smp"
70 "marvell,armada-380-smp"