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[openwrt/svn-archive/archive.git] / target / linux / brcm-2.4 / patches / 001-bcm47xx.patch
1 diff -urN linux.old/arch/mips/bcm947xx/bcmsrom.c linux.dev/arch/mips/bcm947xx/bcmsrom.c
2 --- linux.old/arch/mips/bcm947xx/bcmsrom.c 1970-01-01 01:00:00.000000000 +0100
3 +++ linux.dev/arch/mips/bcm947xx/bcmsrom.c 2006-10-02 21:19:59.000000000 +0200
4 @@ -0,0 +1,1213 @@
5 +/*
6 + * Misc useful routines to access NIC SROM/OTP .
7 + *
8 + * Copyright 2006, Broadcom Corporation
9 + * All Rights Reserved.
10 + *
11 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
12 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
13 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
14 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
15 + * $Id: bcmsrom.c,v 1.1.1.14 2006/04/15 01:28:25 michael Exp $
16 + */
17 +
18 +#include <typedefs.h>
19 +#include <bcmdefs.h>
20 +#include <osl.h>
21 +#include <bcmutils.h>
22 +#include <bcmsrom.h>
23 +#include <bcmdevs.h>
24 +#include <bcmendian.h>
25 +#include <sbpcmcia.h>
26 +#include <pcicfg.h>
27 +#include <sbutils.h>
28 +#include <bcmnvram.h>
29 +
30 +/* debug/trace */
31 +#if defined(WLTEST)
32 +#define BS_ERROR(args) printf args
33 +#else
34 +#define BS_ERROR(args)
35 +#endif /* BCMDBG_ERR || WLTEST */
36 +
37 +#define VARS_MAX 4096 /* should be reduced */
38 +
39 +#define WRITE_ENABLE_DELAY 500 /* 500 ms after write enable/disable toggle */
40 +#define WRITE_WORD_DELAY 20 /* 20 ms between each word write */
41 +
42 +static int initvars_srom_pci(void *sbh, void *curmap, char **vars, uint *count);
43 +static int initvars_cis_pcmcia(void *sbh, osl_t *osh, char **vars, uint *count);
44 +static int initvars_flash_sb(void *sbh, char **vars, uint *count);
45 +static int srom_parsecis(osl_t *osh, uint8 **pcis, uint ciscnt, char **vars, uint *count);
46 +static int sprom_cmd_pcmcia(osl_t *osh, uint8 cmd);
47 +static int sprom_read_pcmcia(osl_t *osh, uint16 addr, uint16 *data);
48 +static int sprom_write_pcmcia(osl_t *osh, uint16 addr, uint16 data);
49 +static int sprom_read_pci(osl_t *osh, uint16 *sprom, uint wordoff, uint16 *buf, uint nwords,
50 + bool check_crc);
51 +
52 +static int initvars_table(osl_t *osh, char *start, char *end, char **vars, uint *count);
53 +static int initvars_flash(osl_t *osh, char **vp, uint len, char *devpath);
54 +
55 +/*
56 + * Initialize local vars from the right source for this platform.
57 + * Return 0 on success, nonzero on error.
58 + */
59 +int
60 +srom_var_init(void *sbh, uint bustype, void *curmap, osl_t *osh, char **vars, uint *count)
61 +{
62 + ASSERT(bustype == BUSTYPE(bustype));
63 + if (vars == NULL || count == NULL)
64 + return (0);
65 +
66 + switch (BUSTYPE(bustype)) {
67 + case SB_BUS:
68 + case JTAG_BUS:
69 + return initvars_flash_sb(sbh, vars, count);
70 +
71 + case PCI_BUS:
72 + ASSERT(curmap); /* can not be NULL */
73 + return initvars_srom_pci(sbh, curmap, vars, count);
74 +
75 + case PCMCIA_BUS:
76 + return initvars_cis_pcmcia(sbh, osh, vars, count);
77 +
78 +
79 + default:
80 + ASSERT(0);
81 + }
82 + return (-1);
83 +}
84 +
85 +/* support only 16-bit word read from srom */
86 +int
87 +srom_read(uint bustype, void *curmap, osl_t *osh, uint byteoff, uint nbytes, uint16 *buf)
88 +{
89 + void *srom;
90 + uint i, off, nw;
91 +
92 + ASSERT(bustype == BUSTYPE(bustype));
93 +
94 + /* check input - 16-bit access only */
95 + if (byteoff & 1 || nbytes & 1 || (byteoff + nbytes) > (SPROM_SIZE * 2))
96 + return 1;
97 +
98 + off = byteoff / 2;
99 + nw = nbytes / 2;
100 +
101 + if (BUSTYPE(bustype) == PCI_BUS) {
102 + if (!curmap)
103 + return 1;
104 + srom = (uchar*)curmap + PCI_BAR0_SPROM_OFFSET;
105 + if (sprom_read_pci(osh, srom, off, buf, nw, FALSE))
106 + return 1;
107 + } else if (BUSTYPE(bustype) == PCMCIA_BUS) {
108 + for (i = 0; i < nw; i++) {
109 + if (sprom_read_pcmcia(osh, (uint16)(off + i), (uint16*)(buf + i)))
110 + return 1;
111 + }
112 + } else {
113 + return 1;
114 + }
115 +
116 + return 0;
117 +}
118 +
119 +/* support only 16-bit word write into srom */
120 +int
121 +srom_write(uint bustype, void *curmap, osl_t *osh, uint byteoff, uint nbytes, uint16 *buf)
122 +{
123 + uint16 *srom;
124 + uint i, nw, crc_range;
125 + uint16 image[SPROM_SIZE];
126 + uint8 crc;
127 + volatile uint32 val32;
128 +
129 + ASSERT(bustype == BUSTYPE(bustype));
130 +
131 + /* check input - 16-bit access only */
132 + if (byteoff & 1 || nbytes & 1 || (byteoff + nbytes) > (SPROM_SIZE * 2))
133 + return 1;
134 +
135 + /* Are we writing the whole thing at once? */
136 + if ((byteoff == 0) &&
137 + ((nbytes == SPROM_SIZE) ||
138 + (nbytes == (SPROM_CRC_RANGE * 2)) ||
139 + (nbytes == (SROM4_WORDS * 2)))) {
140 + crc_range = nbytes;
141 + bcopy((void*)buf, (void*)image, nbytes);
142 + nw = nbytes / 2;
143 + } else {
144 + if ((BUSTYPE(bustype) == PCMCIA_BUS) || (BUSTYPE(bustype) == SDIO_BUS))
145 + crc_range = SPROM_SIZE;
146 + else
147 + crc_range = SPROM_CRC_RANGE * 2; /* Tentative */
148 +
149 + nw = crc_range / 2;
150 + /* read first 64 words from srom */
151 + if (srom_read(bustype, curmap, osh, 0, crc_range, image))
152 + return 1;
153 + if (image[SROM4_SIGN] == SROM4_SIGNATURE) {
154 + crc_range = SROM4_WORDS;
155 + nw = crc_range / 2;
156 + if (srom_read(bustype, curmap, osh, 0, crc_range, image))
157 + return 1;
158 + }
159 + /* make changes */
160 + bcopy((void*)buf, (void*)&image[byteoff / 2], nbytes);
161 + }
162 +
163 + /* calculate crc */
164 + htol16_buf(image, crc_range);
165 + crc = ~hndcrc8((uint8 *)image, crc_range - 1, CRC8_INIT_VALUE);
166 + ltoh16_buf(image, crc_range);
167 + image[(crc_range / 2) - 1] = (crc << 8) | (image[(crc_range / 2) - 1] & 0xff);
168 +
169 + if (BUSTYPE(bustype) == PCI_BUS) {
170 + srom = (uint16*)((uchar*)curmap + PCI_BAR0_SPROM_OFFSET);
171 + /* enable writes to the SPROM */
172 + val32 = OSL_PCI_READ_CONFIG(osh, PCI_SPROM_CONTROL, sizeof(uint32));
173 + val32 |= SPROM_WRITEEN;
174 + OSL_PCI_WRITE_CONFIG(osh, PCI_SPROM_CONTROL, sizeof(uint32), val32);
175 + bcm_mdelay(WRITE_ENABLE_DELAY);
176 + /* write srom */
177 + for (i = 0; i < nw; i++) {
178 + W_REG(osh, &srom[i], image[i]);
179 + bcm_mdelay(WRITE_WORD_DELAY);
180 + }
181 + /* disable writes to the SPROM */
182 + OSL_PCI_WRITE_CONFIG(osh, PCI_SPROM_CONTROL, sizeof(uint32), val32 &
183 + ~SPROM_WRITEEN);
184 + } else if (BUSTYPE(bustype) == PCMCIA_BUS) {
185 + /* enable writes to the SPROM */
186 + if (sprom_cmd_pcmcia(osh, SROM_WEN))
187 + return 1;
188 + bcm_mdelay(WRITE_ENABLE_DELAY);
189 + /* write srom */
190 + for (i = 0; i < nw; i++) {
191 + sprom_write_pcmcia(osh, (uint16)(i), image[i]);
192 + bcm_mdelay(WRITE_WORD_DELAY);
193 + }
194 + /* disable writes to the SPROM */
195 + if (sprom_cmd_pcmcia(osh, SROM_WDS))
196 + return 1;
197 + } else {
198 + return 1;
199 + }
200 +
201 + bcm_mdelay(WRITE_ENABLE_DELAY);
202 + return 0;
203 +}
204 +
205 +
206 +static int
207 +srom_parsecis(osl_t *osh, uint8 **pcis, uint ciscnt, char **vars, uint *count)
208 +{
209 + char eabuf[32];
210 + char *vp, *base;
211 + uint8 *cis, tup, tlen, sromrev = 1;
212 + int i, j;
213 + uint varsize;
214 + bool ag_init = FALSE;
215 + uint32 w32;
216 +
217 + ASSERT(vars);
218 + ASSERT(count);
219 +
220 + base = vp = MALLOC(osh, VARS_MAX);
221 + ASSERT(vp);
222 + if (!vp)
223 + return -2;
224 +
225 + while (ciscnt--) {
226 + cis = *pcis++;
227 + i = 0;
228 + do {
229 + tup = cis[i++];
230 + tlen = cis[i++];
231 + if ((i + tlen) >= CIS_SIZE)
232 + break;
233 +
234 + switch (tup) {
235 + case CISTPL_MANFID:
236 + vp += sprintf(vp, "manfid=%d", (cis[i + 1] << 8) + cis[i]);
237 + vp++;
238 + vp += sprintf(vp, "prodid=%d", (cis[i + 3] << 8) + cis[i + 2]);
239 + vp++;
240 + break;
241 +
242 + case CISTPL_FUNCE:
243 + switch (cis[i]) {
244 + case LAN_NID:
245 + ASSERT(cis[i + 1] == 6);
246 + bcm_ether_ntoa((struct ether_addr *)&cis[i + 2], eabuf);
247 + vp += sprintf(vp, "il0macaddr=%s", eabuf);
248 + vp++;
249 + break;
250 + case 1: /* SDIO Extended Data */
251 + vp += sprintf(vp, "sdmaxblk=%d",
252 + (cis[i + 13] << 8) | cis[i + 12]);
253 + vp++;
254 + break;
255 + }
256 + break;
257 +
258 + case CISTPL_CFTABLE:
259 + vp += sprintf(vp, "regwindowsz=%d", (cis[i + 7] << 8) | cis[i + 6]);
260 + vp++;
261 + break;
262 +
263 + case CISTPL_BRCM_HNBU:
264 + switch (cis[i]) {
265 + case HNBU_SROMREV:
266 + sromrev = cis[i + 1];
267 + break;
268 +
269 + case HNBU_CHIPID:
270 + vp += sprintf(vp, "vendid=%d", (cis[i + 2] << 8) +
271 + cis[i + 1]);
272 + vp++;
273 + vp += sprintf(vp, "devid=%d", (cis[i + 4] << 8) +
274 + cis[i + 3]);
275 + vp++;
276 + if (tlen == 7) {
277 + vp += sprintf(vp, "chiprev=%d",
278 + (cis[i + 6] << 8) + cis[i + 5]);
279 + vp++;
280 + }
281 + break;
282 +
283 + case HNBU_BOARDREV:
284 + vp += sprintf(vp, "boardrev=%d", cis[i + 1]);
285 + vp++;
286 + break;
287 +
288 + case HNBU_AA:
289 + vp += sprintf(vp, "aa2g=%d", cis[i + 1]);
290 + vp++;
291 + break;
292 +
293 + case HNBU_AG:
294 + vp += sprintf(vp, "ag0=%d", cis[i + 1]);
295 + vp++;
296 + ag_init = TRUE;
297 + break;
298 +
299 + case HNBU_CC:
300 + ASSERT(sromrev == 1);
301 + vp += sprintf(vp, "cc=%d", cis[i + 1]);
302 + vp++;
303 + break;
304 +
305 + case HNBU_PAPARMS:
306 + if (tlen == 2) {
307 + ASSERT(sromrev == 1);
308 + vp += sprintf(vp, "pa0maxpwr=%d", cis[i + 1]);
309 + vp++;
310 + } else if (tlen >= 9) {
311 + if (tlen == 10) {
312 + ASSERT(sromrev == 2);
313 + vp += sprintf(vp, "opo=%d", cis[i + 9]);
314 + vp++;
315 + } else
316 + ASSERT(tlen == 9);
317 +
318 + for (j = 0; j < 3; j++) {
319 + vp += sprintf(vp, "pa0b%d=%d", j,
320 + (cis[i + (j * 2) + 2] << 8) +
321 + cis[i + (j * 2) + 1]);
322 + vp++;
323 + }
324 + vp += sprintf(vp, "pa0itssit=%d", cis[i + 7]);
325 + vp++;
326 + vp += sprintf(vp, "pa0maxpwr=%d", cis[i + 8]);
327 + vp++;
328 + } else
329 + ASSERT(tlen >= 9);
330 + break;
331 +
332 + case HNBU_OEM:
333 + ASSERT(sromrev == 1);
334 + vp += sprintf(vp, "oem=%02x%02x%02x%02x%02x%02x%02x%02x",
335 + cis[i + 1], cis[i + 2],
336 + cis[i + 3], cis[i + 4],
337 + cis[i + 5], cis[i + 6],
338 + cis[i + 7], cis[i + 8]);
339 + vp++;
340 + break;
341 +
342 + case HNBU_BOARDFLAGS:
343 + w32 = (cis[i + 2] << 8) + cis[i + 1];
344 + if (tlen == 5)
345 + w32 |= (cis[i + 4] << 24) + (cis[i + 3] << 16);
346 + vp += sprintf(vp, "boardflags=0x%x", w32);
347 + vp++;
348 + break;
349 +
350 + case HNBU_LEDS:
351 + if (cis[i + 1] != 0xff) {
352 + vp += sprintf(vp, "ledbh0=%d", cis[i + 1]);
353 + vp++;
354 + }
355 + if (cis[i + 2] != 0xff) {
356 + vp += sprintf(vp, "ledbh1=%d", cis[i + 2]);
357 + vp++;
358 + }
359 + if (cis[i + 3] != 0xff) {
360 + vp += sprintf(vp, "ledbh2=%d", cis[i + 3]);
361 + vp++;
362 + }
363 + if (cis[i + 4] != 0xff) {
364 + vp += sprintf(vp, "ledbh3=%d", cis[i + 4]);
365 + vp++;
366 + }
367 + break;
368 +
369 + case HNBU_CCODE:
370 + {
371 + char str[3];
372 + ASSERT(sromrev > 1);
373 + str[0] = cis[i + 1];
374 + str[1] = cis[i + 2];
375 + str[2] = 0;
376 + vp += sprintf(vp, "ccode=%s", str);
377 + vp++;
378 + vp += sprintf(vp, "cctl=0x%x", cis[i + 3]);
379 + vp++;
380 + break;
381 + }
382 +
383 + case HNBU_CCKPO:
384 + ASSERT(sromrev > 2);
385 + vp += sprintf(vp, "cckpo=0x%x",
386 + (cis[i + 2] << 8) | cis[i + 1]);
387 + vp++;
388 + break;
389 +
390 + case HNBU_OFDMPO:
391 + ASSERT(sromrev > 2);
392 + vp += sprintf(vp, "ofdmpo=0x%x",
393 + (cis[i + 4] << 24) |
394 + (cis[i + 3] << 16) |
395 + (cis[i + 2] << 8) |
396 + cis[i + 1]);
397 + vp++;
398 + break;
399 + }
400 + break;
401 +
402 + }
403 + i += tlen;
404 + } while (tup != 0xff);
405 + }
406 +
407 + /* Set the srom version */
408 + vp += sprintf(vp, "sromrev=%d", sromrev);
409 + vp++;
410 +
411 + /* if there is no antenna gain field, set default */
412 + if (ag_init == FALSE) {
413 + ASSERT(sromrev == 1);
414 + vp += sprintf(vp, "ag0=%d", 0xff);
415 + vp++;
416 + }
417 +
418 + /* final nullbyte terminator */
419 + *vp++ = '\0';
420 + varsize = (uint)(vp - base);
421 +
422 + ASSERT((vp - base) < VARS_MAX);
423 +
424 + if (varsize == VARS_MAX) {
425 + *vars = base;
426 + } else {
427 + vp = MALLOC(osh, varsize);
428 + ASSERT(vp);
429 + if (vp)
430 + bcopy(base, vp, varsize);
431 + MFREE(osh, base, VARS_MAX);
432 + *vars = vp;
433 + if (!vp) {
434 + *count = 0;
435 + return -2;
436 + }
437 + }
438 + *count = varsize;
439 +
440 + return (0);
441 +}
442 +
443 +
444 +/* set PCMCIA sprom command register */
445 +static int
446 +sprom_cmd_pcmcia(osl_t *osh, uint8 cmd)
447 +{
448 + uint8 status = 0;
449 + uint wait_cnt = 1000;
450 +
451 + /* write sprom command register */
452 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_CS, &cmd, 1);
453 +
454 + /* wait status */
455 + while (wait_cnt--) {
456 + OSL_PCMCIA_READ_ATTR(osh, SROM_CS, &status, 1);
457 + if (status & SROM_DONE)
458 + return 0;
459 + }
460 +
461 + return 1;
462 +}
463 +
464 +/* read a word from the PCMCIA srom */
465 +static int
466 +sprom_read_pcmcia(osl_t *osh, uint16 addr, uint16 *data)
467 +{
468 + uint8 addr_l, addr_h, data_l, data_h;
469 +
470 + addr_l = (uint8)((addr * 2) & 0xff);
471 + addr_h = (uint8)(((addr * 2) >> 8) & 0xff);
472 +
473 + /* set address */
474 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_ADDRH, &addr_h, 1);
475 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_ADDRL, &addr_l, 1);
476 +
477 + /* do read */
478 + if (sprom_cmd_pcmcia(osh, SROM_READ))
479 + return 1;
480 +
481 + /* read data */
482 + data_h = data_l = 0;
483 + OSL_PCMCIA_READ_ATTR(osh, SROM_DATAH, &data_h, 1);
484 + OSL_PCMCIA_READ_ATTR(osh, SROM_DATAL, &data_l, 1);
485 +
486 + *data = (data_h << 8) | data_l;
487 + return 0;
488 +}
489 +
490 +/* write a word to the PCMCIA srom */
491 +static int
492 +sprom_write_pcmcia(osl_t *osh, uint16 addr, uint16 data)
493 +{
494 + uint8 addr_l, addr_h, data_l, data_h;
495 +
496 + addr_l = (uint8)((addr * 2) & 0xff);
497 + addr_h = (uint8)(((addr * 2) >> 8) & 0xff);
498 + data_l = (uint8)(data & 0xff);
499 + data_h = (uint8)((data >> 8) & 0xff);
500 +
501 + /* set address */
502 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_ADDRH, &addr_h, 1);
503 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_ADDRL, &addr_l, 1);
504 +
505 + /* write data */
506 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_DATAH, &data_h, 1);
507 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_DATAL, &data_l, 1);
508 +
509 + /* do write */
510 + return sprom_cmd_pcmcia(osh, SROM_WRITE);
511 +}
512 +
513 +/*
514 + * Read in and validate sprom.
515 + * Return 0 on success, nonzero on error.
516 + */
517 +static int
518 +sprom_read_pci(osl_t *osh, uint16 *sprom, uint wordoff, uint16 *buf, uint nwords, bool check_crc)
519 +{
520 + int err = 0;
521 + uint i;
522 +
523 + /* read the sprom */
524 + for (i = 0; i < nwords; i++)
525 + buf[i] = R_REG(osh, &sprom[wordoff + i]);
526 +
527 + if (check_crc) {
528 + /* fixup the endianness so crc8 will pass */
529 + htol16_buf(buf, nwords * 2);
530 + if (hndcrc8((uint8*)buf, nwords * 2, CRC8_INIT_VALUE) != CRC8_GOOD_VALUE)
531 + err = 1;
532 + /* now correct the endianness of the byte array */
533 + ltoh16_buf(buf, nwords * 2);
534 + }
535 +
536 + return err;
537 +}
538 +
539 +/*
540 +* Create variable table from memory.
541 +* Return 0 on success, nonzero on error.
542 +*/
543 +static int
544 +initvars_table(osl_t *osh, char *start, char *end, char **vars, uint *count)
545 +{
546 + int c = (int)(end - start);
547 +
548 + /* do it only when there is more than just the null string */
549 + if (c > 1) {
550 + char *vp = MALLOC(osh, c);
551 + ASSERT(vp);
552 + if (!vp)
553 + return BCME_NOMEM;
554 + bcopy(start, vp, c);
555 + *vars = vp;
556 + *count = c;
557 + }
558 + else {
559 + *vars = NULL;
560 + *count = 0;
561 + }
562 +
563 + return 0;
564 +}
565 +
566 +/*
567 + * Find variables with <devpath> from flash. 'base' points to the beginning
568 + * of the table upon enter and to the end of the table upon exit when success.
569 + * Return 0 on success, nonzero on error.
570 + */
571 +static int
572 +initvars_flash(osl_t *osh, char **base, uint len, char *devpath)
573 +{
574 + char *vp = *base;
575 + char *flash;
576 + int err;
577 + char *s;
578 + uint l, dl, copy_len;
579 +
580 + /* allocate memory and read in flash */
581 + if (!(flash = MALLOC(osh, NVRAM_SPACE)))
582 + return BCME_NOMEM;
583 + if ((err = nvram_getall(flash, NVRAM_SPACE)))
584 + goto exit;
585 +
586 + /* grab vars with the <devpath> prefix in name */
587 + dl = strlen(devpath);
588 + for (s = flash; s && *s; s += l + 1) {
589 + l = strlen(s);
590 +
591 + /* skip non-matching variable */
592 + if (strncmp(s, devpath, dl))
593 + continue;
594 +
595 + /* is there enough room to copy? */
596 + copy_len = l - dl + 1;
597 + if (len < copy_len) {
598 + err = BCME_BUFTOOSHORT;
599 + goto exit;
600 + }
601 +
602 + /* no prefix, just the name=value */
603 + strcpy(vp, &s[dl]);
604 + vp += copy_len;
605 + len -= copy_len;
606 + }
607 +
608 + /* add null string as terminator */
609 + if (len < 1) {
610 + err = BCME_BUFTOOSHORT;
611 + goto exit;
612 + }
613 + *vp++ = '\0';
614 +
615 + *base = vp;
616 +
617 +exit: MFREE(osh, flash, NVRAM_SPACE);
618 + return err;
619 +}
620 +
621 +/*
622 + * Initialize nonvolatile variable table from flash.
623 + * Return 0 on success, nonzero on error.
624 + */
625 +static int
626 +initvars_flash_sb(void *sbh, char **vars, uint *count)
627 +{
628 + osl_t *osh = sb_osh(sbh);
629 + char devpath[SB_DEVPATH_BUFSZ];
630 + char *vp, *base;
631 + int err;
632 +
633 + ASSERT(vars);
634 + ASSERT(count);
635 +
636 + if ((err = sb_devpath(sbh, devpath, sizeof(devpath))))
637 + return err;
638 +
639 + base = vp = MALLOC(osh, VARS_MAX);
640 + ASSERT(vp);
641 + if (!vp)
642 + return BCME_NOMEM;
643 +
644 + if ((err = initvars_flash(osh, &vp, VARS_MAX, devpath)))
645 + goto err;
646 +
647 + err = initvars_table(osh, base, vp, vars, count);
648 +
649 +err: MFREE(osh, base, VARS_MAX);
650 + return err;
651 +}
652 +
653 +#ifdef WLTEST
654 +char mfgsromvars[256];
655 +char *defaultsromvars = "il0macaddr=00:11:22:33:44:51\0"
656 + "et0macaddr=00:11:22:33:44:52\0"
657 + "et1macaddr=00:11:22:33:44:53\0"
658 + "boardtype=0xffff\0"
659 + "boardrev=0x10\0"
660 + "boardflags=8\0"
661 + "sromrev=2\0"
662 + "aa2g=3";
663 +#define MFGSROM_DEFVARSLEN 147 /* default srom len */
664 +#endif /* WL_TEST */
665 +
666 +/*
667 + * Initialize nonvolatile variable table from sprom.
668 + * Return 0 on success, nonzero on error.
669 + */
670 +static int
671 +initvars_srom_pci(void *sbh, void *curmap, char **vars, uint *count)
672 +{
673 + uint16 w, *b;
674 + uint8 sromrev = 0;
675 + struct ether_addr ea;
676 + char eabuf[32];
677 + uint32 w32;
678 + int woff, i;
679 + char *vp, *base;
680 + osl_t *osh = sb_osh(sbh);
681 + bool flash = FALSE;
682 + char name[SB_DEVPATH_BUFSZ+16], *value;
683 + char devpath[SB_DEVPATH_BUFSZ];
684 + int err;
685 +
686 + /*
687 + * Apply CRC over SROM content regardless SROM is present or not,
688 + * and use variable <devpath>sromrev's existance in flash to decide
689 + * if we should return an error when CRC fails or read SROM variables
690 + * from flash.
691 + */
692 + b = MALLOC(osh, SROM_MAX);
693 + ASSERT(b);
694 + if (!b)
695 + return -2;
696 +
697 + err = sprom_read_pci(osh, (void*)((int8*)curmap + PCI_BAR0_SPROM_OFFSET), 0, b,
698 + 64, TRUE);
699 + if (b[SROM4_SIGN] == SROM4_SIGNATURE) {
700 + /* sromrev >= 4, read more */
701 + err = sprom_read_pci(osh, (void*)((int8*)curmap + PCI_BAR0_SPROM_OFFSET), 0, b, SROM4_WORDS, TRUE);
702 + sromrev = b[SROM4_WORDS - 1] & 0xff;
703 + } else if (err == 0) {
704 + /* srom is good and is rev < 4 */
705 + /* top word of sprom contains version and crc8 */
706 + sromrev = b[63] & 0xff;
707 + /* bcm4401 sroms misprogrammed */
708 + if (sromrev == 0x10)
709 + sromrev = 1;
710 + }
711 +
712 + if (err) {
713 +#ifdef WLTEST
714 + BS_ERROR(("SROM Crc Error, so see if we could use a default\n"));
715 + w32 = OSL_PCI_READ_CONFIG(osh, PCI_SPROM_CONTROL, sizeof(uint32));
716 + if (w32 & SPROM_OTPIN_USE) {
717 + BS_ERROR(("srom crc failed with OTP, use default vars....\n"));
718 + vp = base = mfgsromvars;
719 + if (sb_chip(sbh) == BCM4311_CHIP_ID) {
720 + BS_ERROR(("setting the devid to be 4311\n"));
721 + vp += sprintf(vp, "devid=0x4311");
722 + vp++;
723 + }
724 + bcopy(defaultsromvars, vp, MFGSROM_DEFVARSLEN);
725 + vp += MFGSROM_DEFVARSLEN;
726 + goto varsdone;
727 + } else {
728 + BS_ERROR(("srom crc failed with SPROM....\n"));
729 +#endif /* WLTEST */
730 + if ((err = sb_devpath(sbh, devpath, sizeof(devpath))))
731 + return err;
732 + sprintf(name, "%ssromrev", devpath);
733 + if (!(value = getvar(NULL, name)))
734 + return (-1);
735 + sromrev = (uint8)bcm_strtoul(value, NULL, 0);
736 + flash = TRUE;
737 +#ifdef WLTEST
738 + }
739 +#endif /* WLTEST */
740 + }
741 +
742 + /* srom version check */
743 + if (sromrev > 4)
744 + return (-2);
745 +
746 + ASSERT(vars);
747 + ASSERT(count);
748 +
749 + base = vp = MALLOC(osh, VARS_MAX);
750 + ASSERT(vp);
751 + if (!vp)
752 + return -2;
753 +
754 + /* read variables from flash */
755 + if (flash) {
756 + if ((err = initvars_flash(osh, &vp, VARS_MAX, devpath)))
757 + goto err;
758 + goto varsdone;
759 + }
760 +
761 + vp += sprintf(vp, "sromrev=%d", sromrev);
762 + vp++;
763 +
764 + if (sromrev >= 4) {
765 + uint path, pathbase;
766 + const uint pathbases[MAX_PATH] = {SROM4_PATH0, SROM4_PATH1,
767 + SROM4_PATH2, SROM4_PATH3};
768 +
769 + vp += sprintf(vp, "boardrev=%d", b[SROM4_BREV]);
770 + vp++;
771 +
772 + vp += sprintf(vp, "boardflags=%d", (b[SROM4_BFL1] << 16) | b[SROM4_BFL0]);
773 + vp++;
774 +
775 + vp += sprintf(vp, "boardflags2=%d", (b[SROM4_BFL3] << 16) | b[SROM4_BFL2]);
776 + vp++;
777 +
778 + /* The macaddr */
779 + ea.octet[0] = (b[SROM4_MACHI] >> 8) & 0xff;
780 + ea.octet[1] = b[SROM4_MACHI] & 0xff;
781 + ea.octet[2] = (b[SROM4_MACMID] >> 8) & 0xff;
782 + ea.octet[3] = b[SROM4_MACMID] & 0xff;
783 + ea.octet[4] = (b[SROM4_MACLO] >> 8) & 0xff;
784 + ea.octet[5] = b[SROM4_MACLO] & 0xff;
785 + bcm_ether_ntoa(&ea, eabuf);
786 + vp += sprintf(vp, "macaddr=%s", eabuf);
787 + vp++;
788 +
789 + w = b[SROM4_CCODE];
790 + if (w == 0)
791 + vp += sprintf(vp, "ccode=");
792 + else
793 + vp += sprintf(vp, "ccode=%c%c", (w >> 8), (w & 0xff));
794 + vp++;
795 + vp += sprintf(vp, "regrev=%d", b[SROM4_REGREV]);
796 + vp++;
797 +
798 + w = b[SROM4_LEDBH10];
799 + if ((w != 0) && (w != 0xffff)) {
800 + /* ledbh0 */
801 + vp += sprintf(vp, "ledbh0=%d", (w & 0xff));
802 + vp++;
803 +
804 + /* ledbh1 */
805 + vp += sprintf(vp, "ledbh1=%d", (w >> 8) & 0xff);
806 + vp++;
807 + }
808 + w = b[SROM4_LEDBH32];
809 + if ((w != 0) && (w != 0xffff)) {
810 + /* ledbh2 */
811 + vp += sprintf(vp, "ledbh2=%d", w & 0xff);
812 + vp++;
813 +
814 + /* ledbh3 */
815 + vp += sprintf(vp, "ledbh3=%d", (w >> 8) & 0xff);
816 + vp++;
817 + }
818 + /* LED Powersave duty cycle (oncount >> 24) (offcount >> 8) */
819 + if (w != 0xffff) {
820 + w = b[SROM4_LEDDC];
821 + w32 = ((uint32)((unsigned char)(w >> 8) & 0xff) << 24) | /* oncount */
822 + ((uint32)((unsigned char)(w & 0xff)) << 8); /* offcount */
823 + vp += sprintf(vp, "leddc=%d", w32);
824 + vp++;
825 + }
826 +
827 + w = b[SROM4_AA];
828 + vp += sprintf(vp, "aa2g=%d", w & SROM4_AA2G_MASK);
829 + vp++;
830 + vp += sprintf(vp, "aa5g=%d", w >> SROM4_AA5G_SHIFT);
831 + vp++;
832 +
833 + w = b[SROM4_AG10];
834 + vp += sprintf(vp, "ag0=%d", w & 0xff);
835 + vp++;
836 + vp += sprintf(vp, "ag1=%d", (w >> 8) & 0xff);
837 + vp++;
838 + w = b[SROM4_AG32];
839 + vp += sprintf(vp, "ag2=%d", w & 0xff);
840 + vp++;
841 + vp += sprintf(vp, "ag3=%d", (w >> 8) & 0xff);
842 + vp++;
843 +
844 + /* Fixed power indices when power control is disabled */
845 + for (i = 0; i < 2; i++) {
846 + w = b[SROM4_TXPID2G + i];
847 + vp += sprintf(vp, "txpid2ga%d=%d", 2 * i, w & 0xff);
848 + vp++;
849 + vp += sprintf(vp, "txpid2ga%d=%d", (2 * i) + 1, (w >> 8) & 0xff);
850 + vp++;
851 + w = b[SROM4_TXPID5G + i];
852 + vp += sprintf(vp, "txpid5ga%d=%d", 2 * i, w & 0xff);
853 + vp++;
854 + vp += sprintf(vp, "txpid5ga%d=%d", (2 * i) + 1, (w >> 8) & 0xff);
855 + vp++;
856 + w = b[SROM4_TXPID5GL + i];
857 + vp += sprintf(vp, "txpid5gla%d=%d", 2 * i, w & 0xff);
858 + vp++;
859 + vp += sprintf(vp, "txpid5gla%d=%d", (2 * i) + 1, (w >> 8) & 0xff);
860 + vp++;
861 + w = b[SROM4_TXPID5GH + i];
862 + vp += sprintf(vp, "txpid5gha%d=%d", 2 * i, w & 0xff);
863 + vp++;
864 + vp += sprintf(vp, "txpid5gha%d=%d", (2 * i) + 1, (w >> 8) & 0xff);
865 + vp++;
866 + }
867 +
868 + /* Per path variables */
869 + for (path = 0; path < MAX_PATH; path++) {
870 + pathbase = pathbases[path];
871 + w = b[pathbase + SROM4_2G_ITT_MAXP];
872 + vp += sprintf(vp, "itt2ga%d=%d", path, w >> B2G_ITT_SHIFT);
873 + vp++;
874 + vp += sprintf(vp, "maxp2ga%d=%d", path, w & B2G_MAXP_MASK);
875 + vp++;
876 +
877 + for (i = 0; i < 4; i++) {
878 + vp += sprintf(vp, "pa2gw%da%d=%d", i, path,
879 + b[pathbase + SROM4_2G_PA + i]);
880 + vp++;
881 + }
882 +
883 + w = b[pathbase + SROM4_5G_ITT_MAXP];
884 + vp += sprintf(vp, "itt5ga%d=%d", path, w >> B5G_ITT_SHIFT);
885 + vp++;
886 + vp += sprintf(vp, "maxp5ga%d=%d", path, w & B5G_MAXP_MASK);
887 + vp++;
888 +
889 + w = b[pathbase + SROM4_5GLH_MAXP];
890 + vp += sprintf(vp, "maxp5lga%d=%d", path, w >> B5GL_MAXP_SHIFT);
891 + vp++;
892 + vp += sprintf(vp, "maxp5gha%d=%d", path, w & B5GH_MAXP_MASK);
893 + vp++;
894 +
895 + for (i = 0; i < 4; i++) {
896 + vp += sprintf(vp, "pa5gw%da%d=%d", i, path,
897 + b[pathbase + SROM4_5G_PA + i]);
898 + vp++;
899 + vp += sprintf(vp, "pa5glw%da%d=%d", i, path,
900 + b[pathbase + SROM4_5GL_PA + i]);
901 + vp++;
902 + vp += sprintf(vp, "pa5hgw%da%d=%d", i, path,
903 + b[pathbase + SROM4_5GH_PA + i]);
904 + vp++;
905 + }
906 + }
907 +
908 + vp += sprintf(vp, "cck2gpo=%d", b[SROM4_2G_CCKPO]);
909 + vp++;
910 +
911 + w32 = ((uint32)b[SROM4_2G_OFDMPO + 1] << 16) | b[SROM4_2G_OFDMPO];
912 + vp += sprintf(vp, "ofdm2gpo=%d", w32);
913 + vp++;
914 +
915 + w32 = ((uint32)b[SROM4_5G_OFDMPO + 1] << 16) | b[SROM4_5G_OFDMPO];
916 + vp += sprintf(vp, "ofdm5gpo=%d", w32);
917 + vp++;
918 +
919 + w32 = ((uint32)b[SROM4_5GL_OFDMPO + 1] << 16) | b[SROM4_5GL_OFDMPO];
920 + vp += sprintf(vp, "ofdm5glpo=%d", w32);
921 + vp++;
922 +
923 + w32 = ((uint32)b[SROM4_5GH_OFDMPO + 1] << 16) | b[SROM4_5GH_OFDMPO];
924 + vp += sprintf(vp, "ofdm5ghpo=%d", w32);
925 + vp++;
926 +
927 + for (i = 0; i < 8; i++) {
928 + vp += sprintf(vp, "mcs2gpo%d=%d", i, b[SROM4_2G_MCSPO]);
929 + vp++;
930 + vp += sprintf(vp, "mcs5gpo%d=%d", i, b[SROM4_5G_MCSPO]);
931 + vp++;
932 + vp += sprintf(vp, "mcs5glpo%d=%d", i, b[SROM4_5GL_MCSPO]);
933 + vp++;
934 + vp += sprintf(vp, "mcs5ghpo%d=%d", i, b[SROM4_5GH_MCSPO]);
935 + vp++;
936 + }
937 +
938 + vp += sprintf(vp, "ccdpo%d=%d", i, b[SROM4_CCDPO]);
939 + vp++;
940 + vp += sprintf(vp, "stbcpo%d=%d", i, b[SROM4_STBCPO]);
941 + vp++;
942 + vp += sprintf(vp, "bw40po%d=%d", i, b[SROM4_BW40PO]);
943 + vp++;
944 + vp += sprintf(vp, "bwduppo%d=%d", i, b[SROM4_BWDUPPO]);
945 + vp++;
946 +
947 + goto done;
948 + }
949 + if (sromrev >= 3) {
950 + /* New section takes over the 3th hardware function space */
951 +
952 + /* Words 22+23 are 11a (mid) ofdm power offsets */
953 + w32 = ((uint32)b[23] << 16) | b[22];
954 + vp += sprintf(vp, "ofdmapo=%d", w32);
955 + vp++;
956 +
957 + /* Words 24+25 are 11a (low) ofdm power offsets */
958 + w32 = ((uint32)b[25] << 16) | b[24];
959 + vp += sprintf(vp, "ofdmalpo=%d", w32);
960 + vp++;
961 +
962 + /* Words 26+27 are 11a (high) ofdm power offsets */
963 + w32 = ((uint32)b[27] << 16) | b[26];
964 + vp += sprintf(vp, "ofdmahpo=%d", w32);
965 + vp++;
966 +
967 + /* LED Powersave duty cycle (oncount >> 24) (offcount >> 8) */
968 + w32 = ((uint32)((unsigned char)(b[21] >> 8) & 0xff) << 24) | /* oncount */
969 + ((uint32)((unsigned char)(b[21] & 0xff)) << 8); /* offcount */
970 + vp += sprintf(vp, "leddc=%d", w32);
971 +
972 + vp++;
973 + }
974 +
975 + if (sromrev >= 2) {
976 + /* New section takes over the 4th hardware function space */
977 +
978 + /* Word 29 is max power 11a high/low */
979 + w = b[29];
980 + vp += sprintf(vp, "pa1himaxpwr=%d", w & 0xff);
981 + vp++;
982 + vp += sprintf(vp, "pa1lomaxpwr=%d", (w >> 8) & 0xff);
983 + vp++;
984 +
985 + /* Words 30-32 set the 11alow pa settings,
986 + * 33-35 are the 11ahigh ones.
987 + */
988 + for (i = 0; i < 3; i++) {
989 + vp += sprintf(vp, "pa1lob%d=%d", i, b[30 + i]);
990 + vp++;
991 + vp += sprintf(vp, "pa1hib%d=%d", i, b[33 + i]);
992 + vp++;
993 + }
994 + w = b[59];
995 + if (w == 0)
996 + vp += sprintf(vp, "ccode=");
997 + else
998 + vp += sprintf(vp, "ccode=%c%c", (w >> 8), (w & 0xff));
999 + vp++;
1000 +
1001 + }
1002 +
1003 + /* parameter section of sprom starts at byte offset 72 */
1004 + woff = 72/2;
1005 +
1006 + /* first 6 bytes are il0macaddr */
1007 + ea.octet[0] = (b[woff] >> 8) & 0xff;
1008 + ea.octet[1] = b[woff] & 0xff;
1009 + ea.octet[2] = (b[woff+1] >> 8) & 0xff;
1010 + ea.octet[3] = b[woff+1] & 0xff;
1011 + ea.octet[4] = (b[woff+2] >> 8) & 0xff;
1012 + ea.octet[5] = b[woff+2] & 0xff;
1013 + woff += 3;
1014 + bcm_ether_ntoa(&ea, eabuf);
1015 + vp += sprintf(vp, "il0macaddr=%s", eabuf);
1016 + vp++;
1017 +
1018 + /* next 6 bytes are et0macaddr */
1019 + ea.octet[0] = (b[woff] >> 8) & 0xff;
1020 + ea.octet[1] = b[woff] & 0xff;
1021 + ea.octet[2] = (b[woff+1] >> 8) & 0xff;
1022 + ea.octet[3] = b[woff+1] & 0xff;
1023 + ea.octet[4] = (b[woff+2] >> 8) & 0xff;
1024 + ea.octet[5] = b[woff+2] & 0xff;
1025 + woff += 3;
1026 + bcm_ether_ntoa(&ea, eabuf);
1027 + vp += sprintf(vp, "et0macaddr=%s", eabuf);
1028 + vp++;
1029 +
1030 + /* next 6 bytes are et1macaddr */
1031 + ea.octet[0] = (b[woff] >> 8) & 0xff;
1032 + ea.octet[1] = b[woff] & 0xff;
1033 + ea.octet[2] = (b[woff+1] >> 8) & 0xff;
1034 + ea.octet[3] = b[woff+1] & 0xff;
1035 + ea.octet[4] = (b[woff+2] >> 8) & 0xff;
1036 + ea.octet[5] = b[woff+2] & 0xff;
1037 + woff += 3;
1038 + bcm_ether_ntoa(&ea, eabuf);
1039 + vp += sprintf(vp, "et1macaddr=%s", eabuf);
1040 + vp++;
1041 +
1042 + /*
1043 + * Enet phy settings one or two singles or a dual
1044 + * Bits 4-0 : MII address for enet0 (0x1f for not there)
1045 + * Bits 9-5 : MII address for enet1 (0x1f for not there)
1046 + * Bit 14 : Mdio for enet0
1047 + * Bit 15 : Mdio for enet1
1048 + */
1049 + w = b[woff];
1050 + vp += sprintf(vp, "et0phyaddr=%d", (w & 0x1f));
1051 + vp++;
1052 + vp += sprintf(vp, "et1phyaddr=%d", ((w >> 5) & 0x1f));
1053 + vp++;
1054 + vp += sprintf(vp, "et0mdcport=%d", ((w >> 14) & 0x1));
1055 + vp++;
1056 + vp += sprintf(vp, "et1mdcport=%d", ((w >> 15) & 0x1));
1057 + vp++;
1058 +
1059 + /* Word 46 has board rev, antennas 0/1 & Country code/control */
1060 + w = b[46];
1061 + vp += sprintf(vp, "boardrev=%d", w & 0xff);
1062 + vp++;
1063 +
1064 + if (sromrev > 1)
1065 + vp += sprintf(vp, "cctl=%d", (w >> 8) & 0xf);
1066 + else
1067 + vp += sprintf(vp, "cc=%d", (w >> 8) & 0xf);
1068 + vp++;
1069 +
1070 + vp += sprintf(vp, "aa2g=%d", (w >> 12) & 0x3);
1071 + vp++;
1072 +
1073 + vp += sprintf(vp, "aa5g=%d", (w >> 14) & 0x3);
1074 + vp++;
1075 +
1076 + /* Words 47-49 set the (wl) pa settings */
1077 + woff = 47;
1078 +
1079 + for (i = 0; i < 3; i++) {
1080 + vp += sprintf(vp, "pa0b%d=%d", i, b[woff+i]);
1081 + vp++;
1082 + vp += sprintf(vp, "pa1b%d=%d", i, b[woff+i+6]);
1083 + vp++;
1084 + }
1085 +
1086 + /*
1087 + * Words 50-51 set the customer-configured wl led behavior.
1088 + * 8 bits/gpio pin. High bit: activehi=0, activelo=1;
1089 + * LED behavior values defined in wlioctl.h .
1090 + */
1091 + w = b[50];
1092 + if ((w != 0) && (w != 0xffff)) {
1093 + /* ledbh0 */
1094 + vp += sprintf(vp, "ledbh0=%d", (w & 0xff));
1095 + vp++;
1096 +
1097 + /* ledbh1 */
1098 + vp += sprintf(vp, "ledbh1=%d", (w >> 8) & 0xff);
1099 + vp++;
1100 + }
1101 + w = b[51];
1102 + if ((w != 0) && (w != 0xffff)) {
1103 + /* ledbh2 */
1104 + vp += sprintf(vp, "ledbh2=%d", w & 0xff);
1105 + vp++;
1106 +
1107 + /* ledbh */
1108 + vp += sprintf(vp, "ledbh3=%d", (w >> 8) & 0xff);
1109 + vp++;
1110 + }
1111 +
1112 + /* Word 52 is max power 0/1 */
1113 + w = b[52];
1114 + vp += sprintf(vp, "pa0maxpwr=%d", w & 0xff);
1115 + vp++;
1116 + vp += sprintf(vp, "pa1maxpwr=%d", (w >> 8) & 0xff);
1117 + vp++;
1118 +
1119 + /* Word 56 is idle tssi target 0/1 */
1120 + w = b[56];
1121 + vp += sprintf(vp, "pa0itssit=%d", w & 0xff);
1122 + vp++;
1123 + vp += sprintf(vp, "pa1itssit=%d", (w >> 8) & 0xff);
1124 + vp++;
1125 +
1126 + /* Word 57 is boardflags, if not programmed make it zero */
1127 + w32 = (uint32)b[57];
1128 + if (w32 == 0xffff) w32 = 0;
1129 + if (sromrev > 1) {
1130 + /* Word 28 is the high bits of boardflags */
1131 + w32 |= (uint32)b[28] << 16;
1132 + }
1133 + vp += sprintf(vp, "boardflags=%d", w32);
1134 + vp++;
1135 +
1136 + /* Word 58 is antenna gain 0/1 */
1137 + w = b[58];
1138 + vp += sprintf(vp, "ag0=%d", w & 0xff);
1139 + vp++;
1140 +
1141 + vp += sprintf(vp, "ag1=%d", (w >> 8) & 0xff);
1142 + vp++;
1143 +
1144 + if (sromrev == 1) {
1145 + /* set the oem string */
1146 + vp += sprintf(vp, "oem=%02x%02x%02x%02x%02x%02x%02x%02x",
1147 + ((b[59] >> 8) & 0xff), (b[59] & 0xff),
1148 + ((b[60] >> 8) & 0xff), (b[60] & 0xff),
1149 + ((b[61] >> 8) & 0xff), (b[61] & 0xff),
1150 + ((b[62] >> 8) & 0xff), (b[62] & 0xff));
1151 + vp++;
1152 + } else if (sromrev == 2) {
1153 + /* Word 60 OFDM tx power offset from CCK level */
1154 + /* OFDM Power Offset - opo */
1155 + vp += sprintf(vp, "opo=%d", b[60] & 0xff);
1156 + vp++;
1157 + } else {
1158 + /* Word 60: cck power offsets */
1159 + vp += sprintf(vp, "cckpo=%d", b[60]);
1160 + vp++;
1161 +
1162 + /* Words 61+62: 11g ofdm power offsets */
1163 + w32 = ((uint32)b[62] << 16) | b[61];
1164 + vp += sprintf(vp, "ofdmgpo=%d", w32);
1165 + vp++;
1166 + }
1167 +
1168 + /* final nullbyte terminator */
1169 +done: *vp++ = '\0';
1170 +
1171 + ASSERT((vp - base) <= VARS_MAX);
1172 +
1173 +varsdone:
1174 + err = initvars_table(osh, base, vp, vars, count);
1175 +
1176 +err:
1177 +#ifdef WLTEST
1178 + if (base != mfgsromvars)
1179 +#endif
1180 + MFREE(osh, base, VARS_MAX);
1181 + MFREE(osh, b, SROM_MAX);
1182 + return err;
1183 +}
1184 +
1185 +/*
1186 + * Read the cis and call parsecis to initialize the vars.
1187 + * Return 0 on success, nonzero on error.
1188 + */
1189 +static int
1190 +initvars_cis_pcmcia(void *sbh, osl_t *osh, char **vars, uint *count)
1191 +{
1192 + uint8 *cis = NULL;
1193 + int rc;
1194 + uint data_sz;
1195 +
1196 + data_sz = (sb_pcmciarev(sbh) == 1) ? (SPROM_SIZE * 2) : CIS_SIZE;
1197 +
1198 + if ((cis = MALLOC(osh, data_sz)) == NULL)
1199 + return (-2);
1200 +
1201 + if (sb_pcmciarev(sbh) == 1) {
1202 + if (srom_read(PCMCIA_BUS, (void *)NULL, osh, 0, data_sz, (uint16 *)cis)) {
1203 + MFREE(osh, cis, data_sz);
1204 + return (-1);
1205 + }
1206 + /* fix up endianess for 16-bit data vs 8-bit parsing */
1207 + ltoh16_buf((uint16 *)cis, data_sz);
1208 + } else
1209 + OSL_PCMCIA_READ_ATTR(osh, 0, cis, data_sz);
1210 +
1211 + rc = srom_parsecis(osh, &cis, 1, vars, count);
1212 +
1213 + MFREE(osh, cis, data_sz);
1214 +
1215 + return (rc);
1216 +}
1217 +
1218 diff -urN linux.old/arch/mips/bcm947xx/bcmutils.c linux.dev/arch/mips/bcm947xx/bcmutils.c
1219 --- linux.old/arch/mips/bcm947xx/bcmutils.c 1970-01-01 01:00:00.000000000 +0100
1220 +++ linux.dev/arch/mips/bcm947xx/bcmutils.c 2006-10-02 21:19:59.000000000 +0200
1221 @@ -0,0 +1,247 @@
1222 +/*
1223 + * Misc useful OS-independent routines.
1224 + *
1225 + * Copyright 2006, Broadcom Corporation
1226 + * All Rights Reserved.
1227 + *
1228 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1229 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1230 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1231 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1232 + * $Id: bcmutils.c,v 1.1.1.12 2006/02/27 03:43:16 honor Exp $
1233 + */
1234 +
1235 +#include <typedefs.h>
1236 +#include <bcmdefs.h>
1237 +#include <stdarg.h>
1238 +#include <bcmutils.h>
1239 +#include <osl.h>
1240 +#include <sbutils.h>
1241 +#include <bcmnvram.h>
1242 +#include <bcmendian.h>
1243 +#include <bcmdevs.h>
1244 +
1245 +unsigned char bcm_ctype[] = {
1246 + _BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C, /* 0-7 */
1247 + _BCM_C, _BCM_C|_BCM_S, _BCM_C|_BCM_S, _BCM_C|_BCM_S, _BCM_C|_BCM_S, _BCM_C|_BCM_S, _BCM_C,
1248 + _BCM_C, /* 8-15 */
1249 + _BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C, /* 16-23 */
1250 + _BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C, /* 24-31 */
1251 + _BCM_S|_BCM_SP,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 32-39 */
1252 + _BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 40-47 */
1253 + _BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D, /* 48-55 */
1254 + _BCM_D,_BCM_D,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 56-63 */
1255 + _BCM_P, _BCM_U|_BCM_X, _BCM_U|_BCM_X, _BCM_U|_BCM_X, _BCM_U|_BCM_X, _BCM_U|_BCM_X,
1256 + _BCM_U|_BCM_X, _BCM_U, /* 64-71 */
1257 + _BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U, /* 72-79 */
1258 + _BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U, /* 80-87 */
1259 + _BCM_U,_BCM_U,_BCM_U,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 88-95 */
1260 + _BCM_P, _BCM_L|_BCM_X, _BCM_L|_BCM_X, _BCM_L|_BCM_X, _BCM_L|_BCM_X, _BCM_L|_BCM_X,
1261 + _BCM_L|_BCM_X, _BCM_L, /* 96-103 */
1262 + _BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L, /* 104-111 */
1263 + _BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L, /* 112-119 */
1264 + _BCM_L,_BCM_L,_BCM_L,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_C, /* 120-127 */
1265 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 128-143 */
1266 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 144-159 */
1267 + _BCM_S|_BCM_SP, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P,
1268 + _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, /* 160-175 */
1269 + _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P,
1270 + _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, /* 176-191 */
1271 + _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U,
1272 + _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, /* 192-207 */
1273 + _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_P, _BCM_U, _BCM_U, _BCM_U,
1274 + _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_L, /* 208-223 */
1275 + _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L,
1276 + _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, /* 224-239 */
1277 + _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_P, _BCM_L, _BCM_L, _BCM_L,
1278 + _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L /* 240-255 */
1279 +};
1280 +
1281 +
1282 +ulong
1283 +bcm_strtoul(char *cp, char **endp, uint base)
1284 +{
1285 + ulong result, value;
1286 + bool minus;
1287 +
1288 + minus = FALSE;
1289 +
1290 + while (bcm_isspace(*cp))
1291 + cp++;
1292 +
1293 + if (cp[0] == '+')
1294 + cp++;
1295 + else if (cp[0] == '-') {
1296 + minus = TRUE;
1297 + cp++;
1298 + }
1299 +
1300 + if (base == 0) {
1301 + if (cp[0] == '0') {
1302 + if ((cp[1] == 'x') || (cp[1] == 'X')) {
1303 + base = 16;
1304 + cp = &cp[2];
1305 + } else {
1306 + base = 8;
1307 + cp = &cp[1];
1308 + }
1309 + } else
1310 + base = 10;
1311 + } else if (base == 16 && (cp[0] == '0') && ((cp[1] == 'x') || (cp[1] == 'X'))) {
1312 + cp = &cp[2];
1313 + }
1314 +
1315 + result = 0;
1316 +
1317 + while (bcm_isxdigit(*cp) &&
1318 + (value = bcm_isdigit(*cp) ? *cp-'0' : bcm_toupper(*cp)-'A'+10) < base) {
1319 + result = result*base + value;
1320 + cp++;
1321 + }
1322 +
1323 + if (minus)
1324 + result = (ulong)(result * -1);
1325 +
1326 + if (endp)
1327 + *endp = (char *)cp;
1328 +
1329 + return (result);
1330 +}
1331 +
1332 +uchar
1333 +bcm_toupper(uchar c)
1334 +{
1335 + if (bcm_islower(c))
1336 + c -= 'a'-'A';
1337 + return (c);
1338 +}
1339 +
1340 +char*
1341 +bcm_ether_ntoa(struct ether_addr *ea, char *buf)
1342 +{
1343 + sprintf(buf, "%02x:%02x:%02x:%02x:%02x:%02x",
1344 + ea->octet[0]&0xff, ea->octet[1]&0xff, ea->octet[2]&0xff,
1345 + ea->octet[3]&0xff, ea->octet[4]&0xff, ea->octet[5]&0xff);
1346 + return (buf);
1347 +}
1348 +
1349 +
1350 +/*
1351 + * Search the name=value vars for a specific one and return its value.
1352 + * Returns NULL if not found.
1353 + */
1354 +char*
1355 +getvar(char *vars, char *name)
1356 +{
1357 + char *s;
1358 + int len;
1359 +
1360 + len = strlen(name);
1361 +
1362 + /* first look in vars[] */
1363 + for (s = vars; s && *s;) {
1364 + /* CSTYLED */
1365 + if ((memcmp(s, name, len) == 0) && (s[len] == '='))
1366 + return (&s[len+1]);
1367 +
1368 + while (*s++)
1369 + ;
1370 + }
1371 +
1372 + /* then query nvram */
1373 + return (nvram_get(name));
1374 +}
1375 +
1376 +/*
1377 + * Search the vars for a specific one and return its value as
1378 + * an integer. Returns 0 if not found.
1379 + */
1380 +int
1381 +getintvar(char *vars, char *name)
1382 +{
1383 + char *val;
1384 +
1385 + if ((val = getvar(vars, name)) == NULL)
1386 + return (0);
1387 +
1388 + return (bcm_strtoul(val, NULL, 0));
1389 +}
1390 +
1391 +
1392 +/*******************************************************************************
1393 + * crc8
1394 + *
1395 + * Computes a crc8 over the input data using the polynomial:
1396 + *
1397 + * x^8 + x^7 +x^6 + x^4 + x^2 + 1
1398 + *
1399 + * The caller provides the initial value (either CRC8_INIT_VALUE
1400 + * or the previous returned value) to allow for processing of
1401 + * discontiguous blocks of data. When generating the CRC the
1402 + * caller is responsible for complementing the final return value
1403 + * and inserting it into the byte stream. When checking, a final
1404 + * return value of CRC8_GOOD_VALUE indicates a valid CRC.
1405 + *
1406 + * Reference: Dallas Semiconductor Application Note 27
1407 + * Williams, Ross N., "A Painless Guide to CRC Error Detection Algorithms",
1408 + * ver 3, Aug 1993, ross@guest.adelaide.edu.au, Rocksoft Pty Ltd.,
1409 + * ftp://ftp.rocksoft.com/clients/rocksoft/papers/crc_v3.txt
1410 + *
1411 + * ****************************************************************************
1412 + */
1413 +
1414 +static uint8 crc8_table[256] = {
1415 + 0x00, 0xF7, 0xB9, 0x4E, 0x25, 0xD2, 0x9C, 0x6B,
1416 + 0x4A, 0xBD, 0xF3, 0x04, 0x6F, 0x98, 0xD6, 0x21,
1417 + 0x94, 0x63, 0x2D, 0xDA, 0xB1, 0x46, 0x08, 0xFF,
1418 + 0xDE, 0x29, 0x67, 0x90, 0xFB, 0x0C, 0x42, 0xB5,
1419 + 0x7F, 0x88, 0xC6, 0x31, 0x5A, 0xAD, 0xE3, 0x14,
1420 + 0x35, 0xC2, 0x8C, 0x7B, 0x10, 0xE7, 0xA9, 0x5E,
1421 + 0xEB, 0x1C, 0x52, 0xA5, 0xCE, 0x39, 0x77, 0x80,
1422 + 0xA1, 0x56, 0x18, 0xEF, 0x84, 0x73, 0x3D, 0xCA,
1423 + 0xFE, 0x09, 0x47, 0xB0, 0xDB, 0x2C, 0x62, 0x95,
1424 + 0xB4, 0x43, 0x0D, 0xFA, 0x91, 0x66, 0x28, 0xDF,
1425 + 0x6A, 0x9D, 0xD3, 0x24, 0x4F, 0xB8, 0xF6, 0x01,
1426 + 0x20, 0xD7, 0x99, 0x6E, 0x05, 0xF2, 0xBC, 0x4B,
1427 + 0x81, 0x76, 0x38, 0xCF, 0xA4, 0x53, 0x1D, 0xEA,
1428 + 0xCB, 0x3C, 0x72, 0x85, 0xEE, 0x19, 0x57, 0xA0,
1429 + 0x15, 0xE2, 0xAC, 0x5B, 0x30, 0xC7, 0x89, 0x7E,
1430 + 0x5F, 0xA8, 0xE6, 0x11, 0x7A, 0x8D, 0xC3, 0x34,
1431 + 0xAB, 0x5C, 0x12, 0xE5, 0x8E, 0x79, 0x37, 0xC0,
1432 + 0xE1, 0x16, 0x58, 0xAF, 0xC4, 0x33, 0x7D, 0x8A,
1433 + 0x3F, 0xC8, 0x86, 0x71, 0x1A, 0xED, 0xA3, 0x54,
1434 + 0x75, 0x82, 0xCC, 0x3B, 0x50, 0xA7, 0xE9, 0x1E,
1435 + 0xD4, 0x23, 0x6D, 0x9A, 0xF1, 0x06, 0x48, 0xBF,
1436 + 0x9E, 0x69, 0x27, 0xD0, 0xBB, 0x4C, 0x02, 0xF5,
1437 + 0x40, 0xB7, 0xF9, 0x0E, 0x65, 0x92, 0xDC, 0x2B,
1438 + 0x0A, 0xFD, 0xB3, 0x44, 0x2F, 0xD8, 0x96, 0x61,
1439 + 0x55, 0xA2, 0xEC, 0x1B, 0x70, 0x87, 0xC9, 0x3E,
1440 + 0x1F, 0xE8, 0xA6, 0x51, 0x3A, 0xCD, 0x83, 0x74,
1441 + 0xC1, 0x36, 0x78, 0x8F, 0xE4, 0x13, 0x5D, 0xAA,
1442 + 0x8B, 0x7C, 0x32, 0xC5, 0xAE, 0x59, 0x17, 0xE0,
1443 + 0x2A, 0xDD, 0x93, 0x64, 0x0F, 0xF8, 0xB6, 0x41,
1444 + 0x60, 0x97, 0xD9, 0x2E, 0x45, 0xB2, 0xFC, 0x0B,
1445 + 0xBE, 0x49, 0x07, 0xF0, 0x9B, 0x6C, 0x22, 0xD5,
1446 + 0xF4, 0x03, 0x4D, 0xBA, 0xD1, 0x26, 0x68, 0x9F
1447 +};
1448 +
1449 +#define CRC_INNER_LOOP(n, c, x) \
1450 + (c) = ((c) >> 8) ^ crc##n##_table[((c) ^ (x)) & 0xff]
1451 +
1452 +uint8
1453 +hndcrc8(
1454 + uint8 *pdata, /* pointer to array of data to process */
1455 + uint nbytes, /* number of input data bytes to process */
1456 + uint8 crc /* either CRC8_INIT_VALUE or previous return value */
1457 +)
1458 +{
1459 + /* hard code the crc loop instead of using CRC_INNER_LOOP macro
1460 + * to avoid the undefined and unnecessary (uint8 >> 8) operation.
1461 + */
1462 + while (nbytes-- > 0)
1463 + crc = crc8_table[(crc ^ *pdata++) & 0xff];
1464 +
1465 + return crc;
1466 +}
1467 +
1468 +
1469 diff -urN linux.old/arch/mips/bcm947xx/cfe_env.c linux.dev/arch/mips/bcm947xx/cfe_env.c
1470 --- linux.old/arch/mips/bcm947xx/cfe_env.c 1970-01-01 01:00:00.000000000 +0100
1471 +++ linux.dev/arch/mips/bcm947xx/cfe_env.c 2006-10-02 21:19:59.000000000 +0200
1472 @@ -0,0 +1,234 @@
1473 +/*
1474 + * NVRAM variable manipulation (Linux kernel half)
1475 + *
1476 + * Copyright 2001-2003, Broadcom Corporation
1477 + * All Rights Reserved.
1478 + *
1479 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1480 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1481 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1482 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1483 + *
1484 + * $Id$
1485 + */
1486 +
1487 +#include <linux/config.h>
1488 +#include <linux/init.h>
1489 +#include <linux/module.h>
1490 +#include <linux/kernel.h>
1491 +#include <linux/string.h>
1492 +#include <asm/io.h>
1493 +#include <asm/uaccess.h>
1494 +
1495 +#include <typedefs.h>
1496 +#include <osl.h>
1497 +#include <bcmendian.h>
1498 +#include <bcmutils.h>
1499 +
1500 +#define NVRAM_SIZE (0x1ff0)
1501 +static char _nvdata[NVRAM_SIZE] __initdata;
1502 +static char _valuestr[256] __initdata;
1503 +
1504 +/*
1505 + * TLV types. These codes are used in the "type-length-value"
1506 + * encoding of the items stored in the NVRAM device (flash or EEPROM)
1507 + *
1508 + * The layout of the flash/nvram is as follows:
1509 + *
1510 + * <type> <length> <data ...> <type> <length> <data ...> <type_end>
1511 + *
1512 + * The type code of "ENV_TLV_TYPE_END" marks the end of the list.
1513 + * The "length" field marks the length of the data section, not
1514 + * including the type and length fields.
1515 + *
1516 + * Environment variables are stored as follows:
1517 + *
1518 + * <type_env> <length> <flags> <name> = <value>
1519 + *
1520 + * If bit 0 (low bit) is set, the length is an 8-bit value.
1521 + * If bit 0 (low bit) is clear, the length is a 16-bit value
1522 + *
1523 + * Bit 7 set indicates "user" TLVs. In this case, bit 0 still
1524 + * indicates the size of the length field.
1525 + *
1526 + * Flags are from the constants below:
1527 + *
1528 + */
1529 +#define ENV_LENGTH_16BITS 0x00 /* for low bit */
1530 +#define ENV_LENGTH_8BITS 0x01
1531 +
1532 +#define ENV_TYPE_USER 0x80
1533 +
1534 +#define ENV_CODE_SYS(n,l) (((n)<<1)|(l))
1535 +#define ENV_CODE_USER(n,l) ((((n)<<1)|(l)) | ENV_TYPE_USER)
1536 +
1537 +/*
1538 + * The actual TLV types we support
1539 + */
1540 +
1541 +#define ENV_TLV_TYPE_END 0x00
1542 +#define ENV_TLV_TYPE_ENV ENV_CODE_SYS(0,ENV_LENGTH_8BITS)
1543 +
1544 +/*
1545 + * Environment variable flags
1546 + */
1547 +
1548 +#define ENV_FLG_NORMAL 0x00 /* normal read/write */
1549 +#define ENV_FLG_BUILTIN 0x01 /* builtin - not stored in flash */
1550 +#define ENV_FLG_READONLY 0x02 /* read-only - cannot be changed */
1551 +
1552 +#define ENV_FLG_MASK 0xFF /* mask of attributes we keep */
1553 +#define ENV_FLG_ADMIN 0x100 /* lets us internally override permissions */
1554 +
1555 +
1556 +/* *********************************************************************
1557 + * _nvram_read(buffer,offset,length)
1558 + *
1559 + * Read data from the NVRAM device
1560 + *
1561 + * Input parameters:
1562 + * buffer - destination buffer
1563 + * offset - offset of data to read
1564 + * length - number of bytes to read
1565 + *
1566 + * Return value:
1567 + * number of bytes read, or <0 if error occured
1568 + ********************************************************************* */
1569 +static int
1570 +_nvram_read(unsigned char *nv_buf, unsigned char *buffer, int offset, int length)
1571 +{
1572 + int i;
1573 + if (offset > NVRAM_SIZE)
1574 + return -1;
1575 +
1576 + for ( i = 0; i < length; i++) {
1577 + buffer[i] = ((volatile unsigned char*)nv_buf)[offset + i];
1578 + }
1579 + return length;
1580 +}
1581 +
1582 +
1583 +static char*
1584 +_strnchr(const char *dest,int c,size_t cnt)
1585 +{
1586 + while (*dest && (cnt > 0)) {
1587 + if (*dest == c) return (char *) dest;
1588 + dest++;
1589 + cnt--;
1590 + }
1591 + return NULL;
1592 +}
1593 +
1594 +
1595 +
1596 +/*
1597 + * Core support API: Externally visible.
1598 + */
1599 +
1600 +/*
1601 + * Get the value of an NVRAM variable
1602 + * @param name name of variable to get
1603 + * @return value of variable or NULL if undefined
1604 + */
1605 +
1606 +char*
1607 +cfe_env_get(unsigned char *nv_buf, char* name)
1608 +{
1609 + int size;
1610 + unsigned char *buffer;
1611 + unsigned char *ptr;
1612 + unsigned char *envval;
1613 + unsigned int reclen;
1614 + unsigned int rectype;
1615 + int offset;
1616 + int flg;
1617 +
1618 + size = NVRAM_SIZE;
1619 + buffer = &_nvdata[0];
1620 +
1621 + ptr = buffer;
1622 + offset = 0;
1623 +
1624 + /* Read the record type and length */
1625 + if (_nvram_read(nv_buf, ptr,offset,1) != 1) {
1626 + goto error;
1627 + }
1628 +
1629 + while ((*ptr != ENV_TLV_TYPE_END) && (size > 1)) {
1630 +
1631 + /* Adjust pointer for TLV type */
1632 + rectype = *(ptr);
1633 + offset++;
1634 + size--;
1635 +
1636 + /*
1637 + * Read the length. It can be either 1 or 2 bytes
1638 + * depending on the code
1639 + */
1640 + if (rectype & ENV_LENGTH_8BITS) {
1641 + /* Read the record type and length - 8 bits */
1642 + if (_nvram_read(nv_buf, ptr,offset,1) != 1) {
1643 + goto error;
1644 + }
1645 + reclen = *(ptr);
1646 + size--;
1647 + offset++;
1648 + }
1649 + else {
1650 + /* Read the record type and length - 16 bits, MSB first */
1651 + if (_nvram_read(nv_buf, ptr,offset,2) != 2) {
1652 + goto error;
1653 + }
1654 + reclen = (((unsigned int) *(ptr)) << 8) + (unsigned int) *(ptr+1);
1655 + size -= 2;
1656 + offset += 2;
1657 + }
1658 +
1659 + if (reclen > size)
1660 + break; /* should not happen, bad NVRAM */
1661 +
1662 + switch (rectype) {
1663 + case ENV_TLV_TYPE_ENV:
1664 + /* Read the TLV data */
1665 + if (_nvram_read(nv_buf, ptr,offset,reclen) != reclen)
1666 + goto error;
1667 + flg = *ptr++;
1668 + envval = (unsigned char *) _strnchr(ptr,'=',(reclen-1));
1669 + if (envval) {
1670 + *envval++ = '\0';
1671 + memcpy(_valuestr,envval,(reclen-1)-(envval-ptr));
1672 + _valuestr[(reclen-1)-(envval-ptr)] = '\0';
1673 +#if 0
1674 + printk(KERN_INFO "NVRAM:%s=%s\n", ptr, _valuestr);
1675 +#endif
1676 + if(!strcmp(ptr, name)){
1677 + return _valuestr;
1678 + }
1679 + if((strlen(ptr) > 1) && !strcmp(&ptr[1], name))
1680 + return _valuestr;
1681 + }
1682 + break;
1683 +
1684 + default:
1685 + /* Unknown TLV type, skip it. */
1686 + break;
1687 + }
1688 +
1689 + /*
1690 + * Advance to next TLV
1691 + */
1692 +
1693 + size -= (int)reclen;
1694 + offset += reclen;
1695 +
1696 + /* Read the next record type */
1697 + ptr = buffer;
1698 + if (_nvram_read(nv_buf, ptr,offset,1) != 1)
1699 + goto error;
1700 + }
1701 +
1702 +error:
1703 + return NULL;
1704 +
1705 +}
1706 +
1707 diff -urN linux.old/arch/mips/bcm947xx/compressed/Makefile linux.dev/arch/mips/bcm947xx/compressed/Makefile
1708 --- linux.old/arch/mips/bcm947xx/compressed/Makefile 1970-01-01 01:00:00.000000000 +0100
1709 +++ linux.dev/arch/mips/bcm947xx/compressed/Makefile 2006-10-02 21:19:59.000000000 +0200
1710 @@ -0,0 +1,33 @@
1711 +#
1712 +# Makefile for Broadcom BCM947XX boards
1713 +#
1714 +# Copyright 2001-2003, Broadcom Corporation
1715 +# All Rights Reserved.
1716 +#
1717 +# THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1718 +# KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1719 +# SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1720 +# FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1721 +#
1722 +# $Id: Makefile,v 1.2 2005/04/02 12:12:57 wbx Exp $
1723 +#
1724 +
1725 +OBJCOPY_ARGS = -O binary -R .reginfo -R .note -R .comment -R .mdebug -S
1726 +SYSTEM ?= $(TOPDIR)/vmlinux
1727 +
1728 +all: vmlinuz
1729 +
1730 +# Don't build dependencies, this may die if $(CC) isn't gcc
1731 +dep:
1732 +
1733 +# Create a gzipped version named vmlinuz for compatibility
1734 +vmlinuz: piggy
1735 + gzip -c9 $< > $@
1736 +
1737 +piggy: $(SYSTEM)
1738 + $(OBJCOPY) $(OBJCOPY_ARGS) $< $@
1739 +
1740 +mrproper: clean
1741 +
1742 +clean:
1743 + rm -f vmlinuz piggy
1744 diff -urN linux.old/arch/mips/bcm947xx/export.c linux.dev/arch/mips/bcm947xx/export.c
1745 --- linux.old/arch/mips/bcm947xx/export.c 1970-01-01 01:00:00.000000000 +0100
1746 +++ linux.dev/arch/mips/bcm947xx/export.c 2006-10-02 21:19:59.000000000 +0200
1747 @@ -0,0 +1,66 @@
1748 +#include <linux/module.h>
1749 +
1750 +#define _export(n) \
1751 + void n(void); \
1752 + EXPORT_SYMBOL(n);
1753 +
1754 +_export(bcm947xx_sbh)
1755 +
1756 +_export(sb_attach)
1757 +_export(sb_kattach)
1758 +_export(sb_boardtype)
1759 +_export(sb_boardvendor)
1760 +_export(sb_btcgpiowar)
1761 +_export(sb_bus)
1762 +_export(sb_chip)
1763 +_export(sb_chiprev)
1764 +_export(sb_chipcrev)
1765 +_export(sb_chippkg)
1766 +_export(sb_clkctl_clk)
1767 +_export(sb_clkctl_fast_pwrup_delay)
1768 +_export(sb_clkctl_init)
1769 +_export(sb_clkctl_xtal)
1770 +_export(sb_core_disable)
1771 +_export(sb_core_reset)
1772 +_export(sb_core_tofixup)
1773 +_export(sb_coreflags)
1774 +_export(sb_coreflagshi)
1775 +_export(sb_coreidx)
1776 +_export(sb_corerev)
1777 +_export(sb_coreunit)
1778 +_export(sb_detach)
1779 +_export(sb_deviceremoved)
1780 +_export(sb_gpiosetcore)
1781 +_export(sb_gpiocontrol)
1782 +_export(sb_gpioled)
1783 +_export(sb_gpioin)
1784 +_export(sb_gpioout)
1785 +_export(sb_gpioouten)
1786 +_export(sb_gpiotimerval)
1787 +_export(sb_iscoreup)
1788 +_export(sb_pci_setup)
1789 +_export(sb_pcirev)
1790 +_export(sb_pcmcia_init)
1791 +_export(sb_pcmciarev)
1792 +_export(sb_register_intr_callback)
1793 +_export(sb_setcore)
1794 +_export(sb_war16165)
1795 +_export(sb_war32414_forceHT)
1796 +_export(sb_osh)
1797 +
1798 +_export(getvar)
1799 +_export(getintvar)
1800 +_export(bcm_strtoul)
1801 +_export(bcm_ctype)
1802 +_export(bcm_toupper)
1803 +_export(bcm_ether_ntoa)
1804 +
1805 +_export(nvram_get)
1806 +_export(nvram_getall)
1807 +_export(nvram_set)
1808 +_export(nvram_unset)
1809 +_export(nvram_commit)
1810 +
1811 +_export(srom_read)
1812 +_export(srom_write)
1813 +
1814 diff -urN linux.old/arch/mips/bcm947xx/generic/int-handler.S linux.dev/arch/mips/bcm947xx/generic/int-handler.S
1815 --- linux.old/arch/mips/bcm947xx/generic/int-handler.S 1970-01-01 01:00:00.000000000 +0100
1816 +++ linux.dev/arch/mips/bcm947xx/generic/int-handler.S 2006-10-02 21:19:59.000000000 +0200
1817 @@ -0,0 +1,51 @@
1818 +/*
1819 + * Generic interrupt handler for Broadcom MIPS boards
1820 + *
1821 + * Copyright 2004, Broadcom Corporation
1822 + * All Rights Reserved.
1823 + *
1824 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1825 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1826 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1827 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1828 + *
1829 + * $Id: int-handler.S,v 1.1 2005/03/16 13:50:00 wbx Exp $
1830 + */
1831 +
1832 +#include <linux/config.h>
1833 +
1834 +#include <asm/asm.h>
1835 +#include <asm/mipsregs.h>
1836 +#include <asm/regdef.h>
1837 +#include <asm/stackframe.h>
1838 +
1839 +/*
1840 + * MIPS IRQ Source
1841 + * -------- ------
1842 + * 0 Software (ignored)
1843 + * 1 Software (ignored)
1844 + * 2 Combined hardware interrupt (hw0)
1845 + * 3 Hardware
1846 + * 4 Hardware
1847 + * 5 Hardware
1848 + * 6 Hardware
1849 + * 7 R4k timer
1850 + */
1851 +
1852 + .text
1853 + .set noreorder
1854 + .set noat
1855 + .align 5
1856 + NESTED(brcmIRQ, PT_SIZE, sp)
1857 + SAVE_ALL
1858 + CLI
1859 + .set at
1860 + .set noreorder
1861 +
1862 + jal brcm_irq_dispatch
1863 + move a0, sp
1864 +
1865 + j ret_from_irq
1866 + nop
1867 +
1868 + END(brcmIRQ)
1869 diff -urN linux.old/arch/mips/bcm947xx/generic/irq.c linux.dev/arch/mips/bcm947xx/generic/irq.c
1870 --- linux.old/arch/mips/bcm947xx/generic/irq.c 1970-01-01 01:00:00.000000000 +0100
1871 +++ linux.dev/arch/mips/bcm947xx/generic/irq.c 2006-10-02 21:19:59.000000000 +0200
1872 @@ -0,0 +1,130 @@
1873 +/*
1874 + * Generic interrupt control functions for Broadcom MIPS boards
1875 + *
1876 + * Copyright 2004, Broadcom Corporation
1877 + * All Rights Reserved.
1878 + *
1879 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1880 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1881 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1882 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1883 + *
1884 + * $Id: irq.c,v 1.1 2005/03/16 13:50:00 wbx Exp $
1885 + */
1886 +
1887 +#include <linux/config.h>
1888 +#include <linux/init.h>
1889 +#include <linux/kernel.h>
1890 +#include <linux/types.h>
1891 +#include <linux/interrupt.h>
1892 +#include <linux/irq.h>
1893 +
1894 +#include <asm/irq.h>
1895 +#include <asm/mipsregs.h>
1896 +#include <asm/gdb-stub.h>
1897 +
1898 +#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5)
1899 +
1900 +extern asmlinkage void brcmIRQ(void);
1901 +extern asmlinkage unsigned int do_IRQ(int irq, struct pt_regs *regs);
1902 +
1903 +void
1904 +brcm_irq_dispatch(struct pt_regs *regs)
1905 +{
1906 + u32 cause;
1907 +
1908 + cause = read_c0_cause() &
1909 + read_c0_status() &
1910 + CAUSEF_IP;
1911 +
1912 +#ifdef CONFIG_KERNPROF
1913 + change_c0_status(cause | 1, 1);
1914 +#else
1915 + clear_c0_status(cause);
1916 +#endif
1917 +
1918 + if (cause & CAUSEF_IP7)
1919 + do_IRQ(7, regs);
1920 + if (cause & CAUSEF_IP2)
1921 + do_IRQ(2, regs);
1922 + if (cause & CAUSEF_IP3)
1923 + do_IRQ(3, regs);
1924 + if (cause & CAUSEF_IP4)
1925 + do_IRQ(4, regs);
1926 + if (cause & CAUSEF_IP5)
1927 + do_IRQ(5, regs);
1928 + if (cause & CAUSEF_IP6)
1929 + do_IRQ(6, regs);
1930 +}
1931 +
1932 +static void
1933 +enable_brcm_irq(unsigned int irq)
1934 +{
1935 + if (irq < 8)
1936 + set_c0_status(1 << (irq + 8));
1937 + else
1938 + set_c0_status(IE_IRQ0);
1939 +}
1940 +
1941 +static void
1942 +disable_brcm_irq(unsigned int irq)
1943 +{
1944 + if (irq < 8)
1945 + clear_c0_status(1 << (irq + 8));
1946 + else
1947 + clear_c0_status(IE_IRQ0);
1948 +}
1949 +
1950 +static void
1951 +ack_brcm_irq(unsigned int irq)
1952 +{
1953 + /* Already done in brcm_irq_dispatch */
1954 +}
1955 +
1956 +static unsigned int
1957 +startup_brcm_irq(unsigned int irq)
1958 +{
1959 + enable_brcm_irq(irq);
1960 +
1961 + return 0; /* never anything pending */
1962 +}
1963 +
1964 +static void
1965 +end_brcm_irq(unsigned int irq)
1966 +{
1967 + if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
1968 + enable_brcm_irq(irq);
1969 +}
1970 +
1971 +static struct hw_interrupt_type brcm_irq_type = {
1972 + typename: "MIPS",
1973 + startup: startup_brcm_irq,
1974 + shutdown: disable_brcm_irq,
1975 + enable: enable_brcm_irq,
1976 + disable: disable_brcm_irq,
1977 + ack: ack_brcm_irq,
1978 + end: end_brcm_irq,
1979 + NULL
1980 +};
1981 +
1982 +void __init
1983 +init_IRQ(void)
1984 +{
1985 + int i;
1986 +
1987 + for (i = 0; i < NR_IRQS; i++) {
1988 + irq_desc[i].status = IRQ_DISABLED;
1989 + irq_desc[i].action = 0;
1990 + irq_desc[i].depth = 1;
1991 + irq_desc[i].handler = &brcm_irq_type;
1992 + }
1993 +
1994 + set_except_vector(0, brcmIRQ);
1995 + change_c0_status(ST0_IM, ALLINTS);
1996 +
1997 +#ifdef CONFIG_REMOTE_DEBUG
1998 + printk("Breaking into debugger...\n");
1999 + set_debug_traps();
2000 + breakpoint();
2001 +#endif
2002 +}
2003 diff -urN linux.old/arch/mips/bcm947xx/generic/Makefile linux.dev/arch/mips/bcm947xx/generic/Makefile
2004 --- linux.old/arch/mips/bcm947xx/generic/Makefile 1970-01-01 01:00:00.000000000 +0100
2005 +++ linux.dev/arch/mips/bcm947xx/generic/Makefile 2006-10-02 21:26:29.000000000 +0200
2006 @@ -0,0 +1,12 @@
2007 +#
2008 +# Makefile for the BCM947xx specific kernel interface routines
2009 +# under Linux.
2010 +#
2011 +EXTRA_CFLAGS += -fno-delayed-branch
2012 +USE_STANDARD_AS_RULE := true
2013 +
2014 +O_TARGET := brcm.o
2015 +
2016 +obj-y := int-handler.o irq.o
2017 +
2018 +include $(TOPDIR)/Rules.make
2019 diff -urN linux.old/arch/mips/bcm947xx/gpio.c linux.dev/arch/mips/bcm947xx/gpio.c
2020 --- linux.old/arch/mips/bcm947xx/gpio.c 1970-01-01 01:00:00.000000000 +0100
2021 +++ linux.dev/arch/mips/bcm947xx/gpio.c 2006-10-02 21:19:59.000000000 +0200
2022 @@ -0,0 +1,159 @@
2023 +/*
2024 + * GPIO char driver
2025 + *
2026 + * Copyright 2005, Broadcom Corporation
2027 + * All Rights Reserved.
2028 + *
2029 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2030 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2031 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2032 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2033 + *
2034 + * $Id$
2035 + */
2036 +
2037 +#include <linux/module.h>
2038 +#include <linux/init.h>
2039 +#include <linux/fs.h>
2040 +#include <linux/miscdevice.h>
2041 +#include <asm/uaccess.h>
2042 +
2043 +#include <typedefs.h>
2044 +#include <osl.h>
2045 +#include <bcmutils.h>
2046 +#include <sbutils.h>
2047 +#include <bcmdevs.h>
2048 +
2049 +static sb_t *gpio_sbh;
2050 +static int gpio_major;
2051 +static devfs_handle_t gpio_dir;
2052 +static struct {
2053 + char *name;
2054 + devfs_handle_t handle;
2055 +} gpio_file[] = {
2056 + { "in", NULL },
2057 + { "out", NULL },
2058 + { "outen", NULL },
2059 + { "control", NULL }
2060 +};
2061 +
2062 +static int
2063 +gpio_open(struct inode *inode, struct file * file)
2064 +{
2065 + if (MINOR(inode->i_rdev) > ARRAYSIZE(gpio_file))
2066 + return -ENODEV;
2067 +
2068 + MOD_INC_USE_COUNT;
2069 + return 0;
2070 +}
2071 +
2072 +static int
2073 +gpio_release(struct inode *inode, struct file * file)
2074 +{
2075 + MOD_DEC_USE_COUNT;
2076 + return 0;
2077 +}
2078 +
2079 +static ssize_t
2080 +gpio_read(struct file *file, char *buf, size_t count, loff_t *ppos)
2081 +{
2082 + u32 val;
2083 +
2084 + switch (MINOR(file->f_dentry->d_inode->i_rdev)) {
2085 + case 0:
2086 + val = sb_gpioin(gpio_sbh);
2087 + break;
2088 + case 1:
2089 + val = sb_gpioout(gpio_sbh, 0, 0, GPIO_DRV_PRIORITY);
2090 + break;
2091 + case 2:
2092 + val = sb_gpioouten(gpio_sbh, 0, 0, GPIO_DRV_PRIORITY);
2093 + break;
2094 + case 3:
2095 + val = sb_gpiocontrol(gpio_sbh, 0, 0, GPIO_DRV_PRIORITY);
2096 + break;
2097 + default:
2098 + return -ENODEV;
2099 + }
2100 +
2101 + if (put_user(val, (u32 *) buf))
2102 + return -EFAULT;
2103 +
2104 + return sizeof(val);
2105 +}
2106 +
2107 +static ssize_t
2108 +gpio_write(struct file *file, const char *buf, size_t count, loff_t *ppos)
2109 +{
2110 + u32 val;
2111 +
2112 + if (get_user(val, (u32 *) buf))
2113 + return -EFAULT;
2114 +
2115 + switch (MINOR(file->f_dentry->d_inode->i_rdev)) {
2116 + case 0:
2117 + return -EACCES;
2118 + case 1:
2119 + sb_gpioout(gpio_sbh, ~0, val, GPIO_DRV_PRIORITY);
2120 + break;
2121 + case 2:
2122 + sb_gpioouten(gpio_sbh, ~0, val, GPIO_DRV_PRIORITY);
2123 + break;
2124 + case 3:
2125 + sb_gpiocontrol(gpio_sbh, ~0, val, GPIO_DRV_PRIORITY);
2126 + break;
2127 + default:
2128 + return -ENODEV;
2129 + }
2130 +
2131 + return sizeof(val);
2132 +}
2133 +
2134 +static struct file_operations gpio_fops = {
2135 + owner: THIS_MODULE,
2136 + open: gpio_open,
2137 + release: gpio_release,
2138 + read: gpio_read,
2139 + write: gpio_write,
2140 +};
2141 +
2142 +static int __init
2143 +gpio_init(void)
2144 +{
2145 + int i;
2146 +
2147 + if (!(gpio_sbh = sb_kattach()))
2148 + return -ENODEV;
2149 +
2150 + sb_gpiosetcore(gpio_sbh);
2151 +
2152 + if ((gpio_major = devfs_register_chrdev(0, "gpio", &gpio_fops)) < 0)
2153 + return gpio_major;
2154 +
2155 + gpio_dir = devfs_mk_dir(NULL, "gpio", NULL);
2156 +
2157 + for (i = 0; i < ARRAYSIZE(gpio_file); i++) {
2158 + gpio_file[i].handle = devfs_register(gpio_dir,
2159 + gpio_file[i].name,
2160 + DEVFS_FL_DEFAULT, gpio_major, i,
2161 + S_IFCHR | S_IRUGO | S_IWUGO,
2162 + &gpio_fops, NULL);
2163 + }
2164 +
2165 + return 0;
2166 +}
2167 +
2168 +static void __exit
2169 +gpio_exit(void)
2170 +{
2171 + int i;
2172 +
2173 + for (i = 0; i < ARRAYSIZE(gpio_file); i++)
2174 + devfs_unregister(gpio_file[i].handle);
2175 + devfs_unregister(gpio_dir);
2176 + devfs_unregister_chrdev(gpio_major, "gpio");
2177 + sb_detach(gpio_sbh);
2178 +}
2179 +
2180 +module_init(gpio_init);
2181 +module_exit(gpio_exit);
2182 diff -urN linux.old/arch/mips/bcm947xx/hndchipc.c linux.dev/arch/mips/bcm947xx/hndchipc.c
2183 --- linux.old/arch/mips/bcm947xx/hndchipc.c 1970-01-01 01:00:00.000000000 +0100
2184 +++ linux.dev/arch/mips/bcm947xx/hndchipc.c 2006-10-02 21:19:59.000000000 +0200
2185 @@ -0,0 +1,158 @@
2186 +/*
2187 + * BCM47XX support code for some chipcommon (old extif) facilities (uart)
2188 + *
2189 + * Copyright 2006, Broadcom Corporation
2190 + * All Rights Reserved.
2191 + *
2192 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2193 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2194 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2195 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2196 + *
2197 + * $Id: hndchipc.c,v 1.1.1.1 2006/02/27 03:43:16 honor Exp $
2198 + */
2199 +
2200 +#include <typedefs.h>
2201 +#include <bcmdefs.h>
2202 +#include <osl.h>
2203 +#include <bcmutils.h>
2204 +#include <sbutils.h>
2205 +#include <bcmdevs.h>
2206 +#include <bcmnvram.h>
2207 +#include <sbconfig.h>
2208 +#include <sbextif.h>
2209 +#include <sbchipc.h>
2210 +#include <hndcpu.h>
2211 +
2212 +/*
2213 + * Returns TRUE if an external UART exists at the given base
2214 + * register.
2215 + */
2216 +static bool
2217 +BCMINITFN(serial_exists)(osl_t *osh, uint8 *regs)
2218 +{
2219 + uint8 save_mcr, status1;
2220 +
2221 + save_mcr = R_REG(osh, &regs[UART_MCR]);
2222 + W_REG(osh, &regs[UART_MCR], UART_MCR_LOOP | 0x0a);
2223 + status1 = R_REG(osh, &regs[UART_MSR]) & 0xf0;
2224 + W_REG(osh, &regs[UART_MCR], save_mcr);
2225 +
2226 + return (status1 == 0x90);
2227 +}
2228 +
2229 +/*
2230 + * Initializes UART access. The callback function will be called once
2231 + * per found UART.
2232 + */
2233 +void
2234 +BCMINITFN(sb_serial_init)(sb_t *sbh, void (*add)(void *regs, uint irq, uint baud_base,
2235 + uint reg_shift))
2236 +{
2237 + osl_t *osh;
2238 + void *regs;
2239 + ulong base;
2240 + uint irq;
2241 + int i, n;
2242 +
2243 + osh = sb_osh(sbh);
2244 +
2245 + if ((regs = sb_setcore(sbh, SB_EXTIF, 0))) {
2246 + extifregs_t *eir = (extifregs_t *) regs;
2247 + sbconfig_t *sb;
2248 +
2249 + /* Determine external UART register base */
2250 + sb = (sbconfig_t *)((ulong) eir + SBCONFIGOFF);
2251 + base = EXTIF_CFGIF_BASE(sb_base(R_REG(osh, &sb->sbadmatch1)));
2252 +
2253 + /* Determine IRQ */
2254 + irq = sb_irq(sbh);
2255 +
2256 + /* Disable GPIO interrupt initially */
2257 + W_REG(osh, &eir->gpiointpolarity, 0);
2258 + W_REG(osh, &eir->gpiointmask, 0);
2259 +
2260 + /* Search for external UARTs */
2261 + n = 2;
2262 + for (i = 0; i < 2; i++) {
2263 + regs = (void *) REG_MAP(base + (i * 8), 8);
2264 + if (serial_exists(osh, regs)) {
2265 + /* Set GPIO 1 to be the external UART IRQ */
2266 + W_REG(osh, &eir->gpiointmask, 2);
2267 + /* XXXDetermine external UART clock */
2268 + if (add)
2269 + add(regs, irq, 13500000, 0);
2270 + }
2271 + }
2272 +
2273 + /* Add internal UART if enabled */
2274 + if (R_REG(osh, &eir->corecontrol) & CC_UE)
2275 + if (add)
2276 + add((void *) &eir->uartdata, irq, sb_clock(sbh), 2);
2277 + } else if ((regs = sb_setcore(sbh, SB_CC, 0))) {
2278 + chipcregs_t *cc = (chipcregs_t *) regs;
2279 + uint32 rev, cap, pll, baud_base, div;
2280 +
2281 + /* Determine core revision and capabilities */
2282 + rev = sb_corerev(sbh);
2283 + cap = R_REG(osh, &cc->capabilities);
2284 + pll = cap & CAP_PLL_MASK;
2285 +
2286 + /* Determine IRQ */
2287 + irq = sb_irq(sbh);
2288 +
2289 + if (pll == PLL_TYPE1) {
2290 + /* PLL clock */
2291 + baud_base = sb_clock_rate(pll,
2292 + R_REG(osh, &cc->clockcontrol_n),
2293 + R_REG(osh, &cc->clockcontrol_m2));
2294 + div = 1;
2295 + } else {
2296 + /* Fixed ALP clock */
2297 + if (rev >= 11 && rev != 15) {
2298 + baud_base = 20000000;
2299 + div = 1;
2300 + /* Set the override bit so we don't divide it */
2301 + W_REG(osh, &cc->corecontrol, CC_UARTCLKO);
2302 + }
2303 + /* Internal backplane clock */
2304 + else if (rev >= 3) {
2305 + baud_base = sb_clock(sbh);
2306 + div = 2; /* Minimum divisor */
2307 + W_REG(osh, &cc->clkdiv,
2308 + ((R_REG(osh, &cc->clkdiv) & ~CLKD_UART) | div));
2309 + }
2310 + /* Fixed internal backplane clock */
2311 + else {
2312 + baud_base = 88000000;
2313 + div = 48;
2314 + }
2315 +
2316 + /* Clock source depends on strapping if UartClkOverride is unset */
2317 + if ((rev > 0) &&
2318 + ((R_REG(osh, &cc->corecontrol) & CC_UARTCLKO) == 0)) {
2319 + if ((cap & CAP_UCLKSEL) == CAP_UINTCLK) {
2320 + /* Internal divided backplane clock */
2321 + baud_base /= div;
2322 + } else {
2323 + /* Assume external clock of 1.8432 MHz */
2324 + baud_base = 1843200;
2325 + }
2326 + }
2327 + }
2328 +
2329 + /* Add internal UARTs */
2330 + n = cap & CAP_UARTS_MASK;
2331 + for (i = 0; i < n; i++) {
2332 + /* Register offset changed after revision 0 */
2333 + if (rev)
2334 + regs = (void *)((ulong) &cc->uart0data + (i * 256));
2335 + else
2336 + regs = (void *)((ulong) &cc->uart0data + (i * 8));
2337 +
2338 + if (add)
2339 + add(regs, irq, baud_base, 0);
2340 + }
2341 + }
2342 +}
2343 +
2344 diff -urN linux.old/arch/mips/bcm947xx/include/bcm4710.h linux.dev/arch/mips/bcm947xx/include/bcm4710.h
2345 --- linux.old/arch/mips/bcm947xx/include/bcm4710.h 1970-01-01 01:00:00.000000000 +0100
2346 +++ linux.dev/arch/mips/bcm947xx/include/bcm4710.h 2006-10-02 21:19:59.000000000 +0200
2347 @@ -0,0 +1,91 @@
2348 +/*
2349 + * BCM4710 address space map and definitions
2350 + * Think twice before adding to this file, this is not the kitchen sink
2351 + * These definitions are not guaranteed for all 47xx chips, only the 4710
2352 + *
2353 + * Copyright 2004, Broadcom Corporation
2354 + * All Rights Reserved.
2355 + *
2356 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2357 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2358 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2359 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2360 + *
2361 + * $Id: bcm4710.h,v 1.3 2004/09/27 07:23:30 tallest Exp $
2362 + */
2363 +
2364 +#ifndef _bcm4710_h_
2365 +#define _bcm4710_h_
2366 +
2367 +/* Address map */
2368 +#define BCM4710_SDRAM 0x00000000 /* Physical SDRAM */
2369 +#define BCM4710_PCI_MEM 0x08000000 /* Host Mode PCI memory access space (64 MB) */
2370 +#define BCM4710_PCI_CFG 0x0c000000 /* Host Mode PCI configuration space (64 MB) */
2371 +#define BCM4710_PCI_DMA 0x40000000 /* Client Mode PCI memory access space (1 GB) */
2372 +#define BCM4710_SDRAM_SWAPPED 0x10000000 /* Byteswapped Physical SDRAM */
2373 +#define BCM4710_ENUM 0x18000000 /* Beginning of core enumeration space */
2374 +
2375 +/* Core register space */
2376 +#define BCM4710_REG_SDRAM 0x18000000 /* SDRAM core registers */
2377 +#define BCM4710_REG_ILINE20 0x18001000 /* InsideLine20 core registers */
2378 +#define BCM4710_REG_EMAC0 0x18002000 /* Ethernet MAC 0 core registers */
2379 +#define BCM4710_REG_CODEC 0x18003000 /* Codec core registers */
2380 +#define BCM4710_REG_USB 0x18004000 /* USB core registers */
2381 +#define BCM4710_REG_PCI 0x18005000 /* PCI core registers */
2382 +#define BCM4710_REG_MIPS 0x18006000 /* MIPS core registers */
2383 +#define BCM4710_REG_EXTIF 0x18007000 /* External Interface core registers */
2384 +#define BCM4710_REG_EMAC1 0x18008000 /* Ethernet MAC 1 core registers */
2385 +
2386 +#define BCM4710_EXTIF 0x1f000000 /* External Interface base address */
2387 +#define BCM4710_PCMCIA_MEM 0x1f000000 /* External Interface PCMCIA memory access */
2388 +#define BCM4710_PCMCIA_IO 0x1f100000 /* PCMCIA I/O access */
2389 +#define BCM4710_PCMCIA_CONF 0x1f200000 /* PCMCIA configuration */
2390 +#define BCM4710_PROG 0x1f800000 /* Programable interface */
2391 +#define BCM4710_FLASH 0x1fc00000 /* Flash */
2392 +
2393 +#define BCM4710_EJTAG 0xff200000 /* MIPS EJTAG space (2M) */
2394 +
2395 +#define BCM4710_UART (BCM4710_REG_EXTIF + 0x00000300)
2396 +
2397 +#define BCM4710_EUART (BCM4710_EXTIF + 0x00800000)
2398 +#define BCM4710_LED (BCM4710_EXTIF + 0x00900000)
2399 +
2400 +#define SBFLAG_PCI 0
2401 +#define SBFLAG_ENET0 1
2402 +#define SBFLAG_ILINE20 2
2403 +#define SBFLAG_CODEC 3
2404 +#define SBFLAG_USB 4
2405 +#define SBFLAG_EXTIF 5
2406 +#define SBFLAG_ENET1 6
2407 +
2408 +#ifdef CONFIG_HWSIM
2409 +#define BCM4710_TRACE(trval) do { *((int *)0xa0000f18) = (trval); } while (0)
2410 +#else
2411 +#define BCM4710_TRACE(trval)
2412 +#endif
2413 +
2414 +
2415 +/* BCM94702 CPCI -ExtIF used for LocalBus devs */
2416 +
2417 +#define BCM94702_CPCI_RESET_ADDR BCM4710_EXTIF
2418 +#define BCM94702_CPCI_BOARDID_ADDR (BCM4710_EXTIF | 0x4000)
2419 +#define BCM94702_CPCI_DOC_ADDR (BCM4710_EXTIF | 0x6000)
2420 +#define BCM94702_DOC_ADDR BCM94702_CPCI_DOC_ADDR
2421 +#define BCM94702_CPCI_LED_ADDR (BCM4710_EXTIF | 0xc000)
2422 +#define BCM94702_CPCI_NVRAM_ADDR (BCM4710_EXTIF | 0xe000)
2423 +#define BCM94702_CPCI_NVRAM_SIZE 0x1ff0 /* 8K NVRAM : DS1743/STM48txx*/
2424 +#define BCM94702_CPCI_TOD_REG_BASE (BCM94702_CPCI_NVRAM_ADDR | 0x1ff0)
2425 +
2426 +#define LED_REG(x) \
2427 + (*(volatile unsigned char *) (KSEG1ADDR(BCM94702_CPCI_LED_ADDR) + (x)))
2428 +
2429 +/*
2430 + * Reset function implemented in PLD. Read or write should trigger hard reset
2431 + */
2432 +#define SYS_HARD_RESET() \
2433 + { for (;;) \
2434 + *( (volatile unsigned char *)\
2435 + KSEG1ADDR(BCM94702_CPCI_RESET_ADDR) ) = 0x80; \
2436 + }
2437 +
2438 +#endif /* _bcm4710_h_ */
2439 diff -urN linux.old/arch/mips/bcm947xx/include/bcmdefs.h linux.dev/arch/mips/bcm947xx/include/bcmdefs.h
2440 --- linux.old/arch/mips/bcm947xx/include/bcmdefs.h 1970-01-01 01:00:00.000000000 +0100
2441 +++ linux.dev/arch/mips/bcm947xx/include/bcmdefs.h 2006-10-02 21:19:59.000000000 +0200
2442 @@ -0,0 +1,106 @@
2443 +/*
2444 + * Misc system wide definitions
2445 + *
2446 + * Copyright 2006, Broadcom Corporation
2447 + * All Rights Reserved.
2448 + *
2449 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2450 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2451 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2452 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2453 + * $Id: bcmdefs.h,v 1.1.1.3 2006/04/08 06:13:39 honor Exp $
2454 + */
2455 +
2456 +#ifndef _bcmdefs_h_
2457 +#define _bcmdefs_h_
2458 +
2459 +/*
2460 + * One doesn't need to include this file explicitly, gets included automatically if
2461 + * typedefs.h is included.
2462 + */
2463 +
2464 +/* Reclaiming text and data :
2465 + * The following macros specify special linker sections that can be reclaimed
2466 + * after a system is considered 'up'.
2467 + */
2468 +#if defined(__GNUC__) && defined(BCMRECLAIM)
2469 +extern bool bcmreclaimed;
2470 +#define BCMINITDATA(_data) __attribute__ ((__section__ (".dataini." #_data))) _data
2471 +#define BCMINITFN(_fn) __attribute__ ((__section__ (".textini." #_fn))) _fn
2472 +#else /* #if defined(__GNUC__) && defined(BCMRECLAIM) */
2473 +#define BCMINITDATA(_data) _data
2474 +#define BCMINITFN(_fn) _fn
2475 +#define bcmreclaimed 0
2476 +#endif /* #if defined(__GNUC__) && defined(BCMRECLAIM) */
2477 +
2478 +/* Reclaim uninit functions if BCMNODOWN is defined */
2479 +/* and if they are not already removed by -gc-sections */
2480 +#ifdef BCMNODOWN
2481 +#define BCMUNINITFN(_fn) BCMINITFN(_fn)
2482 +#else
2483 +#define BCMUNINITFN(_fn) _fn
2484 +#endif
2485 +
2486 +#ifdef BCMRECLAIM
2487 +#define CONST
2488 +#else
2489 +#define CONST const
2490 +#endif /* BCMRECLAIM */
2491 +
2492 +/* Compatibility with old-style BCMRECLAIM */
2493 +#define BCMINIT(_id) _id
2494 +
2495 +
2496 +/* Put some library data/code into ROM to reduce RAM requirements */
2497 +#if defined(__GNUC__) && defined(BCMROMOFFLOAD)
2498 +#define BCMROMDATA(_data) __attribute__ ((__section__ (".datarom." #_data))) _data
2499 +#define BCMROMFN(_fn) __attribute__ ((__section__ (".textrom." #_fn))) _fn
2500 +#else
2501 +#define BCMROMDATA(_data) _data
2502 +#define BCMROMFN(_fn) _fn
2503 +#endif
2504 +
2505 +/* Bus types */
2506 +#define SB_BUS 0 /* Silicon Backplane */
2507 +#define PCI_BUS 1 /* PCI target */
2508 +#define PCMCIA_BUS 2 /* PCMCIA target */
2509 +#define SDIO_BUS 3 /* SDIO target */
2510 +#define JTAG_BUS 4 /* JTAG */
2511 +#define NO_BUS 0xFF /* Bus that does not support R/W REG */
2512 +
2513 +/* Allows optimization for single-bus support */
2514 +#ifdef BCMBUSTYPE
2515 +#define BUSTYPE(bus) (BCMBUSTYPE)
2516 +#else
2517 +#define BUSTYPE(bus) (bus)
2518 +#endif
2519 +
2520 +/* Defines for DMA Address Width - Shared between OSL and HNDDMA */
2521 +#define DMADDR_MASK_32 0x0 /* Address mask for 32-bits */
2522 +#define DMADDR_MASK_30 0xc0000000 /* Address mask for 30-bits */
2523 +#define DMADDR_MASK_0 0xffffffff /* Address mask for 0-bits (hi-part) */
2524 +
2525 +#define DMADDRWIDTH_30 30 /* 30-bit addressing capability */
2526 +#define DMADDRWIDTH_32 32 /* 32-bit addressing capability */
2527 +#define DMADDRWIDTH_63 63 /* 64-bit addressing capability */
2528 +#define DMADDRWIDTH_64 64 /* 64-bit addressing capability */
2529 +
2530 +/* packet headroom necessary to accomodate the largest header in the system, (i.e TXOFF).
2531 + * By doing, we avoid the need to allocate an extra buffer for the header when bridging to WL.
2532 + * There is a compile time check in wlc.c which ensure that this value is at least as big
2533 + * as TXOFF. This value is used in dma_rxfill (hnddma.c).
2534 + */
2535 +#define BCMEXTRAHDROOM 160
2536 +
2537 +/* Headroom required for dongle-to-host communication. Packets allocated
2538 + * locally in the dongle (e.g. for CDC ioctls or RNDIS messages) should
2539 + * leave this much room in front for low-level message headers which may
2540 + * be needed to get across the dongle bus to the host. (These messages
2541 + * don't go over the network, so room for the full WL header above would
2542 + * be a waste.)
2543 + */
2544 +#define BCMDONGLEHDRSZ 8
2545 +
2546 +
2547 +
2548 +#endif /* _bcmdefs_h_ */
2549 diff -urN linux.old/arch/mips/bcm947xx/include/bcmdevs1.h linux.dev/arch/mips/bcm947xx/include/bcmdevs1.h
2550 --- linux.old/arch/mips/bcm947xx/include/bcmdevs1.h 1970-01-01 01:00:00.000000000 +0100
2551 +++ linux.dev/arch/mips/bcm947xx/include/bcmdevs1.h 2006-10-02 21:19:59.000000000 +0200
2552 @@ -0,0 +1,391 @@
2553 +/*
2554 + * Broadcom device-specific manifest constants.
2555 + *
2556 + * Copyright 2005, Broadcom Corporation
2557 + * All Rights Reserved.
2558 + *
2559 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2560 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2561 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2562 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2563 + * $Id$
2564 + */
2565 +
2566 +#ifndef _BCMDEVS_H
2567 +#define _BCMDEVS_H
2568 +
2569 +
2570 +/* Known PCI vendor Id's */
2571 +#define VENDOR_EPIGRAM 0xfeda
2572 +#define VENDOR_BROADCOM 0x14e4
2573 +#define VENDOR_3COM 0x10b7
2574 +#define VENDOR_NETGEAR 0x1385
2575 +#define VENDOR_DIAMOND 0x1092
2576 +#define VENDOR_DELL 0x1028
2577 +#define VENDOR_HP 0x0e11
2578 +#define VENDOR_APPLE 0x106b
2579 +
2580 +/* PCI Device Id's */
2581 +#define BCM4210_DEVICE_ID 0x1072 /* never used */
2582 +#define BCM4211_DEVICE_ID 0x4211
2583 +#define BCM4230_DEVICE_ID 0x1086 /* never used */
2584 +#define BCM4231_DEVICE_ID 0x4231
2585 +
2586 +#define BCM4410_DEVICE_ID 0x4410 /* bcm44xx family pci iline */
2587 +#define BCM4430_DEVICE_ID 0x4430 /* bcm44xx family cardbus iline */
2588 +#define BCM4412_DEVICE_ID 0x4412 /* bcm44xx family pci enet */
2589 +#define BCM4432_DEVICE_ID 0x4432 /* bcm44xx family cardbus enet */
2590 +
2591 +#define BCM3352_DEVICE_ID 0x3352 /* bcm3352 device id */
2592 +#define BCM3360_DEVICE_ID 0x3360 /* bcm3360 device id */
2593 +
2594 +#define EPI41210_DEVICE_ID 0xa0fa /* bcm4210 */
2595 +#define EPI41230_DEVICE_ID 0xa10e /* bcm4230 */
2596 +
2597 +#define BCM47XX_ILINE_ID 0x4711 /* 47xx iline20 */
2598 +#define BCM47XX_V90_ID 0x4712 /* 47xx v90 codec */
2599 +#define BCM47XX_ENET_ID 0x4713 /* 47xx enet */
2600 +#define BCM47XX_EXT_ID 0x4714 /* 47xx external i/f */
2601 +#define BCM47XX_USB_ID 0x4715 /* 47xx usb */
2602 +#define BCM47XX_USBH_ID 0x4716 /* 47xx usb host */
2603 +#define BCM47XX_USBD_ID 0x4717 /* 47xx usb device */
2604 +#define BCM47XX_IPSEC_ID 0x4718 /* 47xx ipsec */
2605 +#define BCM47XX_ROBO_ID 0x4719 /* 47xx/53xx roboswitch core */
2606 +#define BCM47XX_USB20H_ID 0x471a /* 47xx usb 2.0 host */
2607 +#define BCM47XX_USB20D_ID 0x471b /* 47xx usb 2.0 device */
2608 +
2609 +#define BCM4710_DEVICE_ID 0x4710 /* 4710 primary function 0 */
2610 +
2611 +#define BCM4610_DEVICE_ID 0x4610 /* 4610 primary function 0 */
2612 +#define BCM4610_ILINE_ID 0x4611 /* 4610 iline100 */
2613 +#define BCM4610_V90_ID 0x4612 /* 4610 v90 codec */
2614 +#define BCM4610_ENET_ID 0x4613 /* 4610 enet */
2615 +#define BCM4610_EXT_ID 0x4614 /* 4610 external i/f */
2616 +#define BCM4610_USB_ID 0x4615 /* 4610 usb */
2617 +
2618 +#define BCM4402_DEVICE_ID 0x4402 /* 4402 primary function 0 */
2619 +#define BCM4402_ENET_ID 0x4402 /* 4402 enet */
2620 +#define BCM4402_V90_ID 0x4403 /* 4402 v90 codec */
2621 +#define BCM4401_ENET_ID 0x170c /* 4401b0 production enet cards */
2622 +
2623 +#define BCM4301_DEVICE_ID 0x4301 /* 4301 primary function 0 */
2624 +#define BCM4301_D11B_ID 0x4301 /* 4301 802.11b */
2625 +
2626 +#define BCM4307_DEVICE_ID 0x4307 /* 4307 primary function 0 */
2627 +#define BCM4307_V90_ID 0x4305 /* 4307 v90 codec */
2628 +#define BCM4307_ENET_ID 0x4306 /* 4307 enet */
2629 +#define BCM4307_D11B_ID 0x4307 /* 4307 802.11b */
2630 +
2631 +#define BCM4306_DEVICE_ID 0x4306 /* 4306 chipcommon chipid */
2632 +#define BCM4306_D11G_ID 0x4320 /* 4306 802.11g */
2633 +#define BCM4306_D11G_ID2 0x4325
2634 +#define BCM4306_D11A_ID 0x4321 /* 4306 802.11a */
2635 +#define BCM4306_UART_ID 0x4322 /* 4306 uart */
2636 +#define BCM4306_V90_ID 0x4323 /* 4306 v90 codec */
2637 +#define BCM4306_D11DUAL_ID 0x4324 /* 4306 dual A+B */
2638 +
2639 +#define BCM4309_PKG_ID 1 /* 4309 package id */
2640 +
2641 +#define BCM4303_D11B_ID 0x4303 /* 4303 802.11b */
2642 +#define BCM4303_PKG_ID 2 /* 4303 package id */
2643 +
2644 +#define BCM4310_DEVICE_ID 0x4310 /* 4310 chipcommon chipid */
2645 +#define BCM4310_D11B_ID 0x4311 /* 4310 802.11b */
2646 +#define BCM4310_UART_ID 0x4312 /* 4310 uart */
2647 +#define BCM4310_ENET_ID 0x4313 /* 4310 enet */
2648 +#define BCM4310_USB_ID 0x4315 /* 4310 usb */
2649 +
2650 +#define BCMGPRS_UART_ID 0x4333 /* Uart id used by 4306/gprs card */
2651 +#define BCMGPRS2_UART_ID 0x4344 /* Uart id used by 4306/gprs card */
2652 +
2653 +
2654 +#define BCM4704_DEVICE_ID 0x4704 /* 4704 chipcommon chipid */
2655 +#define BCM4704_ENET_ID 0x4706 /* 4704 enet (Use 47XX_ENET_ID instead!) */
2656 +
2657 +#define BCM4317_DEVICE_ID 0x4317 /* 4317 chip common chipid */
2658 +
2659 +#define BCM4318_DEVICE_ID 0x4318 /* 4318 chip common chipid */
2660 +#define BCM4318_D11G_ID 0x4318 /* 4318 801.11b/g id */
2661 +#define BCM4318_D11DUAL_ID 0x4319 /* 4318 801.11a/b/g id */
2662 +#define BCM4318_JTAGM_ID 0x4331 /* 4318 jtagm device id */
2663 +
2664 +#define FPGA_JTAGM_ID 0x4330 /* ??? */
2665 +
2666 +/* Address map */
2667 +#define BCM4710_SDRAM 0x00000000 /* Physical SDRAM */
2668 +#define BCM4710_PCI_MEM 0x08000000 /* Host Mode PCI memory access space (64 MB) */
2669 +#define BCM4710_PCI_CFG 0x0c000000 /* Host Mode PCI configuration space (64 MB) */
2670 +#define BCM4710_PCI_DMA 0x40000000 /* Client Mode PCI memory access space (1 GB) */
2671 +#define BCM4710_SDRAM_SWAPPED 0x10000000 /* Byteswapped Physical SDRAM */
2672 +#define BCM4710_ENUM 0x18000000 /* Beginning of core enumeration space */
2673 +
2674 +/* Core register space */
2675 +#define BCM4710_REG_SDRAM 0x18000000 /* SDRAM core registers */
2676 +#define BCM4710_REG_ILINE20 0x18001000 /* InsideLine20 core registers */
2677 +#define BCM4710_REG_EMAC0 0x18002000 /* Ethernet MAC 0 core registers */
2678 +#define BCM4710_REG_CODEC 0x18003000 /* Codec core registers */
2679 +#define BCM4710_REG_USB 0x18004000 /* USB core registers */
2680 +#define BCM4710_REG_PCI 0x18005000 /* PCI core registers */
2681 +#define BCM4710_REG_MIPS 0x18006000 /* MIPS core registers */
2682 +#define BCM4710_REG_EXTIF 0x18007000 /* External Interface core registers */
2683 +#define BCM4710_REG_EMAC1 0x18008000 /* Ethernet MAC 1 core registers */
2684 +
2685 +#define BCM4710_EXTIF 0x1f000000 /* External Interface base address */
2686 +#define BCM4710_PCMCIA_MEM 0x1f000000 /* External Interface PCMCIA memory access */
2687 +#define BCM4710_PCMCIA_IO 0x1f100000 /* PCMCIA I/O access */
2688 +#define BCM4710_PCMCIA_CONF 0x1f200000 /* PCMCIA configuration */
2689 +#define BCM4710_PROG 0x1f800000 /* Programable interface */
2690 +#define BCM4710_FLASH 0x1fc00000 /* Flash */
2691 +
2692 +#define BCM4710_EJTAG 0xff200000 /* MIPS EJTAG space (2M) */
2693 +
2694 +#define BCM4710_UART (BCM4710_REG_EXTIF + 0x00000300)
2695 +
2696 +#define BCM4710_EUART (BCM4710_EXTIF + 0x00800000)
2697 +#define BCM4710_LED (BCM4710_EXTIF + 0x00900000)
2698 +
2699 +#define BCM4712_DEVICE_ID 0x4712 /* 4712 chipcommon chipid */
2700 +#define BCM4712_MIPS_ID 0x4720 /* 4712 base devid */
2701 +#define BCM4712LARGE_PKG_ID 0 /* 340pin 4712 package id */
2702 +#define BCM4712SMALL_PKG_ID 1 /* 200pin 4712 package id */
2703 +#define BCM4712MID_PKG_ID 2 /* 225pin 4712 package id */
2704 +
2705 +#define SDIOH_FPGA_ID 0x4380 /* sdio host fpga */
2706 +
2707 +#define BCM5365_DEVICE_ID 0x5365 /* 5365 chipcommon chipid */
2708 +#define BCM5350_DEVICE_ID 0x5350 /* bcm5350 chipcommon chipid */
2709 +#define BCM5352_DEVICE_ID 0x5352 /* bcm5352 chipcommon chipid */
2710 +
2711 +#define BCM4320_DEVICE_ID 0x4320 /* bcm4320 chipcommon chipid */
2712 +
2713 +/* PCMCIA vendor Id's */
2714 +
2715 +#define VENDOR_BROADCOM_PCMCIA 0x02d0
2716 +
2717 +/* SDIO vendor Id's */
2718 +#define VENDOR_BROADCOM_SDIO 0x00BF
2719 +
2720 +
2721 +/* boardflags */
2722 +#define BFL_BTCOEXIST 0x0001 /* This board implements Bluetooth coexistance */
2723 +#define BFL_PACTRL 0x0002 /* This board has gpio 9 controlling the PA */
2724 +#define BFL_AIRLINEMODE 0x0004 /* This board implements gpio13 radio disable indication */
2725 +#define BFL_ENETROBO 0x0010 /* This board has robo switch or core */
2726 +#define BFL_CCKHIPWR 0x0040 /* Can do high-power CCK transmission */
2727 +#define BFL_ENETADM 0x0080 /* This board has ADMtek switch */
2728 +#define BFL_ENETVLAN 0x0100 /* This board has vlan capability */
2729 +#define BFL_AFTERBURNER 0x0200 /* This board supports Afterburner mode */
2730 +#define BFL_NOPCI 0x0400 /* This board leaves PCI floating */
2731 +#define BFL_FEM 0x0800 /* This board supports the Front End Module */
2732 +#define BFL_EXTLNA 0x1000 /* This board has an external LNA */
2733 +#define BFL_HGPA 0x2000 /* This board has a high gain PA */
2734 +#define BFL_BTCMOD 0x4000 /* This board' BTCOEXIST is in the alternate gpios */
2735 +#define BFL_ALTIQ 0x8000 /* Alternate I/Q settings */
2736 +
2737 +/* board specific GPIO assignment, gpio 0-3 are also customer-configurable led */
2738 +#define BOARD_GPIO_HWRAD_B 0x010 /* bit 4 is HWRAD input on 4301 */
2739 +#define BOARD_GPIO_BTCMOD_IN 0x010 /* bit 4 is the alternate BT Coexistance Input */
2740 +#define BOARD_GPIO_BTCMOD_OUT 0x020 /* bit 5 is the alternate BT Coexistance Out */
2741 +#define BOARD_GPIO_BTC_IN 0x080 /* bit 7 is BT Coexistance Input */
2742 +#define BOARD_GPIO_BTC_OUT 0x100 /* bit 8 is BT Coexistance Out */
2743 +#define BOARD_GPIO_PACTRL 0x200 /* bit 9 controls the PA on new 4306 boards */
2744 +#define PCI_CFG_GPIO_SCS 0x10 /* PCI config space bit 4 for 4306c0 slow clock source */
2745 +#define PCI_CFG_GPIO_HWRAD 0x20 /* PCI config space GPIO 13 for hw radio disable */
2746 +#define PCI_CFG_GPIO_XTAL 0x40 /* PCI config space GPIO 14 for Xtal powerup */
2747 +#define PCI_CFG_GPIO_PLL 0x80 /* PCI config space GPIO 15 for PLL powerdown */
2748 +
2749 +/* Bus types */
2750 +#define SB_BUS 0 /* Silicon Backplane */
2751 +#define PCI_BUS 1 /* PCI target */
2752 +#define PCMCIA_BUS 2 /* PCMCIA target */
2753 +#define SDIO_BUS 3 /* SDIO target */
2754 +#define JTAG_BUS 4 /* JTAG */
2755 +
2756 +/* Allows optimization for single-bus support */
2757 +#ifdef BCMBUSTYPE
2758 +#define BUSTYPE(bus) (BCMBUSTYPE)
2759 +#else
2760 +#define BUSTYPE(bus) (bus)
2761 +#endif
2762 +
2763 +/* power control defines */
2764 +#define PLL_DELAY 150 /* us pll on delay */
2765 +#define FREF_DELAY 200 /* us fref change delay */
2766 +#define MIN_SLOW_CLK 32 /* us Slow clock period */
2767 +#define XTAL_ON_DELAY 1000 /* us crystal power-on delay */
2768 +
2769 +/* Reference Board Types */
2770 +
2771 +#define BU4710_BOARD 0x0400
2772 +#define VSIM4710_BOARD 0x0401
2773 +#define QT4710_BOARD 0x0402
2774 +
2775 +#define BU4610_BOARD 0x0403
2776 +#define VSIM4610_BOARD 0x0404
2777 +
2778 +#define BU4307_BOARD 0x0405
2779 +#define BCM94301CB_BOARD 0x0406
2780 +#define BCM94301PC_BOARD 0x0406 /* Pcmcia 5v card */
2781 +#define BCM94301MP_BOARD 0x0407
2782 +#define BCM94307MP_BOARD 0x0408
2783 +#define BCMAP4307_BOARD 0x0409
2784 +
2785 +#define BU4309_BOARD 0x040a
2786 +#define BCM94309CB_BOARD 0x040b
2787 +#define BCM94309MP_BOARD 0x040c
2788 +#define BCM4309AP_BOARD 0x040d
2789 +
2790 +#define BCM94302MP_BOARD 0x040e
2791 +
2792 +#define VSIM4310_BOARD 0x040f
2793 +#define BU4711_BOARD 0x0410
2794 +#define BCM94310U_BOARD 0x0411
2795 +#define BCM94310AP_BOARD 0x0412
2796 +#define BCM94310MP_BOARD 0x0414
2797 +
2798 +#define BU4306_BOARD 0x0416
2799 +#define BCM94306CB_BOARD 0x0417
2800 +#define BCM94306MP_BOARD 0x0418
2801 +
2802 +#define BCM94710D_BOARD 0x041a
2803 +#define BCM94710R1_BOARD 0x041b
2804 +#define BCM94710R4_BOARD 0x041c
2805 +#define BCM94710AP_BOARD 0x041d
2806 +
2807 +
2808 +#define BU2050_BOARD 0x041f
2809 +
2810 +
2811 +#define BCM94309G_BOARD 0x0421
2812 +
2813 +#define BCM94301PC3_BOARD 0x0422 /* Pcmcia 3.3v card */
2814 +
2815 +#define BU4704_BOARD 0x0423
2816 +#define BU4702_BOARD 0x0424
2817 +
2818 +#define BCM94306PC_BOARD 0x0425 /* pcmcia 3.3v 4306 card */
2819 +
2820 +#define BU4317_BOARD 0x0426
2821 +
2822 +
2823 +#define BCM94702MN_BOARD 0x0428
2824 +
2825 +/* BCM4702 1U CompactPCI Board */
2826 +#define BCM94702CPCI_BOARD 0x0429
2827 +
2828 +/* BCM4702 with BCM95380 VLAN Router */
2829 +#define BCM95380RR_BOARD 0x042a
2830 +
2831 +/* cb4306 with SiGe PA */
2832 +#define BCM94306CBSG_BOARD 0x042b
2833 +
2834 +/* mp4301 with 2050 radio */
2835 +#define BCM94301MPL_BOARD 0x042c
2836 +
2837 +/* cb4306 with SiGe PA */
2838 +#define PCSG94306_BOARD 0x042d
2839 +
2840 +/* bu4704 with sdram */
2841 +#define BU4704SD_BOARD 0x042e
2842 +
2843 +/* Dual 11a/11g Router */
2844 +#define BCM94704AGR_BOARD 0x042f
2845 +
2846 +/* 11a-only minipci */
2847 +#define BCM94308MP_BOARD 0x0430
2848 +
2849 +
2850 +
2851 +/* BCM94317 boards */
2852 +#define BCM94317CB_BOARD 0x0440
2853 +#define BCM94317MP_BOARD 0x0441
2854 +#define BCM94317PCMCIA_BOARD 0x0442
2855 +#define BCM94317SDIO_BOARD 0x0443
2856 +
2857 +#define BU4712_BOARD 0x0444
2858 +#define BU4712SD_BOARD 0x045d
2859 +#define BU4712L_BOARD 0x045f
2860 +
2861 +/* BCM4712 boards */
2862 +#define BCM94712AP_BOARD 0x0445
2863 +#define BCM94712P_BOARD 0x0446
2864 +
2865 +/* BCM4318 boards */
2866 +#define BU4318_BOARD 0x0447
2867 +#define CB4318_BOARD 0x0448
2868 +#define MPG4318_BOARD 0x0449
2869 +#define MP4318_BOARD 0x044a
2870 +#define SD4318_BOARD 0x044b
2871 +
2872 +/* BCM63XX boards */
2873 +#define BCM96338_BOARD 0x6338
2874 +#define BCM96345_BOARD 0x6345
2875 +#define BCM96348_BOARD 0x6348
2876 +
2877 +/* Another mp4306 with SiGe */
2878 +#define BCM94306P_BOARD 0x044c
2879 +
2880 +/* CF-like 4317 modules */
2881 +#define BCM94317CF_BOARD 0x044d
2882 +
2883 +/* mp4303 */
2884 +#define BCM94303MP_BOARD 0x044e
2885 +
2886 +/* mpsgh4306 */
2887 +#define BCM94306MPSGH_BOARD 0x044f
2888 +
2889 +/* BRCM 4306 w/ Front End Modules */
2890 +#define BCM94306MPM 0x0450
2891 +#define BCM94306MPL 0x0453
2892 +
2893 +/* 4712agr */
2894 +#define BCM94712AGR_BOARD 0x0451
2895 +
2896 +/* The real CF 4317 board */
2897 +#define CFI4317_BOARD 0x0452
2898 +
2899 +/* pcmcia 4303 */
2900 +#define PC4303_BOARD 0x0454
2901 +
2902 +/* 5350K */
2903 +#define BCM95350K_BOARD 0x0455
2904 +
2905 +/* 5350R */
2906 +#define BCM95350R_BOARD 0x0456
2907 +
2908 +/* 4306mplna */
2909 +#define BCM94306MPLNA_BOARD 0x0457
2910 +
2911 +/* 4320 boards */
2912 +#define BU4320_BOARD 0x0458
2913 +#define BU4320S_BOARD 0x0459
2914 +#define BCM94320PH_BOARD 0x045a
2915 +
2916 +/* 4306mph */
2917 +#define BCM94306MPH_BOARD 0x045b
2918 +
2919 +/* 4306pciv */
2920 +#define BCM94306PCIV_BOARD 0x045c
2921 +
2922 +#define BU4712SD_BOARD 0x045d
2923 +
2924 +#define BCM94320PFLSH_BOARD 0x045e
2925 +
2926 +#define BU4712L_BOARD 0x045f
2927 +#define BCM94712LGR_BOARD 0x0460
2928 +#define BCM94320R_BOARD 0x0461
2929 +
2930 +#define BU5352_BOARD 0x0462
2931 +
2932 +#define BCM94318MPGH_BOARD 0x0463
2933 +
2934 +
2935 +#define BCM95352GR_BOARD 0x0467
2936 +
2937 +/* bcm95351agr */
2938 +#define BCM95351AGR_BOARD 0x0470
2939 +
2940 +/* # of GPIO pins */
2941 +#define GPIO_NUMPINS 16
2942 +
2943 +#endif /* _BCMDEVS_H */
2944 diff -urN linux.old/arch/mips/bcm947xx/include/bcmdevs.h linux.dev/arch/mips/bcm947xx/include/bcmdevs.h
2945 --- linux.old/arch/mips/bcm947xx/include/bcmdevs.h 1970-01-01 01:00:00.000000000 +0100
2946 +++ linux.dev/arch/mips/bcm947xx/include/bcmdevs.h 2006-10-02 21:19:59.000000000 +0200
2947 @@ -0,0 +1,369 @@
2948 +/*
2949 + * Broadcom device-specific manifest constants.
2950 + *
2951 + * Copyright 2006, Broadcom Corporation
2952 + * All Rights Reserved.
2953 + *
2954 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2955 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2956 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2957 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2958 + * $Id: bcmdevs.h,v 1.1.1.17 2006/04/15 01:29:08 michael Exp $
2959 + */
2960 +
2961 +#ifndef _BCMDEVS_H
2962 +#define _BCMDEVS_H
2963 +
2964 +#include "bcm4710.h"
2965 +
2966 +/* Known PCI vendor Id's */
2967 +#define VENDOR_EPIGRAM 0xfeda
2968 +#define VENDOR_BROADCOM 0x14e4
2969 +#define VENDOR_3COM 0x10b7
2970 +#define VENDOR_NETGEAR 0x1385
2971 +#define VENDOR_DIAMOND 0x1092
2972 +#define VENDOR_DELL 0x1028
2973 +#define VENDOR_HP 0x0e11
2974 +#define VENDOR_APPLE 0x106b
2975 +
2976 +/* PCI Device Id's */
2977 +#define BCM4210_DEVICE_ID 0x1072 /* never used */
2978 +#define BCM4211_DEVICE_ID 0x4211
2979 +#define BCM4230_DEVICE_ID 0x1086 /* never used */
2980 +#define BCM4231_DEVICE_ID 0x4231
2981 +
2982 +#define BCM4410_DEVICE_ID 0x4410 /* bcm44xx family pci iline */
2983 +#define BCM4430_DEVICE_ID 0x4430 /* bcm44xx family cardbus iline */
2984 +#define BCM4412_DEVICE_ID 0x4412 /* bcm44xx family pci enet */
2985 +#define BCM4432_DEVICE_ID 0x4432 /* bcm44xx family cardbus enet */
2986 +
2987 +#define BCM3352_DEVICE_ID 0x3352 /* bcm3352 device id */
2988 +#define BCM3360_DEVICE_ID 0x3360 /* bcm3360 device id */
2989 +
2990 +#define EPI41210_DEVICE_ID 0xa0fa /* bcm4210 */
2991 +#define EPI41230_DEVICE_ID 0xa10e /* bcm4230 */
2992 +
2993 +#define BCM47XX_ILINE_ID 0x4711 /* 47xx iline20 */
2994 +#define BCM47XX_V90_ID 0x4712 /* 47xx v90 codec */
2995 +#define BCM47XX_ENET_ID 0x4713 /* 47xx enet */
2996 +#define BCM47XX_EXT_ID 0x4714 /* 47xx external i/f */
2997 +#define BCM47XX_USB_ID 0x4715 /* 47xx usb */
2998 +#define BCM47XX_USBH_ID 0x4716 /* 47xx usb host */
2999 +#define BCM47XX_USBD_ID 0x4717 /* 47xx usb device */
3000 +#define BCM47XX_IPSEC_ID 0x4718 /* 47xx ipsec */
3001 +#define BCM47XX_ROBO_ID 0x4719 /* 47xx/53xx roboswitch core */
3002 +#define BCM47XX_USB20H_ID 0x471a /* 47xx usb 2.0 host */
3003 +#define BCM47XX_USB20D_ID 0x471b /* 47xx usb 2.0 device */
3004 +#define BCM47XX_ATA100_ID 0x471d /* 47xx parallel ATA */
3005 +#define BCM47XX_SATAXOR_ID 0x471e /* 47xx serial ATA & XOR DMA */
3006 +#define BCM47XX_GIGETH_ID 0x471f /* 47xx GbE (5700) */
3007 +
3008 +#define BCM47XX_SMBUS_EMU_ID 0x47fe /* 47xx emulated SMBus device */
3009 +#define BCM47XX_XOR_EMU_ID 0x47ff /* 47xx emulated XOR engine */
3010 +
3011 +#define BCM4710_CHIP_ID 0x4710 /* 4710 chipid returned by sb_chip() */
3012 +#define BCM4710_DEVICE_ID 0x4710 /* 4710 primary function 0 */
3013 +
3014 +#define BCM4402_CHIP_ID 0x4402 /* 4402 chipid */
3015 +#define BCM4402_ENET_ID 0x4402 /* 4402 enet */
3016 +#define BCM4402_V90_ID 0x4403 /* 4402 v90 codec */
3017 +#define BCM4401_ENET_ID 0x170c /* 4401b0 production enet cards */
3018 +
3019 +#define BCM4306_CHIP_ID 0x4306 /* 4306 chipcommon chipid */
3020 +#define BCM4306_D11G_ID 0x4320 /* 4306 802.11g */
3021 +#define BCM4306_D11G_ID2 0x4325
3022 +#define BCM4306_D11A_ID 0x4321 /* 4306 802.11a */
3023 +#define BCM4306_UART_ID 0x4322 /* 4306 uart */
3024 +#define BCM4306_V90_ID 0x4323 /* 4306 v90 codec */
3025 +#define BCM4306_D11DUAL_ID 0x4324 /* 4306 dual A+B */
3026 +
3027 +#define BCM4309_PKG_ID 1 /* 4309 package id */
3028 +
3029 +#define BCM4311_CHIP_ID 0x4311 /* 4311 PCIe 802.11a/b/g */
3030 +#define BCM4311_D11G_ID 0x4311 /* 4311 802.11b/g id */
3031 +#define BCM4311_D11DUAL_ID 0x4312 /* 4311 802.11a/b/g id */
3032 +#define BCM4311_D11A_ID 0x4313 /* 4311 802.11a id */
3033 +
3034 +#define BCM4303_D11B_ID 0x4303 /* 4303 802.11b */
3035 +#define BCM4303_PKG_ID 2 /* 4303 package id */
3036 +
3037 +#define BCMGPRS_UART_ID 0x4333 /* Uart id used by 4306/gprs card */
3038 +#define BCMGPRS2_UART_ID 0x4344 /* Uart id used by 4306/gprs card */
3039 +
3040 +#define BCM4704_CHIP_ID 0x4704 /* 4704 chipcommon chipid */
3041 +#define BCM4704_ENET_ID 0x4706 /* 4704 enet (Use 47XX_ENET_ID instead!) */
3042 +
3043 +#define BCM4318_CHIP_ID 0x4318 /* 4318 chip common chipid */
3044 +#define BCM4318_D11G_ID 0x4318 /* 4318 802.11b/g id */
3045 +#define BCM4318_D11DUAL_ID 0x4319 /* 4318 802.11a/b/g id */
3046 +#define BCM4318_D11A_ID 0x431a /* 4318 802.11a id */
3047 +
3048 +#define BCM4321_CHIP_ID 0x4321 /* 4321 chip common chipid */
3049 +#define BCM4321_D11N_ID 0x4328 /* 4321 802.11n dualband id */
3050 +#define BCM4321_D11N2G_ID 0x4329 /* 4321 802.11n 2.4Hgz band id */
3051 +#define BCM4321_D11N5G_ID 0x432a /* 4321 802.11n 5Ghz band id */
3052 +
3053 +#define BCM4331_CHIP_ID 0x4331 /* 4331 chip common chipid */
3054 +#define BCM4331_D11N2G_ID 0x4330 /* 4331 802.11n 2.4Ghz band id */
3055 +#define BCM4331_D11N_ID 0x4331 /* 4331 802.11n dualband id */
3056 +#define BCM4331_D11N5G_ID 0x4332 /* 4331 802.11n 5Ghz band id */
3057 +
3058 +#define HDLSIM5350_PKG_ID 1 /* HDL simulator package id for a 5350 */
3059 +#define HDLSIM_PKG_ID 14 /* HDL simulator package id */
3060 +#define HWSIM_PKG_ID 15 /* Hardware simulator package id */
3061 +
3062 +#define BCM4712_CHIP_ID 0x4712 /* 4712 chipcommon chipid */
3063 +#define BCM4712_MIPS_ID 0x4720 /* 4712 base devid */
3064 +#define BCM4712LARGE_PKG_ID 0 /* 340pin 4712 package id */
3065 +#define BCM4712SMALL_PKG_ID 1 /* 200pin 4712 package id */
3066 +#define BCM4712MID_PKG_ID 2 /* 225pin 4712 package id */
3067 +
3068 +#define BCM5365_CHIP_ID 0x5365 /* 5365 chipcommon chipid */
3069 +#define BCM5350_CHIP_ID 0x5350 /* bcm5350 chipcommon chipid */
3070 +#define BCM5352_CHIP_ID 0x5352 /* bcm5352 chipcommon chipid */
3071 +
3072 +#define BCM4320_CHIP_ID 0x4320 /* bcm4320 chipcommon chipid */
3073 +
3074 +#define BCM4328_CHIP_ID 0x4328 /* bcm4328 chipcommon chipid */
3075 +
3076 +#define FPGA_JTAGM_ID 0x43f0 /* FPGA jtagm device id */
3077 +#define BCM43XX_JTAGM_ID 0x43f1 /* 43xx jtagm device id */
3078 +#define BCM43XXOLD_JTAGM_ID 0x4331 /* 43xx old jtagm device id */
3079 +
3080 +#define SDIOH_FPGA_ID 0x43f2 /* sdio host fpga */
3081 +#define SDIOD_FPGA_ID 0x43f4 /* sdio device fpga */
3082 +
3083 +#define MIMO_FPGA_ID 0x43f8 /* FPGA mimo minimacphy device id */
3084 +
3085 +#define BCM4785_CHIP_ID 0x4785 /* 4785 chipcommon chipid */
3086 +
3087 +/* PCMCIA vendor Id's */
3088 +
3089 +#define VENDOR_BROADCOM_PCMCIA 0x02d0
3090 +
3091 +/* SDIO vendor Id's */
3092 +#define VENDOR_BROADCOM_SDIO 0x00BF
3093 +
3094 +
3095 +/* boardflags */
3096 +#define BFL_BTCOEXIST 0x0001 /* This board implements Bluetooth coexistance */
3097 +#define BFL_PACTRL 0x0002 /* This board has gpio 9 controlling the PA */
3098 +#define BFL_AIRLINEMODE 0x0004 /* This board implements gpio13 radio disable indication */
3099 +#define BFL_ENETROBO 0x0010 /* This board has robo switch or core */
3100 +#define BFL_CCKHIPWR 0x0040 /* Can do high-power CCK transmission */
3101 +#define BFL_ENETADM 0x0080 /* This board has ADMtek switch */
3102 +#define BFL_ENETVLAN 0x0100 /* This board has vlan capability */
3103 +#define BFL_AFTERBURNER 0x0200 /* This board supports Afterburner mode */
3104 +#define BFL_NOPCI 0x0400 /* This board leaves PCI floating */
3105 +#define BFL_FEM 0x0800 /* This board supports the Front End Module */
3106 +#define BFL_EXTLNA 0x1000 /* This board has an external LNA */
3107 +#define BFL_HGPA 0x2000 /* This board has a high gain PA */
3108 +#define BFL_BTCMOD 0x4000 /* This board' BTCOEXIST is in the alternate gpios */
3109 +#define BFL_ALTIQ 0x8000 /* Alternate I/Q settings */
3110 +
3111 +/* boardflags2 */
3112 +#define BFL2_RXBB_INT_REG_DIS 0x00000001 /* This board has an external rxbb regulator */
3113 +#define BFL2_SSWITCH_AVAIL 0x00000002 /* This board has a superswitch for > 2 antennas */
3114 +#define BFL2_TXPWRCTRL_EN 0x00000004 /* This board permits TX Power Control to be enabled */
3115 +
3116 +/* board specific GPIO assignment, gpio 0-3 are also customer-configurable led */
3117 +#define BOARD_GPIO_BTCMOD_IN 0x010 /* bit 4 is the alternate BT Coexistance Input */
3118 +#define BOARD_GPIO_BTCMOD_OUT 0x020 /* bit 5 is the alternate BT Coexistance Out */
3119 +#define BOARD_GPIO_BTC_IN 0x080 /* bit 7 is BT Coexistance Input */
3120 +#define BOARD_GPIO_BTC_OUT 0x100 /* bit 8 is BT Coexistance Out */
3121 +#define BOARD_GPIO_PACTRL 0x200 /* bit 9 controls the PA on new 4306 boards */
3122 +#define PCI_CFG_GPIO_SCS 0x10 /* PCI config space bit 4 for 4306c0 slow clock source */
3123 +#define PCI_CFG_GPIO_HWRAD 0x20 /* PCI config space GPIO 13 for hw radio disable */
3124 +#define PCI_CFG_GPIO_XTAL 0x40 /* PCI config space GPIO 14 for Xtal powerup */
3125 +#define PCI_CFG_GPIO_PLL 0x80 /* PCI config space GPIO 15 for PLL powerdown */
3126 +
3127 +/* power control defines */
3128 +#define PLL_DELAY 150 /* us pll on delay */
3129 +#define FREF_DELAY 200 /* us fref change delay */
3130 +#define MIN_SLOW_CLK 32 /* us Slow clock period */
3131 +#define XTAL_ON_DELAY 1000 /* us crystal power-on delay */
3132 +
3133 +/* Reference Board Types */
3134 +
3135 +#define BU4710_BOARD 0x0400
3136 +#define VSIM4710_BOARD 0x0401
3137 +#define QT4710_BOARD 0x0402
3138 +
3139 +#define BU4309_BOARD 0x040a
3140 +#define BCM94309CB_BOARD 0x040b
3141 +#define BCM94309MP_BOARD 0x040c
3142 +#define BCM4309AP_BOARD 0x040d
3143 +
3144 +#define BCM94302MP_BOARD 0x040e
3145 +
3146 +#define BU4306_BOARD 0x0416
3147 +#define BCM94306CB_BOARD 0x0417
3148 +#define BCM94306MP_BOARD 0x0418
3149 +
3150 +#define BCM94710D_BOARD 0x041a
3151 +#define BCM94710R1_BOARD 0x041b
3152 +#define BCM94710R4_BOARD 0x041c
3153 +#define BCM94710AP_BOARD 0x041d
3154 +
3155 +#define BU2050_BOARD 0x041f
3156 +
3157 +
3158 +#define BCM94309G_BOARD 0x0421
3159 +
3160 +#define BU4704_BOARD 0x0423
3161 +#define BU4702_BOARD 0x0424
3162 +
3163 +#define BCM94306PC_BOARD 0x0425 /* pcmcia 3.3v 4306 card */
3164 +
3165 +
3166 +#define BCM94702MN_BOARD 0x0428
3167 +
3168 +/* BCM4702 1U CompactPCI Board */
3169 +#define BCM94702CPCI_BOARD 0x0429
3170 +
3171 +/* BCM4702 with BCM95380 VLAN Router */
3172 +#define BCM95380RR_BOARD 0x042a
3173 +
3174 +/* cb4306 with SiGe PA */
3175 +#define BCM94306CBSG_BOARD 0x042b
3176 +
3177 +/* cb4306 with SiGe PA */
3178 +#define PCSG94306_BOARD 0x042d
3179 +
3180 +/* bu4704 with sdram */
3181 +#define BU4704SD_BOARD 0x042e
3182 +
3183 +/* Dual 11a/11g Router */
3184 +#define BCM94704AGR_BOARD 0x042f
3185 +
3186 +/* 11a-only minipci */
3187 +#define BCM94308MP_BOARD 0x0430
3188 +
3189 +
3190 +
3191 +#define BU4712_BOARD 0x0444
3192 +#define BU4712SD_BOARD 0x045d
3193 +#define BU4712L_BOARD 0x045f
3194 +
3195 +/* BCM4712 boards */
3196 +#define BCM94712AP_BOARD 0x0445
3197 +#define BCM94712P_BOARD 0x0446
3198 +
3199 +/* BCM4318 boards */
3200 +#define BU4318_BOARD 0x0447
3201 +#define CB4318_BOARD 0x0448
3202 +#define MPG4318_BOARD 0x0449
3203 +#define MP4318_BOARD 0x044a
3204 +#define SD4318_BOARD 0x044b
3205 +
3206 +/* BCM63XX boards */
3207 +#define BCM96338_BOARD 0x6338
3208 +#define BCM96348_BOARD 0x6348
3209 +
3210 +/* Another mp4306 with SiGe */
3211 +#define BCM94306P_BOARD 0x044c
3212 +
3213 +/* mp4303 */
3214 +#define BCM94303MP_BOARD 0x044e
3215 +
3216 +/* mpsgh4306 */
3217 +#define BCM94306MPSGH_BOARD 0x044f
3218 +
3219 +/* BRCM 4306 w/ Front End Modules */
3220 +#define BCM94306MPM 0x0450
3221 +#define BCM94306MPL 0x0453
3222 +
3223 +/* 4712agr */
3224 +#define BCM94712AGR_BOARD 0x0451
3225 +
3226 +/* pcmcia 4303 */
3227 +#define PC4303_BOARD 0x0454
3228 +
3229 +/* 5350K */
3230 +#define BCM95350K_BOARD 0x0455
3231 +
3232 +/* 5350R */
3233 +#define BCM95350R_BOARD 0x0456
3234 +
3235 +/* 4306mplna */
3236 +#define BCM94306MPLNA_BOARD 0x0457
3237 +
3238 +/* 4320 boards */
3239 +#define BU4320_BOARD 0x0458
3240 +#define BU4320S_BOARD 0x0459
3241 +#define BCM94320PH_BOARD 0x045a
3242 +
3243 +/* 4306mph */
3244 +#define BCM94306MPH_BOARD 0x045b
3245 +
3246 +/* 4306pciv */
3247 +#define BCM94306PCIV_BOARD 0x045c
3248 +
3249 +#define BU4712SD_BOARD 0x045d
3250 +
3251 +#define BCM94320PFLSH_BOARD 0x045e
3252 +
3253 +#define BU4712L_BOARD 0x045f
3254 +#define BCM94712LGR_BOARD 0x0460
3255 +#define BCM94320R_BOARD 0x0461
3256 +
3257 +#define BU5352_BOARD 0x0462
3258 +
3259 +#define BCM94318MPGH_BOARD 0x0463
3260 +
3261 +#define BU4311_BOARD 0x0464
3262 +#define BCM94311MC_BOARD 0x0465
3263 +#define BCM94311MCAG_BOARD 0x0466
3264 +
3265 +#define BCM95352GR_BOARD 0x0467
3266 +
3267 +/* bcm95351agr */
3268 +#define BCM95351AGR_BOARD 0x0470
3269 +
3270 +/* bcm94704mpcb */
3271 +#define BCM94704MPCB_BOARD 0x0472
3272 +
3273 +/* 4785 boards */
3274 +#define BU4785_BOARD 0x0478
3275 +
3276 +/* 4321 boards */
3277 +#define BU4321_BOARD 0x046b
3278 +#define BU4321E_BOARD 0x047c
3279 +#define MP4321_BOARD 0x046c
3280 +#define CB2_4321_BOARD 0x046d
3281 +#define MC4321_BOARD 0x046e
3282 +
3283 +/* # of GPIO pins */
3284 +#define GPIO_NUMPINS 16
3285 +
3286 +/* radio ID codes */
3287 +#define NORADIO_ID 0xe4f5
3288 +#define NORADIO_IDCODE 0x4e4f5246
3289 +
3290 +#define BCM2050_ID 0x2050
3291 +#define BCM2050_IDCODE 0x02050000
3292 +#define BCM2050A0_IDCODE 0x1205017f
3293 +#define BCM2050A1_IDCODE 0x2205017f
3294 +#define BCM2050R8_IDCODE 0x8205017f
3295 +
3296 +#define BCM2055_ID 0x2055
3297 +#define BCM2055_IDCODE 0x02055000
3298 +#define BCM2055A0_IDCODE 0x1205517f
3299 +
3300 +#define BCM2060_ID 0x2060
3301 +#define BCM2060_IDCODE 0x02060000
3302 +#define BCM2060WW_IDCODE 0x1206017f
3303 +
3304 +#define BCM2062_ID 0x2062
3305 +#define BCM2062_IDCODE 0x02062000
3306 +#define BCM2062A0_IDCODE 0x0206217f
3307 +
3308 +/* parts of an idcode: */
3309 +#define IDCODE_MFG_MASK 0x00000fff
3310 +#define IDCODE_MFG_SHIFT 0
3311 +#define IDCODE_ID_MASK 0x0ffff000
3312 +#define IDCODE_ID_SHIFT 12
3313 +#define IDCODE_REV_MASK 0xf0000000
3314 +#define IDCODE_REV_SHIFT 28
3315 +
3316 +#endif /* _BCMDEVS_H */
3317 diff -urN linux.old/arch/mips/bcm947xx/include/bcmendian.h linux.dev/arch/mips/bcm947xx/include/bcmendian.h
3318 --- linux.old/arch/mips/bcm947xx/include/bcmendian.h 1970-01-01 01:00:00.000000000 +0100
3319 +++ linux.dev/arch/mips/bcm947xx/include/bcmendian.h 2006-10-02 21:19:59.000000000 +0200
3320 @@ -0,0 +1,198 @@
3321 +/*
3322 + * local version of endian.h - byte order defines
3323 + *
3324 + * Copyright 2006, Broadcom Corporation
3325 + * All Rights Reserved.
3326 + *
3327 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
3328 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
3329 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
3330 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
3331 + *
3332 + * $Id: bcmendian.h,v 1.1.1.10 2006/02/27 03:43:16 honor Exp $
3333 +*/
3334 +
3335 +#ifndef _BCMENDIAN_H_
3336 +#define _BCMENDIAN_H_
3337 +
3338 +#include <typedefs.h>
3339 +
3340 +/* Byte swap a 16 bit value */
3341 +#define BCMSWAP16(val) \
3342 + ((uint16)(\
3343 + (((uint16)(val) & (uint16)0x00ffU) << 8) | \
3344 + (((uint16)(val) & (uint16)0xff00U) >> 8)))
3345 +
3346 +/* Byte swap a 32 bit value */
3347 +#define BCMSWAP32(val) \
3348 + ((uint32)(\
3349 + (((uint32)(val) & (uint32)0x000000ffUL) << 24) | \
3350 + (((uint32)(val) & (uint32)0x0000ff00UL) << 8) | \
3351 + (((uint32)(val) & (uint32)0x00ff0000UL) >> 8) | \
3352 + (((uint32)(val) & (uint32)0xff000000UL) >> 24)))
3353 +
3354 +/* 2 Byte swap a 32 bit value */
3355 +#define BCMSWAP32BY16(val) \
3356 + ((uint32)(\
3357 + (((uint32)(val) & (uint32)0x0000ffffUL) << 16) | \
3358 + (((uint32)(val) & (uint32)0xffff0000UL) >> 16)))
3359 +
3360 +
3361 +static INLINE uint16
3362 +bcmswap16(uint16 val)
3363 +{
3364 + return BCMSWAP16(val);
3365 +}
3366 +
3367 +static INLINE uint32
3368 +bcmswap32(uint32 val)
3369 +{
3370 + return BCMSWAP32(val);
3371 +}
3372 +
3373 +static INLINE uint32
3374 +bcmswap32by16(uint32 val)
3375 +{
3376 + return BCMSWAP32BY16(val);
3377 +}
3378 +
3379 +/* buf - start of buffer of shorts to swap */
3380 +/* len - byte length of buffer */
3381 +static INLINE void
3382 +bcmswap16_buf(uint16 *buf, uint len)
3383 +{
3384 + len = len/2;
3385 +
3386 + while (len--) {
3387 + *buf = bcmswap16(*buf);
3388 + buf++;
3389 + }
3390 +}
3391 +
3392 +#ifndef hton16
3393 +#ifndef IL_BIGENDIAN
3394 +#define HTON16(i) BCMSWAP16(i)
3395 +#define hton16(i) bcmswap16(i)
3396 +#define hton32(i) bcmswap32(i)
3397 +#define ntoh16(i) bcmswap16(i)
3398 +#define ntoh32(i) bcmswap32(i)
3399 +#define ltoh16(i) (i)
3400 +#define ltoh32(i) (i)
3401 +#define htol16(i) (i)
3402 +#define htol32(i) (i)
3403 +#else
3404 +#define HTON16(i) (i)
3405 +#define hton16(i) (i)
3406 +#define hton32(i) (i)
3407 +#define ntoh16(i) (i)
3408 +#define ntoh32(i) (i)
3409 +#define ltoh16(i) bcmswap16(i)
3410 +#define ltoh32(i) bcmswap32(i)
3411 +#define htol16(i) bcmswap16(i)
3412 +#define htol32(i) bcmswap32(i)
3413 +#endif /* IL_BIGENDIAN */
3414 +#endif /* hton16 */
3415 +
3416 +#ifndef IL_BIGENDIAN
3417 +#define ltoh16_buf(buf, i)
3418 +#define htol16_buf(buf, i)
3419 +#else
3420 +#define ltoh16_buf(buf, i) bcmswap16_buf((uint16*)buf, i)
3421 +#define htol16_buf(buf, i) bcmswap16_buf((uint16*)buf, i)
3422 +#endif /* IL_BIGENDIAN */
3423 +
3424 +/*
3425 +* store 16-bit value to unaligned little endian byte array.
3426 +*/
3427 +static INLINE void
3428 +htol16_ua_store(uint16 val, uint8 *bytes)
3429 +{
3430 + bytes[0] = val&0xff;
3431 + bytes[1] = val>>8;
3432 +}
3433 +
3434 +/*
3435 +* store 32-bit value to unaligned little endian byte array.
3436 +*/
3437 +static INLINE void
3438 +htol32_ua_store(uint32 val, uint8 *bytes)
3439 +{
3440 + bytes[0] = val&0xff;
3441 + bytes[1] = (val>>8)&0xff;
3442 + bytes[2] = (val>>16)&0xff;
3443 + bytes[3] = val>>24;
3444 +}
3445 +
3446 +/*
3447 +* store 16-bit value to unaligned network(big) endian byte array.
3448 +*/
3449 +static INLINE void
3450 +hton16_ua_store(uint16 val, uint8 *bytes)
3451 +{
3452 + bytes[1] = val&0xff;
3453 + bytes[0] = val>>8;
3454 +}
3455 +
3456 +/*
3457 +* store 32-bit value to unaligned network(big) endian byte array.
3458 +*/
3459 +static INLINE void
3460 +hton32_ua_store(uint32 val, uint8 *bytes)
3461 +{
3462 + bytes[3] = val&0xff;
3463 + bytes[2] = (val>>8)&0xff;
3464 + bytes[1] = (val>>16)&0xff;
3465 + bytes[0] = val>>24;
3466 +}
3467 +
3468 +/*
3469 +* load 16-bit value from unaligned little endian byte array.
3470 +*/
3471 +static INLINE uint16
3472 +ltoh16_ua(void *bytes)
3473 +{
3474 + return (((uint8*)bytes)[1]<<8)+((uint8 *)bytes)[0];
3475 +}
3476 +
3477 +/*
3478 +* load 32-bit value from unaligned little endian byte array.
3479 +*/
3480 +static INLINE uint32
3481 +ltoh32_ua(void *bytes)
3482 +{
3483 + return (((uint8*)bytes)[3]<<24)+(((uint8*)bytes)[2]<<16)+
3484 + (((uint8*)bytes)[1]<<8)+((uint8*)bytes)[0];
3485 +}
3486 +
3487 +/*
3488 +* load 16-bit value from unaligned big(network) endian byte array.
3489 +*/
3490 +static INLINE uint16
3491 +ntoh16_ua(void *bytes)
3492 +{
3493 + return (((uint8*)bytes)[0]<<8)+((uint8*)bytes)[1];
3494 +}
3495 +
3496 +/*
3497 +* load 32-bit value from unaligned big(network) endian byte array.
3498 +*/
3499 +static INLINE uint32
3500 +ntoh32_ua(void *bytes)
3501 +{
3502 + return (((uint8*)bytes)[0]<<24)+(((uint8*)bytes)[1]<<16)+
3503 + (((uint8*)bytes)[2]<<8)+((uint8*)bytes)[3];
3504 +}
3505 +
3506 +#define ltoh_ua(ptr) (\
3507 + sizeof(*(ptr)) == sizeof(uint8) ? *(uint8 *)ptr : \
3508 + sizeof(*(ptr)) == sizeof(uint16) ? (((uint8 *)ptr)[1]<<8)+((uint8 *)ptr)[0] : \
3509 + (((uint8 *)ptr)[3]<<24)+(((uint8 *)ptr)[2]<<16)+(((uint8 *)ptr)[1]<<8)+((uint8 *)ptr)[0] \
3510 +)
3511 +
3512 +#define ntoh_ua(ptr) (\
3513 + sizeof(*(ptr)) == sizeof(uint8) ? *(uint8 *)ptr : \
3514 + sizeof(*(ptr)) == sizeof(uint16) ? (((uint8 *)ptr)[0]<<8)+((uint8 *)ptr)[1] : \
3515 + (((uint8 *)ptr)[0]<<24)+(((uint8 *)ptr)[1]<<16)+(((uint8 *)ptr)[2]<<8)+((uint8 *)ptr)[3] \
3516 +)
3517 +
3518 +#endif /* _BCMENDIAN_H_ */
3519 diff -urN linux.old/arch/mips/bcm947xx/include/bcmnvram.h linux.dev/arch/mips/bcm947xx/include/bcmnvram.h
3520 --- linux.old/arch/mips/bcm947xx/include/bcmnvram.h 1970-01-01 01:00:00.000000000 +0100
3521 +++ linux.dev/arch/mips/bcm947xx/include/bcmnvram.h 2006-10-02 21:19:59.000000000 +0200
3522 @@ -0,0 +1,159 @@
3523 +/*
3524 + * NVRAM variable manipulation
3525 + *
3526 + * Copyright 2006, Broadcom Corporation
3527 + * All Rights Reserved.
3528 + *
3529 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
3530 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
3531 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
3532 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
3533 + *
3534 + * $Id: bcmnvram.h,v 1.17 2006/03/02 12:33:44 honor Exp $
3535 + */
3536 +
3537 +#ifndef _bcmnvram_h_
3538 +#define _bcmnvram_h_
3539 +
3540 +#ifndef _LANGUAGE_ASSEMBLY
3541 +
3542 +#include <typedefs.h>
3543 +#include <bcmdefs.h>
3544 +
3545 +struct nvram_header {
3546 + uint32 magic;
3547 + uint32 len;
3548 + uint32 crc_ver_init; /* 0:7 crc, 8:15 ver, 16:31 sdram_init */
3549 + uint32 config_refresh; /* 0:15 sdram_config, 16:31 sdram_refresh */
3550 + uint32 config_ncdl; /* ncdl values for memc */
3551 +};
3552 +
3553 +struct nvram_tuple {
3554 + char *name;
3555 + char *value;
3556 + struct nvram_tuple *next;
3557 +};
3558 +
3559 +/*
3560 + * Initialize NVRAM access. May be unnecessary or undefined on certain
3561 + * platforms.
3562 + */
3563 +extern int nvram_init(void *sbh);
3564 +
3565 +/*
3566 + * Disable NVRAM access. May be unnecessary or undefined on certain
3567 + * platforms.
3568 + */
3569 +extern void nvram_exit(void *sbh);
3570 +
3571 +/*
3572 + * Get the value of an NVRAM variable. The pointer returned may be
3573 + * invalid after a set.
3574 + * @param name name of variable to get
3575 + * @return value of variable or NULL if undefined
3576 + */
3577 +extern char * nvram_get(const char *name);
3578 +
3579 +/*
3580 + * Read the reset GPIO value from the nvram and set the GPIO
3581 + * as input
3582 + */
3583 +extern int BCMINITFN(nvram_resetgpio_init)(void *sbh);
3584 +extern int BCMINITFN(nvram_gpio_init)(const char *name, void *sbh);
3585 +extern int BCMINITFN(nvram_gpio_set)(const char *name, void *sbh, int type);
3586 +
3587 +/*
3588 + * Get the value of an NVRAM variable.
3589 + * @param name name of variable to get
3590 + * @return value of variable or NUL if undefined
3591 + */
3592 +#define nvram_safe_get(name) (nvram_get(name) ? : "")
3593 +
3594 +#define nvram_safe_unset(name) ({ \
3595 + if(nvram_get(name)) \
3596 + nvram_unset(name); \
3597 +})
3598 +
3599 +#define nvram_safe_set(name, value) ({ \
3600 + if(!nvram_get(name) || strcmp(nvram_get(name), value)) \
3601 + nvram_set(name, value); \
3602 +})
3603 +
3604 +/*
3605 + * Match an NVRAM variable.
3606 + * @param name name of variable to match
3607 + * @param match value to compare against value of variable
3608 + * @return TRUE if variable is defined and its value is string equal
3609 + * to match or FALSE otherwise
3610 + */
3611 +static INLINE int
3612 +nvram_match(char *name, char *match) {
3613 + const char *value = nvram_get(name);
3614 + return (value && !strcmp(value, match));
3615 +}
3616 +
3617 +/*
3618 + * Inversely match an NVRAM variable.
3619 + * @param name name of variable to match
3620 + * @param match value to compare against value of variable
3621 + * @return TRUE if variable is defined and its value is not string
3622 + * equal to invmatch or FALSE otherwise
3623 + */
3624 +static INLINE int
3625 +nvram_invmatch(char *name, char *invmatch) {
3626 + const char *value = nvram_get(name);
3627 + return (value && strcmp(value, invmatch));
3628 +}
3629 +
3630 +/*
3631 + * Set the value of an NVRAM variable. The name and value strings are
3632 + * copied into private storage. Pointers to previously set values
3633 + * may become invalid. The new value may be immediately
3634 + * retrieved but will not be permanently stored until a commit.
3635 + * @param name name of variable to set
3636 + * @param value value of variable
3637 + * @return 0 on success and errno on failure
3638 + */
3639 +extern int nvram_set(const char *name, const char *value);
3640 +
3641 +/*
3642 + * Unset an NVRAM variable. Pointers to previously set values
3643 + * remain valid until a set.
3644 + * @param name name of variable to unset
3645 + * @return 0 on success and errno on failure
3646 + * NOTE: use nvram_commit to commit this change to flash.
3647 + */
3648 +extern int nvram_unset(const char *name);
3649 +
3650 +/*
3651 + * Commit NVRAM variables to permanent storage. All pointers to values
3652 + * may be invalid after a commit.
3653 + * NVRAM values are undefined after a commit.
3654 + * @return 0 on success and errno on failure
3655 + */
3656 +extern int nvram_commit(void);
3657 +
3658 +/*
3659 + * Get all NVRAM variables (format name=value\0 ... \0\0).
3660 + * @param buf buffer to store variables
3661 + * @param count size of buffer in bytes
3662 + * @return 0 on success and errno on failure
3663 + */
3664 +extern int nvram_getall(char *buf, int count);
3665 +
3666 +extern int file2nvram(char *filename, char *varname);
3667 +extern int nvram2file(char *varname, char *filename);
3668 +
3669 +#endif /* _LANGUAGE_ASSEMBLY */
3670 +
3671 +#define NVRAM_MAGIC 0x48534C46 /* 'FLSH' */
3672 +#define NVRAM_CLEAR_MAGIC 0x0
3673 +#define NVRAM_INVALID_MAGIC 0xFFFFFFFF
3674 +#define NVRAM_VERSION 1
3675 +#define NVRAM_HEADER_SIZE 20
3676 +#define NVRAM_SPACE 0x8000
3677 +
3678 +#define NVRAM_MAX_VALUE_LEN 255
3679 +#define NVRAM_MAX_PARAM_LEN 64
3680 +
3681 +#endif /* _bcmnvram_h_ */
3682 diff -urN linux.old/arch/mips/bcm947xx/include/bcmsrom.h linux.dev/arch/mips/bcm947xx/include/bcmsrom.h
3683 --- linux.old/arch/mips/bcm947xx/include/bcmsrom.h 1970-01-01 01:00:00.000000000 +0100
3684 +++ linux.dev/arch/mips/bcm947xx/include/bcmsrom.h 2006-10-02 21:19:59.000000000 +0200
3685 @@ -0,0 +1,108 @@
3686 +/*
3687 + * Misc useful routines to access NIC local SROM/OTP .
3688 + *
3689 + * Copyright 2006, Broadcom Corporation
3690 + * All Rights Reserved.
3691 + *
3692 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
3693 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
3694 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
3695 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
3696 + *
3697 + * $Id: bcmsrom.h,v 1.1.1.13 2006/04/15 01:29:08 michael Exp $
3698 + */
3699 +
3700 +#ifndef _bcmsrom_h_
3701 +#define _bcmsrom_h_
3702 +
3703 +/* Maximum srom: 4 Kilobits == 512 bytes */
3704 +#define SROM_MAX 512
3705 +
3706 +/* SROM Rev 4: Reallocate the software part of the srom to accomodate
3707 + * MIMO features. It assumes up to two PCIE functions and 440 bytes
3708 + * of useable srom i.e. the useable storage in chips with OTP that
3709 + * implements hardware redundancy.
3710 + */
3711 +
3712 +#define SROM4_WORDS 220
3713 +
3714 +#define SROM4_SIGN 32
3715 +#define SROM4_SIGNATURE 0x5372
3716 +
3717 +#define SROM4_BREV 33
3718 +
3719 +#define SROM4_BFL0 34
3720 +#define SROM4_BFL1 35
3721 +#define SROM4_BFL2 36
3722 +#define SROM4_BFL3 37
3723 +
3724 +#define SROM4_MACHI 38
3725 +#define SROM4_MACMID 39
3726 +#define SROM4_MACLO 40
3727 +
3728 +#define SROM4_CCODE 41
3729 +#define SROM4_REGREV 42
3730 +
3731 +#define SROM4_LEDBH10 43
3732 +#define SROM4_LEDBH32 44
3733 +
3734 +#define SROM4_LEDDC 45
3735 +
3736 +#define SROM4_AA 46
3737 +#define SROM4_AA2G_MASK 0x00ff
3738 +#define SROM4_AA2G_SHIFT 0
3739 +#define SROM4_AA5G_MASK 0xff00
3740 +#define SROM4_AA5G_SHIFT 8
3741 +
3742 +#define SROM4_AG10 47
3743 +#define SROM4_AG32 48
3744 +
3745 +#define SROM4_TXPID2G 49
3746 +#define SROM4_TXPID5G 51
3747 +#define SROM4_TXPID5GL 53
3748 +#define SROM4_TXPID5GH 55
3749 +
3750 +/* Per-path fields */
3751 +#define MAX_PATH 4
3752 +#define SROM4_PATH0 64
3753 +#define SROM4_PATH1 87
3754 +#define SROM4_PATH2 110
3755 +#define SROM4_PATH3 133
3756 +
3757 +#define SROM4_2G_ITT_MAXP 0
3758 +#define SROM4_2G_PA 1
3759 +#define SROM4_5G_ITT_MAXP 5
3760 +#define SROM4_5GLH_MAXP 6
3761 +#define SROM4_5G_PA 7
3762 +#define SROM4_5GL_PA 11
3763 +#define SROM4_5GH_PA 15
3764 +
3765 +/* Fields in the ITT_MAXP and 5GLH_MAXP words */
3766 +#define B2G_MAXP_MASK 0xff
3767 +#define B2G_ITT_SHIFT 8
3768 +#define B5G_MAXP_MASK 0xff
3769 +#define B5G_ITT_SHIFT 8
3770 +#define B5GH_MAXP_MASK 0xff
3771 +#define B5GL_MAXP_SHIFT 8
3772 +
3773 +/* All the miriad power offsets */
3774 +#define SROM4_2G_CCKPO 156
3775 +#define SROM4_2G_OFDMPO 157
3776 +#define SROM4_5G_OFDMPO 159
3777 +#define SROM4_5GL_OFDMPO 161
3778 +#define SROM4_5GH_OFDMPO 163
3779 +#define SROM4_2G_MCSPO 165
3780 +#define SROM4_5G_MCSPO 173
3781 +#define SROM4_5GL_MCSPO 181
3782 +#define SROM4_5GH_MCSPO 189
3783 +#define SROM4_CCDPO 197
3784 +#define SROM4_STBCPO 198
3785 +#define SROM4_BW40PO 199
3786 +#define SROM4_BWDUPPO 200
3787 +
3788 +extern int srom_var_init(void *sbh, uint bus, void *curmap, osl_t *osh, char **vars, uint *count);
3789 +
3790 +extern int srom_read(uint bus, void *curmap, osl_t *osh, uint byteoff, uint nbytes, uint16 *buf);
3791 +extern int srom_write(uint bus, void *curmap, osl_t *osh, uint byteoff, uint nbytes, uint16 *buf);
3792 +
3793 +#endif /* _bcmsrom_h_ */
3794 diff -urN linux.old/arch/mips/bcm947xx/include/bcmutils.h linux.dev/arch/mips/bcm947xx/include/bcmutils.h
3795 --- linux.old/arch/mips/bcm947xx/include/bcmutils.h 1970-01-01 01:00:00.000000000 +0100
3796 +++ linux.dev/arch/mips/bcm947xx/include/bcmutils.h 2006-10-02 21:19:59.000000000 +0200
3797 @@ -0,0 +1,433 @@
3798 +/*
3799 + * Misc useful os-independent macros and functions.
3800 + *
3801 + * Copyright 2006, Broadcom Corporation
3802 + * All Rights Reserved.
3803 + *
3804 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
3805 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
3806 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
3807 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
3808 + * $Id: bcmutils.h,v 1.1.1.16 2006/04/08 06:13:39 honor Exp $
3809 + */
3810 +
3811 +#ifndef _bcmutils_h_
3812 +#define _bcmutils_h_
3813 +
3814 +/* ** driver-only section ** */
3815 +#ifdef BCMDRIVER
3816 +
3817 +#define _BCM_U 0x01 /* upper */
3818 +#define _BCM_L 0x02 /* lower */
3819 +#define _BCM_D 0x04 /* digit */
3820 +#define _BCM_C 0x08 /* cntrl */
3821 +#define _BCM_P 0x10 /* punct */
3822 +#define _BCM_S 0x20 /* white space (space/lf/tab) */
3823 +#define _BCM_X 0x40 /* hex digit */
3824 +#define _BCM_SP 0x80 /* hard space (0x20) */
3825 +
3826 +#define GPIO_PIN_NOTDEFINED 0x20 /* Pin not defined */
3827 +
3828 +extern unsigned char bcm_ctype[];
3829 +#define bcm_ismask(x) (bcm_ctype[(int)(unsigned char)(x)])
3830 +
3831 +#define bcm_isalnum(c) ((bcm_ismask(c)&(_BCM_U|_BCM_L|_BCM_D)) != 0)
3832 +#define bcm_isalpha(c) ((bcm_ismask(c)&(_BCM_U|_BCM_L)) != 0)
3833 +#define bcm_iscntrl(c) ((bcm_ismask(c)&(_BCM_C)) != 0)
3834 +#define bcm_isdigit(c) ((bcm_ismask(c)&(_BCM_D)) != 0)
3835 +#define bcm_isgraph(c) ((bcm_ismask(c)&(_BCM_P|_BCM_U|_BCM_L|_BCM_D)) != 0)
3836 +#define bcm_islower(c) ((bcm_ismask(c)&(_BCM_L)) != 0)
3837 +#define bcm_isprint(c) ((bcm_ismask(c)&(_BCM_P|_BCM_U|_BCM_L|_BCM_D|_BCM_SP)) != 0)
3838 +#define bcm_ispunct(c) ((bcm_ismask(c)&(_BCM_P)) != 0)
3839 +#define bcm_isspace(c) ((bcm_ismask(c)&(_BCM_S)) != 0)
3840 +#define bcm_isupper(c) ((bcm_ismask(c)&(_BCM_U)) != 0)
3841 +#define bcm_isxdigit(c) ((bcm_ismask(c)&(_BCM_D|_BCM_X)) != 0)
3842 +
3843 +/*
3844 + * Spin at most 'us' microseconds while 'exp' is true.
3845 + * Caller should explicitly test 'exp' when this completes
3846 + * and take appropriate error action if 'exp' is still true.
3847 + */
3848 +#define SPINWAIT(exp, us) { \
3849 + uint countdown = (us) + 9; \
3850 + while ((exp) && (countdown >= 10)) {\
3851 + OSL_DELAY(10); \
3852 + countdown -= 10; \
3853 + } \
3854 +}
3855 +
3856 +struct ether_addr {
3857 + uint8 octet[6];
3858 +} __attribute__((packed));
3859 +
3860 +/* string */
3861 +extern uchar bcm_toupper(uchar c);
3862 +extern ulong bcm_strtoul(char *cp, char **endp, uint base);
3863 +extern char *bcmstrstr(char *haystack, char *needle);
3864 +extern char *bcmstrcat(char *dest, const char *src);
3865 +extern ulong wchar2ascii(char *abuf, ushort *wbuf, ushort wbuflen, ulong abuflen);
3866 +/* ethernet address */
3867 +extern char *bcm_ether_ntoa(struct ether_addr *ea, char *buf);
3868 +/* variable access */
3869 +extern char *getvar(char *vars, char *name);
3870 +extern int getintvar(char *vars, char *name);
3871 +extern uint getgpiopin(char *vars, char *pin_name, uint def_pin);
3872 +#ifdef BCMPERFSTATS
3873 +extern void bcm_perf_enable(void);
3874 +extern void bcmstats(char *fmt);
3875 +extern void bcmlog(char *fmt, uint a1, uint a2);
3876 +extern void bcmdumplog(char *buf, int size);
3877 +extern int bcmdumplogent(char *buf, uint idx);
3878 +#else
3879 +#define bcm_perf_enable()
3880 +#define bcmstats(fmt)
3881 +#define bcmlog(fmt, a1, a2)
3882 +#define bcmdumplog(buf, size) *buf = '\0'
3883 +#define bcmdumplogent(buf, idx) -1
3884 +#endif /* BCMPERFSTATS */
3885 +extern char *bcm_nvram_vars(uint *length);
3886 +extern int bcm_nvram_cache(void *sbh);
3887 +
3888 +/* Support for sharing code across in-driver iovar implementations.
3889 + * The intent is that a driver use this structure to map iovar names
3890 + * to its (private) iovar identifiers, and the lookup function to
3891 + * find the entry. Macros are provided to map ids and get/set actions
3892 + * into a single number space for a switch statement.
3893 + */
3894 +
3895 +/* iovar structure */
3896 +typedef struct bcm_iovar {
3897 + const char *name; /* name for lookup and display */
3898 + uint16 varid; /* id for switch */
3899 + uint16 flags; /* driver-specific flag bits */
3900 + uint16 type; /* base type of argument */
3901 + uint16 minlen; /* min length for buffer vars */
3902 +} bcm_iovar_t;
3903 +
3904 +/* varid definitions are per-driver, may use these get/set bits */
3905 +
3906 +/* IOVar action bits for id mapping */
3907 +#define IOV_GET 0 /* Get an iovar */
3908 +#define IOV_SET 1 /* Set an iovar */
3909 +
3910 +/* Varid to actionid mapping */
3911 +#define IOV_GVAL(id) ((id)*2)
3912 +#define IOV_SVAL(id) (((id)*2)+IOV_SET)
3913 +#define IOV_ISSET(actionid) ((actionid & IOV_SET) == IOV_SET)
3914 +
3915 +/* flags are per-driver based on driver attributes */
3916 +
3917 +/* Base type definitions */
3918 +#define IOVT_VOID 0 /* no value (implictly set only) */
3919 +#define IOVT_BOOL 1 /* any value ok (zero/nonzero) */
3920 +#define IOVT_INT8 2 /* integer values are range-checked */
3921 +#define IOVT_UINT8 3 /* unsigned int 8 bits */
3922 +#define IOVT_INT16 4 /* int 16 bits */
3923 +#define IOVT_UINT16 5 /* unsigned int 16 bits */
3924 +#define IOVT_INT32 6 /* int 32 bits */
3925 +#define IOVT_UINT32 7 /* unsigned int 32 bits */
3926 +#define IOVT_BUFFER 8 /* buffer is size-checked as per minlen */
3927 +
3928 +extern const bcm_iovar_t *bcm_iovar_lookup(const bcm_iovar_t *table, const char *name);
3929 +extern int bcm_iovar_lencheck(const bcm_iovar_t *table, void *arg, int len, bool set);
3930 +
3931 +#endif /* #ifdef BCMDRIVER */
3932 +
3933 +/* ** driver/apps-shared section ** */
3934 +
3935 +#define BCME_STRLEN 64 /* Max string length for BCM errors */
3936 +#define VALID_BCMERROR(e) ((e <= 0) && (e >= BCME_LAST))
3937 +
3938 +
3939 +/*
3940 + * error codes could be added but the defined ones shouldn't be changed/deleted
3941 + * these error codes are exposed to the user code
3942 + * when ever a new error code is added to this list
3943 + * please update errorstring table with the related error string and
3944 + * update osl files with os specific errorcode map
3945 +*/
3946 +
3947 +#define BCME_OK 0 /* Success */
3948 +#define BCME_ERROR -1 /* Error generic */
3949 +#define BCME_BADARG -2 /* Bad Argument */
3950 +#define BCME_BADOPTION -3 /* Bad option */
3951 +#define BCME_NOTUP -4 /* Not up */
3952 +#define BCME_NOTDOWN -5 /* Not down */
3953 +#define BCME_NOTAP -6 /* Not AP */
3954 +#define BCME_NOTSTA -7 /* Not STA */
3955 +#define BCME_BADKEYIDX -8 /* BAD Key Index */
3956 +#define BCME_RADIOOFF -9 /* Radio Off */
3957 +#define BCME_NOTBANDLOCKED -10 /* Not band locked */
3958 +#define BCME_NOCLK -11 /* No Clock */
3959 +#define BCME_BADRATESET -12 /* BAD Rate valueset */
3960 +#define BCME_BADBAND -13 /* BAD Band */
3961 +#define BCME_BUFTOOSHORT -14 /* Buffer too short */
3962 +#define BCME_BUFTOOLONG -15 /* Buffer too long */
3963 +#define BCME_BUSY -16 /* Busy */
3964 +#define BCME_NOTASSOCIATED -17 /* Not Associated */
3965 +#define BCME_BADSSIDLEN -18 /* Bad SSID len */
3966 +#define BCME_OUTOFRANGECHAN -19 /* Out of Range Channel */
3967 +#define BCME_BADCHAN -20 /* Bad Channel */
3968 +#define BCME_BADADDR -21 /* Bad Address */
3969 +#define BCME_NORESOURCE -22 /* Not Enough Resources */
3970 +#define BCME_UNSUPPORTED -23 /* Unsupported */
3971 +#define BCME_BADLEN -24 /* Bad length */
3972 +#define BCME_NOTREADY -25 /* Not Ready */
3973 +#define BCME_EPERM -26 /* Not Permitted */
3974 +#define BCME_NOMEM -27 /* No Memory */
3975 +#define BCME_ASSOCIATED -28 /* Associated */
3976 +#define BCME_RANGE -29 /* Not In Range */
3977 +#define BCME_NOTFOUND -30 /* Not Found */
3978 +#define BCME_WME_NOT_ENABLED -31 /* WME Not Enabled */
3979 +#define BCME_TSPEC_NOTFOUND -32 /* TSPEC Not Found */
3980 +#define BCME_ACM_NOTSUPPORTED -33 /* ACM Not Supported */
3981 +#define BCME_NOT_WME_ASSOCIATION -34 /* Not WME Association */
3982 +#define BCME_SDIO_ERROR -35 /* SDIO Bus Error */
3983 +#define BCME_DONGLE_DOWN -36 /* Dongle Not Accessible */
3984 +#define BCME_LAST BCME_DONGLE_DOWN
3985 +
3986 +/* These are collection of BCME Error strings */
3987 +#define BCMERRSTRINGTABLE { \
3988 + "OK", \
3989 + "Undefined error", \
3990 + "Bad Argument", \
3991 + "Bad Option", \
3992 + "Not up", \
3993 + "Not down", \
3994 + "Not AP", \
3995 + "Not STA", \
3996 + "Bad Key Index", \
3997 + "Radio Off", \
3998 + "Not band locked", \
3999 + "No clock", \
4000 + "Bad Rate valueset", \
4001 + "Bad Band", \
4002 + "Buffer too short", \
4003 + "Buffer too long", \
4004 + "Busy", \
4005 + "Not Associated", \
4006 + "Bad SSID len", \
4007 + "Out of Range Channel", \
4008 + "Bad Channel", \
4009 + "Bad Address", \
4010 + "Not Enough Resources", \
4011 + "Unsupported", \
4012 + "Bad length", \
4013 + "Not Ready", \
4014 + "Not Permitted", \
4015 + "No Memory", \
4016 + "Associated", \
4017 + "Not In Range", \
4018 + "Not Found", \
4019 + "WME Not Enabled", \
4020 + "TSPEC Not Found", \
4021 + "ACM Not Supported", \
4022 + "Not WME Association", \
4023 + "SDIO Bus Error", \
4024 + "Dongle Not Accessible" \
4025 +}
4026 +
4027 +#ifndef ABS
4028 +#define ABS(a) (((a) < 0)?-(a):(a))
4029 +#endif /* ABS */
4030 +
4031 +#ifndef MIN
4032 +#define MIN(a, b) (((a) < (b))?(a):(b))
4033 +#endif /* MIN */
4034 +
4035 +#ifndef MAX
4036 +#define MAX(a, b) (((a) > (b))?(a):(b))
4037 +#endif /* MAX */
4038 +
4039 +#define CEIL(x, y) (((x) + ((y)-1)) / (y))
4040 +#define ROUNDUP(x, y) ((((x)+((y)-1))/(y))*(y))
4041 +#define ISALIGNED(a, x) (((a) & ((x)-1)) == 0)
4042 +#define ISPOWEROF2(x) ((((x)-1)&(x)) == 0)
4043 +#define VALID_MASK(mask) !((mask) & ((mask) + 1))
4044 +#define OFFSETOF(type, member) ((uint)(uintptr)&((type *)0)->member)
4045 +#define ARRAYSIZE(a) (sizeof(a)/sizeof(a[0]))
4046 +
4047 +/* bit map related macros */
4048 +#ifndef setbit
4049 +#ifndef NBBY /* the BSD family defines NBBY */
4050 +#define NBBY 8 /* 8 bits per byte */
4051 +#endif /* #ifndef NBBY */
4052 +#define setbit(a, i) (((uint8 *)a)[(i)/NBBY] |= 1<<((i)%NBBY))
4053 +#define clrbit(a, i) (((uint8 *)a)[(i)/NBBY] &= ~(1<<((i)%NBBY)))
4054 +#define isset(a, i) (((uint8 *)a)[(i)/NBBY] & (1<<((i)%NBBY)))
4055 +#define isclr(a, i) ((((uint8 *)a)[(i)/NBBY] & (1<<((i)%NBBY))) == 0)
4056 +#endif /* setbit */
4057 +
4058 +#define NBITS(type) (sizeof(type) * 8)
4059 +#define NBITVAL(nbits) (1 << (nbits))
4060 +#define MAXBITVAL(nbits) ((1 << (nbits)) - 1)
4061 +#define NBITMASK(nbits) MAXBITVAL(nbits)
4062 +#define MAXNBVAL(nbyte) MAXBITVAL((nbyte) * 8)
4063 +
4064 +/* basic mux operation - can be optimized on several architectures */
4065 +#define MUX(pred, true, false) ((pred) ? (true) : (false))
4066 +
4067 +/* modulo inc/dec - assumes x E [0, bound - 1] */
4068 +#define MODDEC(x, bound) MUX((x) == 0, (bound) - 1, (x) - 1)
4069 +#define MODINC(x, bound) MUX((x) == (bound) - 1, 0, (x) + 1)
4070 +
4071 +/* modulo inc/dec, bound = 2^k */
4072 +#define MODDEC_POW2(x, bound) (((x) - 1) & ((bound) - 1))
4073 +#define MODINC_POW2(x, bound) (((x) + 1) & ((bound) - 1))
4074 +
4075 +/* modulo add/sub - assumes x, y E [0, bound - 1] */
4076 +#define MODADD(x, y, bound) \
4077 + MUX((x) + (y) >= (bound), (x) + (y) - (bound), (x) + (y))
4078 +#define MODSUB(x, y, bound) \
4079 + MUX(((int)(x)) - ((int)(y)) < 0, (x) - (y) + (bound), (x) - (y))
4080 +
4081 +/* module add/sub, bound = 2^k */
4082 +#define MODADD_POW2(x, y, bound) (((x) + (y)) & ((bound) - 1))
4083 +#define MODSUB_POW2(x, y, bound) (((x) - (y)) & ((bound) - 1))
4084 +
4085 +/* crc defines */
4086 +#define CRC8_INIT_VALUE 0xff /* Initial CRC8 checksum value */
4087 +#define CRC8_GOOD_VALUE 0x9f /* Good final CRC8 checksum value */
4088 +#define CRC16_INIT_VALUE 0xffff /* Initial CRC16 checksum value */
4089 +#define CRC16_GOOD_VALUE 0xf0b8 /* Good final CRC16 checksum value */
4090 +#define CRC32_INIT_VALUE 0xffffffff /* Initial CRC32 checksum value */
4091 +#define CRC32_GOOD_VALUE 0xdebb20e3 /* Good final CRC32 checksum value */
4092 +
4093 +/* bcm_format_flags() bit description structure */
4094 +typedef struct bcm_bit_desc {
4095 + uint32 bit;
4096 + char* name;
4097 +} bcm_bit_desc_t;
4098 +
4099 +/* tag_ID/length/value_buffer tuple */
4100 +typedef struct bcm_tlv {
4101 + uint8 id;
4102 + uint8 len;
4103 + uint8 data[1];
4104 +} bcm_tlv_t;
4105 +
4106 +/* Check that bcm_tlv_t fits into the given buflen */
4107 +#define bcm_valid_tlv(elt, buflen) ((buflen) >= 2 && (int)(buflen) >= (int)(2 + (elt)->len))
4108 +
4109 +/* buffer length for ethernet address from bcm_ether_ntoa() */
4110 +#define ETHER_ADDR_STR_LEN 18 /* 18-bytes of Ethernet address buffer length */
4111 +
4112 +/* unaligned load and store macros */
4113 +#ifdef IL_BIGENDIAN
4114 +static INLINE uint32
4115 +load32_ua(uint8 *a)
4116 +{
4117 + return ((a[0] << 24) | (a[1] << 16) | (a[2] << 8) | a[3]);
4118 +}
4119 +
4120 +static INLINE void
4121 +store32_ua(uint8 *a, uint32 v)
4122 +{
4123 + a[0] = (v >> 24) & 0xff;
4124 + a[1] = (v >> 16) & 0xff;
4125 + a[2] = (v >> 8) & 0xff;
4126 + a[3] = v & 0xff;
4127 +}
4128 +
4129 +static INLINE uint16
4130 +load16_ua(uint8 *a)
4131 +{
4132 + return ((a[0] << 8) | a[1]);
4133 +}
4134 +
4135 +static INLINE void
4136 +store16_ua(uint8 *a, uint16 v)
4137 +{
4138 + a[0] = (v >> 8) & 0xff;
4139 + a[1] = v & 0xff;
4140 +}
4141 +
4142 +#else
4143 +
4144 +static INLINE uint32
4145 +load32_ua(uint8 *a)
4146 +{
4147 + return ((a[3] << 24) | (a[2] << 16) | (a[1] << 8) | a[0]);
4148 +}
4149 +
4150 +static INLINE void
4151 +store32_ua(uint8 *a, uint32 v)
4152 +{
4153 + a[3] = (v >> 24) & 0xff;
4154 + a[2] = (v >> 16) & 0xff;
4155 + a[1] = (v >> 8) & 0xff;
4156 + a[0] = v & 0xff;
4157 +}
4158 +
4159 +static INLINE uint16
4160 +load16_ua(uint8 *a)
4161 +{
4162 + return ((a[1] << 8) | a[0]);
4163 +}
4164 +
4165 +static INLINE void
4166 +store16_ua(uint8 *a, uint16 v)
4167 +{
4168 + a[1] = (v >> 8) & 0xff;
4169 + a[0] = v & 0xff;
4170 +}
4171 +
4172 +#endif /* IL_BIGENDIAN */
4173 +
4174 +/* externs */
4175 +/* crc */
4176 +extern uint8 hndcrc8(uint8 *p, uint nbytes, uint8 crc);
4177 +extern uint16 hndcrc16(uint8 *p, uint nbytes, uint16 crc);
4178 +extern uint32 hndcrc32(uint8 *p, uint nbytes, uint32 crc);
4179 +/* format/print */
4180 +extern void printfbig(char *buf);
4181 +
4182 +/* IE parsing */
4183 +extern bcm_tlv_t *bcm_next_tlv(bcm_tlv_t *elt, int *buflen);
4184 +extern bcm_tlv_t *bcm_parse_tlvs(void *buf, int buflen, uint key);
4185 +extern bcm_tlv_t *bcm_parse_ordered_tlvs(void *buf, int buflen, uint key);
4186 +
4187 +/* bcmerror */
4188 +extern const char *bcmerrorstr(int bcmerror);
4189 +
4190 +/* multi-bool data type: set of bools, mbool is true if any is set */
4191 +typedef uint32 mbool;
4192 +#define mboolset(mb, bit) (mb |= bit) /* set one bool */
4193 +#define mboolclr(mb, bit) (mb &= ~bit) /* clear one bool */
4194 +#define mboolisset(mb, bit) ((mb & bit) != 0) /* TRUE if one bool is set */
4195 +#define mboolmaskset(mb, mask, val) ((mb) = (((mb) & ~(mask)) | (val)))
4196 +
4197 +/* power conversion */
4198 +extern uint16 bcm_qdbm_to_mw(uint8 qdbm);
4199 +extern uint8 bcm_mw_to_qdbm(uint16 mw);
4200 +
4201 +/* generic datastruct to help dump routines */
4202 +struct fielddesc {
4203 + char *nameandfmt;
4204 + uint32 offset;
4205 + uint32 len;
4206 +};
4207 +
4208 +/* Buffer structure for collecting string-formatted data
4209 +* using bcm_bprintf() API.
4210 +* Use bcm_binit() to initialize before use
4211 +*/
4212 +struct bcmstrbuf
4213 +{
4214 + char *buf; /* pointer to current position in origbuf */
4215 + uint size; /* current (residual) size in bytes */
4216 + char *origbuf; /* unmodified pointer to orignal buffer */
4217 + uint origsize; /* unmodified orignal buffer size in bytes */
4218 +};
4219 +
4220 +extern void bcm_binit(struct bcmstrbuf *b, char *buf, uint size);
4221 +extern int bcm_bprintf(struct bcmstrbuf *b, const char *fmt, ...);
4222 +
4223 +typedef uint32 (*readreg_rtn)(void *arg0, void *arg1, uint32 offset);
4224 +extern uint bcmdumpfields(readreg_rtn func_ptr, void *arg0, void *arg1, struct fielddesc *str,
4225 + char *buf, uint32 bufsize);
4226 +
4227 +extern uint bcm_mkiovar(char *name, char *data, uint datalen, char *buf, uint len);
4228 +extern uint bcm_bitcount(uint8 *bitmap, uint bytelength);
4229 +
4230 +#endif /* _bcmutils_h_ */
4231 diff -urN linux.old/arch/mips/bcm947xx/include/hndcpu.h linux.dev/arch/mips/bcm947xx/include/hndcpu.h
4232 --- linux.old/arch/mips/bcm947xx/include/hndcpu.h 1970-01-01 01:00:00.000000000 +0100
4233 +++ linux.dev/arch/mips/bcm947xx/include/hndcpu.h 2006-10-02 21:19:59.000000000 +0200
4234 @@ -0,0 +1,28 @@
4235 +/*
4236 + * HND SiliconBackplane MIPS/ARM cores software interface.
4237 + *
4238 + * Copyright 2006, Broadcom Corporation
4239 + * All Rights Reserved.
4240 + *
4241 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
4242 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
4243 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
4244 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
4245 + *
4246 + * $Id: hndcpu.h,v 1.1.1.1 2006/02/27 03:43:16 honor Exp $
4247 + */
4248 +
4249 +#ifndef _hndcpu_h_
4250 +#define _hndcpu_h_
4251 +
4252 +#if defined(mips)
4253 +#include <hndmips.h>
4254 +#elif defined(__ARM_ARCH_4T__)
4255 +#include <hndarm.h>
4256 +#endif
4257 +
4258 +extern uint sb_irq(sb_t *sbh);
4259 +extern uint32 sb_cpu_clock(sb_t *sbh);
4260 +extern void sb_cpu_wait(void);
4261 +
4262 +#endif /* _hndcpu_h_ */
4263 diff -urN linux.old/arch/mips/bcm947xx/include/hndmips.h linux.dev/arch/mips/bcm947xx/include/hndmips.h
4264 --- linux.old/arch/mips/bcm947xx/include/hndmips.h 1970-01-01 01:00:00.000000000 +0100
4265 +++ linux.dev/arch/mips/bcm947xx/include/hndmips.h 2006-10-02 21:19:59.000000000 +0200
4266 @@ -0,0 +1,45 @@
4267 +/*
4268 + * HND SiliconBackplane MIPS core software interface.
4269 + *
4270 + * Copyright 2006, Broadcom Corporation
4271 + * All Rights Reserved.
4272 + *
4273 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
4274 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
4275 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
4276 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
4277 + *
4278 + * $Id: hndmips.h,v 1.1.1.8 2006/02/27 03:43:16 honor Exp $
4279 + */
4280 +
4281 +#ifndef _hndmips_h_
4282 +#define _hndmips_h_
4283 +
4284 +extern void sb_mips_init(sb_t *sbh, uint shirq_map_base);
4285 +extern bool sb_mips_setclock(sb_t *sbh, uint32 mipsclock, uint32 sbclock, uint32 pciclock);
4286 +extern void enable_pfc(uint32 mode);
4287 +extern uint32 sb_memc_get_ncdl(sb_t *sbh);
4288 +
4289 +#if defined(BCMPERFSTATS)
4290 +/* enable counting - exclusive version. Only one set of counters allowed at a time */
4291 +extern void hndmips_perf_instrcount_enable(void);
4292 +extern void hndmips_perf_icachecount_enable(void);
4293 +extern void hndmips_perf_dcachecount_enable(void);
4294 +/* start and stop counting */
4295 +#define hndmips_perf_start01() \
4296 + MTC0(C0_PERFORMANCE, 4, MFC0(C0_PERFORMANCE, 4) | 0x80008000)
4297 +#define hndmips_perf_stop01() \
4298 + MTC0(C0_PERFORMANCE, 4, MFC0(C0_PERFORMANCE, 4) & ~0x80008000)
4299 +/* retrieve coutners - counters *decrement* */
4300 +#define hndmips_perf_read0() -(long)(MFC0(C0_PERFORMANCE, 0))
4301 +#define hndmips_perf_read1() -(long)(MFC0(C0_PERFORMANCE, 1))
4302 +#define hndmips_perf_read2() -(long)(MFC0(C0_PERFORMANCE, 2))
4303 +/* enable counting - modular version. Each counters can be enabled separately. */
4304 +extern void hndmips_perf_icache_hit_enable(void);
4305 +extern void hndmips_perf_icache_miss_enable(void);
4306 +extern uint32 hndmips_perf_read_instrcount(void);
4307 +extern uint32 hndmips_perf_read_cache_miss(void);
4308 +extern uint32 hndmips_perf_read_cache_hit(void);
4309 +#endif /* defined(BCMINTERNAL) || defined (BCMPERFSTATS) */
4310 +
4311 +#endif /* _hndmips_h_ */
4312 diff -urN linux.old/arch/mips/bcm947xx/include/hndpci.h linux.dev/arch/mips/bcm947xx/include/hndpci.h
4313 --- linux.old/arch/mips/bcm947xx/include/hndpci.h 1970-01-01 01:00:00.000000000 +0100
4314 +++ linux.dev/arch/mips/bcm947xx/include/hndpci.h 2006-10-02 21:19:59.000000000 +0200
4315 @@ -0,0 +1,30 @@
4316 +/*
4317 + * HND SiliconBackplane PCI core software interface.
4318 + *
4319 + * $Id: hndpci.h,v 1.1.1.1 2006/02/27 03:43:16 honor Exp $
4320 + * Copyright 2006, Broadcom Corporation
4321 + * All Rights Reserved.
4322 + *
4323 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
4324 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
4325 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
4326 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
4327 + */
4328 +
4329 +#ifndef _hndpci_h_
4330 +#define _hndpci_h_
4331 +
4332 +extern int sbpci_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf,
4333 + int len);
4334 +extern int extpci_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf,
4335 + int len);
4336 +extern int sbpci_write_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf,
4337 + int len);
4338 +extern int extpci_write_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf,
4339 + int len);
4340 +extern void sbpci_ban(uint16 core);
4341 +extern int sbpci_init(sb_t *sbh);
4342 +extern int sbpci_init_pci(sb_t *sbh);
4343 +extern void sbpci_check(sb_t *sbh);
4344 +
4345 +#endif /* _hndpci_h_ */
4346 diff -urN linux.old/arch/mips/bcm947xx/include/linuxver.h linux.dev/arch/mips/bcm947xx/include/linuxver.h
4347 --- linux.old/arch/mips/bcm947xx/include/linuxver.h 1970-01-01 01:00:00.000000000 +0100
4348 +++ linux.dev/arch/mips/bcm947xx/include/linuxver.h 2006-10-02 21:19:59.000000000 +0200
4349 @@ -0,0 +1,417 @@
4350 +/*
4351 + * Linux-specific abstractions to gain some independence from linux kernel versions.
4352 + * Pave over some 2.2 versus 2.4 versus 2.6 kernel differences.
4353 + *
4354 + * Copyright 2006, Broadcom Corporation
4355 + * All Rights Reserved.
4356 + *
4357 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
4358 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
4359 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
4360 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
4361 + *
4362 + * $Id: linuxver.h,v 1.1.1.10 2006/02/27 03:43:16 honor Exp $
4363 + */
4364 +
4365 +#ifndef _linuxver_h_
4366 +#define _linuxver_h_
4367 +
4368 +#include <linux/config.h>
4369 +#include <linux/version.h>
4370 +
4371 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 0))
4372 +/* __NO_VERSION__ must be defined for all linkables except one in 2.2 */
4373 +#ifdef __UNDEF_NO_VERSION__
4374 +#undef __NO_VERSION__
4375 +#else
4376 +#define __NO_VERSION__
4377 +#endif
4378 +#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 0) */
4379 +
4380 +#if defined(MODULE) && defined(MODVERSIONS)
4381 +#include <linux/modversions.h>
4382 +#endif
4383 +
4384 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 5, 0)
4385 +#include <linux/moduleparam.h>
4386 +#endif
4387 +
4388 +
4389 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 5, 0)
4390 +#define module_param(_name_, _type_, _perm_) MODULE_PARM(_name_, "i")
4391 +#define module_param_string(_name_, _string_, _size_, _perm_) \
4392 + MODULE_PARM(_string_, "c" __MODULE_STRING(_size_))
4393 +#endif
4394 +
4395 +/* linux/malloc.h is deprecated, use linux/slab.h instead. */
4396 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 4, 9))
4397 +#include <linux/malloc.h>
4398 +#else
4399 +#include <linux/slab.h>
4400 +#endif
4401 +
4402 +#include <linux/types.h>
4403 +#include <linux/init.h>
4404 +#include <linux/mm.h>
4405 +#include <linux/string.h>
4406 +#include <linux/pci.h>
4407 +#include <linux/interrupt.h>
4408 +#include <linux/netdevice.h>
4409 +#include <asm/io.h>
4410 +
4411 +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 41))
4412 +#include <linux/workqueue.h>
4413 +#else
4414 +#include <linux/tqueue.h>
4415 +#ifndef work_struct
4416 +#define work_struct tq_struct
4417 +#endif
4418 +#ifndef INIT_WORK
4419 +#define INIT_WORK(_work, _func, _data) INIT_TQUEUE((_work), (_func), (_data))
4420 +#endif
4421 +#ifndef schedule_work
4422 +#define schedule_work(_work) schedule_task((_work))
4423 +#endif
4424 +#ifndef flush_scheduled_work
4425 +#define flush_scheduled_work() flush_scheduled_tasks()
4426 +#endif
4427 +#endif /* LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 41) */
4428 +
4429 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 0))
4430 +/* Some distributions have their own 2.6.x compatibility layers */
4431 +#ifndef IRQ_NONE
4432 +typedef void irqreturn_t;
4433 +#define IRQ_NONE
4434 +#define IRQ_HANDLED
4435 +#define IRQ_RETVAL(x)
4436 +#endif
4437 +#else
4438 +typedef irqreturn_t(*FN_ISR) (int irq, void *dev_id, struct pt_regs *ptregs);
4439 +#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 0) */
4440 +
4441 +#if defined(CONFIG_PCMCIA) || defined(CONFIG_PCMCIA_MODULE)
4442 +
4443 +#include <pcmcia/version.h>
4444 +#include <pcmcia/cs_types.h>
4445 +#include <pcmcia/cs.h>
4446 +#include <pcmcia/cistpl.h>
4447 +#include <pcmcia/cisreg.h>
4448 +#include <pcmcia/ds.h>
4449 +
4450 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 5, 69))
4451 +/* In 2.5 (as of 2.5.69 at least) there is a cs_error exported which
4452 + * does this, but it's not in 2.4 so we do our own for now.
4453 + */
4454 +static inline void
4455 +cs_error(client_handle_t handle, int func, int ret)
4456 +{
4457 + error_info_t err = { func, ret };
4458 + CardServices(ReportError, handle, &err);
4459 +}
4460 +#endif
4461 +
4462 +#endif /* CONFIG_PCMCIA */
4463 +
4464 +#ifndef __exit
4465 +#define __exit
4466 +#endif
4467 +#ifndef __devexit
4468 +#define __devexit
4469 +#endif
4470 +#ifndef __devinit
4471 +#define __devinit __init
4472 +#endif
4473 +#ifndef __devinitdata
4474 +#define __devinitdata
4475 +#endif
4476 +#ifndef __devexit_p
4477 +#define __devexit_p(x) x
4478 +#endif
4479 +
4480 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 4, 0))
4481 +
4482 +#define pci_get_drvdata(dev) (dev)->sysdata
4483 +#define pci_set_drvdata(dev, value) (dev)->sysdata = (value)
4484 +
4485 +/*
4486 + * New-style (2.4.x) PCI/hot-pluggable PCI/CardBus registration
4487 + */
4488 +
4489 +struct pci_device_id {
4490 + unsigned int vendor, device; /* Vendor and device ID or PCI_ANY_ID */
4491 + unsigned int subvendor, subdevice; /* Subsystem ID's or PCI_ANY_ID */
4492 + unsigned int class, class_mask; /* (class,subclass,prog-if) triplet */
4493 + unsigned long driver_data; /* Data private to the driver */
4494 +};
4495 +
4496 +struct pci_driver {
4497 + struct list_head node;
4498 + char *name;
4499 + const struct pci_device_id *id_table; /* NULL if wants all devices */
4500 + int (*probe)(struct pci_dev *dev,
4501 + const struct pci_device_id *id); /* New device inserted */
4502 + void (*remove)(struct pci_dev *dev); /* Device removed (NULL if not a hot-plug
4503 + * capable driver)
4504 + */
4505 + void (*suspend)(struct pci_dev *dev); /* Device suspended */
4506 + void (*resume)(struct pci_dev *dev); /* Device woken up */
4507 +};
4508 +
4509 +#define MODULE_DEVICE_TABLE(type, name)
4510 +#define PCI_ANY_ID (~0)
4511 +
4512 +/* compatpci.c */
4513 +#define pci_module_init pci_register_driver
4514 +extern int pci_register_driver(struct pci_driver *drv);
4515 +extern void pci_unregister_driver(struct pci_driver *drv);
4516 +
4517 +#endif /* PCI registration */
4518 +
4519 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 2, 18))
4520 +#ifdef MODULE
4521 +#define module_init(x) int init_module(void) { return x(); }
4522 +#define module_exit(x) void cleanup_module(void) { x(); }
4523 +#else
4524 +#define module_init(x) __initcall(x);
4525 +#define module_exit(x) __exitcall(x);
4526 +#endif
4527 +#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(2, 2, 18) */
4528 +
4529 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 48))
4530 +#define list_for_each(pos, head) \
4531 + for (pos = (head)->next; pos != (head); pos = pos->next)
4532 +#endif
4533 +
4534 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 13))
4535 +#define pci_resource_start(dev, bar) ((dev)->base_address[(bar)])
4536 +#elif (LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 44))
4537 +#define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
4538 +#endif
4539 +
4540 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 23))
4541 +#define pci_enable_device(dev) do { } while (0)
4542 +#endif
4543 +
4544 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 14))
4545 +#define net_device device
4546 +#endif
4547 +
4548 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 42))
4549 +
4550 +/*
4551 + * DMA mapping
4552 + *
4553 + * See linux/Documentation/DMA-mapping.txt
4554 + */
4555 +
4556 +#ifndef PCI_DMA_TODEVICE
4557 +#define PCI_DMA_TODEVICE 1
4558 +#define PCI_DMA_FROMDEVICE 2
4559 +#endif
4560 +
4561 +typedef u32 dma_addr_t;
4562 +
4563 +/* Pure 2^n version of get_order */
4564 +static inline int get_order(unsigned long size)
4565 +{
4566 + int order;
4567 +
4568 + size = (size-1) >> (PAGE_SHIFT-1);
4569 + order = -1;
4570 + do {
4571 + size >>= 1;
4572 + order++;
4573 + } while (size);
4574 + return order;
4575 +}
4576 +
4577 +static inline void *pci_alloc_consistent(struct pci_dev *hwdev, size_t size,
4578 + dma_addr_t *dma_handle)
4579 +{
4580 + void *ret;
4581 + int gfp = GFP_ATOMIC | GFP_DMA;
4582 +
4583 + ret = (void *)__get_free_pages(gfp, get_order(size));
4584 +
4585 + if (ret != NULL) {
4586 + memset(ret, 0, size);
4587 + *dma_handle = virt_to_bus(ret);
4588 + }
4589 + return ret;
4590 +}
4591 +static inline void pci_free_consistent(struct pci_dev *hwdev, size_t size,
4592 + void *vaddr, dma_addr_t dma_handle)
4593 +{
4594 + free_pages((unsigned long)vaddr, get_order(size));
4595 +}
4596 +#ifdef ILSIM
4597 +extern uint pci_map_single(void *dev, void *va, uint size, int direction);
4598 +extern void pci_unmap_single(void *dev, uint pa, uint size, int direction);
4599 +#else
4600 +#define pci_map_single(cookie, address, size, dir) virt_to_bus(address)
4601 +#define pci_unmap_single(cookie, address, size, dir)
4602 +#endif
4603 +
4604 +#endif /* DMA mapping */
4605 +
4606 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 43))
4607 +
4608 +#define dev_kfree_skb_any(a) dev_kfree_skb(a)
4609 +#define netif_down(dev) do { (dev)->start = 0; } while (0)
4610 +
4611 +/* pcmcia-cs provides its own netdevice compatibility layer */
4612 +#ifndef _COMPAT_NETDEVICE_H
4613 +
4614 +/*
4615 + * SoftNet
4616 + *
4617 + * For pre-softnet kernels we need to tell the upper layer not to
4618 + * re-enter start_xmit() while we are in there. However softnet
4619 + * guarantees not to enter while we are in there so there is no need
4620 + * to do the netif_stop_queue() dance unless the transmit queue really
4621 + * gets stuck. This should also improve performance according to tests
4622 + * done by Aman Singla.
4623 + */
4624 +
4625 +#define dev_kfree_skb_irq(a) dev_kfree_skb(a)
4626 +#define netif_wake_queue(dev) \
4627 + do { clear_bit(0, &(dev)->tbusy); mark_bh(NET_BH); } while (0)
4628 +#define netif_stop_queue(dev) set_bit(0, &(dev)->tbusy)
4629 +
4630 +static inline void netif_start_queue(struct net_device *dev)
4631 +{
4632 + dev->tbusy = 0;
4633 + dev->interrupt = 0;
4634 + dev->start = 1;
4635 +}
4636 +
4637 +#define netif_queue_stopped(dev) (dev)->tbusy
4638 +#define netif_running(dev) (dev)->start
4639 +
4640 +#endif /* _COMPAT_NETDEVICE_H */
4641 +
4642 +#define netif_device_attach(dev) netif_start_queue(dev)
4643 +#define netif_device_detach(dev) netif_stop_queue(dev)
4644 +
4645 +/* 2.4.x renamed bottom halves to tasklets */
4646 +#define tasklet_struct tq_struct
4647 +static inline void tasklet_schedule(struct tasklet_struct *tasklet)
4648 +{
4649 + queue_task(tasklet, &tq_immediate);
4650 + mark_bh(IMMEDIATE_BH);
4651 +}
4652 +
4653 +static inline void tasklet_init(struct tasklet_struct *tasklet,
4654 + void (*func)(unsigned long),
4655 + unsigned long data)
4656 +{
4657 + tasklet->next = NULL;
4658 + tasklet->sync = 0;
4659 + tasklet->routine = (void (*)(void *))func;
4660 + tasklet->data = (void *)data;
4661 +}
4662 +#define tasklet_kill(tasklet) { do{} while (0); }
4663 +
4664 +/* 2.4.x introduced del_timer_sync() */
4665 +#define del_timer_sync(timer) del_timer(timer)
4666 +
4667 +#else
4668 +
4669 +#define netif_down(dev)
4670 +
4671 +#endif /* SoftNet */
4672 +
4673 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 4, 3))
4674 +
4675 +/*
4676 + * Emit code to initialise a tq_struct's routine and data pointers
4677 + */
4678 +#define PREPARE_TQUEUE(_tq, _routine, _data) \
4679 + do { \
4680 + (_tq)->routine = _routine; \
4681 + (_tq)->data = _data; \
4682 + } while (0)
4683 +
4684 +/*
4685 + * Emit code to initialise all of a tq_struct
4686 + */
4687 +#define INIT_TQUEUE(_tq, _routine, _data) \
4688 + do { \
4689 + INIT_LIST_HEAD(&(_tq)->list); \
4690 + (_tq)->sync = 0; \
4691 + PREPARE_TQUEUE((_tq), (_routine), (_data)); \
4692 + } while (0)
4693 +
4694 +#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(2, 4, 3) */
4695 +
4696 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 4, 6))
4697 +
4698 +/* Power management related routines */
4699 +
4700 +static inline int
4701 +pci_save_state(struct pci_dev *dev, u32 *buffer)
4702 +{
4703 + int i;
4704 + if (buffer) {
4705 + for (i = 0; i < 16; i++)
4706 + pci_read_config_dword(dev, i * 4, &buffer[i]);
4707 + }
4708 + return 0;
4709 +}
4710 +
4711 +static inline int
4712 +pci_restore_state(struct pci_dev *dev, u32 *buffer)
4713 +{
4714 + int i;
4715 +
4716 + if (buffer) {
4717 + for (i = 0; i < 16; i++)
4718 + pci_write_config_dword(dev, i * 4, buffer[i]);
4719 + }
4720 + /*
4721 + * otherwise, write the context information we know from bootup.
4722 + * This works around a problem where warm-booting from Windows
4723 + * combined with a D3(hot)->D0 transition causes PCI config
4724 + * header data to be forgotten.
4725 + */
4726 + else {
4727 + for (i = 0; i < 6; i ++)
4728 + pci_write_config_dword(dev,
4729 + PCI_BASE_ADDRESS_0 + (i * 4),
4730 + pci_resource_start(dev, i));
4731 + pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
4732 + }
4733 + return 0;
4734 +}
4735 +
4736 +#endif /* PCI power management */
4737 +
4738 +/* Old cp0 access macros deprecated in 2.4.19 */
4739 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 4, 19))
4740 +#define read_c0_count() read_32bit_cp0_register(CP0_COUNT)
4741 +#endif
4742 +
4743 +/* Module refcount handled internally in 2.6.x */
4744 +#ifndef SET_MODULE_OWNER
4745 +#define SET_MODULE_OWNER(dev) do {} while (0)
4746 +#define OLD_MOD_INC_USE_COUNT MOD_INC_USE_COUNT
4747 +#define OLD_MOD_DEC_USE_COUNT MOD_DEC_USE_COUNT
4748 +#else
4749 +#define OLD_MOD_INC_USE_COUNT do {} while (0)
4750 +#define OLD_MOD_DEC_USE_COUNT do {} while (0)
4751 +#endif
4752 +
4753 +#ifndef SET_NETDEV_DEV
4754 +#define SET_NETDEV_DEV(net, pdev) do {} while (0)
4755 +#endif
4756 +
4757 +#ifndef HAVE_FREE_NETDEV
4758 +#define free_netdev(dev) kfree(dev)
4759 +#endif
4760 +
4761 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 0))
4762 +/* struct packet_type redefined in 2.6.x */
4763 +#define af_packet_priv data
4764 +#endif
4765 +
4766 +#endif /* _linuxver_h_ */
4767 diff -urN linux.old/arch/mips/bcm947xx/include/mipsinc.h linux.dev/arch/mips/bcm947xx/include/mipsinc.h
4768 --- linux.old/arch/mips/bcm947xx/include/mipsinc.h 1970-01-01 01:00:00.000000000 +0100
4769 +++ linux.dev/arch/mips/bcm947xx/include/mipsinc.h 2006-10-02 21:19:59.000000000 +0200
4770 @@ -0,0 +1,541 @@
4771 +/*
4772 + * HND Run Time Environment for standalone MIPS programs.
4773 + *
4774 + * Copyright 2006, Broadcom Corporation
4775 + * All Rights Reserved.
4776 + *
4777 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
4778 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
4779 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
4780 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
4781 + *
4782 + * $Id: mipsinc.h,v 1.1.1.5 2006/02/27 03:43:16 honor Exp $
4783 + */
4784 +
4785 +#ifndef _MISPINC_H
4786 +#define _MISPINC_H
4787 +
4788 +
4789 +/* MIPS defines */
4790 +
4791 +#ifdef _LANGUAGE_ASSEMBLY
4792 +
4793 +/*
4794 + * Symbolic register names for 32 bit ABI
4795 + */
4796 +#define zero $0 /* wired zero */
4797 +#define AT $1 /* assembler temp - uppercase because of ".set at" */
4798 +#define v0 $2 /* return value */
4799 +#define v1 $3
4800 +#define a0 $4 /* argument registers */
4801 +#define a1 $5
4802 +#define a2 $6
4803 +#define a3 $7
4804 +#define t0 $8 /* caller saved */
4805 +#define t1 $9
4806 +#define t2 $10
4807 +#define t3 $11
4808 +#define t4 $12
4809 +#define t5 $13
4810 +#define t6 $14
4811 +#define t7 $15
4812 +#define s0 $16 /* callee saved */
4813 +#define s1 $17
4814 +#define s2 $18
4815 +#define s3 $19
4816 +#define s4 $20
4817 +#define s5 $21
4818 +#define s6 $22
4819 +#define s7 $23
4820 +#define t8 $24 /* caller saved */
4821 +#define t9 $25
4822 +#define jp $25 /* PIC jump register */
4823 +#define k0 $26 /* kernel scratch */
4824 +#define k1 $27
4825 +#define gp $28 /* global pointer */
4826 +#define sp $29 /* stack pointer */
4827 +#define fp $30 /* frame pointer */
4828 +#define s8 $30 /* same like fp! */
4829 +#define ra $31 /* return address */
4830 +
4831 +
4832 +/* CP0 Registers */
4833 +
4834 +#define C0_INX $0
4835 +#define C0_RAND $1
4836 +#define C0_TLBLO0 $2
4837 +#define C0_TLBLO C0_TLBLO0
4838 +#define C0_TLBLO1 $3
4839 +#define C0_CTEXT $4
4840 +#define C0_PGMASK $5
4841 +#define C0_WIRED $6
4842 +#define C0_BADVADDR $8
4843 +#define C0_COUNT $9
4844 +#define C0_TLBHI $10
4845 +#define C0_COMPARE $11
4846 +#define C0_SR $12
4847 +#define C0_STATUS C0_SR
4848 +#define C0_CAUSE $13
4849 +#define C0_EPC $14
4850 +#define C0_PRID $15
4851 +#define C0_CONFIG $16
4852 +#define C0_LLADDR $17
4853 +#define C0_WATCHLO $18
4854 +#define C0_WATCHHI $19
4855 +#define C0_XCTEXT $20
4856 +#define C0_DIAGNOSTIC $22
4857 +#define C0_BROADCOM C0_DIAGNOSTIC
4858 +#define C0_PERFORMANCE $25
4859 +#define C0_ECC $26
4860 +#define C0_CACHEERR $27
4861 +#define C0_TAGLO $28
4862 +#define C0_TAGHI $29
4863 +#define C0_ERREPC $30
4864 +#define C0_DESAVE $31
4865 +
4866 +/*
4867 + * LEAF - declare leaf routine
4868 + */
4869 +#define LEAF(symbol) \
4870 + .globl symbol; \
4871 + .align 2; \
4872 + .type symbol, @function; \
4873 + .ent symbol, 0; \
4874 +symbol: .frame sp, 0, ra
4875 +
4876 +/*
4877 + * END - mark end of function
4878 + */
4879 +#define END(function) \
4880 + .end function; \
4881 + .size function, . - function
4882 +
4883 +#define _ULCAST_
4884 +
4885 +#define MFC0_SEL(dst, src, sel) \
4886 + .word\t(0x40000000 | ((dst) << 16) | ((src) << 11) | (sel))
4887 +
4888 +
4889 +#define MTC0_SEL(dst, src, sel) \
4890 + .word\t(0x40800000 | ((dst) << 16) | ((src) << 11) | (sel))
4891 +
4892 +#else
4893 +
4894 +/*
4895 + * The following macros are especially useful for __asm__
4896 + * inline assembler.
4897 + */
4898 +#ifndef __STR
4899 +#define __STR(x) #x
4900 +#endif
4901 +#ifndef STR
4902 +#define STR(x) __STR(x)
4903 +#endif
4904 +
4905 +#define _ULCAST_ (unsigned long)
4906 +
4907 +
4908 +/* CP0 Registers */
4909 +
4910 +#define C0_INX 0 /* CP0: TLB Index */
4911 +#define C0_RAND 1 /* CP0: TLB Random */
4912 +#define C0_TLBLO0 2 /* CP0: TLB EntryLo0 */
4913 +#define C0_TLBLO C0_TLBLO0 /* CP0: TLB EntryLo0 */
4914 +#define C0_TLBLO1 3 /* CP0: TLB EntryLo1 */
4915 +#define C0_CTEXT 4 /* CP0: Context */
4916 +#define C0_PGMASK 5 /* CP0: TLB PageMask */
4917 +#define C0_WIRED 6 /* CP0: TLB Wired */
4918 +#define C0_BADVADDR 8 /* CP0: Bad Virtual Address */
4919 +#define C0_COUNT 9 /* CP0: Count */
4920 +#define C0_TLBHI 10 /* CP0: TLB EntryHi */
4921 +#define C0_COMPARE 11 /* CP0: Compare */
4922 +#define C0_SR 12 /* CP0: Processor Status */
4923 +#define C0_STATUS C0_SR /* CP0: Processor Status */
4924 +#define C0_CAUSE 13 /* CP0: Exception Cause */
4925 +#define C0_EPC 14 /* CP0: Exception PC */
4926 +#define C0_PRID 15 /* CP0: Processor Revision Indentifier */
4927 +#define C0_CONFIG 16 /* CP0: Config */
4928 +#define C0_LLADDR 17 /* CP0: LLAddr */
4929 +#define C0_WATCHLO 18 /* CP0: WatchpointLo */
4930 +#define C0_WATCHHI 19 /* CP0: WatchpointHi */
4931 +#define C0_XCTEXT 20 /* CP0: XContext */
4932 +#define C0_DIAGNOSTIC 22 /* CP0: Diagnostic */
4933 +#define C0_BROADCOM C0_DIAGNOSTIC /* CP0: Broadcom Register */
4934 +#define C0_PERFORMANCE 25 /* CP0: Performance Counter/Control Registers */
4935 +#define C0_ECC 26 /* CP0: ECC */
4936 +#define C0_CACHEERR 27 /* CP0: CacheErr */
4937 +#define C0_TAGLO 28 /* CP0: TagLo */
4938 +#define C0_TAGHI 29 /* CP0: TagHi */
4939 +#define C0_ERREPC 30 /* CP0: ErrorEPC */
4940 +#define C0_DESAVE 31 /* CP0: DebugSave */
4941 +
4942 +#endif /* _LANGUAGE_ASSEMBLY */
4943 +
4944 +/*
4945 + * Memory segments (32bit kernel mode addresses)
4946 + */
4947 +#undef KUSEG
4948 +#undef KSEG0
4949 +#undef KSEG1
4950 +#undef KSEG2
4951 +#undef KSEG3
4952 +#define KUSEG 0x00000000
4953 +#define KSEG0 0x80000000
4954 +#define KSEG1 0xa0000000
4955 +#define KSEG2 0xc0000000
4956 +#define KSEG3 0xe0000000
4957 +#define PHYSADDR_MASK 0x1fffffff
4958 +
4959 +/*
4960 + * Map an address to a certain kernel segment
4961 + */
4962 +#undef PHYSADDR
4963 +#undef KSEG0ADDR
4964 +#undef KSEG1ADDR
4965 +#undef KSEG2ADDR
4966 +#undef KSEG3ADDR
4967 +
4968 +#define PHYSADDR(a) (_ULCAST_(a) & PHYSADDR_MASK)
4969 +#define KSEG0ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG0)
4970 +#define KSEG1ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG1)
4971 +#define KSEG2ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG2)
4972 +#define KSEG3ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG3)
4973 +
4974 +
4975 +#ifndef Index_Invalidate_I
4976 +/*
4977 + * Cache Operations
4978 + */
4979 +#define Index_Invalidate_I 0x00
4980 +#define Index_Writeback_Inv_D 0x01
4981 +#define Index_Invalidate_SI 0x02
4982 +#define Index_Writeback_Inv_SD 0x03
4983 +#define Index_Load_Tag_I 0x04
4984 +#define Index_Load_Tag_D 0x05
4985 +#define Index_Load_Tag_SI 0x06
4986 +#define Index_Load_Tag_SD 0x07
4987 +#define Index_Store_Tag_I 0x08
4988 +#define Index_Store_Tag_D 0x09
4989 +#define Index_Store_Tag_SI 0x0A
4990 +#define Index_Store_Tag_SD 0x0B
4991 +#define Create_Dirty_Excl_D 0x0d
4992 +#define Create_Dirty_Excl_SD 0x0f
4993 +#define Hit_Invalidate_I 0x10
4994 +#define Hit_Invalidate_D 0x11
4995 +#define Hit_Invalidate_SI 0x12
4996 +#define Hit_Invalidate_SD 0x13
4997 +#define Fill_I 0x14
4998 +#define Hit_Writeback_Inv_D 0x15
4999 + /* 0x16 is unused */
5000 +#define Hit_Writeback_Inv_SD 0x17
5001 +#define R5K_Page_Invalidate_S 0x17
5002 +#define Hit_Writeback_I 0x18
5003 +#define Hit_Writeback_D 0x19
5004 + /* 0x1a is unused */
5005 +#define Hit_Writeback_SD 0x1b
5006 + /* 0x1c is unused */
5007 + /* 0x1e is unused */
5008 +#define Hit_Set_Virtual_SI 0x1e
5009 +#define Hit_Set_Virtual_SD 0x1f
5010 +#endif /* !Index_Invalidate_I */
5011 +
5012 +
5013 +/*
5014 + * R4x00 interrupt enable / cause bits
5015 + */
5016 +#define IE_SW0 (_ULCAST_(1) << 8)
5017 +#define IE_SW1 (_ULCAST_(1) << 9)
5018 +#define IE_IRQ0 (_ULCAST_(1) << 10)
5019 +#define IE_IRQ1 (_ULCAST_(1) << 11)
5020 +#define IE_IRQ2 (_ULCAST_(1) << 12)
5021 +#define IE_IRQ3 (_ULCAST_(1) << 13)
5022 +#define IE_IRQ4 (_ULCAST_(1) << 14)
5023 +#define IE_IRQ5 (_ULCAST_(1) << 15)
5024 +
5025 +#ifndef ST0_UM
5026 +/*
5027 + * Bitfields in the mips32 cp0 status register
5028 + */
5029 +#define ST0_IE 0x00000001
5030 +#define ST0_EXL 0x00000002
5031 +#define ST0_ERL 0x00000004
5032 +#define ST0_UM 0x00000010
5033 +#define ST0_SWINT0 0x00000100
5034 +#define ST0_SWINT1 0x00000200
5035 +#define ST0_HWINT0 0x00000400
5036 +#define ST0_HWINT1 0x00000800
5037 +#define ST0_HWINT2 0x00001000
5038 +#define ST0_HWINT3 0x00002000
5039 +#define ST0_HWINT4 0x00004000
5040 +#define ST0_HWINT5 0x00008000
5041 +#define ST0_IM 0x0000ff00
5042 +#define ST0_NMI 0x00080000
5043 +#define ST0_SR 0x00100000
5044 +#define ST0_TS 0x00200000
5045 +#define ST0_BEV 0x00400000
5046 +#define ST0_RE 0x02000000
5047 +#define ST0_RP 0x08000000
5048 +#define ST0_CU 0xf0000000
5049 +#define ST0_CU0 0x10000000
5050 +#define ST0_CU1 0x20000000
5051 +#define ST0_CU2 0x40000000
5052 +#define ST0_CU3 0x80000000
5053 +#endif /* !ST0_UM */
5054 +
5055 +
5056 +/*
5057 + * Bitfields in the mips32 cp0 cause register
5058 + */
5059 +#define C_EXC 0x0000007c
5060 +#define C_EXC_SHIFT 2
5061 +#define C_INT 0x0000ff00
5062 +#define C_INT_SHIFT 8
5063 +#define C_SW0 (_ULCAST_(1) << 8)
5064 +#define C_SW1 (_ULCAST_(1) << 9)
5065 +#define C_IRQ0 (_ULCAST_(1) << 10)
5066 +#define C_IRQ1 (_ULCAST_(1) << 11)
5067 +#define C_IRQ2 (_ULCAST_(1) << 12)
5068 +#define C_IRQ3 (_ULCAST_(1) << 13)
5069 +#define C_IRQ4 (_ULCAST_(1) << 14)
5070 +#define C_IRQ5 (_ULCAST_(1) << 15)
5071 +#define C_WP 0x00400000
5072 +#define C_IV 0x00800000
5073 +#define C_CE 0x30000000
5074 +#define C_CE_SHIFT 28
5075 +#define C_BD 0x80000000
5076 +
5077 +/* Values in C_EXC */
5078 +#define EXC_INT 0
5079 +#define EXC_TLBM 1
5080 +#define EXC_TLBL 2
5081 +#define EXC_TLBS 3
5082 +#define EXC_AEL 4
5083 +#define EXC_AES 5
5084 +#define EXC_IBE 6
5085 +#define EXC_DBE 7
5086 +#define EXC_SYS 8
5087 +#define EXC_BPT 9
5088 +#define EXC_RI 10
5089 +#define EXC_CU 11
5090 +#define EXC_OV 12
5091 +#define EXC_TR 13
5092 +#define EXC_WATCH 23
5093 +#define EXC_MCHK 24
5094 +
5095 +
5096 +/*
5097 + * Bits in the cp0 config register.
5098 + */
5099 +#define CONF_CM_CACHABLE_NO_WA 0
5100 +#define CONF_CM_CACHABLE_WA 1
5101 +#define CONF_CM_UNCACHED 2
5102 +#define CONF_CM_CACHABLE_NONCOHERENT 3
5103 +#define CONF_CM_CACHABLE_CE 4
5104 +#define CONF_CM_CACHABLE_COW 5
5105 +#define CONF_CM_CACHABLE_CUW 6
5106 +#define CONF_CM_CACHABLE_ACCELERATED 7
5107 +#define CONF_CM_CMASK 7
5108 +#define CONF_CU (_ULCAST_(1) << 3)
5109 +#define CONF_DB (_ULCAST_(1) << 4)
5110 +#define CONF_IB (_ULCAST_(1) << 5)
5111 +#define CONF_SE (_ULCAST_(1) << 12)
5112 +#ifndef CONF_BE /* duplicate in mipsregs.h */
5113 +#define CONF_BE (_ULCAST_(1) << 15)
5114 +#endif
5115 +#define CONF_SC (_ULCAST_(1) << 17)
5116 +#define CONF_AC (_ULCAST_(1) << 23)
5117 +#define CONF_HALT (_ULCAST_(1) << 25)
5118 +#ifndef CONF_M /* duplicate in mipsregs.h */
5119 +#define CONF_M (_ULCAST_(1) << 31)
5120 +#endif
5121 +
5122 +
5123 +/*
5124 + * Bits in the cp0 config register select 1.
5125 + */
5126 +#define CONF1_FP 0x00000001 /* FPU present */
5127 +#define CONF1_EP 0x00000002 /* EJTAG present */
5128 +#define CONF1_CA 0x00000004 /* mips16 implemented */
5129 +#define CONF1_WR 0x00000008 /* Watch registers present */
5130 +#define CONF1_PC 0x00000010 /* Performance counters present */
5131 +#define CONF1_DA_SHIFT 7 /* D$ associativity */
5132 +#define CONF1_DA_MASK 0x00000380
5133 +#define CONF1_DA_BASE 1
5134 +#define CONF1_DL_SHIFT 10 /* D$ line size */
5135 +#define CONF1_DL_MASK 0x00001c00
5136 +#define CONF1_DL_BASE 2
5137 +#define CONF1_DS_SHIFT 13 /* D$ sets/way */
5138 +#define CONF1_DS_MASK 0x0000e000
5139 +#define CONF1_DS_BASE 64
5140 +#define CONF1_IA_SHIFT 16 /* I$ associativity */
5141 +#define CONF1_IA_MASK 0x00070000
5142 +#define CONF1_IA_BASE 1
5143 +#define CONF1_IL_SHIFT 19 /* I$ line size */
5144 +#define CONF1_IL_MASK 0x00380000
5145 +#define CONF1_IL_BASE 2
5146 +#define CONF1_IS_SHIFT 22 /* Instruction cache sets/way */
5147 +#define CONF1_IS_MASK 0x01c00000
5148 +#define CONF1_IS_BASE 64
5149 +#define CONF1_MS_MASK 0x7e000000 /* Number of tlb entries */
5150 +#define CONF1_MS_SHIFT 25
5151 +
5152 +/* PRID register */
5153 +#define PRID_COPT_MASK 0xff000000
5154 +#define PRID_COMP_MASK 0x00ff0000
5155 +#define PRID_IMP_MASK 0x0000ff00
5156 +#define PRID_REV_MASK 0x000000ff
5157 +
5158 +#define PRID_COMP_LEGACY 0x000000
5159 +#define PRID_COMP_MIPS 0x010000
5160 +#define PRID_COMP_BROADCOM 0x020000
5161 +#define PRID_COMP_ALCHEMY 0x030000
5162 +#define PRID_COMP_SIBYTE 0x040000
5163 +#define PRID_IMP_BCM4710 0x4000
5164 +#define PRID_IMP_BCM3302 0x9000
5165 +#define PRID_IMP_BCM3303 0x9100
5166 +
5167 +#define PRID_IMP_UNKNOWN 0xff00
5168 +
5169 +#define BCM330X(id) \
5170 + (((id & (PRID_COMP_MASK | PRID_IMP_MASK)) == \
5171 + (PRID_COMP_BROADCOM | PRID_IMP_BCM3302)) || \
5172 + ((id & (PRID_COMP_MASK | PRID_IMP_MASK)) == \
5173 + (PRID_COMP_BROADCOM | PRID_IMP_BCM3303)))
5174 +
5175 +/* Bits in C0_BROADCOM */
5176 +#define BRCM_PFC_AVAIL 0x20000000 /* PFC is available */
5177 +#define BRCM_DC_ENABLE 0x40000000 /* Enable Data $ */
5178 +#define BRCM_IC_ENABLE 0x80000000 /* Enable Instruction $ */
5179 +#define BRCM_PFC_ENABLE 0x00400000 /* Obsolete? Enable PFC (at least on 4310) */
5180 +#define BRCM_CLF_ENABLE 0x00100000 /* Enable cache line first feature */
5181 +
5182 +/* PreFetch Cache aka Read Ahead Cache */
5183 +
5184 +#define PFC_CR0 0xff400000 /* control reg 0 */
5185 +#define PFC_CR1 0xff400004 /* control reg 1 */
5186 +
5187 +/* PFC operations */
5188 +#define PFC_I 0x00000001 /* Enable PFC use for instructions */
5189 +#define PFC_D 0x00000002 /* Enable PFC use for data */
5190 +#define PFC_PFI 0x00000004 /* Enable seq. prefetch for instructions */
5191 +#define PFC_PFD 0x00000008 /* Enable seq. prefetch for data */
5192 +#define PFC_CINV 0x00000010 /* Enable selective (i/d) cacheop flushing */
5193 +#define PFC_NCH 0x00000020 /* Disable flushing based on cacheops */
5194 +#define PFC_DPF 0x00000040 /* Enable directional prefetching */
5195 +#define PFC_FLUSH 0x00000100 /* Flush the PFC */
5196 +#define PFC_BRR 0x40000000 /* Bus error indication */
5197 +#define PFC_PWR 0x80000000 /* Disable power saving (clock gating) */
5198 +
5199 +/* Handy defaults */
5200 +#define PFC_DISABLED 0
5201 +#define PFC_AUTO 0xffffffff /* auto select the default mode */
5202 +#define PFC_INST (PFC_I | PFC_PFI | PFC_CINV)
5203 +#define PFC_INST_NOPF (PFC_I | PFC_CINV)
5204 +#define PFC_DATA (PFC_D | PFC_PFD | PFC_CINV)
5205 +#define PFC_DATA_NOPF (PFC_D | PFC_CINV)
5206 +#define PFC_I_AND_D (PFC_INST | PFC_DATA)
5207 +#define PFC_I_AND_D_NOPF (PFC_INST_NOPF | PFC_DATA_NOPF)
5208 +
5209 +#ifndef _LANGUAGE_ASSEMBLY
5210 +
5211 +/*
5212 + * Macros to access the system control coprocessor
5213 + */
5214 +
5215 +#define MFC0(source, sel) \
5216 +({ \
5217 + int __res; \
5218 + __asm__ __volatile__(" \
5219 + .set\tnoreorder; \
5220 + .set\tnoat; \
5221 + .word\t"STR(0x40010000 | ((source) << 11) | (sel))"; \
5222 + move\t%0, $1; \
5223 + .set\tat; \
5224 + .set\treorder" \
5225 + :"=r" (__res) \
5226 + : \
5227 + :"$1"); \
5228 + __res; \
5229 +})
5230 +
5231 +#define MTC0(source, sel, value) \
5232 +do { \
5233 + __asm__ __volatile__(" \
5234 + .set\tnoreorder; \
5235 + .set\tnoat; \
5236 + move\t$1, %z0; \
5237 + .word\t"STR(0x40810000 | ((source) << 11) | (sel))"; \
5238 + .set\tat; \
5239 + .set\treorder" \
5240 + : \
5241 + :"jr" (value) \
5242 + :"$1"); \
5243 +} while (0)
5244 +
5245 +#define get_c0_count() \
5246 +({ \
5247 + int __res; \
5248 + __asm__ __volatile__(" \
5249 + .set\tnoreorder; \
5250 + .set\tnoat; \
5251 + mfc0\t%0, $9; \
5252 + .set\tat; \
5253 + .set\treorder" \
5254 + :"=r" (__res)); \
5255 + __res; \
5256 +})
5257 +
5258 +static INLINE void icache_probe(uint32 config1, uint *size, uint *lsize)
5259 +{
5260 + uint lsz, sets, ways;
5261 +
5262 + /* Instruction Cache Size = Associativity * Line Size * Sets Per Way */
5263 + if ((lsz = ((config1 & CONF1_IL_MASK) >> CONF1_IL_SHIFT)))
5264 + lsz = CONF1_IL_BASE << lsz;
5265 + sets = CONF1_IS_BASE << ((config1 & CONF1_IS_MASK) >> CONF1_IS_SHIFT);
5266 + ways = CONF1_IA_BASE + ((config1 & CONF1_IA_MASK) >> CONF1_IA_SHIFT);
5267 + *size = lsz * sets * ways;
5268 + *lsize = lsz;
5269 +}
5270 +
5271 +static INLINE void dcache_probe(uint32 config1, uint *size, uint *lsize)
5272 +{
5273 + uint lsz, sets, ways;
5274 +
5275 + /* Data Cache Size = Associativity * Line Size * Sets Per Way */
5276 + if ((lsz = ((config1 & CONF1_DL_MASK) >> CONF1_DL_SHIFT)))
5277 + lsz = CONF1_DL_BASE << lsz;
5278 + sets = CONF1_DS_BASE << ((config1 & CONF1_DS_MASK) >> CONF1_DS_SHIFT);
5279 + ways = CONF1_DA_BASE + ((config1 & CONF1_DA_MASK) >> CONF1_DA_SHIFT);
5280 + *size = lsz * sets * ways;
5281 + *lsize = lsz;
5282 +}
5283 +
5284 +#define cache_op(base, op) \
5285 + __asm__ __volatile__(" \
5286 + .set noreorder; \
5287 + .set mips3; \
5288 + cache %1, (%0); \
5289 + .set mips0; \
5290 + .set reorder" \
5291 + : \
5292 + : "r" (base), \
5293 + "i" (op));
5294 +
5295 +#define cache_unroll4(base, delta, op) \
5296 + __asm__ __volatile__(" \
5297 + .set noreorder; \
5298 + .set mips3; \
5299 + cache %1, 0(%0); \
5300 + cache %1, delta(%0); \
5301 + cache %1, (2 * delta)(%0); \
5302 + cache %1, (3 * delta)(%0); \
5303 + .set mips0; \
5304 + .set reorder" \
5305 + : \
5306 + : "r" (base), \
5307 + "i" (op));
5308 +
5309 +#endif /* !_LANGUAGE_ASSEMBLY */
5310 +
5311 +#endif /* _MISPINC_H */
5312 diff -urN linux.old/arch/mips/bcm947xx/include/osl.h linux.dev/arch/mips/bcm947xx/include/osl.h
5313 --- linux.old/arch/mips/bcm947xx/include/osl.h 1970-01-01 01:00:00.000000000 +0100
5314 +++ linux.dev/arch/mips/bcm947xx/include/osl.h 2006-10-02 21:19:59.000000000 +0200
5315 @@ -0,0 +1,181 @@
5316 +#ifndef __osl_h
5317 +#define __osl_h
5318 +
5319 +#include <linux/delay.h>
5320 +#include <typedefs.h>
5321 +#include <linuxver.h>
5322 +#include <bcmutils.h>
5323 +#include <pcicfg.h>
5324 +
5325 +#define ASSERT(n)
5326 +
5327 +/* Pkttag flag should be part of public information */
5328 +typedef struct {
5329 + bool pkttag;
5330 + uint pktalloced; /* Number of allocated packet buffers */
5331 + void *tx_fn;
5332 + void *tx_ctx;
5333 +} osl_pubinfo_t;
5334 +
5335 +struct osl_info {
5336 + osl_pubinfo_t pub;
5337 + uint magic;
5338 + void *pdev;
5339 + uint malloced;
5340 + uint failed;
5341 + void *dbgmem_list;
5342 +};
5343 +
5344 +typedef struct osl_info osl_t;
5345 +
5346 +#define PCI_CFG_RETRY 10
5347 +
5348 +/* map/unmap direction */
5349 +#define DMA_TX 1 /* TX direction for DMA */
5350 +#define DMA_RX 2 /* RX direction for DMA */
5351 +
5352 +#define AND_REG(osh, r, v) W_REG(osh, (r), R_REG(osh, r) & (v))
5353 +#define OR_REG(osh, r, v) W_REG(osh, (r), R_REG(osh, r) | (v))
5354 +#define SET_REG(osh, r, mask, val) W_REG((osh), (r), ((R_REG((osh), r) & ~(mask)) | (val)))
5355 +
5356 +/* bcopy, bcmp, and bzero */
5357 +#define bcopy(src, dst, len) memcpy((dst), (src), (len))
5358 +#define bcmp(b1, b2, len) memcmp((b1), (b2), (len))
5359 +#define bzero(b, len) memset((b), '\0', (len))
5360 +
5361 +/* uncached virtual address */
5362 +#ifdef mips
5363 +#define OSL_UNCACHED(va) KSEG1ADDR((va))
5364 +#include <asm/addrspace.h>
5365 +#else
5366 +#define OSL_UNCACHED(va) (va)
5367 +#endif /* mips */
5368 +
5369 +
5370 +#ifndef IL_BIGENDIAN
5371 +#define R_REG(osh, r) (\
5372 + sizeof(*(r)) == sizeof(uint8) ? readb((volatile uint8*)(r)) : \
5373 + sizeof(*(r)) == sizeof(uint16) ? readw((volatile uint16*)(r)) : \
5374 + readl((volatile uint32*)(r)) \
5375 +)
5376 +#define W_REG(osh, r, v) do { \
5377 + switch (sizeof(*(r))) { \
5378 + case sizeof(uint8): writeb((uint8)(v), (volatile uint8*)(r)); break; \
5379 + case sizeof(uint16): writew((uint16)(v), (volatile uint16*)(r)); break; \
5380 + case sizeof(uint32): writel((uint32)(v), (volatile uint32*)(r)); break; \
5381 + } \
5382 +} while (0)
5383 +#else /* IL_BIGENDIAN */
5384 +#define R_REG(osh, r) ({ \
5385 + __typeof(*(r)) __osl_v; \
5386 + switch (sizeof(*(r))) { \
5387 + case sizeof(uint8): __osl_v = readb((volatile uint8*)((uint32)r^3)); break; \
5388 + case sizeof(uint16): __osl_v = readw((volatile uint16*)((uint32)r^2)); break; \
5389 + case sizeof(uint32): __osl_v = readl((volatile uint32*)(r)); break; \
5390 + } \
5391 + __osl_v; \
5392 +})
5393 +#define W_REG(osh, r, v) do { \
5394 + switch (sizeof(*(r))) { \
5395 + case sizeof(uint8): writeb((uint8)(v), (volatile uint8*)((uint32)r^3)); break; \
5396 + case sizeof(uint16): writew((uint16)(v), (volatile uint16*)((uint32)r^2)); break; \
5397 + case sizeof(uint32): writel((uint32)(v), (volatile uint32*)(r)); break; \
5398 + } \
5399 +} while (0)
5400 +#endif /* IL_BIGENDIAN */
5401 +
5402 +/* dereference an address that may cause a bus exception */
5403 +#define BUSPROBE(val, addr) get_dbe((val), (addr))
5404 +#include <asm/paccess.h>
5405 +
5406 +/* map/unmap physical to virtual I/O */
5407 +#define REG_MAP(pa, size) ioremap_nocache((unsigned long)(pa), (unsigned long)(size))
5408 +#define REG_UNMAP(va) iounmap((void *)(va))
5409 +
5410 +/* shared (dma-able) memory access macros */
5411 +#define R_SM(r) *(r)
5412 +#define W_SM(r, v) (*(r) = (v))
5413 +#define BZERO_SM(r, len) memset((r), '\0', (len))
5414 +
5415 +#define MALLOC(osh, size) kmalloc((size), GFP_ATOMIC)
5416 +#define MFREE(osh, addr, size) kfree((addr))
5417 +#define MALLOCED(osh) (0)
5418 +
5419 +#define osl_delay OSL_DELAY
5420 +static inline void OSL_DELAY(uint usec)
5421 +{
5422 + uint d;
5423 +
5424 + while (usec > 0) {
5425 + d = MIN(usec, 1000);
5426 + udelay(d);
5427 + usec -= d;
5428 + }
5429 +}
5430 +
5431 +static inline void
5432 +bcm_mdelay(uint ms)
5433 +{
5434 + uint i;
5435 +
5436 + for (i = 0; i < ms; i++) {
5437 + OSL_DELAY(1000);
5438 + }
5439 +}
5440 +
5441 +
5442 +#define OSL_PCMCIA_READ_ATTR(osh, offset, buf, size)
5443 +#define OSL_PCMCIA_WRITE_ATTR(osh, offset, buf, size)
5444 +
5445 +#define OSL_PCI_READ_CONFIG(osh, offset, size) \
5446 + osl_pci_read_config((osh), (offset), (size))
5447 +
5448 +static inline uint32
5449 +osl_pci_read_config(osl_t *osh, uint offset, uint size)
5450 +{
5451 + uint val;
5452 + uint retry = PCI_CFG_RETRY;
5453 +
5454 + do {
5455 + pci_read_config_dword(osh->pdev, offset, &val);
5456 + if (val != 0xffffffff)
5457 + break;
5458 + } while (retry--);
5459 +
5460 + return (val);
5461 +}
5462 +
5463 +#define OSL_PCI_WRITE_CONFIG(osh, offset, size, val) \
5464 + osl_pci_write_config((osh), (offset), (size), (val))
5465 +static inline void
5466 +osl_pci_write_config(osl_t *osh, uint offset, uint size, uint val)
5467 +{
5468 + uint retry = PCI_CFG_RETRY;
5469 +
5470 + do {
5471 + pci_write_config_dword(osh->pdev, offset, val);
5472 + if (offset != PCI_BAR0_WIN)
5473 + break;
5474 + if (osl_pci_read_config(osh, offset, size) == val)
5475 + break;
5476 + } while (retry--);
5477 +}
5478 +
5479 +
5480 +/* return bus # for the pci device pointed by osh->pdev */
5481 +#define OSL_PCI_BUS(osh) osl_pci_bus(osh)
5482 +static inline uint
5483 +osl_pci_bus(osl_t *osh)
5484 +{
5485 + return ((struct pci_dev *)osh->pdev)->bus->number;
5486 +}
5487 +
5488 +/* return slot # for the pci device pointed by osh->pdev */
5489 +#define OSL_PCI_SLOT(osh) osl_pci_slot(osh)
5490 +static inline uint
5491 +osl_pci_slot(osl_t *osh)
5492 +{
5493 + return PCI_SLOT(((struct pci_dev *)osh->pdev)->devfn);
5494 +}
5495 +
5496 +#endif
5497 diff -urN linux.old/arch/mips/bcm947xx/include/pcicfg.h linux.dev/arch/mips/bcm947xx/include/pcicfg.h
5498 --- linux.old/arch/mips/bcm947xx/include/pcicfg.h 1970-01-01 01:00:00.000000000 +0100
5499 +++ linux.dev/arch/mips/bcm947xx/include/pcicfg.h 2006-10-02 21:19:59.000000000 +0200
5500 @@ -0,0 +1,495 @@
5501 +/*
5502 + * pcicfg.h: PCI configuration constants and structures.
5503 + *
5504 + * Copyright 2006, Broadcom Corporation
5505 + * All Rights Reserved.
5506 + *
5507 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
5508 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
5509 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
5510 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
5511 + *
5512 + * $Id: pcicfg.h,v 1.1.1.11 2006/04/08 06:13:40 honor Exp $
5513 + */
5514 +
5515 +#ifndef _h_pcicfg_
5516 +#define _h_pcicfg_
5517 +
5518 +/* The following inside ifndef's so we don't collide with NTDDK.H */
5519 +#ifndef PCI_MAX_BUS
5520 +#define PCI_MAX_BUS 0x100
5521 +#endif
5522 +#ifndef PCI_MAX_DEVICES
5523 +#define PCI_MAX_DEVICES 0x20
5524 +#endif
5525 +#ifndef PCI_MAX_FUNCTION
5526 +#define PCI_MAX_FUNCTION 0x8
5527 +#endif
5528 +
5529 +#ifndef PCI_INVALID_VENDORID
5530 +#define PCI_INVALID_VENDORID 0xffff
5531 +#endif
5532 +#ifndef PCI_INVALID_DEVICEID
5533 +#define PCI_INVALID_DEVICEID 0xffff
5534 +#endif
5535 +
5536 +
5537 +/* Convert between bus-slot-function-register and config addresses */
5538 +
5539 +#define PCICFG_BUS_SHIFT 16 /* Bus shift */
5540 +#define PCICFG_SLOT_SHIFT 11 /* Slot shift */
5541 +#define PCICFG_FUN_SHIFT 8 /* Function shift */
5542 +#define PCICFG_OFF_SHIFT 0 /* Register shift */
5543 +
5544 +#define PCICFG_BUS_MASK 0xff /* Bus mask */
5545 +#define PCICFG_SLOT_MASK 0x1f /* Slot mask */
5546 +#define PCICFG_FUN_MASK 7 /* Function mask */
5547 +#define PCICFG_OFF_MASK 0xff /* Bus mask */
5548 +
5549 +#define PCI_CONFIG_ADDR(b, s, f, o) \
5550 + ((((b) & PCICFG_BUS_MASK) << PCICFG_BUS_SHIFT) \
5551 + | (((s) & PCICFG_SLOT_MASK) << PCICFG_SLOT_SHIFT) \
5552 + | (((f) & PCICFG_FUN_MASK) << PCICFG_FUN_SHIFT) \
5553 + | (((o) & PCICFG_OFF_MASK) << PCICFG_OFF_SHIFT))
5554 +
5555 +#define PCI_CONFIG_BUS(a) (((a) >> PCICFG_BUS_SHIFT) & PCICFG_BUS_MASK)
5556 +#define PCI_CONFIG_SLOT(a) (((a) >> PCICFG_SLOT_SHIFT) & PCICFG_SLOT_MASK)
5557 +#define PCI_CONFIG_FUN(a) (((a) >> PCICFG_FUN_SHIFT) & PCICFG_FUN_MASK)
5558 +#define PCI_CONFIG_OFF(a) (((a) >> PCICFG_OFF_SHIFT) & PCICFG_OFF_MASK)
5559 +
5560 +/* PCIE Config space accessing MACROS */
5561 +
5562 +#define PCIECFG_BUS_SHIFT 24 /* Bus shift */
5563 +#define PCIECFG_SLOT_SHIFT 19 /* Slot/Device shift */
5564 +#define PCIECFG_FUN_SHIFT 16 /* Function shift */
5565 +#define PCIECFG_OFF_SHIFT 0 /* Register shift */
5566 +
5567 +#define PCIECFG_BUS_MASK 0xff /* Bus mask */
5568 +#define PCIECFG_SLOT_MASK 0x1f /* Slot/Device mask */
5569 +#define PCIECFG_FUN_MASK 7 /* Function mask */
5570 +#define PCIECFG_OFF_MASK 0x3ff /* Register mask */
5571 +
5572 +#define PCIE_CONFIG_ADDR(b, s, f, o) \
5573 + ((((b) & PCIECFG_BUS_MASK) << PCIECFG_BUS_SHIFT) \
5574 + | (((s) & PCIECFG_SLOT_MASK) << PCIECFG_SLOT_SHIFT) \
5575 + | (((f) & PCIECFG_FUN_MASK) << PCIECFG_FUN_SHIFT) \
5576 + | (((o) & PCIECFG_OFF_MASK) << PCIECFG_OFF_SHIFT))
5577 +
5578 +#define PCIE_CONFIG_BUS(a) (((a) >> PCIECFG_BUS_SHIFT) & PCIECFG_BUS_MASK)
5579 +#define PCIE_CONFIG_SLOT(a) (((a) >> PCIECFG_SLOT_SHIFT) & PCIECFG_SLOT_MASK)
5580 +#define PCIE_CONFIG_FUN(a) (((a) >> PCIECFG_FUN_SHIFT) & PCIECFG_FUN_MASK)
5581 +#define PCIE_CONFIG_OFF(a) (((a) >> PCIECFG_OFF_SHIFT) & PCIECFG_OFF_MASK)
5582 +
5583 +/* The actual config space */
5584 +
5585 +#define PCI_BAR_MAX 6
5586 +
5587 +#define PCI_ROM_BAR 8
5588 +
5589 +#define PCR_RSVDA_MAX 2
5590 +
5591 +/* Bits in PCI bars' flags */
5592 +
5593 +#define PCIBAR_FLAGS 0xf
5594 +#define PCIBAR_IO 0x1
5595 +#define PCIBAR_MEM1M 0x2
5596 +#define PCIBAR_MEM64 0x4
5597 +#define PCIBAR_PREFETCH 0x8
5598 +#define PCIBAR_MEM32_MASK 0xFFFFFF80
5599 +
5600 +/* pci config status reg has a bit to indicate that capability ptr is present */
5601 +
5602 +#define PCI_CAPPTR_PRESENT 0x0010
5603 +
5604 +typedef struct _pci_config_regs {
5605 + unsigned short vendor;
5606 + unsigned short device;
5607 + unsigned short command;
5608 + unsigned short status;
5609 + unsigned char rev_id;
5610 + unsigned char prog_if;
5611 + unsigned char sub_class;
5612 + unsigned char base_class;
5613 + unsigned char cache_line_size;
5614 + unsigned char latency_timer;
5615 + unsigned char header_type;
5616 + unsigned char bist;
5617 + unsigned long base[PCI_BAR_MAX];
5618 + unsigned long cardbus_cis;
5619 + unsigned short subsys_vendor;
5620 + unsigned short subsys_id;
5621 + unsigned long baserom;
5622 + unsigned long rsvd_a[PCR_RSVDA_MAX];
5623 + unsigned char int_line;
5624 + unsigned char int_pin;
5625 + unsigned char min_gnt;
5626 + unsigned char max_lat;
5627 + unsigned char dev_dep[192];
5628 +} pci_config_regs;
5629 +
5630 +#define SZPCR (sizeof (pci_config_regs))
5631 +#define MINSZPCR 64 /* offsetof (dev_dep[0] */
5632 +
5633 +/* A structure for the config registers is nice, but in most
5634 + * systems the config space is not memory mapped, so we need
5635 + * filed offsetts. :-(
5636 + */
5637 +#define PCI_CFG_VID 0
5638 +#define PCI_CFG_DID 2
5639 +#define PCI_CFG_CMD 4
5640 +#define PCI_CFG_STAT 6
5641 +#define PCI_CFG_REV 8
5642 +#define PCI_CFG_PROGIF 9
5643 +#define PCI_CFG_SUBCL 0xa
5644 +#define PCI_CFG_BASECL 0xb
5645 +#define PCI_CFG_CLSZ 0xc
5646 +#define PCI_CFG_LATTIM 0xd
5647 +#define PCI_CFG_HDR 0xe
5648 +#define PCI_CFG_BIST 0xf
5649 +#define PCI_CFG_BAR0 0x10
5650 +#define PCI_CFG_BAR1 0x14
5651 +#define PCI_CFG_BAR2 0x18
5652 +#define PCI_CFG_BAR3 0x1c
5653 +#define PCI_CFG_BAR4 0x20
5654 +#define PCI_CFG_BAR5 0x24
5655 +#define PCI_CFG_CIS 0x28
5656 +#define PCI_CFG_SVID 0x2c
5657 +#define PCI_CFG_SSID 0x2e
5658 +#define PCI_CFG_ROMBAR 0x30
5659 +#define PCI_CFG_CAPPTR 0x34
5660 +#define PCI_CFG_INT 0x3c
5661 +#define PCI_CFG_PIN 0x3d
5662 +#define PCI_CFG_MINGNT 0x3e
5663 +#define PCI_CFG_MAXLAT 0x3f
5664 +
5665 +#ifdef __NetBSD__
5666 +#undef PCI_CLASS_DISPLAY
5667 +#undef PCI_CLASS_MEMORY
5668 +#undef PCI_CLASS_BRIDGE
5669 +#undef PCI_CLASS_INPUT
5670 +#undef PCI_CLASS_DOCK
5671 +#endif /* __NetBSD__ */
5672 +
5673 +/* Classes and subclasses */
5674 +
5675 +typedef enum {
5676 + PCI_CLASS_OLD = 0,
5677 + PCI_CLASS_DASDI,
5678 + PCI_CLASS_NET,
5679 + PCI_CLASS_DISPLAY,
5680 + PCI_CLASS_MMEDIA,
5681 + PCI_CLASS_MEMORY,
5682 + PCI_CLASS_BRIDGE,
5683 + PCI_CLASS_COMM,
5684 + PCI_CLASS_BASE,
5685 + PCI_CLASS_INPUT,
5686 + PCI_CLASS_DOCK,
5687 + PCI_CLASS_CPU,
5688 + PCI_CLASS_SERIAL,
5689 + PCI_CLASS_INTELLIGENT = 0xe,
5690 + PCI_CLASS_SATELLITE,
5691 + PCI_CLASS_CRYPT,
5692 + PCI_CLASS_DSP,
5693 + PCI_CLASS_XOR = 0xfe
5694 +} pci_classes;
5695 +
5696 +typedef enum {
5697 + PCI_DASDI_SCSI,
5698 + PCI_DASDI_IDE,
5699 + PCI_DASDI_FLOPPY,
5700 + PCI_DASDI_IPI,
5701 + PCI_DASDI_RAID,
5702 + PCI_DASDI_OTHER = 0x80
5703 +} pci_dasdi_subclasses;
5704 +
5705 +typedef enum {
5706 + PCI_NET_ETHER,
5707 + PCI_NET_TOKEN,
5708 + PCI_NET_FDDI,
5709 + PCI_NET_ATM,
5710 + PCI_NET_OTHER = 0x80
5711 +} pci_net_subclasses;
5712 +
5713 +typedef enum {
5714 + PCI_DISPLAY_VGA,
5715 + PCI_DISPLAY_XGA,
5716 + PCI_DISPLAY_3D,
5717 + PCI_DISPLAY_OTHER = 0x80
5718 +} pci_display_subclasses;
5719 +
5720 +typedef enum {
5721 + PCI_MMEDIA_VIDEO,
5722 + PCI_MMEDIA_AUDIO,
5723 + PCI_MMEDIA_PHONE,
5724 + PCI_MEDIA_OTHER = 0x80
5725 +} pci_mmedia_subclasses;
5726 +
5727 +typedef enum {
5728 + PCI_MEMORY_RAM,
5729 + PCI_MEMORY_FLASH,
5730 + PCI_MEMORY_OTHER = 0x80
5731 +} pci_memory_subclasses;
5732 +
5733 +typedef enum {
5734 + PCI_BRIDGE_HOST,
5735 + PCI_BRIDGE_ISA,
5736 + PCI_BRIDGE_EISA,
5737 + PCI_BRIDGE_MC,
5738 + PCI_BRIDGE_PCI,
5739 + PCI_BRIDGE_PCMCIA,
5740 + PCI_BRIDGE_NUBUS,
5741 + PCI_BRIDGE_CARDBUS,
5742 + PCI_BRIDGE_RACEWAY,
5743 + PCI_BRIDGE_OTHER = 0x80
5744 +} pci_bridge_subclasses;
5745 +
5746 +typedef enum {
5747 + PCI_COMM_UART,
5748 + PCI_COMM_PARALLEL,
5749 + PCI_COMM_MULTIUART,
5750 + PCI_COMM_MODEM,
5751 + PCI_COMM_OTHER = 0x80
5752 +} pci_comm_subclasses;
5753 +
5754 +typedef enum {
5755 + PCI_BASE_PIC,
5756 + PCI_BASE_DMA,
5757 + PCI_BASE_TIMER,
5758 + PCI_BASE_RTC,
5759 + PCI_BASE_PCI_HOTPLUG,
5760 + PCI_BASE_OTHER = 0x80
5761 +} pci_base_subclasses;
5762 +
5763 +typedef enum {
5764 + PCI_INPUT_KBD,
5765 + PCI_INPUT_PEN,
5766 + PCI_INPUT_MOUSE,
5767 + PCI_INPUT_SCANNER,
5768 + PCI_INPUT_GAMEPORT,
5769 + PCI_INPUT_OTHER = 0x80
5770 +} pci_input_subclasses;
5771 +
5772 +typedef enum {
5773 + PCI_DOCK_GENERIC,
5774 + PCI_DOCK_OTHER = 0x80
5775 +} pci_dock_subclasses;
5776 +
5777 +typedef enum {
5778 + PCI_CPU_386,
5779 + PCI_CPU_486,
5780 + PCI_CPU_PENTIUM,
5781 + PCI_CPU_ALPHA = 0x10,
5782 + PCI_CPU_POWERPC = 0x20,
5783 + PCI_CPU_MIPS = 0x30,
5784 + PCI_CPU_COPROC = 0x40,
5785 + PCI_CPU_OTHER = 0x80
5786 +} pci_cpu_subclasses;
5787 +
5788 +typedef enum {
5789 + PCI_SERIAL_IEEE1394,
5790 + PCI_SERIAL_ACCESS,
5791 + PCI_SERIAL_SSA,
5792 + PCI_SERIAL_USB,
5793 + PCI_SERIAL_FIBER,
5794 + PCI_SERIAL_SMBUS,
5795 + PCI_SERIAL_OTHER = 0x80
5796 +} pci_serial_subclasses;
5797 +
5798 +typedef enum {
5799 + PCI_INTELLIGENT_I2O
5800 +} pci_intelligent_subclasses;
5801 +
5802 +typedef enum {
5803 + PCI_SATELLITE_TV,
5804 + PCI_SATELLITE_AUDIO,
5805 + PCI_SATELLITE_VOICE,
5806 + PCI_SATELLITE_DATA,
5807 + PCI_SATELLITE_OTHER = 0x80
5808 +} pci_satellite_subclasses;
5809 +
5810 +typedef enum {
5811 + PCI_CRYPT_NETWORK,
5812 + PCI_CRYPT_ENTERTAINMENT,
5813 + PCI_CRYPT_OTHER = 0x80
5814 +} pci_crypt_subclasses;
5815 +
5816 +typedef enum {
5817 + PCI_DSP_DPIO,
5818 + PCI_DSP_OTHER = 0x80
5819 +} pci_dsp_subclasses;
5820 +
5821 +typedef enum {
5822 + PCI_XOR_QDMA,
5823 + PCI_XOR_OTHER = 0x80
5824 +} pci_xor_subclasses;
5825 +
5826 +/* Header types */
5827 +typedef enum {
5828 + PCI_HEADER_NORMAL,
5829 + PCI_HEADER_BRIDGE,
5830 + PCI_HEADER_CARDBUS
5831 +} pci_header_types;
5832 +
5833 +
5834 +/* Overlay for a PCI-to-PCI bridge */
5835 +
5836 +#define PPB_RSVDA_MAX 2
5837 +#define PPB_RSVDD_MAX 8
5838 +
5839 +typedef struct _ppb_config_regs {
5840 + unsigned short vendor;
5841 + unsigned short device;
5842 + unsigned short command;
5843 + unsigned short status;
5844 + unsigned char rev_id;
5845 + unsigned char prog_if;
5846 + unsigned char sub_class;
5847 + unsigned char base_class;
5848 + unsigned char cache_line_size;
5849 + unsigned char latency_timer;
5850 + unsigned char header_type;
5851 + unsigned char bist;
5852 + unsigned long rsvd_a[PPB_RSVDA_MAX];
5853 + unsigned char prim_bus;
5854 + unsigned char sec_bus;
5855 + unsigned char sub_bus;
5856 + unsigned char sec_lat;
5857 + unsigned char io_base;
5858 + unsigned char io_lim;
5859 + unsigned short sec_status;
5860 + unsigned short mem_base;
5861 + unsigned short mem_lim;
5862 + unsigned short pf_mem_base;
5863 + unsigned short pf_mem_lim;
5864 + unsigned long pf_mem_base_hi;
5865 + unsigned long pf_mem_lim_hi;
5866 + unsigned short io_base_hi;
5867 + unsigned short io_lim_hi;
5868 + unsigned short subsys_vendor;
5869 + unsigned short subsys_id;
5870 + unsigned long rsvd_b;
5871 + unsigned char rsvd_c;
5872 + unsigned char int_pin;
5873 + unsigned short bridge_ctrl;
5874 + unsigned char chip_ctrl;
5875 + unsigned char diag_ctrl;
5876 + unsigned short arb_ctrl;
5877 + unsigned long rsvd_d[PPB_RSVDD_MAX];
5878 + unsigned char dev_dep[192];
5879 +} ppb_config_regs;
5880 +
5881 +
5882 +/* PCI CAPABILITY DEFINES */
5883 +#define PCI_CAP_POWERMGMTCAP_ID 0x01
5884 +#define PCI_CAP_MSICAP_ID 0x05
5885 +#define PCI_CAP_PCIECAP_ID 0x10
5886 +
5887 +/* Data structure to define the Message Signalled Interrupt facility
5888 + * Valid for PCI and PCIE configurations
5889 + */
5890 +typedef struct _pciconfig_cap_msi {
5891 + unsigned char capID;
5892 + unsigned char nextptr;
5893 + unsigned short msgctrl;
5894 + unsigned int msgaddr;
5895 +} pciconfig_cap_msi;
5896 +
5897 +/* Data structure to define the Power managment facility
5898 + * Valid for PCI and PCIE configurations
5899 + */
5900 +typedef struct _pciconfig_cap_pwrmgmt {
5901 + unsigned char capID;
5902 + unsigned char nextptr;
5903 + unsigned short pme_cap;
5904 + unsigned short pme_sts_ctrl;
5905 + unsigned char pme_bridge_ext;
5906 + unsigned char data;
5907 +} pciconfig_cap_pwrmgmt;
5908 +
5909 +/* Data structure to define the PCIE capability */
5910 +typedef struct _pciconfig_cap_pcie {
5911 + unsigned char capID;
5912 + unsigned char nextptr;
5913 + unsigned short pcie_cap;
5914 + unsigned int dev_cap;
5915 + unsigned short dev_ctrl;
5916 + unsigned short dev_status;
5917 + unsigned int link_cap;
5918 + unsigned short link_ctrl;
5919 + unsigned short link_status;
5920 +} pciconfig_cap_pcie;
5921 +
5922 +/* PCIE Enhanced CAPABILITY DEFINES */
5923 +#define PCIE_EXTCFG_OFFSET 0x100
5924 +#define PCIE_ADVERRREP_CAPID 0x0001
5925 +#define PCIE_VC_CAPID 0x0002
5926 +#define PCIE_DEVSNUM_CAPID 0x0003
5927 +#define PCIE_PWRBUDGET_CAPID 0x0004
5928 +
5929 +/* Header to define the PCIE specific capabilities in the extended config space */
5930 +typedef struct _pcie_enhanced_caphdr {
5931 + unsigned short capID;
5932 + unsigned short cap_ver : 4;
5933 + unsigned short next_ptr : 12;
5934 +} pcie_enhanced_caphdr;
5935 +
5936 +
5937 +/* Everything below is BRCM HND proprietary */
5938 +
5939 +
5940 +/* Brcm PCI configuration registers */
5941 +#define cap_list rsvd_a[0]
5942 +#define bar0_window dev_dep[0x80 - 0x40]
5943 +#define bar1_window dev_dep[0x84 - 0x40]
5944 +#define sprom_control dev_dep[0x88 - 0x40]
5945 +
5946 +#define PCI_BAR0_WIN 0x80 /* backplane addres space accessed by BAR0 */
5947 +#define PCI_BAR1_WIN 0x84 /* backplane addres space accessed by BAR1 */
5948 +#define PCI_SPROM_CONTROL 0x88 /* sprom property control */
5949 +#define PCI_BAR1_CONTROL 0x8c /* BAR1 region burst control */
5950 +#define PCI_INT_STATUS 0x90 /* PCI and other cores interrupts */
5951 +#define PCI_INT_MASK 0x94 /* mask of PCI and other cores interrupts */
5952 +#define PCI_TO_SB_MB 0x98 /* signal backplane interrupts */
5953 +#define PCI_BACKPLANE_ADDR 0xA0 /* address an arbitrary location on the system backplane */
5954 +#define PCI_BACKPLANE_DATA 0xA4 /* data at the location specified by above address */
5955 +#define PCI_GPIO_IN 0xb0 /* pci config space gpio input (>=rev3) */
5956 +#define PCI_GPIO_OUT 0xb4 /* pci config space gpio output (>=rev3) */
5957 +#define PCI_GPIO_OUTEN 0xb8 /* pci config space gpio output enable (>=rev3) */
5958 +
5959 +#define PCI_BAR0_SHADOW_OFFSET (2 * 1024) /* bar0 + 2K accesses sprom shadow (in pci core) */
5960 +#define PCI_BAR0_SPROM_OFFSET (4 * 1024) /* bar0 + 4K accesses external sprom */
5961 +#define PCI_BAR0_PCIREGS_OFFSET (6 * 1024) /* bar0 + 6K accesses pci core registers */
5962 +#define PCI_BAR0_PCISBR_OFFSET (4 * 1024) /* pci core SB registers are at the end of the
5963 + * 8KB window, so their address is the "regular"
5964 + * address plus 4K
5965 + */
5966 +#define PCI_BAR0_WINSZ 8192 /* bar0 window size */
5967 +
5968 +/* On pci corerev >= 13 and all pcie, the bar0 is now 16KB and it maps: */
5969 +#define PCI_16KB0_PCIREGS_OFFSET (8 * 1024) /* bar0 + 8K accesses pci/pcie core registers */
5970 +#define PCI_16KB0_CCREGS_OFFSET (12 * 1024) /* bar0 + 12K accesses chipc core registers */
5971 +#define PCI_16KBB0_WINSZ (16 * 1024) /* bar0 window size */
5972 +
5973 +/* PCI_INT_STATUS */
5974 +#define PCI_SBIM_STATUS_SERR 0x4 /* backplane SBErr interrupt status */
5975 +
5976 +/* PCI_INT_MASK */
5977 +#define PCI_SBIM_SHIFT 8 /* backplane core interrupt mask bits offset */
5978 +#define PCI_SBIM_MASK 0xff00 /* backplane core interrupt mask */
5979 +#define PCI_SBIM_MASK_SERR 0x4 /* backplane SBErr interrupt mask */
5980 +
5981 +/* PCI_SPROM_CONTROL */
5982 +#define SPROM_SZ_MSK 0x02 /* SPROM Size Mask */
5983 +#define SPROM_LOCKED 0x08 /* SPROM Locked */
5984 +#define SPROM_BLANK 0x04 /* indicating a blank SPROM */
5985 +#define SPROM_WRITEEN 0x10 /* SPROM write enable */
5986 +#define SPROM_BOOTROM_WE 0x20 /* external bootrom write enable */
5987 +#define SPROM_OTPIN_USE 0x80 /* device OTP In use */
5988 +
5989 +#define SPROM_SIZE 256 /* sprom size in 16-bit */
5990 +#define SPROM_CRC_RANGE 64 /* crc cover range in 16-bit */
5991 +
5992 +/* PCI_CFG_CMD_STAT */
5993 +#define PCI_CFG_CMD_STAT_TA 0x08000000 /* target abort status */
5994 +
5995 +#endif /* _h_pcicfg_ */
5996 diff -urN linux.old/arch/mips/bcm947xx/include/sbchipc.h linux.dev/arch/mips/bcm947xx/include/sbchipc.h
5997 --- linux.old/arch/mips/bcm947xx/include/sbchipc.h 1970-01-01 01:00:00.000000000 +0100
5998 +++ linux.dev/arch/mips/bcm947xx/include/sbchipc.h 2006-10-02 21:19:59.000000000 +0200
5999 @@ -0,0 +1,516 @@
6000 +/*
6001 + * SiliconBackplane Chipcommon core hardware definitions.
6002 + *
6003 + * The chipcommon core provides chip identification, SB control,
6004 + * jtag, 0/1/2 uarts, clock frequency control, a watchdog interrupt timer,
6005 + * gpio interface, extbus, and support for serial and parallel flashes.
6006 + *
6007 + * $Id: sbchipc.h,v 1.1.1.14 2006/04/15 01:29:08 michael Exp $
6008 + * Copyright 2006, Broadcom Corporation
6009 + * All Rights Reserved.
6010 + *
6011 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
6012 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
6013 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
6014 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
6015 + *
6016 + */
6017 +
6018 +#ifndef _SBCHIPC_H
6019 +#define _SBCHIPC_H
6020 +
6021 +
6022 +#ifndef _LANGUAGE_ASSEMBLY
6023 +
6024 +/* cpp contortions to concatenate w/arg prescan */
6025 +#ifndef PAD
6026 +#define _PADLINE(line) pad ## line
6027 +#define _XSTR(line) _PADLINE(line)
6028 +#define PAD _XSTR(__LINE__)
6029 +#endif /* PAD */
6030 +
6031 +typedef volatile struct {
6032 + uint32 chipid; /* 0x0 */
6033 + uint32 capabilities;
6034 + uint32 corecontrol; /* corerev >= 1 */
6035 + uint32 bist;
6036 +
6037 + /* OTP */
6038 + uint32 otpstatus; /* 0x10, corerev >= 10 */
6039 + uint32 otpcontrol;
6040 + uint32 otpprog;
6041 + uint32 PAD;
6042 +
6043 + /* Interrupt control */
6044 + uint32 intstatus; /* 0x20 */
6045 + uint32 intmask;
6046 + uint32 chipcontrol; /* 0x28, rev >= 11 */
6047 + uint32 chipstatus; /* 0x2c, rev >= 11 */
6048 +
6049 + /* Jtag Master */
6050 + uint32 jtagcmd; /* 0x30, rev >= 10 */
6051 + uint32 jtagir;
6052 + uint32 jtagdr;
6053 + uint32 jtagctrl;
6054 +
6055 + /* serial flash interface registers */
6056 + uint32 flashcontrol; /* 0x40 */
6057 + uint32 flashaddress;
6058 + uint32 flashdata;
6059 + uint32 PAD[1];
6060 +
6061 + /* Silicon backplane configuration broadcast control */
6062 + uint32 broadcastaddress; /* 0x50 */
6063 + uint32 broadcastdata;
6064 + uint32 PAD[2];
6065 +
6066 + /* gpio - cleared only by power-on-reset */
6067 + uint32 gpioin; /* 0x60 */
6068 + uint32 gpioout;
6069 + uint32 gpioouten;
6070 + uint32 gpiocontrol;
6071 + uint32 gpiointpolarity;
6072 + uint32 gpiointmask;
6073 + uint32 PAD[2];
6074 +
6075 + /* Watchdog timer */
6076 + uint32 watchdog; /* 0x80 */
6077 + uint32 PAD[1];
6078 +
6079 + /* GPIO based LED powersave registers corerev >= 16 */
6080 + uint32 gpiotimerval; /* 0x88 */
6081 + uint32 gpiotimeroutmask;
6082 +
6083 + /* clock control */
6084 + uint32 clockcontrol_n; /* 0x90 */
6085 + uint32 clockcontrol_sb; /* aka m0 */
6086 + uint32 clockcontrol_pci; /* aka m1 */
6087 + uint32 clockcontrol_m2; /* mii/uart/mipsref */
6088 + uint32 clockcontrol_m3; /* cpu */
6089 + uint32 clkdiv; /* corerev >= 3 */
6090 + uint32 PAD[2];
6091 +
6092 + /* pll delay registers (corerev >= 4) */
6093 + uint32 pll_on_delay; /* 0xb0 */
6094 + uint32 fref_sel_delay;
6095 + uint32 slow_clk_ctl; /* 5 < corerev < 10 */
6096 + uint32 PAD[1];
6097 +
6098 + /* Instaclock registers (corerev >= 10) */
6099 + uint32 system_clk_ctl; /* 0xc0 */
6100 + uint32 clkstatestretch;
6101 + uint32 PAD[14];
6102 +
6103 + /* ExtBus control registers (corerev >= 3) */
6104 + uint32 pcmcia_config; /* 0x100 */
6105 + uint32 pcmcia_memwait;
6106 + uint32 pcmcia_attrwait;
6107 + uint32 pcmcia_iowait;
6108 + uint32 ide_config;
6109 + uint32 ide_memwait;
6110 + uint32 ide_attrwait;
6111 + uint32 ide_iowait;
6112 + uint32 prog_config;
6113 + uint32 prog_waitcount;
6114 + uint32 flash_config;
6115 + uint32 flash_waitcount;
6116 + uint32 PAD[44];
6117 +
6118 + /* Clock control and hardware workarounds */
6119 + uint32 clk_ctl_st;
6120 + uint32 hw_war;
6121 + uint32 PAD[70];
6122 +
6123 + /* uarts */
6124 + uint8 uart0data; /* 0x300 */
6125 + uint8 uart0imr;
6126 + uint8 uart0fcr;
6127 + uint8 uart0lcr;
6128 + uint8 uart0mcr;
6129 + uint8 uart0lsr;
6130 + uint8 uart0msr;
6131 + uint8 uart0scratch;
6132 + uint8 PAD[248]; /* corerev >= 1 */
6133 +
6134 + uint8 uart1data; /* 0x400 */
6135 + uint8 uart1imr;
6136 + uint8 uart1fcr;
6137 + uint8 uart1lcr;
6138 + uint8 uart1mcr;
6139 + uint8 uart1lsr;
6140 + uint8 uart1msr;
6141 + uint8 uart1scratch;
6142 +} chipcregs_t;
6143 +
6144 +#endif /* _LANGUAGE_ASSEMBLY */
6145 +
6146 +#define CC_CHIPID 0
6147 +#define CC_CAPABILITIES 4
6148 +#define CC_JTAGCMD 0x30
6149 +#define CC_JTAGIR 0x34
6150 +#define CC_JTAGDR 0x38
6151 +#define CC_JTAGCTRL 0x3c
6152 +#define CC_WATCHDOG 0x80
6153 +#define CC_CLKC_N 0x90
6154 +#define CC_CLKC_M0 0x94
6155 +#define CC_CLKC_M1 0x98
6156 +#define CC_CLKC_M2 0x9c
6157 +#define CC_CLKC_M3 0xa0
6158 +#define CC_CLKDIV 0xa4
6159 +#define CC_SYS_CLK_CTL 0xc0
6160 +#define CC_OTP 0x800
6161 +
6162 +/* chipid */
6163 +#define CID_ID_MASK 0x0000ffff /* Chip Id mask */
6164 +#define CID_REV_MASK 0x000f0000 /* Chip Revision mask */
6165 +#define CID_REV_SHIFT 16 /* Chip Revision shift */
6166 +#define CID_PKG_MASK 0x00f00000 /* Package Option mask */
6167 +#define CID_PKG_SHIFT 20 /* Package Option shift */
6168 +#define CID_CC_MASK 0x0f000000 /* CoreCount (corerev >= 4) */
6169 +#define CID_CC_SHIFT 24
6170 +
6171 +/* capabilities */
6172 +#define CAP_UARTS_MASK 0x00000003 /* Number of uarts */
6173 +#define CAP_MIPSEB 0x00000004 /* MIPS is in big-endian mode */
6174 +#define CAP_UCLKSEL 0x00000018 /* UARTs clock select */
6175 +#define CAP_UINTCLK 0x00000008 /* UARTs are driven by internal divided clock */
6176 +#define CAP_UARTGPIO 0x00000020 /* UARTs own Gpio's 15:12 */
6177 +#define CAP_EXTBUS_MASK 0x000000c0 /* External bus mask */
6178 +#define CAP_EXTBUS_NONE 0x00000000 /* No ExtBus present */
6179 +#define CAP_EXTBUS_FULL 0x00000040 /* ExtBus: PCMCIA, IDE & Prog */
6180 +#define CAP_EXTBUS_PROG 0x00000080 /* ExtBus: ProgIf only */
6181 +#define CAP_FLASH_MASK 0x00000700 /* Type of flash */
6182 +#define CAP_PLL_MASK 0x00038000 /* Type of PLL */
6183 +#define CAP_PWR_CTL 0x00040000 /* Power control */
6184 +#define CAP_OTPSIZE 0x00380000 /* OTP Size (0 = none) */
6185 +#define CAP_OTPSIZE_SHIFT 19 /* OTP Size shift */
6186 +#define CAP_OTPSIZE_BASE 5 /* OTP Size base */
6187 +#define CAP_JTAGP 0x00400000 /* JTAG Master Present */
6188 +#define CAP_ROM 0x00800000 /* Internal boot rom active */
6189 +#define CAP_BKPLN64 0x08000000 /* 64-bit backplane */
6190 +
6191 +/* PLL type */
6192 +#define PLL_NONE 0x00000000
6193 +#define PLL_TYPE1 0x00010000 /* 48Mhz base, 3 dividers */
6194 +#define PLL_TYPE2 0x00020000 /* 48Mhz, 4 dividers */
6195 +#define PLL_TYPE3 0x00030000 /* 25Mhz, 2 dividers */
6196 +#define PLL_TYPE4 0x00008000 /* 48Mhz, 4 dividers */
6197 +#define PLL_TYPE5 0x00018000 /* 25Mhz, 4 dividers */
6198 +#define PLL_TYPE6 0x00028000 /* 100/200 or 120/240 only */
6199 +#define PLL_TYPE7 0x00038000 /* 25Mhz, 4 dividers */
6200 +
6201 +/* corecontrol */
6202 +#define CC_UARTCLKO 0x00000001 /* Drive UART with internal clock */
6203 +#define CC_SE 0x00000002 /* sync clk out enable (corerev >= 3) */
6204 +
6205 +/* chipcontrol */
6206 +#define CHIPCTRL_4321A0_DEFAULT 0x3a4
6207 +#define CHIPCTRL_4321A1_DEFAULT 0x0a4
6208 +
6209 +/* Fields in the otpstatus register */
6210 +#define OTPS_PROGFAIL 0x80000000
6211 +#define OTPS_PROTECT 0x00000007
6212 +#define OTPS_HW_PROTECT 0x00000001
6213 +#define OTPS_SW_PROTECT 0x00000002
6214 +#define OTPS_CID_PROTECT 0x00000004
6215 +
6216 +/* Fields in the otpcontrol register */
6217 +#define OTPC_RECWAIT 0xff000000
6218 +#define OTPC_PROGWAIT 0x00ffff00
6219 +#define OTPC_PRW_SHIFT 8
6220 +#define OTPC_MAXFAIL 0x00000038
6221 +#define OTPC_VSEL 0x00000006
6222 +#define OTPC_SELVL 0x00000001
6223 +
6224 +/* Fields in otpprog */
6225 +#define OTPP_COL_MASK 0x000000ff
6226 +#define OTPP_ROW_MASK 0x0000ff00
6227 +#define OTPP_ROW_SHIFT 8
6228 +#define OTPP_READERR 0x10000000
6229 +#define OTPP_VALUE 0x20000000
6230 +#define OTPP_VALUE_SHIFT 29
6231 +#define OTPP_READ 0x40000000
6232 +#define OTPP_START 0x80000000
6233 +#define OTPP_BUSY 0x80000000
6234 +
6235 +/* jtagcmd */
6236 +#define JCMD_START 0x80000000
6237 +#define JCMD_BUSY 0x80000000
6238 +#define JCMD_PAUSE 0x40000000
6239 +#define JCMD0_ACC_MASK 0x0000f000
6240 +#define JCMD0_ACC_IRDR 0x00000000
6241 +#define JCMD0_ACC_DR 0x00001000
6242 +#define JCMD0_ACC_IR 0x00002000
6243 +#define JCMD0_ACC_RESET 0x00003000
6244 +#define JCMD0_ACC_IRPDR 0x00004000
6245 +#define JCMD0_ACC_PDR 0x00005000
6246 +#define JCMD0_IRW_MASK 0x00000f00
6247 +#define JCMD_ACC_MASK 0x000f0000 /* Changes for corerev 11 */
6248 +#define JCMD_ACC_IRDR 0x00000000
6249 +#define JCMD_ACC_DR 0x00010000
6250 +#define JCMD_ACC_IR 0x00020000
6251 +#define JCMD_ACC_RESET 0x00030000
6252 +#define JCMD_ACC_IRPDR 0x00040000
6253 +#define JCMD_ACC_PDR 0x00050000
6254 +#define JCMD_IRW_MASK 0x00001f00
6255 +#define JCMD_IRW_SHIFT 8
6256 +#define JCMD_DRW_MASK 0x0000003f
6257 +
6258 +/* jtagctrl */
6259 +#define JCTRL_FORCE_CLK 4 /* Force clock */
6260 +#define JCTRL_EXT_EN 2 /* Enable external targets */
6261 +#define JCTRL_EN 1 /* Enable Jtag master */
6262 +
6263 +/* Fields in clkdiv */
6264 +#define CLKD_SFLASH 0x0f000000
6265 +#define CLKD_SFLASH_SHIFT 24
6266 +#define CLKD_OTP 0x000f0000
6267 +#define CLKD_OTP_SHIFT 16
6268 +#define CLKD_JTAG 0x00000f00
6269 +#define CLKD_JTAG_SHIFT 8
6270 +#define CLKD_UART 0x000000ff
6271 +
6272 +/* intstatus/intmask */
6273 +#define CI_GPIO 0x00000001 /* gpio intr */
6274 +#define CI_EI 0x00000002 /* ro: ext intr pin (corerev >= 3) */
6275 +#define CI_WDRESET 0x80000000 /* watchdog reset occurred */
6276 +
6277 +/* slow_clk_ctl */
6278 +#define SCC_SS_MASK 0x00000007 /* slow clock source mask */
6279 +#define SCC_SS_LPO 0x00000000 /* source of slow clock is LPO */
6280 +#define SCC_SS_XTAL 0x00000001 /* source of slow clock is crystal */
6281 +#define SCC_SS_PCI 0x00000002 /* source of slow clock is PCI */
6282 +#define SCC_LF 0x00000200 /* LPOFreqSel, 1: 160Khz, 0: 32KHz */
6283 +#define SCC_LP 0x00000400 /* LPOPowerDown, 1: LPO is disabled,
6284 + * 0: LPO is enabled
6285 + */
6286 +#define SCC_FS 0x00000800 /* ForceSlowClk, 1: sb/cores running on slow clock,
6287 + * 0: power logic control
6288 + */
6289 +#define SCC_IP 0x00001000 /* IgnorePllOffReq, 1/0: power logic ignores/honors
6290 + * PLL clock disable requests from core
6291 + */
6292 +#define SCC_XC 0x00002000 /* XtalControlEn, 1/0: power logic does/doesn't
6293 + * disable crystal when appropriate
6294 + */
6295 +#define SCC_XP 0x00004000 /* XtalPU (RO), 1/0: crystal running/disabled */
6296 +#define SCC_CD_MASK 0xffff0000 /* ClockDivider (SlowClk = 1/(4+divisor)) */
6297 +#define SCC_CD_SHIFT 16
6298 +
6299 +/* system_clk_ctl */
6300 +#define SYCC_IE 0x00000001 /* ILPen: Enable Idle Low Power */
6301 +#define SYCC_AE 0x00000002 /* ALPen: Enable Active Low Power */
6302 +#define SYCC_FP 0x00000004 /* ForcePLLOn */
6303 +#define SYCC_AR 0x00000008 /* Force ALP (or HT if ALPen is not set */
6304 +#define SYCC_HR 0x00000010 /* Force HT */
6305 +#define SYCC_CD_MASK 0xffff0000 /* ClkDiv (ILP = 1/(4 * (divisor + 1)) */
6306 +#define SYCC_CD_SHIFT 16
6307 +
6308 +/* gpiotimerval */
6309 +#define GPIO_ONTIME_SHIFT 16
6310 +
6311 +/* clockcontrol_n */
6312 +#define CN_N1_MASK 0x3f /* n1 control */
6313 +#define CN_N2_MASK 0x3f00 /* n2 control */
6314 +#define CN_N2_SHIFT 8
6315 +#define CN_PLLC_MASK 0xf0000 /* pll control */
6316 +#define CN_PLLC_SHIFT 16
6317 +
6318 +/* clockcontrol_sb/pci/uart */
6319 +#define CC_M1_MASK 0x3f /* m1 control */
6320 +#define CC_M2_MASK 0x3f00 /* m2 control */
6321 +#define CC_M2_SHIFT 8
6322 +#define CC_M3_MASK 0x3f0000 /* m3 control */
6323 +#define CC_M3_SHIFT 16
6324 +#define CC_MC_MASK 0x1f000000 /* mux control */
6325 +#define CC_MC_SHIFT 24
6326 +
6327 +/* N3M Clock control magic field values */
6328 +#define CC_F6_2 0x02 /* A factor of 2 in */
6329 +#define CC_F6_3 0x03 /* 6-bit fields like */
6330 +#define CC_F6_4 0x05 /* N1, M1 or M3 */
6331 +#define CC_F6_5 0x09
6332 +#define CC_F6_6 0x11
6333 +#define CC_F6_7 0x21
6334 +
6335 +#define CC_F5_BIAS 5 /* 5-bit fields get this added */
6336 +
6337 +#define CC_MC_BYPASS 0x08
6338 +#define CC_MC_M1 0x04
6339 +#define CC_MC_M1M2 0x02
6340 +#define CC_MC_M1M2M3 0x01
6341 +#define CC_MC_M1M3 0x11
6342 +
6343 +/* Type 2 Clock control magic field values */
6344 +#define CC_T2_BIAS 2 /* n1, n2, m1 & m3 bias */
6345 +#define CC_T2M2_BIAS 3 /* m2 bias */
6346 +
6347 +#define CC_T2MC_M1BYP 1
6348 +#define CC_T2MC_M2BYP 2
6349 +#define CC_T2MC_M3BYP 4
6350 +
6351 +/* Type 6 Clock control magic field values */
6352 +#define CC_T6_MMASK 1 /* bits of interest in m */
6353 +#define CC_T6_M0 120000000 /* sb clock for m = 0 */
6354 +#define CC_T6_M1 100000000 /* sb clock for m = 1 */
6355 +#define SB2MIPS_T6(sb) (2 * (sb))
6356 +
6357 +/* Common clock base */
6358 +#define CC_CLOCK_BASE1 24000000 /* Half the clock freq */
6359 +#define CC_CLOCK_BASE2 12500000 /* Alternate crystal on some PLL's */
6360 +
6361 +/* Clock control values for 200Mhz in 5350 */
6362 +#define CLKC_5350_N 0x0311
6363 +#define CLKC_5350_M 0x04020009
6364 +
6365 +/* Flash types in the chipcommon capabilities register */
6366 +#define FLASH_NONE 0x000 /* No flash */
6367 +#define SFLASH_ST 0x100 /* ST serial flash */
6368 +#define SFLASH_AT 0x200 /* Atmel serial flash */
6369 +#define PFLASH 0x700 /* Parallel flash */
6370 +
6371 +/* Bits in the ExtBus config registers */
6372 +#define CC_CFG_EN 0x0001 /* Enable */
6373 +#define CC_CFG_EM_MASK 0x000e /* Extif Mode */
6374 +#define CC_CFG_EM_ASYNC 0x0000 /* Async/Parallel flash */
6375 +#define CC_CFG_EM_SYNC 0x0002 /* Synchronous */
6376 +#define CC_CFG_EM_PCMCIA 0x0004 /* PCMCIA */
6377 +#define CC_CFG_EM_IDE 0x0006 /* IDE */
6378 +#define CC_CFG_DS 0x0010 /* Data size, 0=8bit, 1=16bit */
6379 +#define CC_CFG_CD_MASK 0x0060 /* Sync: Clock divisor */
6380 +#define CC_CFG_CE 0x0080 /* Sync: Clock enable */
6381 +#define CC_CFG_SB 0x0100 /* Sync: Size/Bytestrobe */
6382 +
6383 +/* ExtBus address space */
6384 +#define CC_EB_BASE 0x1a000000 /* Chipc ExtBus base address */
6385 +#define CC_EB_PCMCIA_MEM 0x1a000000 /* PCMCIA 0 memory base address */
6386 +#define CC_EB_PCMCIA_IO 0x1a200000 /* PCMCIA 0 I/O base address */
6387 +#define CC_EB_PCMCIA_CFG 0x1a400000 /* PCMCIA 0 config base address */
6388 +#define CC_EB_IDE 0x1a800000 /* IDE memory base */
6389 +#define CC_EB_PCMCIA1_MEM 0x1a800000 /* PCMCIA 1 memory base address */
6390 +#define CC_EB_PCMCIA1_IO 0x1aa00000 /* PCMCIA 1 I/O base address */
6391 +#define CC_EB_PCMCIA1_CFG 0x1ac00000 /* PCMCIA 1 config base address */
6392 +#define CC_EB_PROGIF 0x1b000000 /* ProgIF Async/Sync base address */
6393 +
6394 +
6395 +/* Start/busy bit in flashcontrol */
6396 +#define SFLASH_OPCODE 0x000000ff
6397 +#define SFLASH_ACTION 0x00000700
6398 +#define SFLASH_START 0x80000000
6399 +#define SFLASH_BUSY SFLASH_START
6400 +
6401 +/* flashcontrol action codes */
6402 +#define SFLASH_ACT_OPONLY 0x0000 /* Issue opcode only */
6403 +#define SFLASH_ACT_OP1D 0x0100 /* opcode + 1 data byte */
6404 +#define SFLASH_ACT_OP3A 0x0200 /* opcode + 3 address bytes */
6405 +#define SFLASH_ACT_OP3A1D 0x0300 /* opcode + 3 addres & 1 data bytes */
6406 +#define SFLASH_ACT_OP3A4D 0x0400 /* opcode + 3 addres & 4 data bytes */
6407 +#define SFLASH_ACT_OP3A4X4D 0x0500 /* opcode + 3 addres, 4 don't care & 4 data bytes */
6408 +#define SFLASH_ACT_OP3A1X4D 0x0700 /* opcode + 3 addres, 1 don't care & 4 data bytes */
6409 +
6410 +/* flashcontrol action+opcodes for ST flashes */
6411 +#define SFLASH_ST_WREN 0x0006 /* Write Enable */
6412 +#define SFLASH_ST_WRDIS 0x0004 /* Write Disable */
6413 +#define SFLASH_ST_RDSR 0x0105 /* Read Status Register */
6414 +#define SFLASH_ST_WRSR 0x0101 /* Write Status Register */
6415 +#define SFLASH_ST_READ 0x0303 /* Read Data Bytes */
6416 +#define SFLASH_ST_PP 0x0302 /* Page Program */
6417 +#define SFLASH_ST_SE 0x02d8 /* Sector Erase */
6418 +#define SFLASH_ST_BE 0x00c7 /* Bulk Erase */
6419 +#define SFLASH_ST_DP 0x00b9 /* Deep Power-down */
6420 +#define SFLASH_ST_RES 0x03ab /* Read Electronic Signature */
6421 +
6422 +/* Status register bits for ST flashes */
6423 +#define SFLASH_ST_WIP 0x01 /* Write In Progress */
6424 +#define SFLASH_ST_WEL 0x02 /* Write Enable Latch */
6425 +#define SFLASH_ST_BP_MASK 0x1c /* Block Protect */
6426 +#define SFLASH_ST_BP_SHIFT 2
6427 +#define SFLASH_ST_SRWD 0x80 /* Status Register Write Disable */
6428 +
6429 +/* flashcontrol action+opcodes for Atmel flashes */
6430 +#define SFLASH_AT_READ 0x07e8
6431 +#define SFLASH_AT_PAGE_READ 0x07d2
6432 +#define SFLASH_AT_BUF1_READ
6433 +#define SFLASH_AT_BUF2_READ
6434 +#define SFLASH_AT_STATUS 0x01d7
6435 +#define SFLASH_AT_BUF1_WRITE 0x0384
6436 +#define SFLASH_AT_BUF2_WRITE 0x0387
6437 +#define SFLASH_AT_BUF1_ERASE_PROGRAM 0x0283
6438 +#define SFLASH_AT_BUF2_ERASE_PROGRAM 0x0286
6439 +#define SFLASH_AT_BUF1_PROGRAM 0x0288
6440 +#define SFLASH_AT_BUF2_PROGRAM 0x0289
6441 +#define SFLASH_AT_PAGE_ERASE 0x0281
6442 +#define SFLASH_AT_BLOCK_ERASE 0x0250
6443 +#define SFLASH_AT_BUF1_WRITE_ERASE_PROGRAM 0x0382
6444 +#define SFLASH_AT_BUF2_WRITE_ERASE_PROGRAM 0x0385
6445 +#define SFLASH_AT_BUF1_LOAD 0x0253
6446 +#define SFLASH_AT_BUF2_LOAD 0x0255
6447 +#define SFLASH_AT_BUF1_COMPARE 0x0260
6448 +#define SFLASH_AT_BUF2_COMPARE 0x0261
6449 +#define SFLASH_AT_BUF1_REPROGRAM 0x0258
6450 +#define SFLASH_AT_BUF2_REPROGRAM 0x0259
6451 +
6452 +/* Status register bits for Atmel flashes */
6453 +#define SFLASH_AT_READY 0x80
6454 +#define SFLASH_AT_MISMATCH 0x40
6455 +#define SFLASH_AT_ID_MASK 0x38
6456 +#define SFLASH_AT_ID_SHIFT 3
6457 +
6458 +/* OTP regions */
6459 +#define OTP_HW_REGION OTPS_HW_PROTECT
6460 +#define OTP_SW_REGION OTPS_SW_PROTECT
6461 +#define OTP_CID_REGION OTPS_CID_PROTECT
6462 +
6463 +/* OTP regions (Byte offsets from otp size) */
6464 +#define OTP_SWLIM_OFF (-8)
6465 +#define OTP_CIDBASE_OFF 0
6466 +#define OTP_CIDLIM_OFF 8
6467 +
6468 +/* Predefined OTP words (Word offset from otp size) */
6469 +#define OTP_BOUNDARY_OFF (-4)
6470 +#define OTP_HWSIGN_OFF (-3)
6471 +#define OTP_SWSIGN_OFF (-2)
6472 +#define OTP_CIDSIGN_OFF (-1)
6473 +
6474 +#define OTP_CID_OFF 0
6475 +#define OTP_PKG_OFF 1
6476 +#define OTP_FID_OFF 2
6477 +#define OTP_RSV_OFF 3
6478 +#define OTP_LIM_OFF 4
6479 +
6480 +#define OTP_SIGNATURE 0x578a
6481 +#define OTP_MAGIC 0x4e56
6482 +
6483 +/*
6484 + * These are the UART port assignments, expressed as offsets from the base
6485 + * register. These assignments should hold for any serial port based on
6486 + * a 8250, 16450, or 16550(A).
6487 + */
6488 +
6489 +#define UART_RX 0 /* In: Receive buffer (DLAB=0) */
6490 +#define UART_TX 0 /* Out: Transmit buffer (DLAB=0) */
6491 +#define UART_DLL 0 /* Out: Divisor Latch Low (DLAB=1) */
6492 +#define UART_IER 1 /* In/Out: Interrupt Enable Register (DLAB=0) */
6493 +#define UART_DLM 1 /* Out: Divisor Latch High (DLAB=1) */
6494 +#define UART_IIR 2 /* In: Interrupt Identity Register */
6495 +#define UART_FCR 2 /* Out: FIFO Control Register */
6496 +#define UART_LCR 3 /* Out: Line Control Register */
6497 +#define UART_MCR 4 /* Out: Modem Control Register */
6498 +#define UART_LSR 5 /* In: Line Status Register */
6499 +#define UART_MSR 6 /* In: Modem Status Register */
6500 +#define UART_SCR 7 /* I/O: Scratch Register */
6501 +#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
6502 +#define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */
6503 +#define UART_MCR_OUT2 0x08 /* MCR GPIO out 2 */
6504 +#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
6505 +#define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
6506 +#define UART_LSR_RXRDY 0x01 /* Receiver ready */
6507 +#define UART_FCR_FIFO_ENABLE 1 /* FIFO control register bit controlling FIFO enable/disable */
6508 +
6509 +/* Interrupt Enable Register (IER) bits */
6510 +#define UART_IER_EDSSI 8 /* enable modem status interrupt */
6511 +#define UART_IER_ELSI 4 /* enable receiver line status interrupt */
6512 +#define UART_IER_ETBEI 2 /* enable transmitter holding register empty interrupt */
6513 +#define UART_IER_ERBFI 1 /* enable data available interrupt */
6514 +
6515 +#endif /* _SBCHIPC_H */
6516 diff -urN linux.old/arch/mips/bcm947xx/include/sbconfig.h linux.dev/arch/mips/bcm947xx/include/sbconfig.h
6517 --- linux.old/arch/mips/bcm947xx/include/sbconfig.h 1970-01-01 01:00:00.000000000 +0100
6518 +++ linux.dev/arch/mips/bcm947xx/include/sbconfig.h 2006-10-02 21:19:59.000000000 +0200
6519 @@ -0,0 +1,369 @@
6520 +/*
6521 + * Broadcom SiliconBackplane hardware register definitions.
6522 + *
6523 + * Copyright 2006, Broadcom Corporation
6524 + * All Rights Reserved.
6525 + *
6526 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
6527 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
6528 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
6529 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
6530 + *
6531 + * $Id: sbconfig.h,v 1.1.1.11 2006/02/27 03:43:16 honor Exp $
6532 + */
6533 +
6534 +#ifndef _SBCONFIG_H
6535 +#define _SBCONFIG_H
6536 +
6537 +/* cpp contortions to concatenate w/arg prescan */
6538 +#ifndef PAD
6539 +#define _PADLINE(line) pad ## line
6540 +#define _XSTR(line) _PADLINE(line)
6541 +#define PAD _XSTR(__LINE__)
6542 +#endif
6543 +
6544 +/*
6545 + * SiliconBackplane Address Map.
6546 + * All regions may not exist on all chips.
6547 + */
6548 +#define SB_SDRAM_BASE 0x00000000 /* Physical SDRAM */
6549 +#define SB_PCI_MEM 0x08000000 /* Host Mode sb2pcitranslation0 (64 MB) */
6550 +#define SB_PCI_MEM_SZ (64 * 1024 * 1024)
6551 +#define SB_PCI_CFG 0x0c000000 /* Host Mode sb2pcitranslation1 (64 MB) */
6552 +#define SB_SDRAM_SWAPPED 0x10000000 /* Byteswapped Physical SDRAM */
6553 +#define SB_ENUM_BASE 0x18000000 /* Enumeration space base */
6554 +#define SB_ENUM_LIM 0x18010000 /* Enumeration space limit */
6555 +
6556 +#define SB_FLASH2 0x1c000000 /* Flash Region 2 (region 1 shadowed here) */
6557 +#define SB_FLASH2_SZ 0x02000000 /* Size of Flash Region 2 */
6558 +
6559 +#define SB_EXTIF_BASE 0x1f000000 /* External Interface region base address */
6560 +#define SB_FLASH1 0x1fc00000 /* MIPS Flash Region 1 */
6561 +#define SB_FLASH1_SZ 0x00400000 /* MIPS Size of Flash Region 1 */
6562 +
6563 +#define SB_ROM 0x20000000 /* ARM ROM */
6564 +#define SB_SRAM2 0x80000000 /* ARM SRAM Region 2 */
6565 +#define SB_ARM_FLASH1 0xffff0000 /* ARM Flash Region 1 */
6566 +#define SB_ARM_FLASH1_SZ 0x00010000 /* ARM Size of Flash Region 1 */
6567 +
6568 +#define SB_PCI_DMA 0x40000000 /* Client Mode sb2pcitranslation2 (1 GB) */
6569 +#define SB_PCI_DMA_SZ 0x40000000 /* Client Mode sb2pcitranslation2 size in bytes */
6570 +#define SB_PCIE_DMA_L32 0x00000000 /* PCIE Client Mode sb2pcitranslation2
6571 + * (2 ZettaBytes), low 32 bits
6572 + */
6573 +#define SB_PCIE_DMA_H32 0x80000000 /* PCIE Client Mode sb2pcitranslation2
6574 + * (2 ZettaBytes), high 32 bits
6575 + */
6576 +#define SB_EUART (SB_EXTIF_BASE + 0x00800000)
6577 +#define SB_LED (SB_EXTIF_BASE + 0x00900000)
6578 +
6579 +
6580 +/* enumeration space related defs */
6581 +#define SB_CORE_SIZE 0x1000 /* each core gets 4Kbytes for registers */
6582 +#define SB_MAXCORES ((SB_ENUM_LIM - SB_ENUM_BASE)/SB_CORE_SIZE)
6583 +#define SB_MAXFUNCS 4 /* max. # functions per core */
6584 +#define SBCONFIGOFF 0xf00 /* core sbconfig regs are top 256bytes of regs */
6585 +#define SBCONFIGSIZE 256 /* sizeof (sbconfig_t) */
6586 +
6587 +/* mips address */
6588 +#define SB_EJTAG 0xff200000 /* MIPS EJTAG space (2M) */
6589 +
6590 +/*
6591 + * Sonics Configuration Space Registers.
6592 + */
6593 +#define SBIPSFLAG 0x08
6594 +#define SBTPSFLAG 0x18
6595 +#define SBTMERRLOGA 0x48 /* sonics >= 2.3 */
6596 +#define SBTMERRLOG 0x50 /* sonics >= 2.3 */
6597 +#define SBADMATCH3 0x60
6598 +#define SBADMATCH2 0x68
6599 +#define SBADMATCH1 0x70
6600 +#define SBIMSTATE 0x90
6601 +#define SBINTVEC 0x94
6602 +#define SBTMSTATELOW 0x98
6603 +#define SBTMSTATEHIGH 0x9c
6604 +#define SBBWA0 0xa0
6605 +#define SBIMCONFIGLOW 0xa8
6606 +#define SBIMCONFIGHIGH 0xac
6607 +#define SBADMATCH0 0xb0
6608 +#define SBTMCONFIGLOW 0xb8
6609 +#define SBTMCONFIGHIGH 0xbc
6610 +#define SBBCONFIG 0xc0
6611 +#define SBBSTATE 0xc8
6612 +#define SBACTCNFG 0xd8
6613 +#define SBFLAGST 0xe8
6614 +#define SBIDLOW 0xf8
6615 +#define SBIDHIGH 0xfc
6616 +
6617 +/* All the previous registers are above SBCONFIGOFF, but with Sonics 2.3, we have
6618 + * a few registers *below* that line. I think it would be very confusing to try
6619 + * and change the value of SBCONFIGOFF, so I'm definig them as absolute offsets here,
6620 + */
6621 +
6622 +#define SBIMERRLOGA 0xea8
6623 +#define SBIMERRLOG 0xeb0
6624 +#define SBTMPORTCONNID0 0xed8
6625 +#define SBTMPORTLOCK0 0xef8
6626 +
6627 +#ifndef _LANGUAGE_ASSEMBLY
6628 +
6629 +typedef volatile struct _sbconfig {
6630 + uint32 PAD[2];
6631 + uint32 sbipsflag; /* initiator port ocp slave flag */
6632 + uint32 PAD[3];
6633 + uint32 sbtpsflag; /* target port ocp slave flag */
6634 + uint32 PAD[11];
6635 + uint32 sbtmerrloga; /* (sonics >= 2.3) */
6636 + uint32 PAD;
6637 + uint32 sbtmerrlog; /* (sonics >= 2.3) */
6638 + uint32 PAD[3];
6639 + uint32 sbadmatch3; /* address match3 */
6640 + uint32 PAD;
6641 + uint32 sbadmatch2; /* address match2 */
6642 + uint32 PAD;
6643 + uint32 sbadmatch1; /* address match1 */
6644 + uint32 PAD[7];
6645 + uint32 sbimstate; /* initiator agent state */
6646 + uint32 sbintvec; /* interrupt mask */
6647 + uint32 sbtmstatelow; /* target state */
6648 + uint32 sbtmstatehigh; /* target state */
6649 + uint32 sbbwa0; /* bandwidth allocation table0 */
6650 + uint32 PAD;
6651 + uint32 sbimconfiglow; /* initiator configuration */
6652 + uint32 sbimconfighigh; /* initiator configuration */
6653 + uint32 sbadmatch0; /* address match0 */
6654 + uint32 PAD;
6655 + uint32 sbtmconfiglow; /* target configuration */
6656 + uint32 sbtmconfighigh; /* target configuration */
6657 + uint32 sbbconfig; /* broadcast configuration */
6658 + uint32 PAD;
6659 + uint32 sbbstate; /* broadcast state */
6660 + uint32 PAD[3];
6661 + uint32 sbactcnfg; /* activate configuration */
6662 + uint32 PAD[3];
6663 + uint32 sbflagst; /* current sbflags */
6664 + uint32 PAD[3];
6665 + uint32 sbidlow; /* identification */
6666 + uint32 sbidhigh; /* identification */
6667 +} sbconfig_t;
6668 +
6669 +#endif /* _LANGUAGE_ASSEMBLY */
6670 +
6671 +/* sbipsflag */
6672 +#define SBIPS_INT1_MASK 0x3f /* which sbflags get routed to mips interrupt 1 */
6673 +#define SBIPS_INT1_SHIFT 0
6674 +#define SBIPS_INT2_MASK 0x3f00 /* which sbflags get routed to mips interrupt 2 */
6675 +#define SBIPS_INT2_SHIFT 8
6676 +#define SBIPS_INT3_MASK 0x3f0000 /* which sbflags get routed to mips interrupt 3 */
6677 +#define SBIPS_INT3_SHIFT 16
6678 +#define SBIPS_INT4_MASK 0x3f000000 /* which sbflags get routed to mips interrupt 4 */
6679 +#define SBIPS_INT4_SHIFT 24
6680 +
6681 +/* sbtpsflag */
6682 +#define SBTPS_NUM0_MASK 0x3f /* interrupt sbFlag # generated by this core */
6683 +#define SBTPS_F0EN0 0x40 /* interrupt is always sent on the backplane */
6684 +
6685 +/* sbtmerrlog */
6686 +#define SBTMEL_CM 0x00000007 /* command */
6687 +#define SBTMEL_CI 0x0000ff00 /* connection id */
6688 +#define SBTMEL_EC 0x0f000000 /* error code */
6689 +#define SBTMEL_ME 0x80000000 /* multiple error */
6690 +
6691 +/* sbimstate */
6692 +#define SBIM_PC 0xf /* pipecount */
6693 +#define SBIM_AP_MASK 0x30 /* arbitration policy */
6694 +#define SBIM_AP_BOTH 0x00 /* use both timeslaces and token */
6695 +#define SBIM_AP_TS 0x10 /* use timesliaces only */
6696 +#define SBIM_AP_TK 0x20 /* use token only */
6697 +#define SBIM_AP_RSV 0x30 /* reserved */
6698 +#define SBIM_IBE 0x20000 /* inbanderror */
6699 +#define SBIM_TO 0x40000 /* timeout */
6700 +#define SBIM_BY 0x01800000 /* busy (sonics >= 2.3) */
6701 +#define SBIM_RJ 0x02000000 /* reject (sonics >= 2.3) */
6702 +
6703 +/* sbtmstatelow */
6704 +#define SBTML_RESET 0x1 /* reset */
6705 +#define SBTML_REJ_MASK 0x6 /* reject */
6706 +#define SBTML_REJ_SHIFT 1
6707 +#define SBTML_CLK 0x10000 /* clock enable */
6708 +#define SBTML_FGC 0x20000 /* force gated clocks on */
6709 +#define SBTML_FL_MASK 0x3ffc0000 /* core-specific flags */
6710 +#define SBTML_PE 0x40000000 /* pme enable */
6711 +#define SBTML_BE 0x80000000 /* bist enable */
6712 +
6713 +/* sbtmstatehigh */
6714 +#define SBTMH_SERR 0x1 /* serror */
6715 +#define SBTMH_INT 0x2 /* interrupt */
6716 +#define SBTMH_BUSY 0x4 /* busy */
6717 +#define SBTMH_TO 0x00000020 /* timeout (sonics >= 2.3) */
6718 +#define SBTMH_FL_MASK 0x1fff0000 /* core-specific flags */
6719 +#define SBTMH_DMA64 0x10000000 /* supports DMA with 64-bit addresses */
6720 +#define SBTMH_GCR 0x20000000 /* gated clock request */
6721 +#define SBTMH_BISTF 0x40000000 /* bist failed */
6722 +#define SBTMH_BISTD 0x80000000 /* bist done */
6723 +
6724 +
6725 +/* sbbwa0 */
6726 +#define SBBWA_TAB0_MASK 0xffff /* lookup table 0 */
6727 +#define SBBWA_TAB1_MASK 0xffff /* lookup table 1 */
6728 +#define SBBWA_TAB1_SHIFT 16
6729 +
6730 +/* sbimconfiglow */
6731 +#define SBIMCL_STO_MASK 0x7 /* service timeout */
6732 +#define SBIMCL_RTO_MASK 0x70 /* request timeout */
6733 +#define SBIMCL_RTO_SHIFT 4
6734 +#define SBIMCL_CID_MASK 0xff0000 /* connection id */
6735 +#define SBIMCL_CID_SHIFT 16
6736 +
6737 +/* sbimconfighigh */
6738 +#define SBIMCH_IEM_MASK 0xc /* inband error mode */
6739 +#define SBIMCH_TEM_MASK 0x30 /* timeout error mode */
6740 +#define SBIMCH_TEM_SHIFT 4
6741 +#define SBIMCH_BEM_MASK 0xc0 /* bus error mode */
6742 +#define SBIMCH_BEM_SHIFT 6
6743 +
6744 +/* sbadmatch0 */
6745 +#define SBAM_TYPE_MASK 0x3 /* address type */
6746 +#define SBAM_AD64 0x4 /* reserved */
6747 +#define SBAM_ADINT0_MASK 0xf8 /* type0 size */
6748 +#define SBAM_ADINT0_SHIFT 3
6749 +#define SBAM_ADINT1_MASK 0x1f8 /* type1 size */
6750 +#define SBAM_ADINT1_SHIFT 3
6751 +#define SBAM_ADINT2_MASK 0x1f8 /* type2 size */
6752 +#define SBAM_ADINT2_SHIFT 3
6753 +#define SBAM_ADEN 0x400 /* enable */
6754 +#define SBAM_ADNEG 0x800 /* negative decode */
6755 +#define SBAM_BASE0_MASK 0xffffff00 /* type0 base address */
6756 +#define SBAM_BASE0_SHIFT 8
6757 +#define SBAM_BASE1_MASK 0xfffff000 /* type1 base address for the core */
6758 +#define SBAM_BASE1_SHIFT 12
6759 +#define SBAM_BASE2_MASK 0xffff0000 /* type2 base address for the core */
6760 +#define SBAM_BASE2_SHIFT 16
6761 +
6762 +/* sbtmconfiglow */
6763 +#define SBTMCL_CD_MASK 0xff /* clock divide */
6764 +#define SBTMCL_CO_MASK 0xf800 /* clock offset */
6765 +#define SBTMCL_CO_SHIFT 11
6766 +#define SBTMCL_IF_MASK 0xfc0000 /* interrupt flags */
6767 +#define SBTMCL_IF_SHIFT 18
6768 +#define SBTMCL_IM_MASK 0x3000000 /* interrupt mode */
6769 +#define SBTMCL_IM_SHIFT 24
6770 +
6771 +/* sbtmconfighigh */
6772 +#define SBTMCH_BM_MASK 0x3 /* busy mode */
6773 +#define SBTMCH_RM_MASK 0x3 /* retry mode */
6774 +#define SBTMCH_RM_SHIFT 2
6775 +#define SBTMCH_SM_MASK 0x30 /* stop mode */
6776 +#define SBTMCH_SM_SHIFT 4
6777 +#define SBTMCH_EM_MASK 0x300 /* sb error mode */
6778 +#define SBTMCH_EM_SHIFT 8
6779 +#define SBTMCH_IM_MASK 0xc00 /* int mode */
6780 +#define SBTMCH_IM_SHIFT 10
6781 +
6782 +/* sbbconfig */
6783 +#define SBBC_LAT_MASK 0x3 /* sb latency */
6784 +#define SBBC_MAX0_MASK 0xf0000 /* maxccntr0 */
6785 +#define SBBC_MAX0_SHIFT 16
6786 +#define SBBC_MAX1_MASK 0xf00000 /* maxccntr1 */
6787 +#define SBBC_MAX1_SHIFT 20
6788 +
6789 +/* sbbstate */
6790 +#define SBBS_SRD 0x1 /* st reg disable */
6791 +#define SBBS_HRD 0x2 /* hold reg disable */
6792 +
6793 +/* sbidlow */
6794 +#define SBIDL_CS_MASK 0x3 /* config space */
6795 +#define SBIDL_AR_MASK 0x38 /* # address ranges supported */
6796 +#define SBIDL_AR_SHIFT 3
6797 +#define SBIDL_SYNCH 0x40 /* sync */
6798 +#define SBIDL_INIT 0x80 /* initiator */
6799 +#define SBIDL_MINLAT_MASK 0xf00 /* minimum backplane latency */
6800 +#define SBIDL_MINLAT_SHIFT 8
6801 +#define SBIDL_MAXLAT 0xf000 /* maximum backplane latency */
6802 +#define SBIDL_MAXLAT_SHIFT 12
6803 +#define SBIDL_FIRST 0x10000 /* this initiator is first */
6804 +#define SBIDL_CW_MASK 0xc0000 /* cycle counter width */
6805 +#define SBIDL_CW_SHIFT 18
6806 +#define SBIDL_TP_MASK 0xf00000 /* target ports */
6807 +#define SBIDL_TP_SHIFT 20
6808 +#define SBIDL_IP_MASK 0xf000000 /* initiator ports */
6809 +#define SBIDL_IP_SHIFT 24
6810 +#define SBIDL_RV_MASK 0xf0000000 /* sonics backplane revision code */
6811 +#define SBIDL_RV_SHIFT 28
6812 +#define SBIDL_RV_2_2 0x00000000 /* version 2.2 or earlier */
6813 +#define SBIDL_RV_2_3 0x10000000 /* version 2.3 */
6814 +
6815 +/* sbidhigh */
6816 +#define SBIDH_RC_MASK 0x000f /* revision code */
6817 +#define SBIDH_RCE_MASK 0x7000 /* revision code extension field */
6818 +#define SBIDH_RCE_SHIFT 8
6819 +#define SBCOREREV(sbidh) \
6820 + ((((sbidh) & SBIDH_RCE_MASK) >> SBIDH_RCE_SHIFT) | ((sbidh) & SBIDH_RC_MASK))
6821 +#define SBIDH_CC_MASK 0x8ff0 /* core code */
6822 +#define SBIDH_CC_SHIFT 4
6823 +#define SBIDH_VC_MASK 0xffff0000 /* vendor code */
6824 +#define SBIDH_VC_SHIFT 16
6825 +
6826 +#define SB_COMMIT 0xfd8 /* update buffered registers value */
6827 +
6828 +/* vendor codes */
6829 +#define SB_VEND_BCM 0x4243 /* Broadcom's SB vendor code */
6830 +
6831 +/* core codes */
6832 +#define SB_NODEV 0x700 /* Invalid coreid */
6833 +#define SB_CC 0x800 /* chipcommon core */
6834 +#define SB_ILINE20 0x801 /* iline20 core */
6835 +#define SB_SDRAM 0x803 /* sdram core */
6836 +#define SB_PCI 0x804 /* pci core */
6837 +#define SB_MIPS 0x805 /* mips core */
6838 +#define SB_ENET 0x806 /* enet mac core */
6839 +#define SB_CODEC 0x807 /* v90 codec core */
6840 +#define SB_USB 0x808 /* usb 1.1 host/device core */
6841 +#define SB_ADSL 0x809 /* ADSL core */
6842 +#define SB_ILINE100 0x80a /* iline100 core */
6843 +#define SB_IPSEC 0x80b /* ipsec core */
6844 +#define SB_PCMCIA 0x80d /* pcmcia core */
6845 +#define SB_SDIOD SB_PCMCIA /* pcmcia core has sdio device */
6846 +#define SB_SOCRAM 0x80e /* internal memory core */
6847 +#define SB_MEMC 0x80f /* memc sdram core */
6848 +#define SB_EXTIF 0x811 /* external interface core */
6849 +#define SB_D11 0x812 /* 802.11 MAC core */
6850 +#define SB_MIPS33 0x816 /* mips3302 core */
6851 +#define SB_USB11H 0x817 /* usb 1.1 host core */
6852 +#define SB_USB11D 0x818 /* usb 1.1 device core */
6853 +#define SB_USB20H 0x819 /* usb 2.0 host core */
6854 +#define SB_USB20D 0x81a /* usb 2.0 device core */
6855 +#define SB_SDIOH 0x81b /* sdio host core */
6856 +#define SB_ROBO 0x81c /* roboswitch core */
6857 +#define SB_ATA100 0x81d /* parallel ATA core */
6858 +#define SB_SATAXOR 0x81e /* serial ATA & XOR DMA core */
6859 +#define SB_GIGETH 0x81f /* gigabit ethernet core */
6860 +#define SB_PCIE 0x820 /* pci express core */
6861 +#define SB_MIMO 0x821 /* MIMO phy core */
6862 +#define SB_SRAMC 0x822 /* SRAM controller core */
6863 +#define SB_MINIMAC 0x823 /* MINI MAC/phy core */
6864 +#define SB_ARM11 0x824 /* ARM 1176 core */
6865 +#define SB_ARM7 0x825 /* ARM 7tdmi core */
6866 +
6867 +#define SB_CC_IDX 0 /* chipc, when present, is always core 0 */
6868 +
6869 +/* Not really related to Silicon Backplane, but a couple of software
6870 + * conventions for the use the flash space:
6871 + */
6872 +
6873 +/* Minumum amount of flash we support */
6874 +#define FLASH_MIN 0x00020000 /* Minimum flash size */
6875 +
6876 +/* A boot/binary may have an embedded block that describes its size */
6877 +#define BISZ_OFFSET 0x3e0 /* At this offset into the binary */
6878 +#define BISZ_MAGIC 0x4249535a /* Marked with this value: 'BISZ' */
6879 +#define BISZ_MAGIC_IDX 0 /* Word 0: magic */
6880 +#define BISZ_TXTST_IDX 1 /* 1: text start */
6881 +#define BISZ_TXTEND_IDX 2 /* 2: text start */
6882 +#define BISZ_DATAST_IDX 3 /* 3: text start */
6883 +#define BISZ_DATAEND_IDX 4 /* 4: text start */
6884 +#define BISZ_BSSST_IDX 5 /* 5: text start */
6885 +#define BISZ_BSSEND_IDX 6 /* 6: text start */
6886 +#define BISZ_SIZE 7 /* descriptor size in 32-bit intergers */
6887 +
6888 +#endif /* _SBCONFIG_H */
6889 diff -urN linux.old/arch/mips/bcm947xx/include/sbextif.h linux.dev/arch/mips/bcm947xx/include/sbextif.h
6890 --- linux.old/arch/mips/bcm947xx/include/sbextif.h 1970-01-01 01:00:00.000000000 +0100
6891 +++ linux.dev/arch/mips/bcm947xx/include/sbextif.h 2006-10-02 21:19:59.000000000 +0200
6892 @@ -0,0 +1,243 @@
6893 +/*
6894 + * Hardware-specific External Interface I/O core definitions
6895 + * for the BCM47xx family of SiliconBackplane-based chips.
6896 + *
6897 + * The External Interface core supports a total of three external chip selects
6898 + * supporting external interfaces. One of the external chip selects is
6899 + * used for Flash, one is used for PCMCIA, and the other may be
6900 + * programmed to support either a synchronous interface or an
6901 + * asynchronous interface. The asynchronous interface can be used to
6902 + * support external devices such as UARTs and the BCM2019 Bluetooth
6903 + * baseband processor.
6904 + * The external interface core also contains 2 on-chip 16550 UARTs, clock
6905 + * frequency control, a watchdog interrupt timer, and a GPIO interface.
6906 + *
6907 + * Copyright 2006, Broadcom Corporation
6908 + * All Rights Reserved.
6909 + *
6910 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
6911 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
6912 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
6913 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
6914 + *
6915 + * $Id: sbextif.h,v 1.1.1.8 2006/02/27 03:43:16 honor Exp $
6916 + */
6917 +
6918 +#ifndef _SBEXTIF_H
6919 +#define _SBEXTIF_H
6920 +
6921 +/* external interface address space */
6922 +#define EXTIF_PCMCIA_MEMBASE(x) (x)
6923 +#define EXTIF_PCMCIA_IOBASE(x) ((x) + 0x100000)
6924 +#define EXTIF_PCMCIA_CFGBASE(x) ((x) + 0x200000)
6925 +#define EXTIF_CFGIF_BASE(x) ((x) + 0x800000)
6926 +#define EXTIF_FLASH_BASE(x) ((x) + 0xc00000)
6927 +
6928 +/* cpp contortions to concatenate w/arg prescan */
6929 +#ifndef PAD
6930 +#define _PADLINE(line) pad ## line
6931 +#define _XSTR(line) _PADLINE(line)
6932 +#define PAD _XSTR(__LINE__)
6933 +#endif /* PAD */
6934 +
6935 +/*
6936 + * The multiple instances of output and output enable registers
6937 + * are present to allow driver software for multiple cores to control
6938 + * gpio outputs without needing to share a single register pair.
6939 + */
6940 +struct gpiouser {
6941 + uint32 out;
6942 + uint32 outen;
6943 +};
6944 +#define NGPIOUSER 5
6945 +
6946 +typedef volatile struct {
6947 + uint32 corecontrol;
6948 + uint32 extstatus;
6949 + uint32 PAD[2];
6950 +
6951 + /* pcmcia control registers */
6952 + uint32 pcmcia_config;
6953 + uint32 pcmcia_memwait;
6954 + uint32 pcmcia_attrwait;
6955 + uint32 pcmcia_iowait;
6956 +
6957 + /* programmable interface control registers */
6958 + uint32 prog_config;
6959 + uint32 prog_waitcount;
6960 +
6961 + /* flash control registers */
6962 + uint32 flash_config;
6963 + uint32 flash_waitcount;
6964 + uint32 PAD[4];
6965 +
6966 + uint32 watchdog;
6967 +
6968 + /* clock control */
6969 + uint32 clockcontrol_n;
6970 + uint32 clockcontrol_sb;
6971 + uint32 clockcontrol_pci;
6972 + uint32 clockcontrol_mii;
6973 + uint32 PAD[3];
6974 +
6975 + /* gpio */
6976 + uint32 gpioin;
6977 + struct gpiouser gpio[NGPIOUSER];
6978 + uint32 PAD;
6979 + uint32 ejtagouten;
6980 + uint32 gpiointpolarity;
6981 + uint32 gpiointmask;
6982 + uint32 PAD[153];
6983 +
6984 + uint8 uartdata;
6985 + uint8 PAD[3];
6986 + uint8 uartimer;
6987 + uint8 PAD[3];
6988 + uint8 uartfcr;
6989 + uint8 PAD[3];
6990 + uint8 uartlcr;
6991 + uint8 PAD[3];
6992 + uint8 uartmcr;
6993 + uint8 PAD[3];
6994 + uint8 uartlsr;
6995 + uint8 PAD[3];
6996 + uint8 uartmsr;
6997 + uint8 PAD[3];
6998 + uint8 uartscratch;
6999 + uint8 PAD[3];
7000 +} extifregs_t;
7001 +
7002 +/* corecontrol */
7003 +#define CC_UE (1 << 0) /* uart enable */
7004 +
7005 +/* extstatus */
7006 +#define ES_EM (1 << 0) /* endian mode (ro) */
7007 +#define ES_EI (1 << 1) /* external interrupt pin (ro) */
7008 +#define ES_GI (1 << 2) /* gpio interrupt pin (ro) */
7009 +
7010 +/* gpio bit mask */
7011 +#define GPIO_BIT0 (1 << 0)
7012 +#define GPIO_BIT1 (1 << 1)
7013 +#define GPIO_BIT2 (1 << 2)
7014 +#define GPIO_BIT3 (1 << 3)
7015 +#define GPIO_BIT4 (1 << 4)
7016 +#define GPIO_BIT5 (1 << 5)
7017 +#define GPIO_BIT6 (1 << 6)
7018 +#define GPIO_BIT7 (1 << 7)
7019 +
7020 +
7021 +/* pcmcia/prog/flash_config */
7022 +#define CF_EN (1 << 0) /* enable */
7023 +#define CF_EM_MASK 0xe /* mode */
7024 +#define CF_EM_SHIFT 1
7025 +#define CF_EM_FLASH 0x0 /* flash/asynchronous mode */
7026 +#define CF_EM_SYNC 0x2 /* synchronous mode */
7027 +#define CF_EM_PCMCIA 0x4 /* pcmcia mode */
7028 +#define CF_DS (1 << 4) /* destsize: 0=8bit, 1=16bit */
7029 +#define CF_BS (1 << 5) /* byteswap */
7030 +#define CF_CD_MASK 0xc0 /* clock divider */
7031 +#define CF_CD_SHIFT 6
7032 +#define CF_CD_DIV2 0x0 /* backplane/2 */
7033 +#define CF_CD_DIV3 0x40 /* backplane/3 */
7034 +#define CF_CD_DIV4 0x80 /* backplane/4 */
7035 +#define CF_CE (1 << 8) /* clock enable */
7036 +#define CF_SB (1 << 9) /* size/bytestrobe (synch only) */
7037 +
7038 +/* pcmcia_memwait */
7039 +#define PM_W0_MASK 0x3f /* waitcount0 */
7040 +#define PM_W1_MASK 0x1f00 /* waitcount1 */
7041 +#define PM_W1_SHIFT 8
7042 +#define PM_W2_MASK 0x1f0000 /* waitcount2 */
7043 +#define PM_W2_SHIFT 16
7044 +#define PM_W3_MASK 0x1f000000 /* waitcount3 */
7045 +#define PM_W3_SHIFT 24
7046 +
7047 +/* pcmcia_attrwait */
7048 +#define PA_W0_MASK 0x3f /* waitcount0 */
7049 +#define PA_W1_MASK 0x1f00 /* waitcount1 */
7050 +#define PA_W1_SHIFT 8
7051 +#define PA_W2_MASK 0x1f0000 /* waitcount2 */
7052 +#define PA_W2_SHIFT 16
7053 +#define PA_W3_MASK 0x1f000000 /* waitcount3 */
7054 +#define PA_W3_SHIFT 24
7055 +
7056 +/* pcmcia_iowait */
7057 +#define PI_W0_MASK 0x3f /* waitcount0 */
7058 +#define PI_W1_MASK 0x1f00 /* waitcount1 */
7059 +#define PI_W1_SHIFT 8
7060 +#define PI_W2_MASK 0x1f0000 /* waitcount2 */
7061 +#define PI_W2_SHIFT 16
7062 +#define PI_W3_MASK 0x1f000000 /* waitcount3 */
7063 +#define PI_W3_SHIFT 24
7064 +
7065 +/* prog_waitcount */
7066 +#define PW_W0_MASK 0x0000001f /* waitcount0 */
7067 +#define PW_W1_MASK 0x00001f00 /* waitcount1 */
7068 +#define PW_W1_SHIFT 8
7069 +#define PW_W2_MASK 0x001f0000 /* waitcount2 */
7070 +#define PW_W2_SHIFT 16
7071 +#define PW_W3_MASK 0x1f000000 /* waitcount3 */
7072 +#define PW_W3_SHIFT 24
7073 +
7074 +#define PW_W0 0x0000000c
7075 +#define PW_W1 0x00000a00
7076 +#define PW_W2 0x00020000
7077 +#define PW_W3 0x01000000
7078 +
7079 +/* flash_waitcount */
7080 +#define FW_W0_MASK 0x1f /* waitcount0 */
7081 +#define FW_W1_MASK 0x1f00 /* waitcount1 */
7082 +#define FW_W1_SHIFT 8
7083 +#define FW_W2_MASK 0x1f0000 /* waitcount2 */
7084 +#define FW_W2_SHIFT 16
7085 +#define FW_W3_MASK 0x1f000000 /* waitcount3 */
7086 +#define FW_W3_SHIFT 24
7087 +
7088 +/* watchdog */
7089 +#define WATCHDOG_CLOCK 48000000 /* Hz */
7090 +
7091 +/* clockcontrol_n */
7092 +#define CN_N1_MASK 0x3f /* n1 control */
7093 +#define CN_N2_MASK 0x3f00 /* n2 control */
7094 +#define CN_N2_SHIFT 8
7095 +
7096 +/* clockcontrol_sb/pci/mii */
7097 +#define CC_M1_MASK 0x3f /* m1 control */
7098 +#define CC_M2_MASK 0x3f00 /* m2 control */
7099 +#define CC_M2_SHIFT 8
7100 +#define CC_M3_MASK 0x3f0000 /* m3 control */
7101 +#define CC_M3_SHIFT 16
7102 +#define CC_MC_MASK 0x1f000000 /* mux control */
7103 +#define CC_MC_SHIFT 24
7104 +
7105 +/* Clock control default values */
7106 +#define CC_DEF_N 0x0009 /* Default values for bcm4710 */
7107 +#define CC_DEF_100 0x04020011
7108 +#define CC_DEF_33 0x11030011
7109 +#define CC_DEF_25 0x11050011
7110 +
7111 +/* Clock control values for 125Mhz */
7112 +#define CC_125_N 0x0802
7113 +#define CC_125_M 0x04020009
7114 +#define CC_125_M25 0x11090009
7115 +#define CC_125_M33 0x11090005
7116 +
7117 +/* Clock control magic field values */
7118 +#define CC_F6_2 0x02 /* A factor of 2 in */
7119 +#define CC_F6_3 0x03 /* 6-bit fields like */
7120 +#define CC_F6_4 0x05 /* N1, M1 or M3 */
7121 +#define CC_F6_5 0x09
7122 +#define CC_F6_6 0x11
7123 +#define CC_F6_7 0x21
7124 +
7125 +#define CC_F5_BIAS 5 /* 5-bit fields get this added */
7126 +
7127 +#define CC_MC_BYPASS 0x08
7128 +#define CC_MC_M1 0x04
7129 +#define CC_MC_M1M2 0x02
7130 +#define CC_MC_M1M2M3 0x01
7131 +#define CC_MC_M1M3 0x11
7132 +
7133 +#define CC_CLOCK_BASE 24000000 /* Half the clock freq. in the 4710 */
7134 +
7135 +#endif /* _SBEXTIF_H */
7136 diff -urN linux.old/arch/mips/bcm947xx/include/sbhndmips.h linux.dev/arch/mips/bcm947xx/include/sbhndmips.h
7137 --- linux.old/arch/mips/bcm947xx/include/sbhndmips.h 1970-01-01 01:00:00.000000000 +0100
7138 +++ linux.dev/arch/mips/bcm947xx/include/sbhndmips.h 2006-10-02 21:19:59.000000000 +0200
7139 @@ -0,0 +1,47 @@
7140 +/*
7141 + * Broadcom SiliconBackplane MIPS definitions
7142 + *
7143 + * SB MIPS cores are custom MIPS32 processors with SiliconBackplane
7144 + * OCP interfaces. The CP0 processor ID is 0x00024000, where bits
7145 + * 23:16 mean Broadcom and bits 15:8 mean a MIPS core with an OCP
7146 + * interface. The core revision is stored in the SB ID register in SB
7147 + * configuration space.
7148 + *
7149 + * Copyright 2006, Broadcom Corporation
7150 + * All Rights Reserved.
7151 + *
7152 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7153 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7154 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7155 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7156 + *
7157 + * $Id: sbhndmips.h,v 1.1.1.1 2006/02/27 03:43:16 honor Exp $
7158 + */
7159 +
7160 +#ifndef _sbhndmips_h_
7161 +#define _sbhndmips_h_
7162 +
7163 +#include <mipsinc.h>
7164 +
7165 +#ifndef _LANGUAGE_ASSEMBLY
7166 +
7167 +/* cpp contortions to concatenate w/arg prescan */
7168 +#ifndef PAD
7169 +#define _PADLINE(line) pad ## line
7170 +#define _XSTR(line) _PADLINE(line)
7171 +#define PAD _XSTR(__LINE__)
7172 +#endif /* PAD */
7173 +
7174 +typedef volatile struct {
7175 + uint32 corecontrol;
7176 + uint32 PAD[2];
7177 + uint32 biststatus;
7178 + uint32 PAD[4];
7179 + uint32 intstatus;
7180 + uint32 intmask;
7181 + uint32 timer;
7182 +} mipsregs_t;
7183 +
7184 +#endif /* _LANGUAGE_ASSEMBLY */
7185 +
7186 +#endif /* _sbhndmips_h_ */
7187 diff -urN linux.old/arch/mips/bcm947xx/include/sbmemc.h linux.dev/arch/mips/bcm947xx/include/sbmemc.h
7188 --- linux.old/arch/mips/bcm947xx/include/sbmemc.h 1970-01-01 01:00:00.000000000 +0100
7189 +++ linux.dev/arch/mips/bcm947xx/include/sbmemc.h 2006-10-02 21:19:59.000000000 +0200
7190 @@ -0,0 +1,147 @@
7191 +/*
7192 + * BCM47XX Sonics SiliconBackplane DDR/SDRAM controller core hardware definitions.
7193 + *
7194 + * Copyright 2006, Broadcom Corporation
7195 + * All Rights Reserved.
7196 + *
7197 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7198 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7199 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7200 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7201 + *
7202 + * $Id: sbmemc.h,v 1.6 2006/03/02 12:33:44 honor Exp $
7203 + */
7204 +
7205 +#ifndef _SBMEMC_H
7206 +#define _SBMEMC_H
7207 +
7208 +#ifdef _LANGUAGE_ASSEMBLY
7209 +
7210 +#define MEMC_CONTROL 0x00
7211 +#define MEMC_CONFIG 0x04
7212 +#define MEMC_REFRESH 0x08
7213 +#define MEMC_BISTSTAT 0x0c
7214 +#define MEMC_MODEBUF 0x10
7215 +#define MEMC_BKCLS 0x14
7216 +#define MEMC_PRIORINV 0x18
7217 +#define MEMC_DRAMTIM 0x1c
7218 +#define MEMC_INTSTAT 0x20
7219 +#define MEMC_INTMASK 0x24
7220 +#define MEMC_INTINFO 0x28
7221 +#define MEMC_NCDLCTL 0x30
7222 +#define MEMC_RDNCDLCOR 0x34
7223 +#define MEMC_WRNCDLCOR 0x38
7224 +#define MEMC_MISCDLYCTL 0x3c
7225 +#define MEMC_DQSGATENCDL 0x40
7226 +#define MEMC_SPARE 0x44
7227 +#define MEMC_TPADDR 0x48
7228 +#define MEMC_TPDATA 0x4c
7229 +#define MEMC_BARRIER 0x50
7230 +#define MEMC_CORE 0x54
7231 +
7232 +#else /* !_LANGUAGE_ASSEMBLY */
7233 +
7234 +/* Sonics side: MEMC core registers */
7235 +typedef volatile struct sbmemcregs {
7236 + uint32 control;
7237 + uint32 config;
7238 + uint32 refresh;
7239 + uint32 biststat;
7240 + uint32 modebuf;
7241 + uint32 bkcls;
7242 + uint32 priorinv;
7243 + uint32 dramtim;
7244 + uint32 intstat;
7245 + uint32 intmask;
7246 + uint32 intinfo;
7247 + uint32 reserved1;
7248 + uint32 ncdlctl;
7249 + uint32 rdncdlcor;
7250 + uint32 wrncdlcor;
7251 + uint32 miscdlyctl;
7252 + uint32 dqsgatencdl;
7253 + uint32 spare;
7254 + uint32 tpaddr;
7255 + uint32 tpdata;
7256 + uint32 barrier;
7257 + uint32 core;
7258 +} sbmemcregs_t;
7259 +
7260 +#endif /* _LANGUAGE_ASSEMBLY */
7261 +
7262 +/* MEMC Core Init values (OCP ID 0x80f) */
7263 +
7264 +/* For sdr: */
7265 +#define MEMC_SD_CONFIG_INIT 0x00048000
7266 +#define MEMC_SD_DRAMTIM2_INIT 0x000754d8
7267 +#define MEMC_SD_DRAMTIM3_INIT 0x000754da
7268 +#define MEMC_SD_RDNCDLCOR_INIT 0x00000000
7269 +#define MEMC_SD_WRNCDLCOR_INIT 0x49351200
7270 +#define MEMC_SD1_WRNCDLCOR_INIT 0x14500200 /* For corerev 1 (4712) */
7271 +#define MEMC_SD_MISCDLYCTL_INIT 0x00061c1b
7272 +#define MEMC_SD1_MISCDLYCTL_INIT 0x00021416 /* For corerev 1 (4712) */
7273 +#define MEMC_SD_CONTROL_INIT0 0x00000002
7274 +#define MEMC_SD_CONTROL_INIT1 0x00000008
7275 +#define MEMC_SD_CONTROL_INIT2 0x00000004
7276 +#define MEMC_SD_CONTROL_INIT3 0x00000010
7277 +#define MEMC_SD_CONTROL_INIT4 0x00000001
7278 +#define MEMC_SD_MODEBUF_INIT 0x00000000
7279 +#define MEMC_SD_REFRESH_INIT 0x0000840f
7280 +
7281 +
7282 +/* This is for SDRM8X8X4 */
7283 +#define MEMC_SDR_INIT 0x0008
7284 +#define MEMC_SDR_MODE 0x32
7285 +#define MEMC_SDR_NCDL 0x00020032
7286 +#define MEMC_SDR1_NCDL 0x0002020f /* For corerev 1 (4712) */
7287 +
7288 +/* For ddr: */
7289 +#define MEMC_CONFIG_INIT 0x00048000
7290 +#define MEMC_DRAMTIM2_INIT 0x000754d8
7291 +#define MEMC_DRAMTIM25_INIT 0x000754d9
7292 +#define MEMC_RDNCDLCOR_INIT 0x00000000
7293 +#define MEMC_RDNCDLCOR_SIMINIT 0xf6f6f6f6 /* For hdl sim */
7294 +#define MEMC_WRNCDLCOR_INIT 0x49351200
7295 +#define MEMC_1_WRNCDLCOR_INIT 0x14500200
7296 +#define MEMC_DQSGATENCDL_INIT 0x00030000
7297 +#define MEMC_MISCDLYCTL_INIT 0x21061c1b
7298 +#define MEMC_1_MISCDLYCTL_INIT 0x21021400
7299 +#define MEMC_NCDLCTL_INIT 0x00002001
7300 +#define MEMC_CONTROL_INIT0 0x00000002
7301 +#define MEMC_CONTROL_INIT1 0x00000008
7302 +#define MEMC_MODEBUF_INIT0 0x00004000
7303 +#define MEMC_CONTROL_INIT2 0x00000010
7304 +#define MEMC_MODEBUF_INIT1 0x00000100
7305 +#define MEMC_CONTROL_INIT3 0x00000010
7306 +#define MEMC_CONTROL_INIT4 0x00000008
7307 +#define MEMC_REFRESH_INIT 0x0000840f
7308 +#define MEMC_CONTROL_INIT5 0x00000004
7309 +#define MEMC_MODEBUF_INIT2 0x00000000
7310 +#define MEMC_CONTROL_INIT6 0x00000010
7311 +#define MEMC_CONTROL_INIT7 0x00000001
7312 +
7313 +
7314 +/* This is for DDRM16X16X2 */
7315 +#define MEMC_DDR_INIT 0x0009
7316 +#define MEMC_DDR_MODE 0x62
7317 +#define MEMC_DDR_NCDL 0x0005050a
7318 +#define MEMC_DDR1_NCDL 0x00000a0a /* For corerev 1 (4712) */
7319 +
7320 +/* mask for sdr/ddr calibration registers */
7321 +#define MEMC_RDNCDLCOR_RD_MASK 0x000000ff
7322 +#define MEMC_WRNCDLCOR_WR_MASK 0x000000ff
7323 +#define MEMC_DQSGATENCDL_G_MASK 0x000000ff
7324 +
7325 +/* masks for miscdlyctl registers */
7326 +#define MEMC_MISC_SM_MASK 0x30000000
7327 +#define MEMC_MISC_SM_SHIFT 28
7328 +#define MEMC_MISC_SD_MASK 0x0f000000
7329 +#define MEMC_MISC_SD_SHIFT 24
7330 +
7331 +/* hw threshhold for calculating wr/rd for sdr memc */
7332 +#define MEMC_CD_THRESHOLD 128
7333 +
7334 +/* Low bit of init register says if memc is ddr or sdr */
7335 +#define MEMC_CONFIG_DDR 0x00000001
7336 +
7337 +#endif /* _SBMEMC_H */
7338 diff -urN linux.old/arch/mips/bcm947xx/include/sbpcie.h linux.dev/arch/mips/bcm947xx/include/sbpcie.h
7339 --- linux.old/arch/mips/bcm947xx/include/sbpcie.h 1970-01-01 01:00:00.000000000 +0100
7340 +++ linux.dev/arch/mips/bcm947xx/include/sbpcie.h 2006-10-02 21:19:59.000000000 +0200
7341 @@ -0,0 +1,200 @@
7342 +/*
7343 + * BCM43XX SiliconBackplane PCIE core hardware definitions.
7344 + *
7345 + * Copyright 2006, Broadcom Corporation
7346 + * All Rights Reserved.
7347 + *
7348 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7349 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7350 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7351 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7352 + *
7353 + * $Id: sbpcie.h,v 1.1.1.2 2006/02/27 03:43:16 honor Exp $
7354 + */
7355 +
7356 +#ifndef _SBPCIE_H
7357 +#define _SBPCIE_H
7358 +
7359 +/* cpp contortions to concatenate w/arg prescan */
7360 +#ifndef PAD
7361 +#define _PADLINE(line) pad ## line
7362 +#define _XSTR(line) _PADLINE(line)
7363 +#define PAD _XSTR(__LINE__)
7364 +#endif
7365 +
7366 +/* PCIE Enumeration space offsets */
7367 +#define PCIE_CORE_CONFIG_OFFSET 0x0
7368 +#define PCIE_FUNC0_CONFIG_OFFSET 0x400
7369 +#define PCIE_FUNC1_CONFIG_OFFSET 0x500
7370 +#define PCIE_FUNC2_CONFIG_OFFSET 0x600
7371 +#define PCIE_FUNC3_CONFIG_OFFSET 0x700
7372 +#define PCIE_SPROM_SHADOW_OFFSET 0x800
7373 +#define PCIE_SBCONFIG_OFFSET 0xE00
7374 +
7375 +/* PCIE Bar0 Address Mapping. Each function maps 16KB config space */
7376 +#define PCIE_DEV_BAR0_SIZE 0x4000
7377 +#define PCIE_BAR0_WINMAPCORE_OFFSET 0x0
7378 +#define PCIE_BAR0_EXTSPROM_OFFSET 0x1000
7379 +#define PCIE_BAR0_PCIECORE_OFFSET 0x2000
7380 +#define PCIE_BAR0_CCCOREREG_OFFSET 0x3000
7381 +
7382 +/* SB side: PCIE core and host control registers */
7383 +typedef struct sbpcieregs {
7384 + uint32 PAD[3];
7385 + uint32 biststatus; /* bist Status: 0x00C */
7386 + uint32 PAD[6];
7387 + uint32 sbtopcimailbox; /* sb to pcie mailbox: 0x028 */
7388 + uint32 PAD[54];
7389 + uint32 sbtopcie0; /* sb to pcie translation 0: 0x100 */
7390 + uint32 sbtopcie1; /* sb to pcie translation 1: 0x104 */
7391 + uint32 sbtopcie2; /* sb to pcie translation 2: 0x108 */
7392 + uint32 PAD[4];
7393 +
7394 + /* pcie core supports in direct access to config space */
7395 + uint32 configaddr; /* pcie config space access: Address field: 0x120 */
7396 + uint32 configdata; /* pcie config space access: Data field: 0x124 */
7397 +
7398 + /* mdio access to serdes */
7399 + uint32 mdiocontrol; /* controls the mdio access: 0x128 */
7400 + uint32 mdiodata; /* Data to the mdio access: 0x12c */
7401 +
7402 + /* pcie protocol phy/dllp/tlp register access mechanism */
7403 + uint32 pcieaddr; /* address of the internal registeru: 0x130 */
7404 + uint32 pciedata; /* Data to/from the internal regsiter: 0x134 */
7405 +
7406 + uint32 PAD[434];
7407 + uint16 sprom[36]; /* SPROM shadow Area */
7408 +} sbpcieregs_t;
7409 +
7410 +/* SB to PCIE translation masks */
7411 +#define SBTOPCIE0_MASK 0xfc000000
7412 +#define SBTOPCIE1_MASK 0xfc000000
7413 +#define SBTOPCIE2_MASK 0xc0000000
7414 +
7415 +/* Access type bits (0:1) */
7416 +#define SBTOPCIE_MEM 0
7417 +#define SBTOPCIE_IO 1
7418 +#define SBTOPCIE_CFG0 2
7419 +#define SBTOPCIE_CFG1 3
7420 +
7421 +/* Prefetch enable bit 2 */
7422 +#define SBTOPCIE_PF 4
7423 +
7424 +/* Write Burst enable for memory write bit 3 */
7425 +#define SBTOPCIE_WR_BURST 8
7426 +
7427 +/* config access */
7428 +#define CONFIGADDR_FUNC_MASK 0x7000
7429 +#define CONFIGADDR_FUNC_SHF 12
7430 +#define CONFIGADDR_REG_MASK 0x0FFF
7431 +#define CONFIGADDR_REG_SHF 0
7432 +
7433 +/* PCIE protocol regs Indirect Address */
7434 +#define PCIEADDR_PROT_MASK 0x300
7435 +#define PCIEADDR_PROT_SHF 8
7436 +#define PCIEADDR_PL_TLP 0
7437 +#define PCIEADDR_PL_DLLP 1
7438 +#define PCIEADDR_PL_PLP 2
7439 +
7440 +/* PCIE protocol PHY diagnostic registers */
7441 +#define PCIE_PLP_MODEREG 0x200 /* Mode */
7442 +#define PCIE_PLP_STATUSREG 0x204 /* Status */
7443 +#define PCIE_PLP_LTSSMCTRLREG 0x208 /* LTSSM control */
7444 +#define PCIE_PLP_LTLINKNUMREG 0x20c /* Link Training Link number */
7445 +#define PCIE_PLP_LTLANENUMREG 0x210 /* Link Training Lane number */
7446 +#define PCIE_PLP_LTNFTSREG 0x214 /* Link Training N_FTS */
7447 +#define PCIE_PLP_ATTNREG 0x218 /* Attention */
7448 +#define PCIE_PLP_ATTNMASKREG 0x21C /* Attention Mask */
7449 +#define PCIE_PLP_RXERRCTR 0x220 /* Rx Error */
7450 +#define PCIE_PLP_RXFRMERRCTR 0x224 /* Rx Framing Error */
7451 +#define PCIE_PLP_RXERRTHRESHREG 0x228 /* Rx Error threshold */
7452 +#define PCIE_PLP_TESTCTRLREG 0x22C /* Test Control reg */
7453 +#define PCIE_PLP_SERDESCTRLOVRDREG 0x230 /* SERDES Control Override */
7454 +#define PCIE_PLP_TIMINGOVRDREG 0x234 /* Timing param override */
7455 +#define PCIE_PLP_RXTXSMDIAGREG 0x238 /* RXTX State Machine Diag */
7456 +#define PCIE_PLP_LTSSMDIAGREG 0x23C /* LTSSM State Machine Diag */
7457 +
7458 +/* PCIE protocol DLLP diagnostic registers */
7459 +#define PCIE_DLLP_LCREG 0x100 /* Link Control */
7460 +#define PCIE_DLLP_LSREG 0x104 /* Link Status */
7461 +#define PCIE_DLLP_LAREG 0x108 /* Link Attention */
7462 +#define PCIE_DLLP_LAMASKREG 0x10C /* Link Attention Mask */
7463 +#define PCIE_DLLP_NEXTTXSEQNUMREG 0x110 /* Next Tx Seq Num */
7464 +#define PCIE_DLLP_ACKEDTXSEQNUMREG 0x114 /* Acked Tx Seq Num */
7465 +#define PCIE_DLLP_PURGEDTXSEQNUMREG 0x118 /* Purged Tx Seq Num */
7466 +#define PCIE_DLLP_RXSEQNUMREG 0x11C /* Rx Sequence Number */
7467 +#define PCIE_DLLP_LRREG 0x120 /* Link Replay */
7468 +#define PCIE_DLLP_LACKTOREG 0x124 /* Link Ack Timeout */
7469 +#define PCIE_DLLP_PMTHRESHREG 0x128 /* Power Management Threshold */
7470 +#define PCIE_DLLP_RTRYWPREG 0x12C /* Retry buffer write ptr */
7471 +#define PCIE_DLLP_RTRYRPREG 0x130 /* Retry buffer Read ptr */
7472 +#define PCIE_DLLP_RTRYPPREG 0x134 /* Retry buffer Purged ptr */
7473 +#define PCIE_DLLP_RTRRWREG 0x138 /* Retry buffer Read/Write */
7474 +#define PCIE_DLLP_ECTHRESHREG 0x13C /* Error Count Threshold */
7475 +#define PCIE_DLLP_TLPERRCTRREG 0x140 /* TLP Error Counter */
7476 +#define PCIE_DLLP_ERRCTRREG 0x144 /* Error Counter */
7477 +#define PCIE_DLLP_NAKRXCTRREG 0x148 /* NAK Received Counter */
7478 +#define PCIE_DLLP_TESTREG 0x14C /* Test */
7479 +#define PCIE_DLLP_PKTBIST 0x150 /* Packet BIST */
7480 +
7481 +/* PCIE protocol TLP diagnostic registers */
7482 +#define PCIE_TLP_CONFIGREG 0x000 /* Configuration */
7483 +#define PCIE_TLP_WORKAROUNDSREG 0x004 /* TLP Workarounds */
7484 +#define PCIE_TLP_WRDMAUPPER 0x010 /* Write DMA Upper Address */
7485 +#define PCIE_TLP_WRDMALOWER 0x014 /* Write DMA Lower Address */
7486 +#define PCIE_TLP_WRDMAREQ_LBEREG 0x018 /* Write DMA Len/ByteEn Req */
7487 +#define PCIE_TLP_RDDMAUPPER 0x01C /* Read DMA Upper Address */
7488 +#define PCIE_TLP_RDDMALOWER 0x020 /* Read DMA Lower Address */
7489 +#define PCIE_TLP_RDDMALENREG 0x024 /* Read DMA Len Req */
7490 +#define PCIE_TLP_MSIDMAUPPER 0x028 /* MSI DMA Upper Address */
7491 +#define PCIE_TLP_MSIDMALOWER 0x02C /* MSI DMA Lower Address */
7492 +#define PCIE_TLP_MSIDMALENREG 0x030 /* MSI DMA Len Req */
7493 +#define PCIE_TLP_SLVREQLENREG 0x034 /* Slave Request Len */
7494 +#define PCIE_TLP_FCINPUTSREQ 0x038 /* Flow Control Inputs */
7495 +#define PCIE_TLP_TXSMGRSREQ 0x03C /* Tx StateMachine and Gated Req */
7496 +#define PCIE_TLP_ADRACKCNTARBLEN 0x040 /* Address Ack XferCnt and ARB Len */
7497 +#define PCIE_TLP_DMACPLHDR0 0x044 /* DMA Completion Hdr 0 */
7498 +#define PCIE_TLP_DMACPLHDR1 0x048 /* DMA Completion Hdr 1 */
7499 +#define PCIE_TLP_DMACPLHDR2 0x04C /* DMA Completion Hdr 2 */
7500 +#define PCIE_TLP_DMACPLMISC0 0x050 /* DMA Completion Misc0 */
7501 +#define PCIE_TLP_DMACPLMISC1 0x054 /* DMA Completion Misc1 */
7502 +#define PCIE_TLP_DMACPLMISC2 0x058 /* DMA Completion Misc2 */
7503 +#define PCIE_TLP_SPTCTRLLEN 0x05C /* Split Controller Req len */
7504 +#define PCIE_TLP_SPTCTRLMSIC0 0x060 /* Split Controller Misc 0 */
7505 +#define PCIE_TLP_SPTCTRLMSIC1 0x064 /* Split Controller Misc 1 */
7506 +#define PCIE_TLP_BUSDEVFUNC 0x068 /* Bus/Device/Func */
7507 +#define PCIE_TLP_RESETCTR 0x06C /* Reset Counter */
7508 +#define PCIE_TLP_RTRYBUF 0x070 /* Retry Buffer value */
7509 +#define PCIE_TLP_TGTDEBUG1 0x074 /* Target Debug Reg1 */
7510 +#define PCIE_TLP_TGTDEBUG2 0x078 /* Target Debug Reg2 */
7511 +#define PCIE_TLP_TGTDEBUG3 0x07C /* Target Debug Reg3 */
7512 +#define PCIE_TLP_TGTDEBUG4 0x080 /* Target Debug Reg4 */
7513 +
7514 +/* MDIO control */
7515 +#define MDIOCTL_DIVISOR_MASK 0x7f /* clock to be used on MDIO */
7516 +#define MDIOCTL_DIVISOR_VAL 0x2
7517 +#define MDIOCTL_PREAM_EN 0x80 /* Enable preamble sequnce */
7518 +#define MDIOCTL_ACCESS_DONE 0x100 /* Tranaction complete */
7519 +
7520 +/* MDIO Data */
7521 +#define MDIODATA_MASK 0x0000ffff /* data 2 bytes */
7522 +#define MDIODATA_TA 0x00020000 /* Turnaround */
7523 +#define MDIODATA_REGADDR_SHF 18 /* Regaddr shift */
7524 +#define MDIODATA_REGADDR_MASK 0x003c0000 /* Regaddr Mask */
7525 +#define MDIODATA_DEVADDR_SHF 22 /* Physmedia devaddr shift */
7526 +#define MDIODATA_DEVADDR_MASK 0x0fc00000 /* Physmedia devaddr Mask */
7527 +#define MDIODATA_WRITE 0x10000000 /* write Transaction */
7528 +#define MDIODATA_READ 0x20000000 /* Read Transaction */
7529 +#define MDIODATA_START 0x40000000 /* start of Transaction */
7530 +
7531 +/* MDIO devices (SERDES modules) */
7532 +#define MDIODATA_DEV_PLL 0x1d /* SERDES PLL Dev */
7533 +#define MDIODATA_DEV_TX 0x1e /* SERDES TX Dev */
7534 +#define MDIODATA_DEV_RX 0x1f /* SERDES RX Dev */
7535 +
7536 +/* SERDES registers */
7537 +#define SERDES_RX_TIMER1 2 /* Rx Timer1 */
7538 +#define SERDES_RX_CDR 6 /* CDR */
7539 +#define SERDES_RX_CDRBW 7 /* CDR BW */
7540 +
7541 +#endif /* _SBPCIE_H */
7542 diff -urN linux.old/arch/mips/bcm947xx/include/sbpci.h linux.dev/arch/mips/bcm947xx/include/sbpci.h
7543 --- linux.old/arch/mips/bcm947xx/include/sbpci.h 1970-01-01 01:00:00.000000000 +0100
7544 +++ linux.dev/arch/mips/bcm947xx/include/sbpci.h 2006-10-02 21:19:59.000000000 +0200
7545 @@ -0,0 +1,114 @@
7546 +/*
7547 + * HND SiliconBackplane PCI core hardware definitions.
7548 + *
7549 + * Copyright 2006, Broadcom Corporation
7550 + * All Rights Reserved.
7551 + *
7552 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7553 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7554 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7555 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7556 + *
7557 + * $Id: sbpci.h,v 1.1.1.11 2006/02/27 03:43:16 honor Exp $
7558 + */
7559 +
7560 +#ifndef _sbpci_h_
7561 +#define _sbpci_h_
7562 +
7563 +#ifndef _LANGUAGE_ASSEMBLY
7564 +
7565 +/* cpp contortions to concatenate w/arg prescan */
7566 +#ifndef PAD
7567 +#define _PADLINE(line) pad ## line
7568 +#define _XSTR(line) _PADLINE(line)
7569 +#define PAD _XSTR(__LINE__)
7570 +#endif
7571 +
7572 +/* Sonics side: PCI core and host control registers */
7573 +typedef struct sbpciregs {
7574 + uint32 control; /* PCI control */
7575 + uint32 PAD[3];
7576 + uint32 arbcontrol; /* PCI arbiter control */
7577 + uint32 PAD[3];
7578 + uint32 intstatus; /* Interrupt status */
7579 + uint32 intmask; /* Interrupt mask */
7580 + uint32 sbtopcimailbox; /* Sonics to PCI mailbox */
7581 + uint32 PAD[9];
7582 + uint32 bcastaddr; /* Sonics broadcast address */
7583 + uint32 bcastdata; /* Sonics broadcast data */
7584 + uint32 PAD[2];
7585 + uint32 gpioin; /* ro: gpio input (>=rev2) */
7586 + uint32 gpioout; /* rw: gpio output (>=rev2) */
7587 + uint32 gpioouten; /* rw: gpio output enable (>= rev2) */
7588 + uint32 gpiocontrol; /* rw: gpio control (>= rev2) */
7589 + uint32 PAD[36];
7590 + uint32 sbtopci0; /* Sonics to PCI translation 0 */
7591 + uint32 sbtopci1; /* Sonics to PCI translation 1 */
7592 + uint32 sbtopci2; /* Sonics to PCI translation 2 */
7593 + uint32 PAD[189];
7594 + uint32 pcicfg[4][64]; /* 0x400 - 0x7FF, PCI Cfg Space (>=rev8) */
7595 + uint16 sprom[36]; /* SPROM shadow Area */
7596 + uint32 PAD[46];
7597 +} sbpciregs_t;
7598 +
7599 +#endif /* _LANGUAGE_ASSEMBLY */
7600 +
7601 +/* PCI control */
7602 +#define PCI_RST_OE 0x01 /* When set, drives PCI_RESET out to pin */
7603 +#define PCI_RST 0x02 /* Value driven out to pin */
7604 +#define PCI_CLK_OE 0x04 /* When set, drives clock as gated by PCI_CLK out to pin */
7605 +#define PCI_CLK 0x08 /* Gate for clock driven out to pin */
7606 +
7607 +/* PCI arbiter control */
7608 +#define PCI_INT_ARB 0x01 /* When set, use an internal arbiter */
7609 +#define PCI_EXT_ARB 0x02 /* When set, use an external arbiter */
7610 +/* ParkID - for PCI corerev >= 8 */
7611 +#define PCI_PARKID_MASK 0x1c /* Selects which agent is parked on an idle bus */
7612 +#define PCI_PARKID_SHIFT 2
7613 +#define PCI_PARKID_EXT0 0 /* External master 0 */
7614 +#define PCI_PARKID_EXT1 1 /* External master 1 */
7615 +#define PCI_PARKID_EXT2 2 /* External master 2 */
7616 +#define PCI_PARKID_INT 3 /* Internal master */
7617 +#define PCI_PARKID_LAST 4 /* Last active master */
7618 +
7619 +/* Interrupt status/mask */
7620 +#define PCI_INTA 0x01 /* PCI INTA# is asserted */
7621 +#define PCI_INTB 0x02 /* PCI INTB# is asserted */
7622 +#define PCI_SERR 0x04 /* PCI SERR# has been asserted (write one to clear) */
7623 +#define PCI_PERR 0x08 /* PCI PERR# has been asserted (write one to clear) */
7624 +#define PCI_PME 0x10 /* PCI PME# is asserted */
7625 +
7626 +/* (General) PCI/SB mailbox interrupts, two bits per pci function */
7627 +#define MAILBOX_F0_0 0x100 /* function 0, int 0 */
7628 +#define MAILBOX_F0_1 0x200 /* function 0, int 1 */
7629 +#define MAILBOX_F1_0 0x400 /* function 1, int 0 */
7630 +#define MAILBOX_F1_1 0x800 /* function 1, int 1 */
7631 +#define MAILBOX_F2_0 0x1000 /* function 2, int 0 */
7632 +#define MAILBOX_F2_1 0x2000 /* function 2, int 1 */
7633 +#define MAILBOX_F3_0 0x4000 /* function 3, int 0 */
7634 +#define MAILBOX_F3_1 0x8000 /* function 3, int 1 */
7635 +
7636 +/* Sonics broadcast address */
7637 +#define BCAST_ADDR_MASK 0xff /* Broadcast register address */
7638 +
7639 +/* Sonics to PCI translation types */
7640 +#define SBTOPCI0_MASK 0xfc000000
7641 +#define SBTOPCI1_MASK 0xfc000000
7642 +#define SBTOPCI2_MASK 0xc0000000
7643 +#define SBTOPCI_MEM 0
7644 +#define SBTOPCI_IO 1
7645 +#define SBTOPCI_CFG0 2
7646 +#define SBTOPCI_CFG1 3
7647 +#define SBTOPCI_PREF 0x4 /* prefetch enable */
7648 +#define SBTOPCI_BURST 0x8 /* burst enable */
7649 +#define SBTOPCI_RC_MASK 0x30 /* read command (>= rev11) */
7650 +#define SBTOPCI_RC_READ 0x00 /* memory read */
7651 +#define SBTOPCI_RC_READLINE 0x10 /* memory read line */
7652 +#define SBTOPCI_RC_READMULTI 0x20 /* memory read multiple */
7653 +
7654 +/* PCI core index in SROM shadow area */
7655 +#define SRSH_PI_OFFSET 0 /* first word */
7656 +#define SRSH_PI_MASK 0xf000 /* bit 15:12 */
7657 +#define SRSH_PI_SHIFT 12 /* bit 15:12 */
7658 +
7659 +#endif /* _sbpci_h_ */
7660 diff -urN linux.old/arch/mips/bcm947xx/include/sbpcmcia.h linux.dev/arch/mips/bcm947xx/include/sbpcmcia.h
7661 --- linux.old/arch/mips/bcm947xx/include/sbpcmcia.h 1970-01-01 01:00:00.000000000 +0100
7662 +++ linux.dev/arch/mips/bcm947xx/include/sbpcmcia.h 2006-10-02 21:19:59.000000000 +0200
7663 @@ -0,0 +1,147 @@
7664 +/*
7665 + * BCM43XX Sonics SiliconBackplane PCMCIA core hardware definitions.
7666 + *
7667 + * Copyright 2006, Broadcom Corporation
7668 + * All Rights Reserved.
7669 + *
7670 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7671 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7672 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7673 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7674 + *
7675 + * $Id: sbpcmcia.h,v 1.1.1.9 2006/02/27 03:43:16 honor Exp $
7676 + */
7677 +
7678 +#ifndef _SBPCMCIA_H
7679 +#define _SBPCMCIA_H
7680 +
7681 +
7682 +/* All the addresses that are offsets in attribute space are divided
7683 + * by two to account for the fact that odd bytes are invalid in
7684 + * attribute space and our read/write routines make the space appear
7685 + * as if they didn't exist. Still we want to show the original numbers
7686 + * as documented in the hnd_pcmcia core manual.
7687 + */
7688 +
7689 +/* PCMCIA Function Configuration Registers */
7690 +#define PCMCIA_FCR (0x700 / 2)
7691 +
7692 +#define FCR0_OFF 0
7693 +#define FCR1_OFF (0x40 / 2)
7694 +#define FCR2_OFF (0x80 / 2)
7695 +#define FCR3_OFF (0xc0 / 2)
7696 +
7697 +#define PCMCIA_FCR0 (0x700 / 2)
7698 +#define PCMCIA_FCR1 (0x740 / 2)
7699 +#define PCMCIA_FCR2 (0x780 / 2)
7700 +#define PCMCIA_FCR3 (0x7c0 / 2)
7701 +
7702 +/* Standard PCMCIA FCR registers */
7703 +
7704 +#define PCMCIA_COR 0
7705 +
7706 +#define COR_RST 0x80
7707 +#define COR_LEV 0x40
7708 +#define COR_IRQEN 0x04
7709 +#define COR_BLREN 0x01
7710 +#define COR_FUNEN 0x01
7711 +
7712 +
7713 +#define PCICIA_FCSR (2 / 2)
7714 +#define PCICIA_PRR (4 / 2)
7715 +#define PCICIA_SCR (6 / 2)
7716 +#define PCICIA_ESR (8 / 2)
7717 +
7718 +
7719 +#define PCM_MEMOFF 0x0000
7720 +#define F0_MEMOFF 0x1000
7721 +#define F1_MEMOFF 0x2000
7722 +#define F2_MEMOFF 0x3000
7723 +#define F3_MEMOFF 0x4000
7724 +
7725 +/* Memory base in the function fcr's */
7726 +#define MEM_ADDR0 (0x728 / 2)
7727 +#define MEM_ADDR1 (0x72a / 2)
7728 +#define MEM_ADDR2 (0x72c / 2)
7729 +
7730 +/* PCMCIA base plus Srom access in fcr0: */
7731 +#define PCMCIA_ADDR0 (0x072e / 2)
7732 +#define PCMCIA_ADDR1 (0x0730 / 2)
7733 +#define PCMCIA_ADDR2 (0x0732 / 2)
7734 +
7735 +#define MEM_SEG (0x0734 / 2)
7736 +#define SROM_CS (0x0736 / 2)
7737 +#define SROM_DATAL (0x0738 / 2)
7738 +#define SROM_DATAH (0x073a / 2)
7739 +#define SROM_ADDRL (0x073c / 2)
7740 +#define SROM_ADDRH (0x073e / 2)
7741 +
7742 +/* Values for srom_cs: */
7743 +#define SROM_IDLE 0
7744 +#define SROM_WRITE 1
7745 +#define SROM_READ 2
7746 +#define SROM_WEN 4
7747 +#define SROM_WDS 7
7748 +#define SROM_DONE 8
7749 +
7750 +/* CIS stuff */
7751 +
7752 +/* The CIS stops where the FCRs start */
7753 +#define CIS_SIZE PCMCIA_FCR
7754 +
7755 +/* Standard tuples we know about */
7756 +
7757 +#define CISTPL_MANFID 0x20 /* Manufacturer and device id */
7758 +#define CISTPL_FUNCE 0x22 /* Function extensions */
7759 +#define CISTPL_CFTABLE 0x1b /* Config table entry */
7760 +
7761 +/* Function extensions for LANs */
7762 +
7763 +#define LAN_TECH 1 /* Technology type */
7764 +#define LAN_SPEED 2 /* Raw bit rate */
7765 +#define LAN_MEDIA 3 /* Transmission media */
7766 +#define LAN_NID 4 /* Node identification (aka MAC addr) */
7767 +#define LAN_CONN 5 /* Connector standard */
7768 +
7769 +
7770 +/* CFTable */
7771 +#define CFTABLE_REGWIN_2K 0x08 /* 2k reg windows size */
7772 +#define CFTABLE_REGWIN_4K 0x10 /* 4k reg windows size */
7773 +#define CFTABLE_REGWIN_8K 0x20 /* 8k reg windows size */
7774 +
7775 +/* Vendor unique tuples are 0x80-0x8f. Within Broadcom we'll
7776 + * take one for HNBU, and use "extensions" (a la FUNCE) within it.
7777 + */
7778 +
7779 +#define CISTPL_BRCM_HNBU 0x80
7780 +
7781 +/* Subtypes of BRCM_HNBU: */
7782 +
7783 +#define HNBU_SROMREV 0x00 /* A byte with sromrev, 1 if not present */
7784 +#define HNBU_CHIPID 0x01 /* Two 16bit values: PCI vendor & device id */
7785 +#define HNBU_BOARDREV 0x02 /* One byte board revision */
7786 +#define HNBU_PAPARMS 0x03 /* PA parameters: 8 (sromrev == 1)
7787 + * or 9 (sromrev > 1) bytes
7788 + */
7789 +#define HNBU_OEM 0x04 /* Eight bytes OEM data (sromrev == 1) */
7790 +#define HNBU_CC 0x05 /* Default country code (sromrev == 1) */
7791 +#define HNBU_AA 0x06 /* Antennas available */
7792 +#define HNBU_AG 0x07 /* Antenna gain */
7793 +#define HNBU_BOARDFLAGS 0x08 /* board flags (2 or 4 bytes) */
7794 +#define HNBU_LEDS 0x09 /* LED set */
7795 +#define HNBU_CCODE 0x0a /* Country code (2 bytes ascii + 1 byte cctl)
7796 + * in rev 2
7797 + */
7798 +#define HNBU_CCKPO 0x0b /* 2 byte cck power offsets in rev 3 */
7799 +#define HNBU_OFDMPO 0x0c /* 4 byte 11g ofdm power offsets in rev 3 */
7800 +#define HNBU_GPIOTIMER 0x0d /* 2 bytes with on/off values in rev 3 */
7801 +
7802 +
7803 +/* sbtmstatelow */
7804 +#define SBTML_INT_ACK 0x40000 /* ack the sb interrupt */
7805 +#define SBTML_INT_EN 0x20000 /* enable sb interrupt */
7806 +
7807 +/* sbtmstatehigh */
7808 +#define SBTMH_INT_STATUS 0x40000 /* sb interrupt status */
7809 +
7810 +#endif /* _SBPCMCIA_H */
7811 diff -urN linux.old/arch/mips/bcm947xx/include/sbsdram.h linux.dev/arch/mips/bcm947xx/include/sbsdram.h
7812 --- linux.old/arch/mips/bcm947xx/include/sbsdram.h 1970-01-01 01:00:00.000000000 +0100
7813 +++ linux.dev/arch/mips/bcm947xx/include/sbsdram.h 2006-10-02 21:19:59.000000000 +0200
7814 @@ -0,0 +1,85 @@
7815 +/*
7816 + * BCM47XX Sonics SiliconBackplane SDRAM controller core hardware definitions.
7817 + *
7818 + * Copyright 2006, Broadcom Corporation
7819 + * All Rights Reserved.
7820 + *
7821 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7822 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7823 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7824 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7825 + *
7826 + * $Id: sbsdram.h,v 1.1.1.9 2006/03/02 13:03:52 honor Exp $
7827 + */
7828 +
7829 +#ifndef _SBSDRAM_H
7830 +#define _SBSDRAM_H
7831 +
7832 +#ifndef _LANGUAGE_ASSEMBLY
7833 +
7834 +/* Sonics side: SDRAM core registers */
7835 +typedef volatile struct sbsdramregs {
7836 + uint32 initcontrol; /* Generates external SDRAM initialization sequence */
7837 + uint32 config; /* Initializes external SDRAM mode register */
7838 + uint32 refresh; /* Controls external SDRAM refresh rate */
7839 + uint32 pad1;
7840 + uint32 pad2;
7841 +} sbsdramregs_t;
7842 +
7843 +/* SDRAM simulation */
7844 +#ifdef RAMSZ
7845 +#define SDRAMSZ RAMSZ
7846 +#else
7847 +#define SDRAMSZ (4 * 1024 * 1024)
7848 +#endif
7849 +
7850 +extern uchar sdrambuf[SDRAMSZ];
7851 +
7852 +#endif /* _LANGUAGE_ASSEMBLY */
7853 +
7854 +/* SDRAM initialization control (initcontrol) register bits */
7855 +#define SDRAM_CBR 0x0001 /* Writing 1 generates refresh cycle and toggles bit */
7856 +#define SDRAM_PRE 0x0002 /* Writing 1 generates precharge cycle and toggles bit */
7857 +#define SDRAM_MRS 0x0004 /* Writing 1 generates mode register select cycle and toggles bit */
7858 +#define SDRAM_EN 0x0008 /* When set, enables access to SDRAM */
7859 +#define SDRAM_16Mb 0x0000 /* Use 16 Megabit SDRAM */
7860 +#define SDRAM_64Mb 0x0010 /* Use 64 Megabit SDRAM */
7861 +#define SDRAM_128Mb 0x0020 /* Use 128 Megabit SDRAM */
7862 +#define SDRAM_RSVMb 0x0030 /* Use special SDRAM */
7863 +#define SDRAM_RST 0x0080 /* Writing 1 causes soft reset of controller */
7864 +#define SDRAM_SELFREF 0x0100 /* Writing 1 enables self refresh mode */
7865 +#define SDRAM_PWRDOWN 0x0200 /* Writing 1 causes controller to power down */
7866 +#define SDRAM_32BIT 0x0400 /* When set, indicates 32 bit SDRAM interface */
7867 +#define SDRAM_9BITCOL 0x0800 /* When set, indicates 9 bit column */
7868 +
7869 +/* SDRAM configuration (config) register bits */
7870 +#define SDRAM_BURSTFULL 0x0000 /* Use full page bursts */
7871 +#define SDRAM_BURST8 0x0001 /* Use burst of 8 */
7872 +#define SDRAM_BURST4 0x0002 /* Use burst of 4 */
7873 +#define SDRAM_BURST2 0x0003 /* Use burst of 2 */
7874 +#define SDRAM_CAS3 0x0000 /* Use CAS latency of 3 */
7875 +#define SDRAM_CAS2 0x0004 /* Use CAS latency of 2 */
7876 +
7877 +/* SDRAM refresh control (refresh) register bits */
7878 +#define SDRAM_REF(p) (((p)&0xff) | SDRAM_REF_EN) /* Refresh period */
7879 +#define SDRAM_REF_EN 0x8000 /* Writing 1 enables periodic refresh */
7880 +
7881 +/* SDRAM Core default Init values (OCP ID 0x803) */
7882 +#define SDRAM_INIT MEM4MX16X2
7883 +#define SDRAM_CONFIG SDRAM_BURSTFULL
7884 +#define SDRAM_REFRESH SDRAM_REF(0x40)
7885 +
7886 +#define MEM1MX16 0x009 /* 2 MB */
7887 +#define MEM1MX16X2 0x409 /* 4 MB */
7888 +#define MEM2MX8X2 0x809 /* 4 MB */
7889 +#define MEM2MX8X4 0xc09 /* 8 MB */
7890 +#define MEM2MX32 0x439 /* 8 MB */
7891 +#define MEM4MX16 0x019 /* 8 MB */
7892 +#define MEM4MX16X2 0x419 /* 16 MB */
7893 +#define MEM8MX8X2 0x819 /* 16 MB */
7894 +#define MEM8MX16 0x829 /* 16 MB */
7895 +#define MEM4MX32 0x429 /* 16 MB */
7896 +#define MEM8MX8X4 0xc19 /* 32 MB */
7897 +#define MEM8MX16X2 0xc29 /* 32 MB */
7898 +
7899 +#endif /* _SBSDRAM_H */
7900 diff -urN linux.old/arch/mips/bcm947xx/include/sbsocram.h linux.dev/arch/mips/bcm947xx/include/sbsocram.h
7901 --- linux.old/arch/mips/bcm947xx/include/sbsocram.h 1970-01-01 01:00:00.000000000 +0100
7902 +++ linux.dev/arch/mips/bcm947xx/include/sbsocram.h 2006-10-02 21:19:59.000000000 +0200
7903 @@ -0,0 +1,64 @@
7904 +/*
7905 + * BCM47XX Sonics SiliconBackplane embedded ram core
7906 + *
7907 + * Copyright 2006, Broadcom Corporation
7908 + * All Rights Reserved.
7909 + *
7910 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7911 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7912 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7913 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7914 + *
7915 + * $Id: sbsocram.h,v 1.1.1.3 2006/02/27 03:43:16 honor Exp $
7916 + */
7917 +
7918 +#ifndef _SBSOCRAM_H
7919 +#define _SBSOCRAM_H
7920 +
7921 +#define SR_COREINFO 0x00
7922 +#define SR_BWALLOC 0x04
7923 +#define SR_BISTSTAT 0x0c
7924 +#define SR_BANKINDEX 0x10
7925 +#define SR_BANKSTBYCTL 0x14
7926 +
7927 +
7928 +#ifndef _LANGUAGE_ASSEMBLY
7929 +
7930 +/* Memcsocram core registers */
7931 +typedef volatile struct sbsocramregs {
7932 + uint32 coreinfo;
7933 + uint32 bwalloc;
7934 + uint32 PAD;
7935 + uint32 biststat;
7936 + uint32 bankidx;
7937 + uint32 standbyctrl;
7938 +} sbsocramregs_t;
7939 +
7940 +#endif
7941 +
7942 +/* Coreinfo register */
7943 +#define SRCI_PT_MASK 0x30000
7944 +#define SRCI_PT_SHIFT 16
7945 +
7946 +/* In corerev 0, the memory size is 2 to the power of the
7947 + * base plus 16 plus to the contents of the memsize field plus 1.
7948 + */
7949 +#define SRCI_MS0_MASK 0xf
7950 +#define SR_MS0_BASE 16
7951 +
7952 +/*
7953 + * In corerev 1 the bank size is 2 ^ the bank size field plus 14,
7954 + * the memory size is number of banks times bank size.
7955 + * The same applies to rom size.
7956 + */
7957 +#define SRCI_ROMNB_MASK 0xf000
7958 +#define SRCI_ROMNB_SHIFT 12
7959 +#define SRCI_ROMBSZ_MASK 0xf00
7960 +#define SRCI_ROMBSZ_SHIFT 8
7961 +#define SRCI_SRNB_MASK 0xf0
7962 +#define SRCI_SRNB_SHIFT 4
7963 +#define SRCI_SRBSZ_MASK 0xf
7964 +#define SRCI_SRBSZ_SHIFT 0
7965 +
7966 +#define SR_BSZ_BASE 14
7967 +#endif /* _SBSOCRAM_H */
7968 diff -urN linux.old/arch/mips/bcm947xx/include/sbutils.h linux.dev/arch/mips/bcm947xx/include/sbutils.h
7969 --- linux.old/arch/mips/bcm947xx/include/sbutils.h 1970-01-01 01:00:00.000000000 +0100
7970 +++ linux.dev/arch/mips/bcm947xx/include/sbutils.h 2006-10-02 21:19:59.000000000 +0200
7971 @@ -0,0 +1,151 @@
7972 +/*
7973 + * Misc utility routines for accessing chip-specific features
7974 + * of Broadcom HNBU SiliconBackplane-based chips.
7975 + *
7976 + * Copyright 2006, Broadcom Corporation
7977 + * All Rights Reserved.
7978 + *
7979 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7980 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7981 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7982 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7983 + *
7984 + * $Id: sbutils.h,v 1.4 2006/04/08 07:12:42 honor Exp $
7985 + */
7986 +
7987 +#ifndef _sbutils_h_
7988 +#define _sbutils_h_
7989 +
7990 +/*
7991 + * Datastructure to export all chip specific common variables
7992 + * public (read-only) portion of sbutils handle returned by
7993 + * sb_attach()/sb_kattach()
7994 +*/
7995 +
7996 +struct sb_pub {
7997 +
7998 + uint bustype; /* SB_BUS, PCI_BUS */
7999 + uint buscoretype; /* SB_PCI, SB_PCMCIA, SB_PCIE */
8000 + uint buscorerev; /* buscore rev */
8001 + uint buscoreidx; /* buscore index */
8002 + int ccrev; /* chip common core rev */
8003 + uint boardtype; /* board type */
8004 + uint boardvendor; /* board vendor */
8005 + uint chip; /* chip number */
8006 + uint chiprev; /* chip revision */
8007 + uint chippkg; /* chip package option */
8008 + uint sonicsrev; /* sonics backplane rev */
8009 +};
8010 +
8011 +typedef const struct sb_pub sb_t;
8012 +
8013 +/*
8014 + * Many of the routines below take an 'sbh' handle as their first arg.
8015 + * Allocate this by calling sb_attach(). Free it by calling sb_detach().
8016 + * At any one time, the sbh is logically focused on one particular sb core
8017 + * (the "current core").
8018 + * Use sb_setcore() or sb_setcoreidx() to change the association to another core.
8019 + */
8020 +
8021 +#define SB_OSH NULL /* Use for sb_kattach when no osh is available */
8022 +/* exported externs */
8023 +extern sb_t *sb_attach(uint pcidev, osl_t *osh, void *regs, uint bustype,
8024 + void *sdh, char **vars, uint *varsz);
8025 +extern sb_t *sb_kattach(void);
8026 +extern void sb_detach(sb_t *sbh);
8027 +extern uint sb_chip(sb_t *sbh);
8028 +extern uint sb_chiprev(sb_t *sbh);
8029 +extern uint sb_chipcrev(sb_t *sbh);
8030 +extern uint sb_chippkg(sb_t *sbh);
8031 +extern uint sb_pcirev(sb_t *sbh);
8032 +extern bool sb_war16165(sb_t *sbh);
8033 +extern uint sb_pcmciarev(sb_t *sbh);
8034 +extern uint sb_boardvendor(sb_t *sbh);
8035 +extern uint sb_boardtype(sb_t *sbh);
8036 +extern uint sb_bus(sb_t *sbh);
8037 +extern uint sb_buscoretype(sb_t *sbh);
8038 +extern uint sb_buscorerev(sb_t *sbh);
8039 +extern uint sb_corelist(sb_t *sbh, uint coreid[]);
8040 +extern uint sb_coreid(sb_t *sbh);
8041 +extern uint sb_coreidx(sb_t *sbh);
8042 +extern uint sb_coreunit(sb_t *sbh);
8043 +extern uint sb_corevendor(sb_t *sbh);
8044 +extern uint sb_corerev(sb_t *sbh);
8045 +extern void *sb_osh(sb_t *sbh);
8046 +extern void sb_setosh(sb_t *sbh, osl_t *osh);
8047 +extern void *sb_coreregs(sb_t *sbh);
8048 +extern uint32 sb_coreflags(sb_t *sbh, uint32 mask, uint32 val);
8049 +extern uint32 sb_coreflagshi(sb_t *sbh, uint32 mask, uint32 val);
8050 +extern bool sb_iscoreup(sb_t *sbh);
8051 +extern void *sb_setcoreidx(sb_t *sbh, uint coreidx);
8052 +extern void *sb_setcore(sb_t *sbh, uint coreid, uint coreunit);
8053 +extern int sb_corebist(sb_t *sbh);
8054 +extern void sb_commit(sb_t *sbh);
8055 +extern uint32 sb_base(uint32 admatch);
8056 +extern uint32 sb_size(uint32 admatch);
8057 +extern void sb_core_reset(sb_t *sbh, uint32 bits, uint32 resetbits);
8058 +extern void sb_core_tofixup(sb_t *sbh);
8059 +extern void sb_core_disable(sb_t *sbh, uint32 bits);
8060 +extern uint32 sb_clock_rate(uint32 pll_type, uint32 n, uint32 m);
8061 +extern uint32 sb_clock(sb_t *sbh);
8062 +extern void sb_pci_setup(sb_t *sbh, uint coremask);
8063 +extern void sb_pcmcia_init(sb_t *sbh);
8064 +extern void sb_watchdog(sb_t *sbh, uint ticks);
8065 +extern void *sb_gpiosetcore(sb_t *sbh);
8066 +extern uint32 sb_gpiocontrol(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
8067 +extern uint32 sb_gpioouten(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
8068 +extern uint32 sb_gpioout(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
8069 +extern uint32 sb_gpioin(sb_t *sbh);
8070 +extern uint32 sb_gpiointpolarity(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
8071 +extern uint32 sb_gpiointmask(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
8072 +extern uint32 sb_gpioled(sb_t *sbh, uint32 mask, uint32 val);
8073 +extern uint32 sb_gpioreserve(sb_t *sbh, uint32 gpio_num, uint8 priority);
8074 +extern uint32 sb_gpiorelease(sb_t *sbh, uint32 gpio_num, uint8 priority);
8075 +
8076 +extern void sb_clkctl_init(sb_t *sbh);
8077 +extern uint16 sb_clkctl_fast_pwrup_delay(sb_t *sbh);
8078 +extern bool sb_clkctl_clk(sb_t *sbh, uint mode);
8079 +extern int sb_clkctl_xtal(sb_t *sbh, uint what, bool on);
8080 +extern void sb_register_intr_callback(sb_t *sbh, void *intrsoff_fn, void *intrsrestore_fn,
8081 + void *intrsenabled_fn, void *intr_arg);
8082 +extern uint32 sb_set_initiator_to(sb_t *sbh, uint32 to);
8083 +extern int sb_corepciid(sb_t *sbh, uint func, uint16 *pcivendor, uint16 *pcidevice,
8084 + uint8 *pciclass, uint8 *pcisubclass, uint8 *pciprogif,
8085 + uint8 *pciheader);
8086 +extern uint sb_pcie_readreg(void *sbh, void* arg1, uint offset);
8087 +extern uint sb_pcie_writereg(sb_t *sbh, void *arg1, uint offset, uint val);
8088 +extern uint32 sb_gpiotimerval(sb_t *sbh, uint32 mask, uint32 val);
8089 +extern bool sb_backplane64(sb_t *sbh);
8090 +extern void sb_btcgpiowar(sb_t *sbh);
8091 +
8092 +
8093 +
8094 +
8095 +extern bool sb_deviceremoved(sb_t *sbh);
8096 +extern uint32 sb_socram_size(sb_t *sbh);
8097 +
8098 +/*
8099 +* Build device path. Path size must be >= SB_DEVPATH_BUFSZ.
8100 +* The returned path is NULL terminated and has trailing '/'.
8101 +* Return 0 on success, nonzero otherwise.
8102 +*/
8103 +extern int sb_devpath(sb_t *sbh, char *path, int size);
8104 +
8105 +/* clkctl xtal what flags */
8106 +#define XTAL 0x1 /* primary crystal oscillator (2050) */
8107 +#define PLL 0x2 /* main chip pll */
8108 +
8109 +/* clkctl clk mode */
8110 +#define CLK_FAST 0 /* force fast (pll) clock */
8111 +#define CLK_DYNAMIC 2 /* enable dynamic clock control */
8112 +
8113 +
8114 +/* GPIO usage priorities */
8115 +#define GPIO_DRV_PRIORITY 0 /* Driver */
8116 +#define GPIO_APP_PRIORITY 1 /* Application */
8117 +#define GPIO_HI_PRIORITY 2 /* Highest priority. Ignore GPIO reservation */
8118 +
8119 +/* device path */
8120 +#define SB_DEVPATH_BUFSZ 16 /* min buffer size in bytes */
8121 +
8122 +#endif /* _sbutils_h_ */
8123 diff -urN linux.old/arch/mips/bcm947xx/include/sflash.h linux.dev/arch/mips/bcm947xx/include/sflash.h
8124 --- linux.old/arch/mips/bcm947xx/include/sflash.h 1970-01-01 01:00:00.000000000 +0100
8125 +++ linux.dev/arch/mips/bcm947xx/include/sflash.h 2006-10-02 21:19:59.000000000 +0200
8126 @@ -0,0 +1,36 @@
8127 +/*
8128 + * Broadcom SiliconBackplane chipcommon serial flash interface
8129 + *
8130 + * Copyright 2006, Broadcom Corporation
8131 + * All Rights Reserved.
8132 + *
8133 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8134 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8135 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8136 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
8137 + *
8138 + * $Id: sflash.h,v 1.1.1.8 2006/02/27 03:43:16 honor Exp $
8139 + */
8140 +
8141 +#ifndef _sflash_h_
8142 +#define _sflash_h_
8143 +
8144 +#include <typedefs.h>
8145 +#include <sbchipc.h>
8146 +
8147 +struct sflash {
8148 + uint blocksize; /* Block size */
8149 + uint numblocks; /* Number of blocks */
8150 + uint32 type; /* Type */
8151 + uint size; /* Total size in bytes */
8152 +};
8153 +
8154 +/* Utility functions */
8155 +extern int sflash_poll(chipcregs_t *cc, uint offset);
8156 +extern int sflash_read(chipcregs_t *cc, uint offset, uint len, uchar *buf);
8157 +extern int sflash_write(chipcregs_t *cc, uint offset, uint len, const uchar *buf);
8158 +extern int sflash_erase(chipcregs_t *cc, uint offset);
8159 +extern int sflash_commit(chipcregs_t *cc, uint offset, uint len, const uchar *buf);
8160 +extern struct sflash * sflash_init(chipcregs_t *cc);
8161 +
8162 +#endif /* _sflash_h_ */
8163 diff -urN linux.old/arch/mips/bcm947xx/include/trxhdr.h linux.dev/arch/mips/bcm947xx/include/trxhdr.h
8164 --- linux.old/arch/mips/bcm947xx/include/trxhdr.h 1970-01-01 01:00:00.000000000 +0100
8165 +++ linux.dev/arch/mips/bcm947xx/include/trxhdr.h 2006-10-02 21:19:59.000000000 +0200
8166 @@ -0,0 +1,33 @@
8167 +/*
8168 + * TRX image file header format.
8169 + *
8170 + * Copyright 2005, Broadcom Corporation
8171 + * All Rights Reserved.
8172 + *
8173 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8174 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8175 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8176 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
8177 + *
8178 + * $Id$
8179 + */
8180 +
8181 +#include <typedefs.h>
8182 +
8183 +#define TRX_MAGIC 0x30524448 /* "HDR0" */
8184 +#define TRX_VERSION 1
8185 +#define TRX_MAX_LEN 0x3A0000
8186 +#define TRX_NO_HEADER 1 /* Do not write TRX header */
8187 +#define TRX_GZ_FILES 0x2 /* Contains up to TRX_MAX_OFFSET individual gzip files */
8188 +#define TRX_MAX_OFFSET 3
8189 +
8190 +struct trx_header {
8191 + uint32 magic; /* "HDR0" */
8192 + uint32 len; /* Length of file including header */
8193 + uint32 crc32; /* 32-bit CRC from flag_version to end of file */
8194 + uint32 flag_version; /* 0:15 flags, 16:31 version */
8195 + uint32 offsets[TRX_MAX_OFFSET]; /* Offsets of partitions from start of header */
8196 +};
8197 +
8198 +/* Compatibility */
8199 +typedef struct trx_header TRXHDR, *PTRXHDR;
8200 diff -urN linux.old/arch/mips/bcm947xx/include/typedefs.h linux.dev/arch/mips/bcm947xx/include/typedefs.h
8201 --- linux.old/arch/mips/bcm947xx/include/typedefs.h 1970-01-01 01:00:00.000000000 +0100
8202 +++ linux.dev/arch/mips/bcm947xx/include/typedefs.h 2006-10-02 21:19:59.000000000 +0200
8203 @@ -0,0 +1,361 @@
8204 +/*
8205 + * Copyright 2006, Broadcom Corporation
8206 + * All Rights Reserved.
8207 + *
8208 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8209 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8210 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8211 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
8212 + * $Id: typedefs.h,v 1.1.1.12 2006/04/08 06:13:40 honor Exp $
8213 + */
8214 +
8215 +#ifndef _TYPEDEFS_H_
8216 +#define _TYPEDEFS_H_
8217 +
8218 +
8219 +/* Define 'SITE_TYPEDEFS' in the compile to include a site specific
8220 + * typedef file "site_typedefs.h".
8221 + *
8222 + * If 'SITE_TYPEDEFS' is not defined, then the "Inferred Typedefs"
8223 + * section of this file makes inferences about the compile environment
8224 + * based on defined symbols and possibly compiler pragmas.
8225 + *
8226 + * Following these two sections is the "Default Typedefs"
8227 + * section. This section is only prcessed if 'USE_TYPEDEF_DEFAULTS' is
8228 + * defined. This section has a default set of typedefs and a few
8229 + * proprocessor symbols (TRUE, FALSE, NULL, ...).
8230 + */
8231 +
8232 +#ifdef SITE_TYPEDEFS
8233 +
8234 +/*
8235 + * Site Specific Typedefs
8236 + *
8237 + */
8238 +
8239 +#include "site_typedefs.h"
8240 +
8241 +#else
8242 +
8243 +/*
8244 + * Inferred Typedefs
8245 + *
8246 + */
8247 +
8248 +/* Infer the compile environment based on preprocessor symbols and pramas.
8249 + * Override type definitions as needed, and include configuration dependent
8250 + * header files to define types.
8251 + */
8252 +
8253 +#ifdef __cplusplus
8254 +
8255 +#define TYPEDEF_BOOL
8256 +#ifndef FALSE
8257 +#define FALSE false
8258 +#endif
8259 +#ifndef TRUE
8260 +#define TRUE true
8261 +#endif
8262 +
8263 +#else /* ! __cplusplus */
8264 +
8265 +#if defined(_WIN32)
8266 +
8267 +#define TYPEDEF_BOOL
8268 +typedef unsigned char bool; /* consistent w/BOOL */
8269 +
8270 +#endif /* _WIN32 */
8271 +
8272 +#endif /* ! __cplusplus */
8273 +
8274 +/* use the Windows ULONG_PTR type when compiling for 64 bit */
8275 +#if defined(_WIN64)
8276 +#include <basetsd.h>
8277 +#define TYPEDEF_UINTPTR
8278 +typedef ULONG_PTR uintptr;
8279 +#endif
8280 +
8281 +
8282 +#if defined(_MINOSL_)
8283 +#define _NEED_SIZE_T_
8284 +#endif
8285 +
8286 +#if defined(_NEED_SIZE_T_)
8287 +typedef long unsigned int size_t;
8288 +#endif
8289 +
8290 +#ifdef __DJGPP__
8291 +typedef long unsigned int size_t;
8292 +#endif /* __DJGPP__ */
8293 +
8294 +#ifdef _MSC_VER /* Microsoft C */
8295 +#define TYPEDEF_INT64
8296 +#define TYPEDEF_UINT64
8297 +typedef signed __int64 int64;
8298 +typedef unsigned __int64 uint64;
8299 +#endif
8300 +
8301 +#if defined(MACOSX)
8302 +#define TYPEDEF_BOOL
8303 +#endif
8304 +
8305 +#if defined(__NetBSD__)
8306 +#define TYPEDEF_ULONG
8307 +#endif
8308 +
8309 +
8310 +#if defined(linux)
8311 +#define TYPEDEF_UINT
8312 +#define TYPEDEF_USHORT
8313 +#define TYPEDEF_ULONG
8314 +#endif
8315 +
8316 +#if !defined(linux) && !defined(_WIN32) && !defined(_CFE_) && \
8317 + !defined(_HNDRTE_) && !defined(_MINOSL_) && !defined(__DJGPP__)
8318 +#define TYPEDEF_UINT
8319 +#define TYPEDEF_USHORT
8320 +#endif
8321 +
8322 +
8323 +/* Do not support the (u)int64 types with strict ansi for GNU C */
8324 +#if defined(__GNUC__) && defined(__STRICT_ANSI__)
8325 +#define TYPEDEF_INT64
8326 +#define TYPEDEF_UINT64
8327 +#endif
8328 +
8329 +/* ICL accepts unsigned 64 bit type only, and complains in ANSI mode
8330 + * for singned or unsigned
8331 + */
8332 +#if defined(__ICL)
8333 +
8334 +#define TYPEDEF_INT64
8335 +
8336 +#if defined(__STDC__)
8337 +#define TYPEDEF_UINT64
8338 +#endif
8339 +
8340 +#endif /* __ICL */
8341 +
8342 +#if !defined(_WIN32) && !defined(_CFE_) && !defined(_MINOSL_) && \
8343 + !defined(__DJGPP__)
8344 +
8345 +/* pick up ushort & uint from standard types.h */
8346 +#if defined(linux) && defined(__KERNEL__)
8347 +
8348 +#include <linux/types.h> /* sys/types.h and linux/types.h are oil and water */
8349 +
8350 +#else
8351 +
8352 +#include <sys/types.h>
8353 +
8354 +#endif
8355 +
8356 +#endif /* !_WIN32 && !PMON && !_CFE_ && !_HNDRTE_ && !_MINOSL_ && !__DJGPP__ */
8357 +
8358 +#if defined(MACOSX)
8359 +
8360 +#ifdef __BIG_ENDIAN__
8361 +#define IL_BIGENDIAN
8362 +#else
8363 +#ifdef IL_BIGENDIAN
8364 +#error "IL_BIGENDIAN was defined for a little-endian compile"
8365 +#endif
8366 +#endif /* __BIG_ENDIAN__ */
8367 +
8368 +#if !defined(__cplusplus)
8369 +
8370 +#if defined(__i386__)
8371 +typedef unsigned char bool;
8372 +#else
8373 +typedef unsigned int bool;
8374 +#endif
8375 +#define TYPE_BOOL 1
8376 +enum {
8377 + false = 0,
8378 + true = 1
8379 +};
8380 +
8381 +#if defined(KERNEL)
8382 +#include <IOKit/IOTypes.h>
8383 +#endif /* KERNEL */
8384 +
8385 +#endif /* __cplusplus */
8386 +
8387 +#endif /* MACOSX */
8388 +
8389 +
8390 +/* use the default typedefs in the next section of this file */
8391 +#define USE_TYPEDEF_DEFAULTS
8392 +
8393 +#endif /* SITE_TYPEDEFS */
8394 +
8395 +
8396 +/*
8397 + * Default Typedefs
8398 + *
8399 + */
8400 +
8401 +#ifdef USE_TYPEDEF_DEFAULTS
8402 +#undef USE_TYPEDEF_DEFAULTS
8403 +
8404 +#ifndef TYPEDEF_BOOL
8405 +typedef /* @abstract@ */ unsigned char bool;
8406 +#endif
8407 +
8408 +/* define uchar, ushort, uint, ulong */
8409 +
8410 +#ifndef TYPEDEF_UCHAR
8411 +typedef unsigned char uchar;
8412 +#endif
8413 +
8414 +#ifndef TYPEDEF_USHORT
8415 +typedef unsigned short ushort;
8416 +#endif
8417 +
8418 +#ifndef TYPEDEF_UINT
8419 +typedef unsigned int uint;
8420 +#endif
8421 +
8422 +#ifndef TYPEDEF_ULONG
8423 +typedef unsigned long ulong;
8424 +#endif
8425 +
8426 +/* define [u]int8/16/32/64, uintptr */
8427 +
8428 +#ifndef TYPEDEF_UINT8
8429 +typedef unsigned char uint8;
8430 +#endif
8431 +
8432 +#ifndef TYPEDEF_UINT16
8433 +typedef unsigned short uint16;
8434 +#endif
8435 +
8436 +#ifndef TYPEDEF_UINT32
8437 +typedef unsigned int uint32;
8438 +#endif
8439 +
8440 +#ifndef TYPEDEF_UINT64
8441 +typedef unsigned long long uint64;
8442 +#endif
8443 +
8444 +#ifndef TYPEDEF_UINTPTR
8445 +typedef unsigned int uintptr;
8446 +#endif
8447 +
8448 +#ifndef TYPEDEF_INT8
8449 +typedef signed char int8;
8450 +#endif
8451 +
8452 +#ifndef TYPEDEF_INT16
8453 +typedef signed short int16;
8454 +#endif
8455 +
8456 +#ifndef TYPEDEF_INT32
8457 +typedef signed int int32;
8458 +#endif
8459 +
8460 +#ifndef TYPEDEF_INT64
8461 +typedef signed long long int64;
8462 +#endif
8463 +
8464 +/* define float32/64, float_t */
8465 +
8466 +#ifndef TYPEDEF_FLOAT32
8467 +typedef float float32;
8468 +#endif
8469 +
8470 +#ifndef TYPEDEF_FLOAT64
8471 +typedef double float64;
8472 +#endif
8473 +
8474 +/*
8475 + * abstracted floating point type allows for compile time selection of
8476 + * single or double precision arithmetic. Compiling with -DFLOAT32
8477 + * selects single precision; the default is double precision.
8478 + */
8479 +
8480 +#ifndef TYPEDEF_FLOAT_T
8481 +
8482 +#if defined(FLOAT32)
8483 +typedef float32 float_t;
8484 +#else /* default to double precision floating point */
8485 +typedef float64 float_t;
8486 +#endif
8487 +
8488 +#endif /* TYPEDEF_FLOAT_T */
8489 +
8490 +/* define macro values */
8491 +
8492 +#ifndef FALSE
8493 +#define FALSE 0
8494 +#endif
8495 +
8496 +#ifndef TRUE
8497 +#define TRUE 1 /* TRUE */
8498 +#endif
8499 +
8500 +#ifndef NULL
8501 +#define NULL 0
8502 +#endif
8503 +
8504 +#ifndef OFF
8505 +#define OFF 0
8506 +#endif
8507 +
8508 +#ifndef ON
8509 +#define ON 1 /* ON = 1 */
8510 +#endif
8511 +
8512 +#define AUTO (-1) /* Auto = -1 */
8513 +
8514 +/* define PTRSZ, INLINE */
8515 +
8516 +#ifndef PTRSZ
8517 +#define PTRSZ sizeof(char*)
8518 +#endif
8519 +
8520 +#ifndef INLINE
8521 +
8522 +#ifdef _MSC_VER
8523 +
8524 +#define INLINE __inline
8525 +
8526 +#elif __GNUC__
8527 +
8528 +#define INLINE __inline__
8529 +
8530 +#else
8531 +
8532 +#define INLINE
8533 +
8534 +#endif /* _MSC_VER */
8535 +
8536 +#endif /* INLINE */
8537 +
8538 +#undef TYPEDEF_BOOL
8539 +#undef TYPEDEF_UCHAR
8540 +#undef TYPEDEF_USHORT
8541 +#undef TYPEDEF_UINT
8542 +#undef TYPEDEF_ULONG
8543 +#undef TYPEDEF_UINT8
8544 +#undef TYPEDEF_UINT16
8545 +#undef TYPEDEF_UINT32
8546 +#undef TYPEDEF_UINT64
8547 +#undef TYPEDEF_UINTPTR
8548 +#undef TYPEDEF_INT8
8549 +#undef TYPEDEF_INT16
8550 +#undef TYPEDEF_INT32
8551 +#undef TYPEDEF_INT64
8552 +#undef TYPEDEF_FLOAT32
8553 +#undef TYPEDEF_FLOAT64
8554 +#undef TYPEDEF_FLOAT_T
8555 +
8556 +#endif /* USE_TYPEDEF_DEFAULTS */
8557 +
8558 +/*
8559 + * Including the bcmdefs.h here, to make sure everyone including typedefs.h
8560 + * gets this automatically
8561 +*/
8562 +#include "bcmdefs.h"
8563 +
8564 +#endif /* _TYPEDEFS_H_ */
8565 diff -urN linux.old/arch/mips/bcm947xx/Makefile linux.dev/arch/mips/bcm947xx/Makefile
8566 --- linux.old/arch/mips/bcm947xx/Makefile 1970-01-01 01:00:00.000000000 +0100
8567 +++ linux.dev/arch/mips/bcm947xx/Makefile 2006-10-02 21:26:08.000000000 +0200
8568 @@ -0,0 +1,17 @@
8569 +#
8570 +# Makefile for the BCM947xx specific kernel interface routines
8571 +# under Linux.
8572 +#
8573 +
8574 +EXTRA_CFLAGS+=-I$(TOPDIR)/arch/mips/bcm947xx/include -DBCMDRIVER -fno-delayed-branch
8575 +
8576 +O_TARGET := bcm947xx.o
8577 +
8578 +export-objs := export.o
8579 +obj-y := prom.o setup.o time.o sbmips.o gpio.o
8580 +obj-y += nvram.o nvram_linux.o sflash.o cfe_env.o
8581 +obj-y += sbutils.o bcmutils.o bcmsrom.o hndchipc.o
8582 +obj-$(CONFIG_PCI) += sbpci.o pcibios.o
8583 +obj-y += export.o
8584 +
8585 +include $(TOPDIR)/Rules.make
8586 diff -urN linux.old/arch/mips/bcm947xx/nvram.c linux.dev/arch/mips/bcm947xx/nvram.c
8587 --- linux.old/arch/mips/bcm947xx/nvram.c 1970-01-01 01:00:00.000000000 +0100
8588 +++ linux.dev/arch/mips/bcm947xx/nvram.c 2006-10-02 21:19:59.000000000 +0200
8589 @@ -0,0 +1,315 @@
8590 +/*
8591 + * NVRAM variable manipulation (common)
8592 + *
8593 + * Copyright 2004, Broadcom Corporation
8594 + * All Rights Reserved.
8595 + *
8596 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8597 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8598 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8599 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
8600 + *
8601 + */
8602 +
8603 +#include <typedefs.h>
8604 +#include <osl.h>
8605 +#include <bcmendian.h>
8606 +#include <bcmnvram.h>
8607 +#include <bcmutils.h>
8608 +#include <sbsdram.h>
8609 +
8610 +extern struct nvram_tuple * BCMINIT(_nvram_realloc)(struct nvram_tuple *t, const char *name, const char *value);
8611 +extern void BCMINIT(_nvram_free)(struct nvram_tuple *t);
8612 +extern int BCMINIT(_nvram_read)(void *buf);
8613 +
8614 +char * BCMINIT(_nvram_get)(const char *name);
8615 +int BCMINIT(_nvram_set)(const char *name, const char *value);
8616 +int BCMINIT(_nvram_unset)(const char *name);
8617 +int BCMINIT(_nvram_getall)(char *buf, int count);
8618 +int BCMINIT(_nvram_commit)(struct nvram_header *header);
8619 +int BCMINIT(_nvram_init)(void);
8620 +void BCMINIT(_nvram_exit)(void);
8621 +
8622 +static struct nvram_tuple * BCMINITDATA(nvram_hash)[257];
8623 +static struct nvram_tuple * nvram_dead;
8624 +
8625 +/* Free all tuples. Should be locked. */
8626 +static void
8627 +BCMINITFN(nvram_free)(void)
8628 +{
8629 + uint i;
8630 + struct nvram_tuple *t, *next;
8631 +
8632 + /* Free hash table */
8633 + for (i = 0; i < ARRAYSIZE(BCMINIT(nvram_hash)); i++) {
8634 + for (t = BCMINIT(nvram_hash)[i]; t; t = next) {
8635 + next = t->next;
8636 + BCMINIT(_nvram_free)(t);
8637 + }
8638 + BCMINIT(nvram_hash)[i] = NULL;
8639 + }
8640 +
8641 + /* Free dead table */
8642 + for (t = nvram_dead; t; t = next) {
8643 + next = t->next;
8644 + BCMINIT(_nvram_free)(t);
8645 + }
8646 + nvram_dead = NULL;
8647 +
8648 + /* Indicate to per-port code that all tuples have been freed */
8649 + BCMINIT(_nvram_free)(NULL);
8650 +}
8651 +
8652 +/* String hash */
8653 +static INLINE uint
8654 +hash(const char *s)
8655 +{
8656 + uint hash = 0;
8657 +
8658 + while (*s)
8659 + hash = 31 * hash + *s++;
8660 +
8661 + return hash;
8662 +}
8663 +
8664 +/* (Re)initialize the hash table. Should be locked. */
8665 +static int
8666 +BCMINITFN(nvram_rehash)(struct nvram_header *header)
8667 +{
8668 + char buf[] = "0xXXXXXXXX", *name, *value, *end, *eq;
8669 +
8670 + /* (Re)initialize hash table */
8671 + BCMINIT(nvram_free)();
8672 +
8673 + /* Parse and set "name=value\0 ... \0\0" */
8674 + name = (char *) &header[1];
8675 + end = (char *) header + NVRAM_SPACE - 2;
8676 + end[0] = end[1] = '\0';
8677 + for (; *name; name = value + strlen(value) + 1) {
8678 + if (!(eq = strchr(name, '=')))
8679 + break;
8680 + *eq = '\0';
8681 + value = eq + 1;
8682 + BCMINIT(_nvram_set)(name, value);
8683 + *eq = '=';
8684 + }
8685 +
8686 + /* Set special SDRAM parameters */
8687 + if (!BCMINIT(_nvram_get)("sdram_init")) {
8688 + sprintf(buf, "0x%04X", (uint16)(header->crc_ver_init >> 16));
8689 + BCMINIT(_nvram_set)("sdram_init", buf);
8690 + }
8691 + if (!BCMINIT(_nvram_get)("sdram_config")) {
8692 + sprintf(buf, "0x%04X", (uint16)(header->config_refresh & 0xffff));
8693 + BCMINIT(_nvram_set)("sdram_config", buf);
8694 + }
8695 + if (!BCMINIT(_nvram_get)("sdram_refresh")) {
8696 + sprintf(buf, "0x%04X", (uint16)((header->config_refresh >> 16) & 0xffff));
8697 + BCMINIT(_nvram_set)("sdram_refresh", buf);
8698 + }
8699 + if (!BCMINIT(_nvram_get)("sdram_ncdl")) {
8700 + sprintf(buf, "0x%08X", header->config_ncdl);
8701 + BCMINIT(_nvram_set)("sdram_ncdl", buf);
8702 + }
8703 +
8704 + return 0;
8705 +}
8706 +
8707 +/* Get the value of an NVRAM variable. Should be locked. */
8708 +char *
8709 +BCMINITFN(_nvram_get)(const char *name)
8710 +{
8711 + uint i;
8712 + struct nvram_tuple *t;
8713 + char *value;
8714 +
8715 + if (!name)
8716 + return NULL;
8717 +
8718 + /* Hash the name */
8719 + i = hash(name) % ARRAYSIZE(BCMINIT(nvram_hash));
8720 +
8721 + /* Find the associated tuple in the hash table */
8722 + for (t = BCMINIT(nvram_hash)[i]; t && strcmp(t->name, name); t = t->next);
8723 +
8724 + value = t ? t->value : NULL;
8725 +
8726 + return value;
8727 +}
8728 +
8729 +/* Get the value of an NVRAM variable. Should be locked. */
8730 +int
8731 +BCMINITFN(_nvram_set)(const char *name, const char *value)
8732 +{
8733 + uint i;
8734 + struct nvram_tuple *t, *u, **prev;
8735 +
8736 + /* Hash the name */
8737 + i = hash(name) % ARRAYSIZE(BCMINIT(nvram_hash));
8738 +
8739 + /* Find the associated tuple in the hash table */
8740 + for (prev = &BCMINIT(nvram_hash)[i], t = *prev; t && strcmp(t->name, name); prev = &t->next, t = *prev);
8741 +
8742 + /* (Re)allocate tuple */
8743 + if (!(u = BCMINIT(_nvram_realloc)(t, name, value)))
8744 + return -12; /* -ENOMEM */
8745 +
8746 + /* Value reallocated */
8747 + if (t && t == u)
8748 + return 0;
8749 +
8750 + /* Move old tuple to the dead table */
8751 + if (t) {
8752 + *prev = t->next;
8753 + t->next = nvram_dead;
8754 + nvram_dead = t;
8755 + }
8756 +
8757 + /* Add new tuple to the hash table */
8758 + u->next = BCMINIT(nvram_hash)[i];
8759 + BCMINIT(nvram_hash)[i] = u;
8760 +
8761 + return 0;
8762 +}
8763 +
8764 +/* Unset the value of an NVRAM variable. Should be locked. */
8765 +int
8766 +BCMINITFN(_nvram_unset)(const char *name)
8767 +{
8768 + uint i;
8769 + struct nvram_tuple *t, **prev;
8770 +
8771 + if (!name)
8772 + return 0;
8773 +
8774 + /* Hash the name */
8775 + i = hash(name) % ARRAYSIZE(BCMINIT(nvram_hash));
8776 +
8777 + /* Find the associated tuple in the hash table */
8778 + for (prev = &BCMINIT(nvram_hash)[i], t = *prev; t && strcmp(t->name, name); prev = &t->next, t = *prev);
8779 +
8780 + /* Move it to the dead table */
8781 + if (t) {
8782 + *prev = t->next;
8783 + t->next = nvram_dead;
8784 + nvram_dead = t;
8785 + }
8786 +
8787 + return 0;
8788 +}
8789 +
8790 +/* Get all NVRAM variables. Should be locked. */
8791 +int
8792 +BCMINITFN(_nvram_getall)(char *buf, int count)
8793 +{
8794 + uint i;
8795 + struct nvram_tuple *t;
8796 + int len = 0;
8797 +
8798 + bzero(buf, count);
8799 +
8800 + /* Write name=value\0 ... \0\0 */
8801 + for (i = 0; i < ARRAYSIZE(BCMINIT(nvram_hash)); i++) {
8802 + for (t = BCMINIT(nvram_hash)[i]; t; t = t->next) {
8803 + if ((count - len) > (strlen(t->name) + 1 + strlen(t->value) + 1))
8804 + len += sprintf(buf + len, "%s=%s", t->name, t->value) + 1;
8805 + else
8806 + break;
8807 + }
8808 + }
8809 +
8810 + return 0;
8811 +}
8812 +
8813 +/* Regenerate NVRAM. Should be locked. */
8814 +int
8815 +BCMINITFN(_nvram_commit)(struct nvram_header *header)
8816 +{
8817 + char *init, *config, *refresh, *ncdl;
8818 + char *ptr, *end;
8819 + int i;
8820 + struct nvram_tuple *t;
8821 + struct nvram_header tmp;
8822 + uint8 crc;
8823 +
8824 + /* Regenerate header */
8825 + header->magic = NVRAM_MAGIC;
8826 + header->crc_ver_init = (NVRAM_VERSION << 8);
8827 + if (!(init = BCMINIT(_nvram_get)("sdram_init")) ||
8828 + !(config = BCMINIT(_nvram_get)("sdram_config")) ||
8829 + !(refresh = BCMINIT(_nvram_get)("sdram_refresh")) ||
8830 + !(ncdl = BCMINIT(_nvram_get)("sdram_ncdl"))) {
8831 + header->crc_ver_init |= SDRAM_INIT << 16;
8832 + header->config_refresh = SDRAM_CONFIG;
8833 + header->config_refresh |= SDRAM_REFRESH << 16;
8834 + header->config_ncdl = 0;
8835 + } else {
8836 + header->crc_ver_init |= (bcm_strtoul(init, NULL, 0) & 0xffff) << 16;
8837 + header->config_refresh = bcm_strtoul(config, NULL, 0) & 0xffff;
8838 + header->config_refresh |= (bcm_strtoul(refresh, NULL, 0) & 0xffff) << 16;
8839 + header->config_ncdl = bcm_strtoul(ncdl, NULL, 0);
8840 + }
8841 +
8842 + /* Clear data area */
8843 + ptr = (char *) header + sizeof(struct nvram_header);
8844 + bzero(ptr, NVRAM_SPACE - sizeof(struct nvram_header));
8845 +
8846 + /* Leave space for a double NUL at the end */
8847 + end = (char *) header + NVRAM_SPACE - 2;
8848 +
8849 + /* Write out all tuples */
8850 + for (i = 0; i < ARRAYSIZE(BCMINIT(nvram_hash)); i++) {
8851 + for (t = BCMINIT(nvram_hash)[i]; t; t = t->next) {
8852 + if ((ptr + strlen(t->name) + 1 + strlen(t->value) + 1) > end)
8853 + break;
8854 + ptr += sprintf(ptr, "%s=%s", t->name, t->value) + 1;
8855 + }
8856 + }
8857 +
8858 + /* End with a double NUL */
8859 + ptr += 2;
8860 +
8861 + /* Set new length */
8862 + header->len = ROUNDUP(ptr - (char *) header, 4);
8863 +
8864 + /* Little-endian CRC8 over the last 11 bytes of the header */
8865 + tmp.crc_ver_init = htol32(header->crc_ver_init);
8866 + tmp.config_refresh = htol32(header->config_refresh);
8867 + tmp.config_ncdl = htol32(header->config_ncdl);
8868 + crc = hndcrc8((char *) &tmp + 9, sizeof(struct nvram_header) - 9, CRC8_INIT_VALUE);
8869 +
8870 + /* Continue CRC8 over data bytes */
8871 + crc = hndcrc8((char *) &header[1], header->len - sizeof(struct nvram_header), crc);
8872 +
8873 + /* Set new CRC8 */
8874 + header->crc_ver_init |= crc;
8875 +
8876 + /* Reinitialize hash table */
8877 + return BCMINIT(nvram_rehash)(header);
8878 +}
8879 +
8880 +/* Initialize hash table. Should be locked. */
8881 +int
8882 +BCMINITFN(_nvram_init)(void)
8883 +{
8884 + struct nvram_header *header;
8885 + int ret;
8886 +
8887 + if (!(header = (struct nvram_header *) kmalloc(NVRAM_SPACE, GFP_ATOMIC))) {
8888 + return -12; /* -ENOMEM */
8889 + }
8890 +
8891 + if ((ret = BCMINIT(_nvram_read)(header)) == 0 &&
8892 + header->magic == NVRAM_MAGIC)
8893 + BCMINIT(nvram_rehash)(header);
8894 +
8895 + kfree(header);
8896 + return ret;
8897 +}
8898 +
8899 +/* Free hash table. Should be locked. */
8900 +void
8901 +BCMINITFN(_nvram_exit)(void)
8902 +{
8903 + BCMINIT(nvram_free)();
8904 +}
8905 diff -urN linux.old/arch/mips/bcm947xx/nvram_linux.c linux.dev/arch/mips/bcm947xx/nvram_linux.c
8906 --- linux.old/arch/mips/bcm947xx/nvram_linux.c 1970-01-01 01:00:00.000000000 +0100
8907 +++ linux.dev/arch/mips/bcm947xx/nvram_linux.c 2006-10-02 21:19:59.000000000 +0200
8908 @@ -0,0 +1,723 @@
8909 +/*
8910 + * NVRAM variable manipulation (Linux kernel half)
8911 + *
8912 + * Copyright 2006, Broadcom Corporation
8913 + * All Rights Reserved.
8914 + *
8915 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8916 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8917 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8918 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
8919 + *
8920 + * $Id: nvram_linux.c,v 1.19 2006/04/08 07:12:42 honor Exp $
8921 + */
8922 +
8923 +#include <linux/config.h>
8924 +#include <linux/init.h>
8925 +#include <linux/module.h>
8926 +#include <linux/kernel.h>
8927 +#include <linux/string.h>
8928 +#include <linux/interrupt.h>
8929 +#include <linux/spinlock.h>
8930 +#include <linux/slab.h>
8931 +#include <linux/bootmem.h>
8932 +#include <linux/wrapper.h>
8933 +#include <linux/fs.h>
8934 +#include <linux/miscdevice.h>
8935 +#include <linux/mtd/mtd.h>
8936 +#include <asm/addrspace.h>
8937 +#include <asm/io.h>
8938 +#include <asm/uaccess.h>
8939 +
8940 +#include <typedefs.h>
8941 +#include <osl.h>
8942 +#include <bcmendian.h>
8943 +#include <bcmnvram.h>
8944 +#include <bcmutils.h>
8945 +#include <sbconfig.h>
8946 +#include <sbchipc.h>
8947 +#include <sbutils.h>
8948 +#include <hndmips.h>
8949 +#include <sflash.h>
8950 +
8951 +/* In BSS to minimize text size and page aligned so it can be mmap()-ed */
8952 +static char nvram_buf[NVRAM_SPACE] __attribute__((aligned(PAGE_SIZE)));
8953 +
8954 +#ifdef MODULE
8955 +
8956 +#define early_nvram_get(name) nvram_get(name)
8957 +
8958 +#else /* !MODULE */
8959 +
8960 +/* Global SB handle */
8961 +extern void *bcm947xx_sbh;
8962 +extern spinlock_t bcm947xx_sbh_lock;
8963 +
8964 +static int cfe_env;
8965 +extern char *cfe_env_get(char *nv_buf, const char *name);
8966 +
8967 +/* Convenience */
8968 +#define sbh bcm947xx_sbh
8969 +#define sbh_lock bcm947xx_sbh_lock
8970 +#define KB * 1024
8971 +#define MB * 1024 * 1024
8972 +
8973 +/* Probe for NVRAM header */
8974 +static void __init
8975 +early_nvram_init(void)
8976 +{
8977 + struct nvram_header *header;
8978 + chipcregs_t *cc;
8979 + struct sflash *info = NULL;
8980 + int i;
8981 + uint32 base, off, lim;
8982 + u32 *src, *dst;
8983 +
8984 + if ((cc = sb_setcore(sbh, SB_CC, 0)) != NULL) {
8985 + base = KSEG1ADDR(SB_FLASH2);
8986 + switch (readl(&cc->capabilities) & CAP_FLASH_MASK) {
8987 + case PFLASH:
8988 + lim = SB_FLASH2_SZ;
8989 + break;
8990 +
8991 + case SFLASH_ST:
8992 + case SFLASH_AT:
8993 + if ((info = sflash_init(cc)) == NULL)
8994 + return;
8995 + lim = info->size;
8996 + break;
8997 +
8998 + case FLASH_NONE:
8999 + default:
9000 + return;
9001 + }
9002 + } else {
9003 + /* extif assumed, Stop at 4 MB */
9004 + base = KSEG1ADDR(SB_FLASH1);
9005 + lim = SB_FLASH1_SZ;
9006 + }
9007 +
9008 + /* XXX: hack for supporting the CFE environment stuff on WGT634U */
9009 + src = (u32 *) KSEG1ADDR(base + 8 * 1024 * 1024 - 0x2000);
9010 + dst = (u32 *) nvram_buf;
9011 + if ((lim == 0x02000000) && ((*src & 0xff00ff) == 0x000001)) {
9012 + printk("early_nvram_init: WGT634U NVRAM found.\n");
9013 +
9014 + for (i = 0; i < 0x1ff0; i++) {
9015 + if (*src == 0xFFFFFFFF)
9016 + break;
9017 + *dst++ = *src++;
9018 + }
9019 + cfe_env = 1;
9020 + return;
9021 + }
9022 +
9023 + off = FLASH_MIN;
9024 + while (off <= lim) {
9025 + /* Windowed flash access */
9026 + header = (struct nvram_header *) KSEG1ADDR(base + off - NVRAM_SPACE);
9027 + if (header->magic == NVRAM_MAGIC)
9028 + goto found;
9029 + off <<= 1;
9030 + }
9031 +
9032 + /* Try embedded NVRAM at 4 KB and 1 KB as last resorts */
9033 + header = (struct nvram_header *) KSEG1ADDR(base + 4 KB);
9034 + if (header->magic == NVRAM_MAGIC)
9035 + goto found;
9036 +
9037 + header = (struct nvram_header *) KSEG1ADDR(base + 1 KB);
9038 + if (header->magic == NVRAM_MAGIC)
9039 + goto found;
9040 +
9041 + printk("early_nvram_init: NVRAM not found\n");
9042 + return;
9043 +
9044 +found:
9045 + src = (u32 *) header;
9046 + dst = (u32 *) nvram_buf;
9047 + for (i = 0; i < sizeof(struct nvram_header); i += 4)
9048 + *dst++ = *src++;
9049 + for (; i < header->len && i < NVRAM_SPACE; i += 4)
9050 + *dst++ = ltoh32(*src++);
9051 +}
9052 +
9053 +/* Early (before mm or mtd) read-only access to NVRAM */
9054 +static char * __init
9055 +early_nvram_get(const char *name)
9056 +{
9057 + char *var, *value, *end, *eq;
9058 +
9059 + if (!name)
9060 + return NULL;
9061 +
9062 + /* Too early? */
9063 + if (sbh == NULL)
9064 + return NULL;
9065 +
9066 + if (!nvram_buf[0])
9067 + early_nvram_init();
9068 +
9069 + if (cfe_env)
9070 + return cfe_env_get(nvram_buf, name);
9071 +
9072 + /* Look for name=value and return value */
9073 + var = &nvram_buf[sizeof(struct nvram_header)];
9074 + end = nvram_buf + sizeof(nvram_buf) - 2;
9075 + end[0] = end[1] = '\0';
9076 + for (; *var; var = value + strlen(value) + 1) {
9077 + if (!(eq = strchr(var, '=')))
9078 + break;
9079 + value = eq + 1;
9080 + if ((eq - var) == strlen(name) && strncmp(var, name, (eq - var)) == 0)
9081 + return value;
9082 + }
9083 +
9084 + return NULL;
9085 +}
9086 +
9087 +static int __init
9088 +early_nvram_getall(char *buf, int count)
9089 +{
9090 + char *var, *end;
9091 + int len = 0;
9092 +
9093 + /* Too early? */
9094 + if (sbh == NULL)
9095 + return -1;
9096 +
9097 + if (!nvram_buf[0])
9098 + early_nvram_init();
9099 +
9100 + bzero(buf, count);
9101 +
9102 + /* Write name=value\0 ... \0\0 */
9103 + var = &nvram_buf[sizeof(struct nvram_header)];
9104 + end = nvram_buf + sizeof(nvram_buf) - 2;
9105 + end[0] = end[1] = '\0';
9106 + for (; *var; var += strlen(var) + 1) {
9107 + if ((count - len) <= (strlen(var) + 1))
9108 + break;
9109 + len += sprintf(buf + len, "%s", var) + 1;
9110 + }
9111 +
9112 + return 0;
9113 +}
9114 +#endif /* !MODULE */
9115 +
9116 +extern char * _nvram_get(const char *name);
9117 +extern int _nvram_set(const char *name, const char *value);
9118 +extern int _nvram_unset(const char *name);
9119 +extern int _nvram_getall(char *buf, int count);
9120 +extern int _nvram_commit(struct nvram_header *header);
9121 +extern int _nvram_init(void *sbh);
9122 +extern void _nvram_exit(void);
9123 +
9124 +/* Globals */
9125 +static spinlock_t nvram_lock = SPIN_LOCK_UNLOCKED;
9126 +static struct semaphore nvram_sem;
9127 +static unsigned long nvram_offset = 0;
9128 +static int nvram_major = -1;
9129 +static devfs_handle_t nvram_handle = NULL;
9130 +static struct mtd_info *nvram_mtd = NULL;
9131 +
9132 +int
9133 +_nvram_read(char *buf)
9134 +{
9135 + struct nvram_header *header = (struct nvram_header *) buf;
9136 + size_t len;
9137 +
9138 + if (!nvram_mtd ||
9139 + MTD_READ(nvram_mtd, nvram_mtd->size - NVRAM_SPACE, NVRAM_SPACE, &len, buf) ||
9140 + len != NVRAM_SPACE ||
9141 + header->magic != NVRAM_MAGIC) {
9142 + /* Maybe we can recover some data from early initialization */
9143 + memcpy(buf, nvram_buf, NVRAM_SPACE);
9144 + }
9145 +
9146 + return 0;
9147 +}
9148 +
9149 +struct nvram_tuple *
9150 +_nvram_realloc(struct nvram_tuple *t, const char *name, const char *value)
9151 +{
9152 + if ((nvram_offset + strlen(value) + 1) > NVRAM_SPACE)
9153 + return NULL;
9154 +
9155 + if (!t) {
9156 + if (!(t = kmalloc(sizeof(struct nvram_tuple) + strlen(name) + 1, GFP_ATOMIC)))
9157 + return NULL;
9158 +
9159 + /* Copy name */
9160 + t->name = (char *) &t[1];
9161 + strcpy(t->name, name);
9162 +
9163 + t->value = NULL;
9164 + }
9165 +
9166 + /* Copy value */
9167 + if (!t->value || strcmp(t->value, value)) {
9168 + t->value = &nvram_buf[nvram_offset];
9169 + strcpy(t->value, value);
9170 + nvram_offset += strlen(value) + 1;
9171 + }
9172 +
9173 + return t;
9174 +}
9175 +
9176 +void
9177 +_nvram_free(struct nvram_tuple *t)
9178 +{
9179 + if (!t)
9180 + nvram_offset = 0;
9181 + else
9182 + kfree(t);
9183 +}
9184 +
9185 +int
9186 +nvram_set(const char *name, const char *value)
9187 +{
9188 + unsigned long flags;
9189 + int ret;
9190 + struct nvram_header *header;
9191 +
9192 + spin_lock_irqsave(&nvram_lock, flags);
9193 + if ((ret = _nvram_set(name, value))) {
9194 + /* Consolidate space and try again */
9195 + if ((header = kmalloc(NVRAM_SPACE, GFP_ATOMIC))) {
9196 + if (_nvram_commit(header) == 0)
9197 + ret = _nvram_set(name, value);
9198 + kfree(header);
9199 + }
9200 + }
9201 + spin_unlock_irqrestore(&nvram_lock, flags);
9202 +
9203 + return ret;
9204 +}
9205 +
9206 +char *
9207 +real_nvram_get(const char *name)
9208 +{
9209 + unsigned long flags;
9210 + char *value;
9211 +
9212 + spin_lock_irqsave(&nvram_lock, flags);
9213 + value = _nvram_get(name);
9214 + spin_unlock_irqrestore(&nvram_lock, flags);
9215 +
9216 + return value;
9217 +}
9218 +
9219 +char *
9220 +nvram_get(const char *name)
9221 +{
9222 + if (nvram_major >= 0)
9223 + return real_nvram_get(name);
9224 + else
9225 + return early_nvram_get(name);
9226 +}
9227 +
9228 +int
9229 +nvram_unset(const char *name)
9230 +{
9231 + unsigned long flags;
9232 + int ret;
9233 +
9234 + spin_lock_irqsave(&nvram_lock, flags);
9235 + ret = _nvram_unset(name);
9236 + spin_unlock_irqrestore(&nvram_lock, flags);
9237 +
9238 + return ret;
9239 +}
9240 +
9241 +static void
9242 +erase_callback(struct erase_info *done)
9243 +{
9244 + wait_queue_head_t *wait_q = (wait_queue_head_t *) done->priv;
9245 + wake_up(wait_q);
9246 +}
9247 +
9248 +int
9249 +nvram_commit(void)
9250 +{
9251 + char *buf;
9252 + size_t erasesize, len, magic_len;
9253 + unsigned int i;
9254 + int ret;
9255 + struct nvram_header *header;
9256 + unsigned long flags;
9257 + u_int32_t offset;
9258 + DECLARE_WAITQUEUE(wait, current);
9259 + wait_queue_head_t wait_q;
9260 + struct erase_info erase;
9261 + u_int32_t magic_offset = 0; /* Offset for writing MAGIC # */
9262 +
9263 + if (!nvram_mtd) {
9264 + printk("nvram_commit: NVRAM not found\n");
9265 + return -ENODEV;
9266 + }
9267 +
9268 + if (in_interrupt()) {
9269 + printk("nvram_commit: not committing in interrupt\n");
9270 + return -EINVAL;
9271 + }
9272 +
9273 + /* Backup sector blocks to be erased */
9274 + erasesize = ROUNDUP(NVRAM_SPACE, nvram_mtd->erasesize);
9275 + if (!(buf = kmalloc(erasesize, GFP_KERNEL))) {
9276 + printk("nvram_commit: out of memory\n");
9277 + return -ENOMEM;
9278 + }
9279 +
9280 + down(&nvram_sem);
9281 +
9282 + if ((i = erasesize - NVRAM_SPACE) > 0) {
9283 + offset = nvram_mtd->size - erasesize;
9284 + len = 0;
9285 + ret = MTD_READ(nvram_mtd, offset, i, &len, buf);
9286 + if (ret || len != i) {
9287 + printk("nvram_commit: read error ret = %d, len = %d/%d\n", ret, len, i);
9288 + ret = -EIO;
9289 + goto done;
9290 + }
9291 + header = (struct nvram_header *)(buf + i);
9292 + magic_offset = i + ((void *)&header->magic - (void *)header);
9293 + } else {
9294 + offset = nvram_mtd->size - NVRAM_SPACE;
9295 + magic_offset = ((void *)&header->magic - (void *)header);
9296 + header = (struct nvram_header *)buf;
9297 + }
9298 +
9299 + /* clear the existing magic # to mark the NVRAM as unusable
9300 + we can pull MAGIC bits low without erase */
9301 + header->magic = NVRAM_CLEAR_MAGIC; /* All zeros magic */
9302 +
9303 + /* Unlock sector blocks (for Intel 28F320C3B flash) , 20060309 */
9304 + if(nvram_mtd->unlock)
9305 + nvram_mtd->unlock(nvram_mtd, offset, nvram_mtd->erasesize);
9306 +
9307 + ret = MTD_WRITE(nvram_mtd, offset + magic_offset, sizeof(header->magic),
9308 + &magic_len, (char *)&header->magic);
9309 + if (ret || magic_len != sizeof(header->magic)) {
9310 + printk("nvram_commit: clear MAGIC error\n");
9311 + ret = -EIO;
9312 + goto done;
9313 + }
9314 +
9315 + header->magic = NVRAM_MAGIC; /* reset MAGIC before we regenerate the NVRAM,
9316 + otherwise we'll have an incorrect CRC */
9317 + /* Regenerate NVRAM */
9318 + spin_lock_irqsave(&nvram_lock, flags);
9319 + ret = _nvram_commit(header);
9320 + spin_unlock_irqrestore(&nvram_lock, flags);
9321 + if (ret)
9322 + goto done;
9323 +
9324 + /* Erase sector blocks */
9325 + init_waitqueue_head(&wait_q);
9326 + for (; offset < nvram_mtd->size - NVRAM_SPACE + header->len; offset += nvram_mtd->erasesize) {
9327 + erase.mtd = nvram_mtd;
9328 + erase.addr = offset;
9329 + erase.len = nvram_mtd->erasesize;
9330 + erase.callback = erase_callback;
9331 + erase.priv = (u_long) &wait_q;
9332 +
9333 + set_current_state(TASK_INTERRUPTIBLE);
9334 + add_wait_queue(&wait_q, &wait);
9335 +
9336 + /* Unlock sector blocks */
9337 + if (nvram_mtd->unlock)
9338 + nvram_mtd->unlock(nvram_mtd, offset, nvram_mtd->erasesize);
9339 +
9340 + if ((ret = MTD_ERASE(nvram_mtd, &erase))) {
9341 + set_current_state(TASK_RUNNING);
9342 + remove_wait_queue(&wait_q, &wait);
9343 + printk("nvram_commit: erase error\n");
9344 + goto done;
9345 + }
9346 +
9347 + /* Wait for erase to finish */
9348 + schedule();
9349 + remove_wait_queue(&wait_q, &wait);
9350 + }
9351 +
9352 + /* Write partition up to end of data area */
9353 + header->magic = NVRAM_INVALID_MAGIC; /* All ones magic */
9354 + offset = nvram_mtd->size - erasesize;
9355 + i = erasesize - NVRAM_SPACE + header->len;
9356 + ret = MTD_WRITE(nvram_mtd, offset, i, &len, buf);
9357 + if (ret || len != i) {
9358 + printk("nvram_commit: write error\n");
9359 + ret = -EIO;
9360 + goto done;
9361 + }
9362 +
9363 + /* Now mark the NVRAM in flash as "valid" by setting the correct
9364 + MAGIC # */
9365 + header->magic = NVRAM_MAGIC;
9366 + ret = MTD_WRITE(nvram_mtd, offset + magic_offset, sizeof(header->magic),
9367 + &magic_len, (char *)&header->magic);
9368 + if (ret || magic_len != sizeof(header->magic)) {
9369 + printk("nvram_commit: write MAGIC error\n");
9370 + ret = -EIO;
9371 + goto done;
9372 + }
9373 +
9374 + /*
9375 + * Reading a few bytes back here will put the device
9376 + * back to the correct mode on certain flashes */
9377 + offset = nvram_mtd->size - erasesize;
9378 + ret = MTD_READ(nvram_mtd, offset, 4, &len, buf);
9379 +
9380 + done:
9381 + up(&nvram_sem);
9382 + kfree(buf);
9383 +
9384 + return ret;
9385 +}
9386 +
9387 +int
9388 +nvram_getall(char *buf, int count)
9389 +{
9390 + unsigned long flags;
9391 + int ret;
9392 +
9393 + spin_lock_irqsave(&nvram_lock, flags);
9394 + if (nvram_major >= 0)
9395 + ret = _nvram_getall(buf, count);
9396 + else
9397 + ret = early_nvram_getall(buf, count);
9398 + spin_unlock_irqrestore(&nvram_lock, flags);
9399 +
9400 + return ret;
9401 +}
9402 +
9403 +
9404 +
9405 +
9406 +
9407 +
9408 +
9409 +/* User mode interface below */
9410 +
9411 +static ssize_t
9412 +dev_nvram_read(struct file *file, char *buf, size_t count, loff_t *ppos)
9413 +{
9414 + char tmp[100], *name = tmp, *value;
9415 + ssize_t ret;
9416 + unsigned long off;
9417 +
9418 + if (count > sizeof(tmp)) {
9419 + if (!(name = kmalloc(count, GFP_KERNEL)))
9420 + return -ENOMEM;
9421 + }
9422 +
9423 + if (copy_from_user(name, buf, count)) {
9424 + ret = -EFAULT;
9425 + goto done;
9426 + }
9427 +
9428 + if (*name == '\0') {
9429 + /* Get all variables */
9430 + ret = nvram_getall(name, count);
9431 + if (ret == 0) {
9432 + if (copy_to_user(buf, name, count)) {
9433 + ret = -EFAULT;
9434 + goto done;
9435 + }
9436 + ret = count;
9437 + }
9438 + } else {
9439 + if (!(value = nvram_get(name))) {
9440 + ret = 0;
9441 + goto done;
9442 + }
9443 +
9444 + /* Provide the offset into mmap() space */
9445 + off = (unsigned long) value - (unsigned long) nvram_buf;
9446 +
9447 + if (put_user(off, (unsigned long *) buf)) {
9448 + ret = -EFAULT;
9449 + goto done;
9450 + }
9451 +
9452 + ret = sizeof(unsigned long);
9453 + }
9454 +
9455 + flush_cache_all();
9456 +
9457 +done:
9458 + if (name != tmp)
9459 + kfree(name);
9460 +
9461 + return ret;
9462 +}
9463 +
9464 +static ssize_t
9465 +dev_nvram_write(struct file *file, const char *buf, size_t count, loff_t *ppos)
9466 +{
9467 + char tmp[100], *name = tmp, *value;
9468 + ssize_t ret;
9469 +
9470 + if (count > sizeof(tmp)) {
9471 + if (!(name = kmalloc(count, GFP_KERNEL)))
9472 + return -ENOMEM;
9473 + }
9474 +
9475 + if (copy_from_user(name, buf, count)) {
9476 + ret = -EFAULT;
9477 + goto done;
9478 + }
9479 +
9480 + value = name;
9481 + name = strsep(&value, "=");
9482 + if (value)
9483 + ret = nvram_set(name, value) ? : count;
9484 + else
9485 + ret = nvram_unset(name) ? : count;
9486 +
9487 + done:
9488 + if (name != tmp)
9489 + kfree(name);
9490 +
9491 + return ret;
9492 +}
9493 +
9494 +static int
9495 +dev_nvram_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
9496 +{
9497 + if (cmd != NVRAM_MAGIC)
9498 + return -EINVAL;
9499 +
9500 + return nvram_commit();
9501 +}
9502 +
9503 +static int
9504 +dev_nvram_mmap(struct file *file, struct vm_area_struct *vma)
9505 +{
9506 + unsigned long offset = virt_to_phys(nvram_buf);
9507 +
9508 + if (remap_page_range(vma->vm_start, offset, vma->vm_end-vma->vm_start,
9509 + vma->vm_page_prot))
9510 + return -EAGAIN;
9511 +
9512 + return 0;
9513 +}
9514 +
9515 +static int
9516 +dev_nvram_open(struct inode *inode, struct file * file)
9517 +{
9518 + MOD_INC_USE_COUNT;
9519 + return 0;
9520 +}
9521 +
9522 +static int
9523 +dev_nvram_release(struct inode *inode, struct file * file)
9524 +{
9525 + MOD_DEC_USE_COUNT;
9526 + return 0;
9527 +}
9528 +
9529 +static struct file_operations dev_nvram_fops = {
9530 + owner: THIS_MODULE,
9531 + open: dev_nvram_open,
9532 + release: dev_nvram_release,
9533 + read: dev_nvram_read,
9534 + write: dev_nvram_write,
9535 + ioctl: dev_nvram_ioctl,
9536 + mmap: dev_nvram_mmap,
9537 +};
9538 +
9539 +static void
9540 +dev_nvram_exit(void)
9541 +{
9542 + int order = 0;
9543 + struct page *page, *end;
9544 +
9545 + if (nvram_handle)
9546 + devfs_unregister(nvram_handle);
9547 +
9548 + if (nvram_major >= 0)
9549 + devfs_unregister_chrdev(nvram_major, "nvram");
9550 +
9551 + if (nvram_mtd)
9552 + put_mtd_device(nvram_mtd);
9553 +
9554 + while ((PAGE_SIZE << order) < NVRAM_SPACE)
9555 + order++;
9556 + end = virt_to_page(nvram_buf + (PAGE_SIZE << order) - 1);
9557 + for (page = virt_to_page(nvram_buf); page <= end; page++)
9558 + mem_map_unreserve(page);
9559 +
9560 + _nvram_exit();
9561 +}
9562 +
9563 +static int __init
9564 +dev_nvram_init(void)
9565 +{
9566 + int order = 0, ret = 0;
9567 + struct page *page, *end;
9568 + unsigned int i;
9569 +
9570 + /* Allocate and reserve memory to mmap() */
9571 + while ((PAGE_SIZE << order) < NVRAM_SPACE)
9572 + order++;
9573 + end = virt_to_page(nvram_buf + (PAGE_SIZE << order) - 1);
9574 + for (page = virt_to_page(nvram_buf); page <= end; page++)
9575 + mem_map_reserve(page);
9576 +
9577 +#ifdef CONFIG_MTD
9578 + /* Find associated MTD device */
9579 + for (i = 0; i < MAX_MTD_DEVICES; i++) {
9580 + nvram_mtd = get_mtd_device(NULL, i);
9581 + if (nvram_mtd) {
9582 + if (!strcmp(nvram_mtd->name, "nvram") &&
9583 + nvram_mtd->size >= NVRAM_SPACE)
9584 + break;
9585 + put_mtd_device(nvram_mtd);
9586 + }
9587 + }
9588 + if (i >= MAX_MTD_DEVICES)
9589 + nvram_mtd = NULL;
9590 +#endif
9591 +
9592 + /* Initialize hash table lock */
9593 + spin_lock_init(&nvram_lock);
9594 +
9595 + /* Initialize commit semaphore */
9596 + init_MUTEX(&nvram_sem);
9597 +
9598 + /* Register char device */
9599 + if ((nvram_major = devfs_register_chrdev(0, "nvram", &dev_nvram_fops)) < 0) {
9600 + ret = nvram_major;
9601 + goto err;
9602 + }
9603 +
9604 + /* Initialize hash table */
9605 + _nvram_init(sbh);
9606 +
9607 + /* Create /dev/nvram handle */
9608 + nvram_handle = devfs_register(NULL, "nvram", DEVFS_FL_NONE, nvram_major, 0,
9609 + S_IFCHR | S_IRUSR | S_IWUSR | S_IRGRP, &dev_nvram_fops, NULL);
9610 +
9611 + /* Set the SDRAM NCDL value into NVRAM if not already done */
9612 + if (getintvar(NULL, "sdram_ncdl") == 0) {
9613 + unsigned int ncdl;
9614 + char buf[] = "0x00000000";
9615 +
9616 + if ((ncdl = sb_memc_get_ncdl(sbh))) {
9617 + sprintf(buf, "0x%08x", ncdl);
9618 + nvram_set("sdram_ncdl", buf);
9619 + nvram_commit();
9620 + }
9621 + }
9622 +
9623 + return 0;
9624 +
9625 + err:
9626 + dev_nvram_exit();
9627 + return ret;
9628 +}
9629 +
9630 +module_init(dev_nvram_init);
9631 +module_exit(dev_nvram_exit);
9632 diff -urN linux.old/arch/mips/bcm947xx/pcibios.c linux.dev/arch/mips/bcm947xx/pcibios.c
9633 --- linux.old/arch/mips/bcm947xx/pcibios.c 1970-01-01 01:00:00.000000000 +0100
9634 +++ linux.dev/arch/mips/bcm947xx/pcibios.c 2006-10-02 21:22:56.000000000 +0200
9635 @@ -0,0 +1,380 @@
9636 +/*
9637 + * Low-Level PCI and SB support for BCM47xx (Linux support code)
9638 + *
9639 + * Copyright 2006, Broadcom Corporation
9640 + * All Rights Reserved.
9641 + *
9642 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
9643 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
9644 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
9645 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
9646 + *
9647 + * $Id: pcibios.c,v 1.1.1.9 2006/02/27 03:42:55 honor Exp $
9648 + */
9649 +
9650 +#include <linux/config.h>
9651 +#include <linux/types.h>
9652 +#include <linux/kernel.h>
9653 +#include <linux/sched.h>
9654 +#include <linux/pci.h>
9655 +#include <linux/init.h>
9656 +#include <linux/delay.h>
9657 +#include <asm/io.h>
9658 +#include <asm/irq.h>
9659 +#include <asm/paccess.h>
9660 +
9661 +#include <typedefs.h>
9662 +#include <osl.h>
9663 +#include <bcmutils.h>
9664 +#include <sbconfig.h>
9665 +#include <sbutils.h>
9666 +#include <hndpci.h>
9667 +#include <pcicfg.h>
9668 +#include <bcmdevs.h>
9669 +#include <bcmnvram.h>
9670 +
9671 +/* Global SB handle */
9672 +extern sb_t *bcm947xx_sbh;
9673 +extern spinlock_t bcm947xx_sbh_lock;
9674 +
9675 +/* Convenience */
9676 +#define sbh bcm947xx_sbh
9677 +#define sbh_lock bcm947xx_sbh_lock
9678 +
9679 +static int
9680 +sbpci_read_config_byte(struct pci_dev *dev, int where, u8 *value)
9681 +{
9682 + unsigned long flags;
9683 + int ret;
9684 +
9685 + spin_lock_irqsave(&sbh_lock, flags);
9686 + ret = sbpci_read_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn),
9687 + PCI_FUNC(dev->devfn), where, value, sizeof(*value));
9688 + spin_unlock_irqrestore(&sbh_lock, flags);
9689 + return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
9690 +}
9691 +
9692 +static int
9693 +sbpci_read_config_word(struct pci_dev *dev, int where, u16 *value)
9694 +{
9695 + unsigned long flags;
9696 + int ret;
9697 +
9698 + spin_lock_irqsave(&sbh_lock, flags);
9699 + ret = sbpci_read_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn),
9700 + PCI_FUNC(dev->devfn), where, value, sizeof(*value));
9701 + spin_unlock_irqrestore(&sbh_lock, flags);
9702 + return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
9703 +}
9704 +
9705 +static int
9706 +sbpci_read_config_dword(struct pci_dev *dev, int where, u32 *value)
9707 +{
9708 + unsigned long flags;
9709 + int ret;
9710 +
9711 + spin_lock_irqsave(&sbh_lock, flags);
9712 + ret = sbpci_read_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn),
9713 + PCI_FUNC(dev->devfn), where, value, sizeof(*value));
9714 + spin_unlock_irqrestore(&sbh_lock, flags);
9715 + return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
9716 +}
9717 +
9718 +static int
9719 +sbpci_write_config_byte(struct pci_dev *dev, int where, u8 value)
9720 +{
9721 + unsigned long flags;
9722 + int ret;
9723 +
9724 + spin_lock_irqsave(&sbh_lock, flags);
9725 + ret = sbpci_write_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn),
9726 + PCI_FUNC(dev->devfn), where, &value, sizeof(value));
9727 + spin_unlock_irqrestore(&sbh_lock, flags);
9728 + return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
9729 +}
9730 +
9731 +static int
9732 +sbpci_write_config_word(struct pci_dev *dev, int where, u16 value)
9733 +{
9734 + unsigned long flags;
9735 + int ret;
9736 +
9737 + spin_lock_irqsave(&sbh_lock, flags);
9738 + ret = sbpci_write_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn),
9739 + PCI_FUNC(dev->devfn), where, &value, sizeof(value));
9740 + spin_unlock_irqrestore(&sbh_lock, flags);
9741 + return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
9742 +}
9743 +
9744 +static int
9745 +sbpci_write_config_dword(struct pci_dev *dev, int where, u32 value)
9746 +{
9747 + unsigned long flags;
9748 + int ret;
9749 +
9750 + spin_lock_irqsave(&sbh_lock, flags);
9751 + ret = sbpci_write_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn),
9752 + PCI_FUNC(dev->devfn), where, &value, sizeof(value));
9753 + spin_unlock_irqrestore(&sbh_lock, flags);
9754 + return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
9755 +}
9756 +
9757 +static struct pci_ops pcibios_ops = {
9758 + sbpci_read_config_byte,
9759 + sbpci_read_config_word,
9760 + sbpci_read_config_dword,
9761 + sbpci_write_config_byte,
9762 + sbpci_write_config_word,
9763 + sbpci_write_config_dword
9764 +};
9765 +
9766 +
9767 +void __init
9768 +pcibios_init(void)
9769 +{
9770 + ulong flags;
9771 +
9772 + if (!(sbh = sb_kattach()))
9773 + panic("sb_kattach failed");
9774 + spin_lock_init(&sbh_lock);
9775 +
9776 + spin_lock_irqsave(&sbh_lock, flags);
9777 + sbpci_init(sbh);
9778 + spin_unlock_irqrestore(&sbh_lock, flags);
9779 +
9780 + set_io_port_base((unsigned long) ioremap_nocache(SB_PCI_MEM, 0x04000000));
9781 +
9782 + /* Scan the SB bus */
9783 + pci_scan_bus(0, &pcibios_ops, NULL);
9784 +
9785 +}
9786 +
9787 +char * __init
9788 +pcibios_setup(char *str)
9789 +{
9790 + if (!strncmp(str, "ban=", 4)) {
9791 + sbpci_ban(simple_strtoul(str + 4, NULL, 0));
9792 + return NULL;
9793 + }
9794 +
9795 + return (str);
9796 +}
9797 +
9798 +static u32 pci_iobase = 0x100;
9799 +static u32 pci_membase = SB_PCI_DMA;
9800 +
9801 +void __init
9802 +pcibios_fixup_bus(struct pci_bus *b)
9803 +{
9804 + struct list_head *ln;
9805 + struct pci_dev *d;
9806 + struct resource *res;
9807 + int pos, size;
9808 + u32 *base;
9809 + u8 irq;
9810 +
9811 + printk("PCI: Fixing up bus %d\n", b->number);
9812 +
9813 + /* Fix up SB */
9814 + if (b->number == 0) {
9815 + for (ln = b->devices.next; ln != &b->devices; ln = ln->next) {
9816 + d = pci_dev_b(ln);
9817 + /* Fix up interrupt lines */
9818 + pci_read_config_byte(d, PCI_INTERRUPT_LINE, &irq);
9819 + d->irq = irq + 2;
9820 + pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
9821 + }
9822 + }
9823 +
9824 + /* Fix up external PCI */
9825 + else {
9826 + for (ln = b->devices.next; ln != &b->devices; ln = ln->next) {
9827 + d = pci_dev_b(ln);
9828 + /* Fix up resource bases */
9829 + for (pos = 0; pos < 6; pos++) {
9830 + res = &d->resource[pos];
9831 + base = (res->flags & IORESOURCE_IO) ? &pci_iobase : &pci_membase;
9832 + if (res->end) {
9833 + size = res->end - res->start + 1;
9834 + if (*base & (size - 1))
9835 + *base = (*base + size) & ~(size - 1);
9836 + res->start = *base;
9837 + res->end = res->start + size - 1;
9838 + *base += size;
9839 + pci_write_config_dword(d,
9840 + PCI_BASE_ADDRESS_0 + (pos << 2), res->start);
9841 + }
9842 + /* Fix up PCI bridge BAR0 only */
9843 + if (b->number == 1 && PCI_SLOT(d->devfn) == 0)
9844 + break;
9845 + }
9846 + /* Fix up interrupt lines */
9847 + if (pci_find_device(VENDOR_BROADCOM, SB_PCI, NULL))
9848 + d->irq = (pci_find_device(VENDOR_BROADCOM, SB_PCI, NULL))->irq;
9849 + pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
9850 + }
9851 + }
9852 +}
9853 +
9854 +unsigned int
9855 +pcibios_assign_all_busses(void)
9856 +{
9857 + return 1;
9858 +}
9859 +
9860 +void
9861 +pcibios_align_resource(void *data, struct resource *res,
9862 + unsigned long size, unsigned long align)
9863 +{
9864 +}
9865 +
9866 +int
9867 +pcibios_enable_resources(struct pci_dev *dev)
9868 +{
9869 + u16 cmd, old_cmd;
9870 + int idx;
9871 + struct resource *r;
9872 +
9873 + /* External PCI only */
9874 + if (dev->bus->number == 0)
9875 + return 0;
9876 +
9877 + pci_read_config_word(dev, PCI_COMMAND, &cmd);
9878 + old_cmd = cmd;
9879 + for (idx = 0; idx < 6; idx++) {
9880 + r = &dev->resource[idx];
9881 + if (r->flags & IORESOURCE_IO)
9882 + cmd |= PCI_COMMAND_IO;
9883 + if (r->flags & IORESOURCE_MEM)
9884 + cmd |= PCI_COMMAND_MEMORY;
9885 + }
9886 + if (dev->resource[PCI_ROM_RESOURCE].start)
9887 + cmd |= PCI_COMMAND_MEMORY;
9888 + if (cmd != old_cmd) {
9889 + printk("PCI: Enabling device %s (%04x -> %04x)\n", dev->slot_name, old_cmd, cmd);
9890 + pci_write_config_word(dev, PCI_COMMAND, cmd);
9891 + }
9892 + return 0;
9893 +}
9894 +
9895 +int
9896 +pcibios_enable_device(struct pci_dev *dev, int mask)
9897 +{
9898 + ulong flags;
9899 + uint coreidx;
9900 + void *regs;
9901 +
9902 + /* External PCI device enable */
9903 + if (dev->bus->number != 0)
9904 + return pcibios_enable_resources(dev);
9905 +
9906 + /* These cores come out of reset enabled */
9907 + if (dev->device == SB_MIPS ||
9908 + dev->device == SB_MIPS33 ||
9909 + dev->device == SB_EXTIF ||
9910 + dev->device == SB_CC)
9911 + return 0;
9912 +
9913 + spin_lock_irqsave(&sbh_lock, flags);
9914 + coreidx = sb_coreidx(sbh);
9915 + regs = sb_setcoreidx(sbh, PCI_SLOT(dev->devfn));
9916 + if (!regs)
9917 + return PCIBIOS_DEVICE_NOT_FOUND;
9918 +
9919 + /*
9920 + * The USB core requires a special bit to be set during core
9921 + * reset to enable host (OHCI) mode. Resetting the SB core in
9922 + * pcibios_enable_device() is a hack for compatibility with
9923 + * vanilla usb-ohci so that it does not have to know about
9924 + * SB. A driver that wants to use the USB core in device mode
9925 + * should know about SB and should reset the bit back to 0
9926 + * after calling pcibios_enable_device().
9927 + */
9928 + if (sb_coreid(sbh) == SB_USB) {
9929 + sb_core_disable(sbh, sb_coreflags(sbh, 0, 0));
9930 + sb_core_reset(sbh, 1 << 29, 0);
9931 + }
9932 + /*
9933 + * USB 2.0 special considerations:
9934 + *
9935 + * 1. Since the core supports both OHCI and EHCI functions, it must
9936 + * only be reset once.
9937 + *
9938 + * 2. In addition to the standard SB reset sequence, the Host Control
9939 + * Register must be programmed to bring the USB core and various
9940 + * phy components out of reset.
9941 + */
9942 + else if (sb_coreid(sbh) == SB_USB20H) {
9943 + if (!sb_iscoreup(sbh)) {
9944 + sb_core_reset(sbh, 0, 0);
9945 + writel(0x7FF, (ulong)regs + 0x200);
9946 + udelay(1);
9947 + }
9948 + } else
9949 + sb_core_reset(sbh, 0, 0);
9950 +
9951 + sb_setcoreidx(sbh, coreidx);
9952 + spin_unlock_irqrestore(&sbh_lock, flags);
9953 +
9954 + return 0;
9955 +}
9956 +
9957 +void
9958 +pcibios_update_resource(struct pci_dev *dev, struct resource *root,
9959 + struct resource *res, int resource)
9960 +{
9961 + unsigned long where, size;
9962 + u32 reg;
9963 +
9964 + /* External PCI only */
9965 + if (dev->bus->number == 0)
9966 + return;
9967 +
9968 + where = PCI_BASE_ADDRESS_0 + (resource * 4);
9969 + size = res->end - res->start;
9970 + pci_read_config_dword(dev, where, &reg);
9971 + reg = (reg & size) | (((u32)(res->start - root->start)) & ~size);
9972 + pci_write_config_dword(dev, where, reg);
9973 +}
9974 +
9975 +static void __init
9976 +quirk_sbpci_bridge(struct pci_dev *dev)
9977 +{
9978 + if (dev->bus->number != 1 || PCI_SLOT(dev->devfn) != 0)
9979 + return;
9980 +
9981 + printk("PCI: Fixing up bridge\n");
9982 +
9983 + /* Enable PCI bridge bus mastering and memory space */
9984 + pci_set_master(dev);
9985 + pcibios_enable_resources(dev);
9986 +
9987 + /* Enable PCI bridge BAR1 prefetch and burst */
9988 + pci_write_config_dword(dev, PCI_BAR1_CONTROL, 3);
9989 +}
9990 +
9991 +struct pci_fixup pcibios_fixups[] = {
9992 + { PCI_FIXUP_HEADER, PCI_ANY_ID, PCI_ANY_ID, quirk_sbpci_bridge },
9993 + { 0 }
9994 +};
9995 +
9996 +/*
9997 + * If we set up a device for bus mastering, we need to check the latency
9998 + * timer as certain crappy BIOSes forget to set it properly.
9999 + */
10000 +unsigned int pcibios_max_latency = 255;
10001 +
10002 +void pcibios_set_master(struct pci_dev *dev)
10003 +{
10004 + u8 lat;
10005 + pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
10006 + if (lat < 16)
10007 + lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
10008 + else if (lat > pcibios_max_latency)
10009 + lat = pcibios_max_latency;
10010 + else
10011 + return;
10012 + printk(KERN_DEBUG "PCI: Setting latency timer of device %s to %d\n", dev->slot_name, lat);
10013 + pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
10014 +}
10015 +
10016 diff -urN linux.old/arch/mips/bcm947xx/prom.c linux.dev/arch/mips/bcm947xx/prom.c
10017 --- linux.old/arch/mips/bcm947xx/prom.c 1970-01-01 01:00:00.000000000 +0100
10018 +++ linux.dev/arch/mips/bcm947xx/prom.c 2006-10-02 21:19:59.000000000 +0200
10019 @@ -0,0 +1,41 @@
10020 +/*
10021 + * Early initialization code for BCM94710 boards
10022 + *
10023 + * Copyright 2004, Broadcom Corporation
10024 + * All Rights Reserved.
10025 + *
10026 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
10027 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
10028 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
10029 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
10030 + *
10031 + * $Id: prom.c,v 1.1 2005/03/16 13:49:59 wbx Exp $
10032 + */
10033 +
10034 +#include <linux/config.h>
10035 +#include <linux/init.h>
10036 +#include <linux/kernel.h>
10037 +#include <linux/types.h>
10038 +#include <asm/bootinfo.h>
10039 +
10040 +void __init
10041 +prom_init(int argc, const char **argv)
10042 +{
10043 + unsigned long mem;
10044 +
10045 + mips_machgroup = MACH_GROUP_BRCM;
10046 + mips_machtype = MACH_BCM947XX;
10047 +
10048 + /* Figure out memory size by finding aliases */
10049 + for (mem = (1 << 20); mem < (128 << 20); mem += (1 << 20)) {
10050 + if (*(unsigned long *)((unsigned long)(prom_init) + mem) ==
10051 + *(unsigned long *)(prom_init))
10052 + break;
10053 + }
10054 + add_memory_region(0, mem, BOOT_MEM_RAM);
10055 +}
10056 +
10057 +void __init
10058 +prom_free_prom_memory(void)
10059 +{
10060 +}
10061 diff -urN linux.old/arch/mips/bcm947xx/sbmips.c linux.dev/arch/mips/bcm947xx/sbmips.c
10062 --- linux.old/arch/mips/bcm947xx/sbmips.c 1970-01-01 01:00:00.000000000 +0100
10063 +++ linux.dev/arch/mips/bcm947xx/sbmips.c 2006-10-02 21:19:59.000000000 +0200
10064 @@ -0,0 +1,1132 @@
10065 +/*
10066 + * BCM47XX Sonics SiliconBackplane MIPS core routines
10067 + *
10068 + * Copyright 2006, Broadcom Corporation
10069 + * All Rights Reserved.
10070 + *
10071 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
10072 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
10073 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
10074 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
10075 + *
10076 + * $Id: hndmips.c,v 1.1.1.1 2006/02/27 03:43:16 honor Exp $
10077 + */
10078 +
10079 +#include <typedefs.h>
10080 +#include <bcmdefs.h>
10081 +#include <osl.h>
10082 +#include <bcmutils.h>
10083 +#include <sbutils.h>
10084 +#include <bcmdevs.h>
10085 +#include <bcmnvram.h>
10086 +#include <sbconfig.h>
10087 +#include <sbextif.h>
10088 +#include <sbchipc.h>
10089 +#include <sbmemc.h>
10090 +#include <mipsinc.h>
10091 +#include <sbhndmips.h>
10092 +#include <hndcpu.h>
10093 +
10094 +/* sbipsflag register format, indexed by irq. */
10095 +static const uint32 sbips_int_mask[] = {
10096 + 0, /* placeholder */
10097 + SBIPS_INT1_MASK,
10098 + SBIPS_INT2_MASK,
10099 + SBIPS_INT3_MASK,
10100 + SBIPS_INT4_MASK
10101 +};
10102 +
10103 +static const uint32 sbips_int_shift[] = {
10104 + 0, /* placeholder */
10105 + SBIPS_INT1_SHIFT,
10106 + SBIPS_INT2_SHIFT,
10107 + SBIPS_INT3_SHIFT,
10108 + SBIPS_INT4_SHIFT
10109 +};
10110 +
10111 +/*
10112 + * Map SB cores sharing the MIPS hardware IRQ0 to virtual dedicated OS IRQs.
10113 + * Per-port BSP code is required to provide necessary translations between
10114 + * the shared MIPS IRQ and the virtual OS IRQs based on SB core flag.
10115 + *
10116 + * See sb_irq() for the mapping.
10117 + */
10118 +static uint shirq_map_base = 0;
10119 +
10120 +/* Returns the SB interrupt flag of the current core. */
10121 +static uint32
10122 +sb_getflag(sb_t *sbh)
10123 +{
10124 + osl_t *osh;
10125 + void *regs;
10126 + sbconfig_t *sb;
10127 +
10128 + osh = sb_osh(sbh);
10129 + regs = sb_coreregs(sbh);
10130 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
10131 +
10132 + return (R_REG(osh, &sb->sbtpsflag) & SBTPS_NUM0_MASK);
10133 +}
10134 +
10135 +/*
10136 + * Returns the MIPS IRQ assignment of the current core. If unassigned,
10137 + * 0 is returned.
10138 + */
10139 +uint
10140 +sb_irq(sb_t *sbh)
10141 +{
10142 + osl_t *osh;
10143 + uint idx;
10144 + void *regs;
10145 + sbconfig_t *sb;
10146 + uint32 flag, sbipsflag;
10147 + uint irq = 0;
10148 +
10149 + osh = sb_osh(sbh);
10150 + flag = sb_getflag(sbh);
10151 +
10152 + idx = sb_coreidx(sbh);
10153 +
10154 + if ((regs = sb_setcore(sbh, SB_MIPS, 0)) ||
10155 + (regs = sb_setcore(sbh, SB_MIPS33, 0))) {
10156 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
10157 +
10158 + /* sbipsflag specifies which core is routed to interrupts 1 to 4 */
10159 + sbipsflag = R_REG(osh, &sb->sbipsflag);
10160 + for (irq = 1; irq <= 4; irq++) {
10161 + if (((sbipsflag & sbips_int_mask[irq]) >> sbips_int_shift[irq]) == flag)
10162 + break;
10163 + }
10164 + if (irq == 5)
10165 + irq = 0;
10166 + }
10167 +
10168 + sb_setcoreidx(sbh, idx);
10169 +
10170 + return irq;
10171 +}
10172 +
10173 +/* Clears the specified MIPS IRQ. */
10174 +static void
10175 +BCMINITFN(sb_clearirq)(sb_t *sbh, uint irq)
10176 +{
10177 + osl_t *osh;
10178 + void *regs;
10179 + sbconfig_t *sb;
10180 +
10181 + osh = sb_osh(sbh);
10182 +
10183 + if (!(regs = sb_setcore(sbh, SB_MIPS, 0)) &&
10184 + !(regs = sb_setcore(sbh, SB_MIPS33, 0)))
10185 + ASSERT(regs);
10186 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
10187 +
10188 + if (irq == 0)
10189 + W_REG(osh, &sb->sbintvec, 0);
10190 + else
10191 + OR_REG(osh, &sb->sbipsflag, sbips_int_mask[irq]);
10192 +}
10193 +
10194 +/*
10195 + * Assigns the specified MIPS IRQ to the specified core. Shared MIPS
10196 + * IRQ 0 may be assigned more than once.
10197 + *
10198 + * The old assignment to the specified core is removed first.
10199 + */
10200 +static void
10201 +BCMINITFN(sb_setirq)(sb_t *sbh, uint irq, uint coreid, uint coreunit)
10202 +{
10203 + osl_t *osh;
10204 + void *regs;
10205 + sbconfig_t *sb;
10206 + uint32 flag;
10207 + uint oldirq;
10208 +
10209 + osh = sb_osh(sbh);
10210 +
10211 + regs = sb_setcore(sbh, coreid, coreunit);
10212 + ASSERT(regs);
10213 + flag = sb_getflag(sbh);
10214 + oldirq = sb_irq(sbh);
10215 + if (oldirq)
10216 + sb_clearirq(sbh, oldirq);
10217 +
10218 + if (!(regs = sb_setcore(sbh, SB_MIPS, 0)) &&
10219 + !(regs = sb_setcore(sbh, SB_MIPS33, 0)))
10220 + ASSERT(regs);
10221 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
10222 +
10223 + if (!oldirq)
10224 + AND_REG(osh, &sb->sbintvec, ~(1 << flag));
10225 +
10226 + if (irq == 0)
10227 + OR_REG(osh, &sb->sbintvec, 1 << flag);
10228 + else {
10229 + flag <<= sbips_int_shift[irq];
10230 + ASSERT(!(flag & ~sbips_int_mask[irq]));
10231 + flag |= R_REG(osh, &sb->sbipsflag) & ~sbips_int_mask[irq];
10232 + W_REG(osh, &sb->sbipsflag, flag);
10233 + }
10234 +}
10235 +
10236 +/*
10237 + * Initializes clocks and interrupts. SB and NVRAM access must be
10238 + * initialized prior to calling.
10239 + *
10240 + * 'shirqmap' enables virtual dedicated OS IRQ mapping if non-zero.
10241 + */
10242 +void
10243 +BCMINITFN(sb_mips_init)(sb_t *sbh, uint shirqmap)
10244 +{
10245 + osl_t *osh;
10246 + ulong hz, ns, tmp;
10247 + extifregs_t *eir;
10248 + chipcregs_t *cc;
10249 + char *value;
10250 + uint irq;
10251 +
10252 + osh = sb_osh(sbh);
10253 +
10254 + /* Figure out current SB clock speed */
10255 + if ((hz = sb_clock(sbh)) == 0)
10256 + hz = 100000000;
10257 + ns = 1000000000 / hz;
10258 +
10259 + /* Setup external interface timing */
10260 + if ((eir = sb_setcore(sbh, SB_EXTIF, 0))) {
10261 + /* Initialize extif so we can get to the LEDs and external UART */
10262 + W_REG(osh, &eir->prog_config, CF_EN);
10263 +
10264 + /* Set timing for the flash */
10265 + tmp = CEIL(10, ns) << FW_W3_SHIFT; /* W3 = 10nS */
10266 + tmp = tmp | (CEIL(40, ns) << FW_W1_SHIFT); /* W1 = 40nS */
10267 + tmp = tmp | CEIL(120, ns); /* W0 = 120nS */
10268 + W_REG(osh, &eir->prog_waitcount, tmp); /* 0x01020a0c for a 100Mhz clock */
10269 +
10270 + /* Set programmable interface timing for external uart */
10271 + tmp = CEIL(10, ns) << FW_W3_SHIFT; /* W3 = 10nS */
10272 + tmp = tmp | (CEIL(20, ns) << FW_W2_SHIFT); /* W2 = 20nS */
10273 + tmp = tmp | (CEIL(100, ns) << FW_W1_SHIFT); /* W1 = 100nS */
10274 + tmp = tmp | CEIL(120, ns); /* W0 = 120nS */
10275 + W_REG(osh, &eir->prog_waitcount, tmp); /* 0x01020a0c for a 100Mhz clock */
10276 + } else if ((cc = sb_setcore(sbh, SB_CC, 0))) {
10277 + /* Set timing for the flash */
10278 + tmp = CEIL(10, ns) << FW_W3_SHIFT; /* W3 = 10nS */
10279 + tmp |= CEIL(10, ns) << FW_W1_SHIFT; /* W1 = 10nS */
10280 + tmp |= CEIL(120, ns); /* W0 = 120nS */
10281 + if ((sb_corerev(sbh) < 9) ||
10282 + (BCMINIT(sb_chip)(sbh) == 0x5365))
10283 + W_REG(osh, &cc->flash_waitcount, tmp);
10284 +
10285 + if ((sb_corerev(sbh) < 9) ||
10286 + ((sb_chip(sbh) == BCM5350_CHIP_ID) && sb_chiprev(sbh) == 0) ||
10287 + (BCMINIT(sb_chip)(sbh) == 0x5365)) {
10288 + W_REG(osh, &cc->pcmcia_memwait, tmp);
10289 + }
10290 +
10291 + /* Save shared IRQ mapping base */
10292 + shirq_map_base = shirqmap;
10293 + }
10294 +
10295 + /* Chip specific initialization */
10296 + switch (sb_chip(sbh)) {
10297 + case BCM4710_CHIP_ID:
10298 + /* Clear interrupt map */
10299 + for (irq = 0; irq <= 4; irq++)
10300 + sb_clearirq(sbh, irq);
10301 + sb_setirq(sbh, 0, SB_CODEC, 0);
10302 + sb_setirq(sbh, 0, SB_EXTIF, 0);
10303 + sb_setirq(sbh, 2, SB_ENET, 1);
10304 + sb_setirq(sbh, 3, SB_ILINE20, 0);
10305 + sb_setirq(sbh, 4, SB_PCI, 0);
10306 + ASSERT(eir);
10307 + value = nvram_get("et0phyaddr");
10308 + if (value && !strcmp(value, "31")) {
10309 + /* Enable internal UART */
10310 + W_REG(osh, &eir->corecontrol, CC_UE);
10311 + /* Give USB its own interrupt */
10312 + sb_setirq(sbh, 1, SB_USB, 0);
10313 + } else {
10314 + /* Disable internal UART */
10315 + W_REG(osh, &eir->corecontrol, 0);
10316 + /* Give Ethernet its own interrupt */
10317 + sb_setirq(sbh, 1, SB_ENET, 0);
10318 + sb_setirq(sbh, 0, SB_USB, 0);
10319 + }
10320 + break;
10321 + case BCM5350_CHIP_ID:
10322 + /* Clear interrupt map */
10323 + for (irq = 0; irq <= 4; irq++)
10324 + sb_clearirq(sbh, irq);
10325 + sb_setirq(sbh, 0, SB_CC, 0);
10326 + sb_setirq(sbh, 0, SB_MIPS33, 0);
10327 + sb_setirq(sbh, 1, SB_D11, 0);
10328 + sb_setirq(sbh, 2, SB_ENET, 0);
10329 + sb_setirq(sbh, 3, SB_PCI, 0);
10330 + sb_setirq(sbh, 4, SB_USB, 0);
10331 + break;
10332 + case BCM4785_CHIP_ID:
10333 + /* Reassign PCI to irq 4 */
10334 + sb_setirq(sbh, 4, SB_PCI, 0);
10335 + break;
10336 + }
10337 +}
10338 +
10339 +uint32
10340 +BCMINITFN(sb_cpu_clock)(sb_t *sbh)
10341 +{
10342 + extifregs_t *eir;
10343 + chipcregs_t *cc;
10344 + uint32 n, m;
10345 + uint idx;
10346 + uint32 pll_type, rate = 0;
10347 +
10348 + /* get index of the current core */
10349 + idx = sb_coreidx(sbh);
10350 + pll_type = PLL_TYPE1;
10351 +
10352 + /* switch to extif or chipc core */
10353 + if ((eir = (extifregs_t *) sb_setcore(sbh, SB_EXTIF, 0))) {
10354 + n = R_REG(osh, &eir->clockcontrol_n);
10355 + m = R_REG(osh, &eir->clockcontrol_sb);
10356 + } else if ((cc = (chipcregs_t *) sb_setcore(sbh, SB_CC, 0))) {
10357 + pll_type = R_REG(osh, &cc->capabilities) & CAP_PLL_MASK;
10358 + n = R_REG(osh, &cc->clockcontrol_n);
10359 + if ((pll_type == PLL_TYPE2) ||
10360 + (pll_type == PLL_TYPE4) ||
10361 + (pll_type == PLL_TYPE6) ||
10362 + (pll_type == PLL_TYPE7))
10363 + m = R_REG(osh, &cc->clockcontrol_m3);
10364 + else if (pll_type == PLL_TYPE5) {
10365 + rate = 200000000;
10366 + goto out;
10367 + }
10368 + else if (pll_type == PLL_TYPE3) {
10369 + if (sb_chip(sbh) == BCM5365_CHIP_ID) {
10370 + rate = 200000000;
10371 + goto out;
10372 + }
10373 + /* 5350 uses m2 to control mips */
10374 + else
10375 + m = R_REG(osh, &cc->clockcontrol_m2);
10376 + } else
10377 + m = R_REG(osh, &cc->clockcontrol_sb);
10378 + } else
10379 + goto out;
10380 +
10381 +
10382 + /* calculate rate */
10383 + if (BCMINIT(sb_chip)(sbh) == 0x5365)
10384 + rate = 100000000;
10385 + else
10386 + rate = sb_clock_rate(pll_type, n, m);
10387 +
10388 + if (pll_type == PLL_TYPE6)
10389 + rate = SB2MIPS_T6(rate);
10390 +
10391 +out:
10392 + /* switch back to previous core */
10393 + sb_setcoreidx(sbh, idx);
10394 +
10395 + return rate;
10396 +}
10397 +
10398 +#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4)
10399 +
10400 +static void
10401 +BCMINITFN(handler)(void)
10402 +{
10403 + __asm__(
10404 + ".set\tmips32\n\t"
10405 + "ssnop\n\t"
10406 + "ssnop\n\t"
10407 + /* Disable interrupts */
10408 + /* MTC0(C0_STATUS, 0, MFC0(C0_STATUS, 0) & ~(ALLINTS | STO_IE)); */
10409 + "mfc0 $15, $12\n\t"
10410 + /* Just a Hack to not to use reg 'at' which was causing problems on 4704 A2 */
10411 + "li $14, -31746\n\t"
10412 + "and $15, $15, $14\n\t"
10413 + "mtc0 $15, $12\n\t"
10414 + "eret\n\t"
10415 + "nop\n\t"
10416 + "nop\n\t"
10417 + ".set\tmips0");
10418 +}
10419 +
10420 +/* The following MUST come right after handler() */
10421 +static void
10422 +BCMINITFN(afterhandler)(void)
10423 +{
10424 +}
10425 +
10426 +/*
10427 + * Set the MIPS, backplane and PCI clocks as closely as possible.
10428 + *
10429 + * MIPS clocks synchronization function has been moved from PLL in chipcommon
10430 + * core rev. 15 to a DLL inside the MIPS core in 4785.
10431 + */
10432 +bool
10433 +BCMINITFN(sb_mips_setclock)(sb_t *sbh, uint32 mipsclock, uint32 sbclock, uint32 pciclock)
10434 +{
10435 + extifregs_t *eir = NULL;
10436 + chipcregs_t *cc = NULL;
10437 + mipsregs_t *mipsr = NULL;
10438 + volatile uint32 *clockcontrol_n, *clockcontrol_sb, *clockcontrol_pci, *clockcontrol_m2;
10439 + uint32 orig_n, orig_sb, orig_pci, orig_m2, orig_mips, orig_ratio_parm, orig_ratio_cfg;
10440 + uint32 pll_type, sync_mode;
10441 + uint ic_size, ic_lsize;
10442 + uint idx, i;
10443 +
10444 + /* PLL configuration: type 1 */
10445 + typedef struct {
10446 + uint32 mipsclock;
10447 + uint16 n;
10448 + uint32 sb;
10449 + uint32 pci33;
10450 + uint32 pci25;
10451 + } n3m_table_t;
10452 + static n3m_table_t BCMINITDATA(type1_table)[] = {
10453 + /* 96.000 32.000 24.000 */
10454 + { 96000000, 0x0303, 0x04020011, 0x11030011, 0x11050011 },
10455 + /* 100.000 33.333 25.000 */
10456 + { 100000000, 0x0009, 0x04020011, 0x11030011, 0x11050011 },
10457 + /* 104.000 31.200 24.960 */
10458 + { 104000000, 0x0802, 0x04020011, 0x11050009, 0x11090009 },
10459 + /* 108.000 32.400 24.923 */
10460 + { 108000000, 0x0403, 0x04020011, 0x11050009, 0x02000802 },
10461 + /* 112.000 32.000 24.889 */
10462 + { 112000000, 0x0205, 0x04020011, 0x11030021, 0x02000403 },
10463 + /* 115.200 32.000 24.000 */
10464 + { 115200000, 0x0303, 0x04020009, 0x11030011, 0x11050011 },
10465 + /* 120.000 30.000 24.000 */
10466 + { 120000000, 0x0011, 0x04020011, 0x11050011, 0x11090011 },
10467 + /* 124.800 31.200 24.960 */
10468 + { 124800000, 0x0802, 0x04020009, 0x11050009, 0x11090009 },
10469 + /* 128.000 32.000 24.000 */
10470 + { 128000000, 0x0305, 0x04020011, 0x11050011, 0x02000305 },
10471 + /* 132.000 33.000 24.750 */
10472 + { 132000000, 0x0603, 0x04020011, 0x11050011, 0x02000305 },
10473 + /* 136.000 32.640 24.727 */
10474 + { 136000000, 0x0c02, 0x04020011, 0x11090009, 0x02000603 },
10475 + /* 140.000 30.000 24.706 */
10476 + { 140000000, 0x0021, 0x04020011, 0x11050021, 0x02000c02 },
10477 + /* 144.000 30.857 24.686 */
10478 + { 144000000, 0x0405, 0x04020011, 0x01020202, 0x11090021 },
10479 + /* 150.857 33.000 24.000 */
10480 + { 150857142, 0x0605, 0x04020021, 0x02000305, 0x02000605 },
10481 + /* 152.000 32.571 24.000 */
10482 + { 152000000, 0x0e02, 0x04020011, 0x11050021, 0x02000e02 },
10483 + /* 156.000 31.200 24.960 */
10484 + { 156000000, 0x0802, 0x04020005, 0x11050009, 0x11090009 },
10485 + /* 160.000 32.000 24.000 */
10486 + { 160000000, 0x0309, 0x04020011, 0x11090011, 0x02000309 },
10487 + /* 163.200 32.640 24.727 */
10488 + { 163200000, 0x0c02, 0x04020009, 0x11090009, 0x02000603 },
10489 + /* 168.000 32.000 24.889 */
10490 + { 168000000, 0x0205, 0x04020005, 0x11030021, 0x02000403 },
10491 + /* 176.000 33.000 24.000 */
10492 + { 176000000, 0x0602, 0x04020003, 0x11050005, 0x02000602 },
10493 + };
10494 +
10495 + /* PLL configuration: type 3 */
10496 + typedef struct {
10497 + uint32 mipsclock;
10498 + uint16 n;
10499 + uint32 m2; /* that is the clockcontrol_m2 */
10500 + } type3_table_t;
10501 + static type3_table_t type3_table[] = {
10502 + /* for 5350, mips clock is always double sb clock */
10503 + { 150000000, 0x311, 0x4020005 },
10504 + { 200000000, 0x311, 0x4020003 },
10505 + };
10506 +
10507 + /* PLL configuration: type 2, 4, 7 */
10508 + typedef struct {
10509 + uint32 mipsclock;
10510 + uint32 sbclock;
10511 + uint16 n;
10512 + uint32 sb;
10513 + uint32 pci33;
10514 + uint32 m2;
10515 + uint32 m3;
10516 + uint32 ratio_cfg;
10517 + uint32 ratio_parm;
10518 + uint32 d11_r1;
10519 + uint32 d11_r2;
10520 + } n4m_table_t;
10521 + static n4m_table_t BCMINITDATA(type2_table)[] = {
10522 + { 120000000, 60000000, 0x0303, 0x01000200, 0x01000600, 0x01000200, 0x05000200, 11,
10523 + 0x0aaa0555, 8 /* ratio 4/8 */, 0x00aa0055 },
10524 + { 150000000, 75000000, 0x0303, 0x01000100, 0x01000600, 0x01000100, 0x05000100, 11,
10525 + 0x0aaa0555, 8 /* ratio 4/8 */, 0x00aa0055 },
10526 + { 180000000, 80000000, 0x0403, 0x01010000, 0x01020300, 0x01020600, 0x05000100, 8,
10527 + 0x012a00a9, 9 /* ratio 4/9 */, 0x012a00a9 },
10528 + { 180000000, 90000000, 0x0403, 0x01000100, 0x01020300, 0x01000100, 0x05000100, 11,
10529 + 0x0aaa0555, 8 /* ratio 4/8 */, 0x00aa0055 },
10530 + { 200000000, 100000000, 0x0303, 0x02010000, 0x02040001, 0x02010000, 0x06000001, 11,
10531 + 0x0aaa0555, 8 /* ratio 4/8 */, 0x00aa0055 },
10532 + { 211200000, 105600000, 0x0902, 0x01000200, 0x01030400, 0x01000200, 0x05000200, 11,
10533 + 0x0aaa0555, 8 /* ratio 4/8 */, 0x00aa0055 },
10534 + { 220800000, 110400000, 0x1500, 0x01000200, 0x01030400, 0x01000200, 0x05000200, 11,
10535 + 0x0aaa0555, 8 /* ratio 4/8 */, 0x00aa0055 },
10536 + { 230400000, 115200000, 0x0604, 0x01000200, 0x01020600, 0x01000200, 0x05000200, 11,
10537 + 0x0aaa0555, 8 /* ratio 4/8 */, 0x00aa0055 },
10538 + { 234000000, 104000000, 0x0b01, 0x01010000, 0x01010700, 0x01020600, 0x05000100, 8,
10539 + 0x012a00a9, 9 /* ratio 4/9 */, 0x012a00a9 },
10540 + { 240000000, 120000000, 0x0803, 0x01000200, 0x01020600, 0x01000200, 0x05000200, 11,
10541 + 0x0aaa0555, 8 /* ratio 4/8 */, 0x00aa0055 },
10542 + { 252000000, 126000000, 0x0504, 0x01000100, 0x01020500, 0x01000100, 0x05000100, 11,
10543 + 0x0aaa0555, 8 /* ratio 4/8 */, 0x00aa0055 },
10544 + { 264000000, 132000000, 0x0903, 0x01000200, 0x01020700, 0x01000200, 0x05000200, 11,
10545 + 0x0aaa0555, 8 /* ratio 4/8 */, 0x00aa0055 },
10546 + { 270000000, 120000000, 0x0703, 0x01010000, 0x01030400, 0x01020600, 0x05000100, 8,
10547 + 0x012a00a9, 9 /* ratio 4/9 */, 0x012a00a9 },
10548 + { 276000000, 122666666, 0x1500, 0x01010000, 0x01030400, 0x01020600, 0x05000100, 8,
10549 + 0x012a00a9, 9 /* ratio 4/9 */, 0x012a00a9 },
10550 + { 280000000, 140000000, 0x0503, 0x01000000, 0x01010600, 0x01000000, 0x05000000, 11,
10551 + 0x0aaa0555, 8 /* ratio 4/8 */, 0x00aa0055 },
10552 + { 288000000, 128000000, 0x0604, 0x01010000, 0x01030400, 0x01020600, 0x05000100, 8,
10553 + 0x012a00a9, 9 /* ratio 4/9 */, 0x012a00a9 },
10554 + { 288000000, 144000000, 0x0404, 0x01000000, 0x01010600, 0x01000000, 0x05000000, 11,
10555 + 0x0aaa0555, 8 /* ratio 4/8 */, 0x00aa0055 },
10556 + { 300000000, 133333333, 0x0803, 0x01010000, 0x01020600, 0x01010100, 0x05000100, 8,
10557 + 0x012a00a9, 9 /* ratio 4/9 */, 0x012a00a9 },
10558 + { 300000000, 150000000, 0x0803, 0x01000100, 0x01020600, 0x01010100, 0x05000100, 11,
10559 + 0x0aaa0555, 8 /* ratio 4/8 */, 0x00aa0055 },
10560 + { 330000000, 132000000, 0x0903, 0x01000200, 0x00020200, 0x01010100, 0x05000100, 0,
10561 + 0, 10 /* ratio 4/10 */, 0x02520129 },
10562 + { 330000000, 146666666, 0x0903, 0x01010000, 0x00020200, 0x01010100, 0x05000100, 0,
10563 + 0, 9 /* ratio 4/9 */, 0x012a00a9 },
10564 + { 330000000, 165000000, 0x0903, 0x01000100, 0x00020200, 0x01010100, 0x05000100, 0,
10565 + 0, 8 /* ratio 4/8 */, 0x00aa0055 },
10566 + { 360000000, 120000000, 0x0a03, 0x01000300, 0x00010201, 0x01010200, 0x05000100, 0,
10567 + 0, 12 /* ratio 4/12 */, 0x04920492 },
10568 + { 360000000, 144000000, 0x0a03, 0x01000200, 0x00010201, 0x01010200, 0x05000100, 0,
10569 + 0, 10 /* ratio 4/10 */, 0x02520129 },
10570 + { 360000000, 160000000, 0x0a03, 0x01010000, 0x00010201, 0x01010200, 0x05000100, 0,
10571 + 0, 9 /* ratio 4/9 */, 0x012a00a9 },
10572 + { 360000000, 180000000, 0x0a03, 0x01000100, 0x00010201, 0x01010200, 0x05000100, 0,
10573 + 0, 8 /* ratio 4/8 */, 0x00aa0055 },
10574 + { 390000000, 130000000, 0x0b03, 0x01010100, 0x00020101, 0x01020100, 0x05000100, 0,
10575 + 0, 12 /* ratio 4/12 */, 0x04920492 },
10576 + { 390000000, 156000000, 0x0b03, 0x01000200, 0x00020101, 0x01020100, 0x05000100, 0,
10577 + 0, 10 /* ratio 4/10 */, 0x02520129 },
10578 + { 390000000, 173000000, 0x0b03, 0x01010000, 0x00020101, 0x01020100, 0x05000100, 0,
10579 + 0, 9 /* ratio 4/9 */, 0x012a00a9 },
10580 + { 390000000, 195000000, 0x0b03, 0x01000100, 0x00020101, 0x01020100, 0x05000100, 0,
10581 + 0, 8 /* ratio 4/8 */, 0x00aa0055 },
10582 + };
10583 + static n4m_table_t BCMINITDATA(type4_table)[] = {
10584 + { 120000000, 60000000, 0x0009, 0x11020009, 0x01030203, 0x11020009, 0x04000009, 11,
10585 + 0x0aaa0555 },
10586 + { 150000000, 75000000, 0x0009, 0x11050002, 0x01030203, 0x11050002, 0x04000005, 11,
10587 + 0x0aaa0555 },
10588 + { 192000000, 96000000, 0x0702, 0x04000011, 0x11030011, 0x04000011, 0x04000003, 11,
10589 + 0x0aaa0555 },
10590 + { 198000000, 99000000, 0x0603, 0x11020005, 0x11030011, 0x11020005, 0x04000005, 11,
10591 + 0x0aaa0555 },
10592 + { 200000000, 100000000, 0x0009, 0x04020011, 0x11030011, 0x04020011, 0x04020003, 11,
10593 + 0x0aaa0555 },
10594 + { 204000000, 102000000, 0x0c02, 0x11020005, 0x01030303, 0x11020005, 0x04000005, 11,
10595 + 0x0aaa0555 },
10596 + { 208000000, 104000000, 0x0802, 0x11030002, 0x11090005, 0x11030002, 0x04000003, 11,
10597 + 0x0aaa0555 },
10598 + { 210000000, 105000000, 0x0209, 0x11020005, 0x01030303, 0x11020005, 0x04000005, 11,
10599 + 0x0aaa0555 },
10600 + { 216000000, 108000000, 0x0111, 0x11020005, 0x01030303, 0x11020005, 0x04000005, 11,
10601 + 0x0aaa0555 },
10602 + { 224000000, 112000000, 0x0205, 0x11030002, 0x02002103, 0x11030002, 0x04000003, 11,
10603 + 0x0aaa0555 },
10604 + { 228000000, 101333333, 0x0e02, 0x11030003, 0x11210005, 0x01030305, 0x04000005, 8,
10605 + 0x012a00a9 },
10606 + { 228000000, 114000000, 0x0e02, 0x11020005, 0x11210005, 0x11020005, 0x04000005, 11,
10607 + 0x0aaa0555 },
10608 + { 240000000, 102857143, 0x0109, 0x04000021, 0x01050203, 0x11030021, 0x04000003, 13,
10609 + 0x254a14a9 },
10610 + { 240000000, 120000000, 0x0109, 0x11030002, 0x01050203, 0x11030002, 0x04000003, 11,
10611 + 0x0aaa0555 },
10612 + { 252000000, 100800000, 0x0203, 0x04000009, 0x11050005, 0x02000209, 0x04000002, 9,
10613 + 0x02520129 },
10614 + { 252000000, 126000000, 0x0203, 0x04000005, 0x11050005, 0x04000005, 0x04000002, 11,
10615 + 0x0aaa0555 },
10616 + { 264000000, 132000000, 0x0602, 0x04000005, 0x11050005, 0x04000005, 0x04000002, 11,
10617 + 0x0aaa0555 },
10618 + { 272000000, 116571428, 0x0c02, 0x04000021, 0x02000909, 0x02000221, 0x04000003, 13,
10619 + 0x254a14a9 },
10620 + { 280000000, 120000000, 0x0209, 0x04000021, 0x01030303, 0x02000221, 0x04000003, 13,
10621 + 0x254a14a9 },
10622 + { 288000000, 123428571, 0x0111, 0x04000021, 0x01030303, 0x02000221, 0x04000003, 13,
10623 + 0x254a14a9 },
10624 + { 300000000, 120000000, 0x0009, 0x04000009, 0x01030203, 0x02000902, 0x04000002, 9,
10625 + 0x02520129 },
10626 + { 300000000, 150000000, 0x0009, 0x04000005, 0x01030203, 0x04000005, 0x04000002, 11,
10627 + 0x0aaa0555 }
10628 + };
10629 + static n4m_table_t BCMINITDATA(type7_table)[] = {
10630 + { 183333333, 91666666, 0x0605, 0x04000011, 0x11030011, 0x04000011, 0x04000003, 11,
10631 + 0x0aaa0555 },
10632 + { 187500000, 93750000, 0x0a03, 0x04000011, 0x11030011, 0x04000011, 0x04000003, 11,
10633 + 0x0aaa0555 },
10634 + { 196875000, 98437500, 0x1003, 0x11020005, 0x11050011, 0x11020005, 0x04000005, 11,
10635 + 0x0aaa0555 },
10636 + { 200000000, 100000000, 0x0311, 0x04000011, 0x11030011, 0x04000009, 0x04000003, 11,
10637 + 0x0aaa0555 },
10638 + { 200000000, 100000000, 0x0311, 0x04020011, 0x11030011, 0x04020011, 0x04020003, 11,
10639 + 0x0aaa0555 },
10640 + { 206250000, 103125000, 0x1103, 0x11020005, 0x11050011, 0x11020005, 0x04000005, 11,
10641 + 0x0aaa0555 },
10642 + { 212500000, 106250000, 0x0c05, 0x11020005, 0x01030303, 0x11020005, 0x04000005, 11,
10643 + 0x0aaa0555 },
10644 + { 215625000, 107812500, 0x1203, 0x11090009, 0x11050005, 0x11020005, 0x04000005, 11,
10645 + 0x0aaa0555 },
10646 + { 216666666, 108333333, 0x0805, 0x11020003, 0x11030011, 0x11020003, 0x04000003, 11,
10647 + 0x0aaa0555 },
10648 + { 225000000, 112500000, 0x0d03, 0x11020003, 0x11030011, 0x11020003, 0x04000003, 11,
10649 + 0x0aaa0555 },
10650 + { 233333333, 116666666, 0x0905, 0x11020003, 0x11030011, 0x11020003, 0x04000003, 11,
10651 + 0x0aaa0555 },
10652 + { 237500000, 118750000, 0x0e05, 0x11020005, 0x11210005, 0x11020005, 0x04000005, 11,
10653 + 0x0aaa0555 },
10654 + { 240000000, 120000000, 0x0b11, 0x11020009, 0x11210009, 0x11020009, 0x04000009, 11,
10655 + 0x0aaa0555 },
10656 + { 250000000, 125000000, 0x0f03, 0x11020003, 0x11210003, 0x11020003, 0x04000003, 11,
10657 + 0x0aaa0555 }
10658 + };
10659 +
10660 + ulong start, end, dst;
10661 + bool ret = FALSE;
10662 +
10663 + volatile uint32 *dll_ctrl = (volatile uint32 *)0xff400008;
10664 + volatile uint32 *dll_r1 = (volatile uint32 *)0xff400010;
10665 + volatile uint32 *dll_r2 = (volatile uint32 *)0xff400018;
10666 +
10667 + /* get index of the current core */
10668 + idx = sb_coreidx(sbh);
10669 + clockcontrol_m2 = NULL;
10670 +
10671 + /* switch to extif or chipc core */
10672 + if ((eir = (extifregs_t *) sb_setcore(sbh, SB_EXTIF, 0))) {
10673 + pll_type = PLL_TYPE1;
10674 + clockcontrol_n = &eir->clockcontrol_n;
10675 + clockcontrol_sb = &eir->clockcontrol_sb;
10676 + clockcontrol_pci = &eir->clockcontrol_pci;
10677 + clockcontrol_m2 = &cc->clockcontrol_m2;
10678 + } else if ((cc = (chipcregs_t *) sb_setcore(sbh, SB_CC, 0))) {
10679 + pll_type = R_REG(osh, &cc->capabilities) & CAP_PLL_MASK;
10680 + if (pll_type == PLL_TYPE6) {
10681 + clockcontrol_n = NULL;
10682 + clockcontrol_sb = NULL;
10683 + clockcontrol_pci = NULL;
10684 + } else {
10685 + clockcontrol_n = &cc->clockcontrol_n;
10686 + clockcontrol_sb = &cc->clockcontrol_sb;
10687 + clockcontrol_pci = &cc->clockcontrol_pci;
10688 + clockcontrol_m2 = &cc->clockcontrol_m2;
10689 + }
10690 + } else
10691 + goto done;
10692 +
10693 + if (pll_type == PLL_TYPE6) {
10694 + /* Silence compilers */
10695 + orig_n = orig_sb = orig_pci = 0;
10696 + } else {
10697 + /* Store the current clock register values */
10698 + orig_n = R_REG(osh, clockcontrol_n);
10699 + orig_sb = R_REG(osh, clockcontrol_sb);
10700 + orig_pci = R_REG(osh, clockcontrol_pci);
10701 + }
10702 +
10703 + if (pll_type == PLL_TYPE1) {
10704 + /* Keep the current PCI clock if not specified */
10705 + if (pciclock == 0) {
10706 + pciclock = sb_clock_rate(pll_type, R_REG(osh, clockcontrol_n),
10707 + R_REG(osh, clockcontrol_pci));
10708 + pciclock = (pciclock <= 25000000) ? 25000000 : 33000000;
10709 + }
10710 +
10711 + /* Search for the closest MIPS clock less than or equal to a preferred value */
10712 + for (i = 0; i < ARRAYSIZE(type1_table); i++) {
10713 + ASSERT(type1_table[i].mipsclock ==
10714 + sb_clock_rate(pll_type, type1_table[i].n,
10715 + type1_table[i].sb));
10716 + if (type1_table[i].mipsclock > mipsclock)
10717 + break;
10718 + }
10719 + if (i == 0) {
10720 + ret = FALSE;
10721 + goto done;
10722 + } else {
10723 + ret = TRUE;
10724 + i--;
10725 + }
10726 + ASSERT(type1_table[i].mipsclock <= mipsclock);
10727 +
10728 + /* No PLL change */
10729 + if ((orig_n == type1_table[i].n) &&
10730 + (orig_sb == type1_table[i].sb) &&
10731 + (orig_pci == type1_table[i].pci33))
10732 + goto done;
10733 +
10734 + /* Set the PLL controls */
10735 + W_REG(osh, clockcontrol_n, type1_table[i].n);
10736 + W_REG(osh, clockcontrol_sb, type1_table[i].sb);
10737 + if (pciclock == 25000000)
10738 + W_REG(osh, clockcontrol_pci, type1_table[i].pci25);
10739 + else
10740 + W_REG(osh, clockcontrol_pci, type1_table[i].pci33);
10741 +
10742 + /* Reset */
10743 + sb_watchdog(sbh, 1);
10744 + while (1);
10745 + } else if (pll_type == PLL_TYPE3) {
10746 + /* 5350 */
10747 + if (sb_chip(sbh) != BCM5365_CHIP_ID) {
10748 + /*
10749 + * Search for the closest MIPS clock less than or equal to
10750 + * a preferred value.
10751 + */
10752 + for (i = 0; i < ARRAYSIZE(type3_table); i++) {
10753 + if (type3_table[i].mipsclock > mipsclock)
10754 + break;
10755 + }
10756 + if (i == 0) {
10757 + ret = FALSE;
10758 + goto done;
10759 + } else {
10760 + ret = TRUE;
10761 + i--;
10762 + }
10763 + ASSERT(type3_table[i].mipsclock <= mipsclock);
10764 +
10765 + /* No PLL change */
10766 + orig_m2 = R_REG(osh, &cc->clockcontrol_m2);
10767 + if ((orig_n == type3_table[i].n) &&
10768 + (orig_m2 == type3_table[i].m2)) {
10769 + goto done;
10770 + }
10771 +
10772 + /* Set the PLL controls */
10773 + W_REG(osh, clockcontrol_n, type3_table[i].n);
10774 + W_REG(osh, clockcontrol_m2, type3_table[i].m2);
10775 +
10776 + /* Reset */
10777 + sb_watchdog(sbh, 1);
10778 + while (1);
10779 + }
10780 + } else if ((pll_type == PLL_TYPE2) ||
10781 + (pll_type == PLL_TYPE4) ||
10782 + (pll_type == PLL_TYPE6) ||
10783 + (pll_type == PLL_TYPE7)) {
10784 + n4m_table_t *table = NULL, *te;
10785 + uint tabsz = 0;
10786 +
10787 + ASSERT(cc);
10788 +
10789 + orig_mips = R_REG(osh, &cc->clockcontrol_m3);
10790 +
10791 + switch (pll_type) {
10792 + case PLL_TYPE6: {
10793 + uint32 new_mips = 0;
10794 +
10795 + ret = TRUE;
10796 + if (mipsclock <= SB2MIPS_T6(CC_T6_M1))
10797 + new_mips = CC_T6_MMASK;
10798 +
10799 + if (orig_mips == new_mips)
10800 + goto done;
10801 +
10802 + W_REG(osh, &cc->clockcontrol_m3, new_mips);
10803 + goto end_fill;
10804 + }
10805 + case PLL_TYPE2:
10806 + table = type2_table;
10807 + tabsz = ARRAYSIZE(type2_table);
10808 + break;
10809 + case PLL_TYPE4:
10810 + table = type4_table;
10811 + tabsz = ARRAYSIZE(type4_table);
10812 + break;
10813 + case PLL_TYPE7:
10814 + table = type7_table;
10815 + tabsz = ARRAYSIZE(type7_table);
10816 + break;
10817 + default:
10818 + ASSERT("No table for plltype" == NULL);
10819 + break;
10820 + }
10821 +
10822 + /* Store the current clock register values */
10823 + orig_m2 = R_REG(osh, &cc->clockcontrol_m2);
10824 + orig_ratio_parm = 0;
10825 + orig_ratio_cfg = 0;
10826 +
10827 + /* Look up current ratio */
10828 + for (i = 0; i < tabsz; i++) {
10829 + if ((orig_n == table[i].n) &&
10830 + (orig_sb == table[i].sb) &&
10831 + (orig_pci == table[i].pci33) &&
10832 + (orig_m2 == table[i].m2) &&
10833 + (orig_mips == table[i].m3)) {
10834 + orig_ratio_parm = table[i].ratio_parm;
10835 + orig_ratio_cfg = table[i].ratio_cfg;
10836 + break;
10837 + }
10838 + }
10839 +
10840 + /* Search for the closest MIPS clock greater or equal to a preferred value */
10841 + for (i = 0; i < tabsz; i++) {
10842 + ASSERT(table[i].mipsclock ==
10843 + sb_clock_rate(pll_type, table[i].n, table[i].m3));
10844 + if ((mipsclock <= table[i].mipsclock) &&
10845 + ((sbclock == 0) || (sbclock <= table[i].sbclock)))
10846 + break;
10847 + }
10848 + if (i == tabsz) {
10849 + ret = FALSE;
10850 + goto done;
10851 + } else {
10852 + te = &table[i];
10853 + ret = TRUE;
10854 + }
10855 +
10856 + /* No PLL change */
10857 + if ((orig_n == te->n) &&
10858 + (orig_sb == te->sb) &&
10859 + (orig_pci == te->pci33) &&
10860 + (orig_m2 == te->m2) &&
10861 + (orig_mips == te->m3))
10862 + goto done;
10863 +
10864 + /* Set the PLL controls */
10865 + W_REG(osh, clockcontrol_n, te->n);
10866 + W_REG(osh, clockcontrol_sb, te->sb);
10867 + W_REG(osh, clockcontrol_pci, te->pci33);
10868 + W_REG(osh, &cc->clockcontrol_m2, te->m2);
10869 + W_REG(osh, &cc->clockcontrol_m3, te->m3);
10870 +
10871 + /* Set the chipcontrol bit to change mipsref to the backplane divider if needed */
10872 + if ((pll_type == PLL_TYPE7) && (te->sb != te->m2) &&
10873 + (sb_clock_rate(pll_type, te->n, te->m2) == 120000000))
10874 + W_REG(osh, &cc->chipcontrol,
10875 + R_REG(osh, &cc->chipcontrol) | 0x100);
10876 +
10877 + /* No ratio change */
10878 + if (sb_chip(sbh) != BCM4785_CHIP_ID) {
10879 + if (orig_ratio_parm == te->ratio_parm)
10880 + goto end_fill;
10881 + }
10882 +
10883 + /* Preload the code into the cache */
10884 + icache_probe(MFC0(C0_CONFIG, 1), &ic_size, &ic_lsize);
10885 + if (sb_chip(sbh) == BCM4785_CHIP_ID) {
10886 + start = ((ulong) &&start_fill_4785) & ~(ic_lsize - 1);
10887 + end = ((ulong) &&end_fill_4785 + (ic_lsize - 1)) & ~(ic_lsize - 1);
10888 + }
10889 + else {
10890 + start = ((ulong) &&start_fill) & ~(ic_lsize - 1);
10891 + end = ((ulong) &&end_fill + (ic_lsize - 1)) & ~(ic_lsize - 1);
10892 + }
10893 + while (start < end) {
10894 + cache_op(start, Fill_I);
10895 + start += ic_lsize;
10896 + }
10897 +
10898 + /* Copy the handler */
10899 + start = (ulong) &handler;
10900 + end = (ulong) &afterhandler;
10901 + dst = KSEG1ADDR(0x180);
10902 + for (i = 0; i < (end - start); i += 4)
10903 + *((ulong *)(dst + i)) = *((ulong *)(start + i));
10904 +
10905 + /* Preload the handler into the cache one line at a time */
10906 + for (i = 0; i < (end - start); i += ic_lsize)
10907 + cache_op(dst + i, Fill_I);
10908 +
10909 + /* Clear BEV bit */
10910 + MTC0(C0_STATUS, 0, MFC0(C0_STATUS, 0) & ~ST0_BEV);
10911 +
10912 + /* Enable interrupts */
10913 + MTC0(C0_STATUS, 0, MFC0(C0_STATUS, 0) | (ALLINTS | ST0_IE));
10914 +
10915 + /* 4785 clock freq change procedures */
10916 + if (sb_chip(sbh) == BCM4785_CHIP_ID) {
10917 + start_fill_4785:
10918 + /* Switch to async */
10919 + MTC0(C0_BROADCOM, 4, (1 << 22));
10920 +
10921 + /* Set clock ratio in MIPS */
10922 + *dll_r1 = (*dll_r1 & 0xfffffff0) | (te->d11_r1 - 1);
10923 + *dll_r2 = te->d11_r2;
10924 +
10925 + /* Enable new settings in MIPS */
10926 + *dll_r1 = *dll_r1 | 0xc0000000;
10927 +
10928 + /* Set active cfg */
10929 + MTC0(C0_BROADCOM, 2, MFC0(C0_BROADCOM, 2) | (1 << 3) | 1);
10930 +
10931 + /* Fake soft reset (clock cfg registers not reset) */
10932 + MTC0(C0_BROADCOM, 5, MFC0(C0_BROADCOM, 5) | (1 << 2));
10933 +
10934 + /* Clear active cfg */
10935 + MTC0(C0_BROADCOM, 2, MFC0(C0_BROADCOM, 2) & ~(1 << 3));
10936 +
10937 + /* set watchdog timer */
10938 + W_REG(osh, &cc->watchdog, 20);
10939 + (void) R_REG(osh, &cc->chipid);
10940 +
10941 + /* wait for timer interrupt */
10942 + __asm__ __volatile__(
10943 + ".set\tmips3\n\t"
10944 + "sync\n\t"
10945 + "wait\n\t"
10946 + ".set\tmips0");
10947 + end_fill_4785:
10948 + while (1);
10949 + }
10950 + /* Generic clock freq change procedures */
10951 + else {
10952 + /* Enable MIPS timer interrupt */
10953 + if (!(mipsr = sb_setcore(sbh, SB_MIPS, 0)) &&
10954 + !(mipsr = sb_setcore(sbh, SB_MIPS33, 0)))
10955 + ASSERT(mipsr);
10956 + W_REG(osh, &mipsr->intmask, 1);
10957 +
10958 + start_fill:
10959 + /* step 1, set clock ratios */
10960 + MTC0(C0_BROADCOM, 3, te->ratio_parm);
10961 + MTC0(C0_BROADCOM, 1, te->ratio_cfg);
10962 +
10963 + /* step 2: program timer intr */
10964 + W_REG(osh, &mipsr->timer, 100);
10965 + (void) R_REG(osh, &mipsr->timer);
10966 +
10967 + /* step 3, switch to async */
10968 + sync_mode = MFC0(C0_BROADCOM, 4);
10969 + MTC0(C0_BROADCOM, 4, 1 << 22);
10970 +
10971 + /* step 4, set cfg active */
10972 + MTC0(C0_BROADCOM, 2, (1 << 3) | 1);
10973 +
10974 + /* steps 5 & 6 */
10975 + __asm__ __volatile__(
10976 + ".set\tmips3\n\t"
10977 + "wait\n\t"
10978 + ".set\tmips0");
10979 +
10980 + /* step 7, clear cfg active */
10981 + MTC0(C0_BROADCOM, 2, 0);
10982 +
10983 + /* Additional Step: set back to orig sync mode */
10984 + MTC0(C0_BROADCOM, 4, sync_mode);
10985 +
10986 + /* step 8, fake soft reset */
10987 + MTC0(C0_BROADCOM, 5, MFC0(C0_BROADCOM, 5) | (1 << 2));
10988 +
10989 + end_fill:
10990 + /* set watchdog timer */
10991 + W_REG(osh, &cc->watchdog, 20);
10992 + (void) R_REG(osh, &cc->chipid);
10993 +
10994 + /* wait for timer interrupt */
10995 + __asm__ __volatile__(
10996 + ".set\tmips3\n\t"
10997 + "sync\n\t"
10998 + "wait\n\t"
10999 + ".set\tmips0");
11000 + while (1);
11001 + }
11002 + }
11003 +
11004 +done:
11005 + /* Enable 4785 DLL */
11006 + if (sb_chip(sbh) == BCM4785_CHIP_ID) {
11007 + uint32 tmp;
11008 +
11009 + /* set mask to 1e, enable DLL (bit 0) */
11010 + *dll_ctrl |= 0x0041e021;
11011 +
11012 + /* enable aggressive hardware mode */
11013 + *dll_ctrl |= 0x00000080;
11014 +
11015 + /* wait for lock flag to clear */
11016 + while ((*dll_ctrl & 0x2) == 0);
11017 +
11018 + /* clear sticky flags (clear on write 1) */
11019 + tmp = *dll_ctrl;
11020 + *dll_ctrl = tmp;
11021 +
11022 + /* set mask to 5b'10001 */
11023 + *dll_ctrl = (*dll_ctrl & 0xfffc1fff) | 0x00022000;
11024 +
11025 + /* enable sync mode */
11026 + MTC0(C0_BROADCOM, 4, MFC0(C0_BROADCOM, 4) & 0xfe3fffff);
11027 + (void)MFC0(C0_BROADCOM, 4);
11028 + }
11029 +
11030 + /* switch back to previous core */
11031 + sb_setcoreidx(sbh, idx);
11032 +
11033 + return ret;
11034 +}
11035 +
11036 +void
11037 +BCMINITFN(enable_pfc)(uint32 mode)
11038 +{
11039 + ulong start, end;
11040 + uint ic_size, ic_lsize;
11041 +
11042 + /* If auto then choose the correct mode for this
11043 + * platform, currently we only ever select one mode
11044 + */
11045 + if (mode == PFC_AUTO)
11046 + mode = PFC_INST;
11047 +
11048 + icache_probe(MFC0(C0_CONFIG, 1), &ic_size, &ic_lsize);
11049 +
11050 + /* enable prefetch cache if available */
11051 + if (MFC0(C0_BROADCOM, 0) & BRCM_PFC_AVAIL) {
11052 + start = ((ulong) &&setpfc_start) & ~(ic_lsize - 1);
11053 + end = ((ulong) &&setpfc_end + (ic_lsize - 1)) & ~(ic_lsize - 1);
11054 +
11055 + /* Preload setpfc code into the cache one line at a time */
11056 + while (start < end) {
11057 + cache_op(start, Fill_I);
11058 + start += ic_lsize;
11059 + }
11060 +
11061 + /* Now set the pfc */
11062 + setpfc_start:
11063 + /* write range */
11064 + *(volatile uint32 *)PFC_CR1 = 0xffff0000;
11065 +
11066 + /* enable */
11067 + *(volatile uint32 *)PFC_CR0 = mode;
11068 + setpfc_end:
11069 + /* Compiler foder */
11070 + ic_size = 0;
11071 + }
11072 +}
11073 +
11074 +/* returns the ncdl value to be programmed into sdram_ncdl for calibration */
11075 +uint32
11076 +BCMINITFN(sb_memc_get_ncdl)(sb_t *sbh)
11077 +{
11078 + osl_t *osh;
11079 + sbmemcregs_t *memc;
11080 + uint32 ret = 0;
11081 + uint32 config, rd, wr, misc, dqsg, cd, sm, sd;
11082 + uint idx, rev;
11083 +
11084 + osh = sb_osh(sbh);
11085 +
11086 + idx = sb_coreidx(sbh);
11087 +
11088 + memc = (sbmemcregs_t *)sb_setcore(sbh, SB_MEMC, 0);
11089 + if (memc == 0)
11090 + goto out;
11091 +
11092 + rev = sb_corerev(sbh);
11093 +
11094 + config = R_REG(osh, &memc->config);
11095 + wr = R_REG(osh, &memc->wrncdlcor);
11096 + rd = R_REG(osh, &memc->rdncdlcor);
11097 + misc = R_REG(osh, &memc->miscdlyctl);
11098 + dqsg = R_REG(osh, &memc->dqsgatencdl);
11099 +
11100 + rd &= MEMC_RDNCDLCOR_RD_MASK;
11101 + wr &= MEMC_WRNCDLCOR_WR_MASK;
11102 + dqsg &= MEMC_DQSGATENCDL_G_MASK;
11103 +
11104 + if (config & MEMC_CONFIG_DDR) {
11105 + ret = (wr << 16) | (rd << 8) | dqsg;
11106 + } else {
11107 + if (rev > 0)
11108 + cd = rd;
11109 + else
11110 + cd = (rd == MEMC_CD_THRESHOLD) ? rd : (wr + MEMC_CD_THRESHOLD);
11111 + sm = (misc & MEMC_MISC_SM_MASK) >> MEMC_MISC_SM_SHIFT;
11112 + sd = (misc & MEMC_MISC_SD_MASK) >> MEMC_MISC_SD_SHIFT;
11113 + ret = (sm << 16) | (sd << 8) | cd;
11114 + }
11115 +
11116 +out:
11117 + /* switch back to previous core */
11118 + sb_setcoreidx(sbh, idx);
11119 +
11120 + return ret;
11121 +}
11122 +
11123 +#if defined(BCMPERFSTATS)
11124 +/*
11125 + * CP0 Register 25 supports 4 semi-independent 32bit performance counters.
11126 + * $25 select 0, 1, 2, and 3 are the counters. The counters *decrement* (who thought this one up?)
11127 + * $25 select 4 and 5 each contain 2-16bit control fields, one for each of the 4 counters
11128 + * $25 select 6 is the global perf control register.
11129 + */
11130 +/* enable and start instruction counting */
11131 +
11132 +void
11133 +hndmips_perf_instrcount_enable()
11134 +{
11135 + MTC0(C0_PERFORMANCE, 6, 0x80000200); /* global enable perf counters */
11136 + MTC0(C0_PERFORMANCE, 4,
11137 + 0x8044 | MFC0(C0_PERFORMANCE, 4)); /* enable instruction counting for counter 0 */
11138 + MTC0(C0_PERFORMANCE, 0, 0); /* zero counter zero */
11139 +}
11140 +
11141 +/* enable and start I$ hit and I$ miss counting */
11142 +void
11143 +hndmips_perf_icachecount_enable(void)
11144 +{
11145 + MTC0(C0_PERFORMANCE, 6, 0x80000218); /* enable I$ counting */
11146 + MTC0(C0_PERFORMANCE, 4, 0x80148018); /* count I$ hits in cntr 0 and misses in cntr 1 */
11147 + MTC0(C0_PERFORMANCE, 0, 0); /* zero counter 0 - # I$ hits */
11148 + MTC0(C0_PERFORMANCE, 1, 0); /* zero counter 1 - # I$ misses */
11149 +}
11150 +
11151 +/* enable and start D$ hit and I$ miss counting */
11152 +void
11153 +hndmips_perf_dcachecount_enable(void)
11154 +{
11155 + MTC0(C0_PERFORMANCE, 6, 0x80000211); /* enable D$ counting */
11156 + MTC0(C0_PERFORMANCE, 4, 0x80248028); /* count D$ hits in cntr 0 and misses in cntr 1 */
11157 + MTC0(C0_PERFORMANCE, 0, 0); /* zero counter 0 - # D$ hits */
11158 + MTC0(C0_PERFORMANCE, 1, 0); /* zero counter 1 - # D$ misses */
11159 +}
11160 +
11161 +void
11162 +hndmips_perf_icache_miss_enable()
11163 +{
11164 + MTC0(C0_PERFORMANCE, 4,
11165 + 0x80140000 | MFC0(C0_PERFORMANCE, 4)); /* enable cache misses counting for counter 1 */
11166 + MTC0(C0_PERFORMANCE, 1, 0); /* zero counter one */
11167 +}
11168 +
11169 +
11170 +void
11171 +hndmips_perf_icache_hit_enable()
11172 +{
11173 + MTC0(C0_PERFORMANCE, 5, 0x8018 | MFC0(C0_PERFORMANCE, 5));
11174 + /* enable cache hits counting for counter 2 */
11175 + MTC0(C0_PERFORMANCE, 2, 0); /* zero counter 2 */
11176 +}
11177 +
11178 +uint32
11179 +hndmips_perf_read_instrcount()
11180 +{
11181 + return -(long)(MFC0(C0_PERFORMANCE, 0));
11182 +}
11183 +
11184 +uint32
11185 +hndmips_perf_read_cache_miss()
11186 +{
11187 + return -(long)(MFC0(C0_PERFORMANCE, 1));
11188 +}
11189 +
11190 +uint32
11191 +hndmips_perf_read_cache_hit()
11192 +{
11193 + return -(long)(MFC0(C0_PERFORMANCE, 2));
11194 +}
11195 +
11196 +#endif /* BCMINTERNAL | BCMPERFSTATS */
11197 diff -urN linux.old/arch/mips/bcm947xx/sbpci.c linux.dev/arch/mips/bcm947xx/sbpci.c
11198 --- linux.old/arch/mips/bcm947xx/sbpci.c 1970-01-01 01:00:00.000000000 +0100
11199 +++ linux.dev/arch/mips/bcm947xx/sbpci.c 2006-10-02 21:19:59.000000000 +0200
11200 @@ -0,0 +1,768 @@
11201 +/*
11202 + * Low-Level PCI and SB support for BCM47xx
11203 + *
11204 + * Copyright 2006, Broadcom Corporation
11205 + * All Rights Reserved.
11206 + *
11207 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
11208 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
11209 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
11210 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
11211 + *
11212 + * $Id: hndpci.c,v 1.1.1.3 2006/04/08 06:13:39 honor Exp $
11213 + */
11214 +
11215 +#include <typedefs.h>
11216 +#include <osl.h>
11217 +#include <pcicfg.h>
11218 +#include <bcmdevs.h>
11219 +#include <sbconfig.h>
11220 +#include <bcmutils.h>
11221 +#include <sbutils.h>
11222 +#include <sbpci.h>
11223 +#include <bcmendian.h>
11224 +#include <bcmnvram.h>
11225 +#include <hndcpu.h>
11226 +#include <hndmips.h>
11227 +#include <hndpci.h>
11228 +
11229 +/* debug/trace */
11230 +#ifdef BCMDBG_PCI
11231 +#define PCI_MSG(args) printf args
11232 +#else
11233 +#define PCI_MSG(args)
11234 +#endif /* BCMDBG_PCI */
11235 +
11236 +/* Can free sbpci_init() memory after boot */
11237 +#ifndef linux
11238 +#define __init
11239 +#endif /* linux */
11240 +
11241 +/* Emulated configuration space */
11242 +typedef struct {
11243 + int n;
11244 + uint size0;
11245 + uint size1;
11246 + uint size2;
11247 + uint size3;
11248 +} sb_bar_cfg_t;
11249 +static pci_config_regs sb_config_regs[SB_MAXCORES];
11250 +static sb_bar_cfg_t sb_bar_cfg[SB_MAXCORES];
11251 +
11252 +/* Links to emulated and real PCI configuration spaces */
11253 +#define MAXFUNCS 2
11254 +typedef struct {
11255 + pci_config_regs *emu; /* emulated PCI config */
11256 + pci_config_regs *pci; /* real PCI config */
11257 + sb_bar_cfg_t *bar; /* region sizes */
11258 +} sb_pci_cfg_t;
11259 +static sb_pci_cfg_t sb_pci_cfg[SB_MAXCORES][MAXFUNCS];
11260 +
11261 +/* Special emulated config space for non-existing device */
11262 +static pci_config_regs sb_pci_null = { 0xffff, 0xffff };
11263 +
11264 +/* Banned cores */
11265 +static uint16 pci_ban[SB_MAXCORES] = { 0 };
11266 +static uint pci_banned = 0;
11267 +
11268 +/* CardBus mode */
11269 +static bool cardbus = FALSE;
11270 +
11271 +/* Disable PCI host core */
11272 +static bool pci_disabled = FALSE;
11273 +
11274 +/* Host bridge slot #, default to 0 */
11275 +static uint8 pci_hbslot = 0;
11276 +
11277 +/* Internal macros */
11278 +#define PCI_SLOTAD_MAP 16 /* SLOT<n> mapps to AD<n+16> */
11279 +#define PCI_HBSBCFG_REV 8 /* MIN. core rev. required to
11280 + * access host bridge PCI cfg space
11281 + * from SB
11282 + */
11283 +
11284 +/*
11285 + * Functions for accessing external PCI configuration space
11286 + */
11287 +
11288 +/* Assume one-hot slot wiring */
11289 +#define PCI_SLOT_MAX 16 /* Max. PCI Slots */
11290 +
11291 +static uint32
11292 +config_cmd(sb_t *sbh, uint bus, uint dev, uint func, uint off)
11293 +{
11294 + uint coreidx;
11295 + sbpciregs_t *regs;
11296 + uint32 addr = 0;
11297 + osl_t *osh;
11298 +
11299 + /* CardBusMode supports only one device */
11300 + if (cardbus && dev > 1)
11301 + return 0;
11302 +
11303 + osh = sb_osh(sbh);
11304 +
11305 + coreidx = sb_coreidx(sbh);
11306 + regs = (sbpciregs_t *) sb_setcore(sbh, SB_PCI, 0);
11307 +
11308 + /* Type 0 transaction */
11309 + if (bus == 1) {
11310 + /* Skip unwired slots */
11311 + if (dev < PCI_SLOT_MAX) {
11312 + uint32 win;
11313 +
11314 + /* Slide the PCI window to the appropriate slot */
11315 + win = (SBTOPCI_CFG0 | ((1 << (dev + PCI_SLOTAD_MAP)) & SBTOPCI1_MASK));
11316 + W_REG(osh, &regs->sbtopci1, win);
11317 + addr = SB_PCI_CFG |
11318 + ((1 << (dev + PCI_SLOTAD_MAP)) & ~SBTOPCI1_MASK) |
11319 + (func << PCICFG_FUN_SHIFT) |
11320 + (off & ~3);
11321 + }
11322 + } else {
11323 + /* Type 1 transaction */
11324 + W_REG(osh, &regs->sbtopci1, SBTOPCI_CFG1);
11325 + addr = SB_PCI_CFG |
11326 + (bus << PCICFG_BUS_SHIFT) |
11327 + (dev << PCICFG_SLOT_SHIFT) |
11328 + (func << PCICFG_FUN_SHIFT) |
11329 + (off & ~3);
11330 + }
11331 +
11332 + sb_setcoreidx(sbh, coreidx);
11333 +
11334 + return addr;
11335 +}
11336 +
11337 +/*
11338 + * Read host bridge PCI config registers from Silicon Backplane (>=rev8).
11339 + *
11340 + * It returns TRUE to indicate that access to the host bridge's pci config
11341 + * from SB is ok, and values in 'addr' and 'val' are valid.
11342 + *
11343 + * It can only read registers at multiple of 4-bytes. Callers must pick up
11344 + * needed bytes from 'val' based on 'off' value. Value in 'addr' reflects
11345 + * the register address where value in 'val' is read.
11346 + */
11347 +static bool
11348 +sb_pcihb_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off,
11349 + uint32 **addr, uint32 *val)
11350 +{
11351 + sbpciregs_t *regs;
11352 + osl_t *osh;
11353 + uint coreidx;
11354 + bool ret = FALSE;
11355 +
11356 + /* sanity check */
11357 + ASSERT(bus == 1);
11358 + ASSERT(dev == pci_hbslot);
11359 + ASSERT(func == 0);
11360 +
11361 + osh = sb_osh(sbh);
11362 +
11363 + /* read pci config when core rev >= 8 */
11364 + coreidx = sb_coreidx(sbh);
11365 + regs = (sbpciregs_t *)sb_setcore(sbh, SB_PCI, 0);
11366 + if (regs && sb_corerev(sbh) >= PCI_HBSBCFG_REV) {
11367 + *addr = (uint32 *)&regs->pcicfg[func][off >> 2];
11368 + *val = R_REG(osh, *addr);
11369 + ret = TRUE;
11370 + }
11371 + sb_setcoreidx(sbh, coreidx);
11372 +
11373 + return ret;
11374 +}
11375 +
11376 +int
11377 +extpci_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
11378 +{
11379 + uint32 addr = 0, *reg = NULL, val;
11380 + int ret = 0;
11381 +
11382 + /*
11383 + * Set value to -1 when:
11384 + * flag 'pci_disabled' is true;
11385 + * value of 'addr' is zero;
11386 + * REG_MAP() fails;
11387 + * BUSPROBE() fails;
11388 + */
11389 + if (pci_disabled)
11390 + val = 0xffffffff;
11391 + else if (bus == 1 && dev == pci_hbslot && func == 0 &&
11392 + sb_pcihb_read_config(sbh, bus, dev, func, off, &reg, &val))
11393 + ;
11394 + else if (((addr = config_cmd(sbh, bus, dev, func, off)) == 0) ||
11395 + ((reg = (uint32 *)REG_MAP(addr, len)) == 0) ||
11396 + (BUSPROBE(val, reg) != 0))
11397 + val = 0xffffffff;
11398 +
11399 + PCI_MSG(("%s: 0x%x <= 0x%p(0x%x), len %d, off 0x%x, buf 0x%p\n",
11400 + __FUNCTION__, val, reg, addr, len, off, buf));
11401 +
11402 + val >>= 8 * (off & 3);
11403 + if (len == 4)
11404 + *((uint32 *) buf) = val;
11405 + else if (len == 2)
11406 + *((uint16 *) buf) = (uint16) val;
11407 + else if (len == 1)
11408 + *((uint8 *) buf) = (uint8) val;
11409 + else
11410 + ret = -1;
11411 +
11412 + if (reg && addr)
11413 + REG_UNMAP(reg);
11414 +
11415 + return ret;
11416 +}
11417 +
11418 +int
11419 +extpci_write_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
11420 +{
11421 + osl_t *osh;
11422 + uint32 addr = 0, *reg = NULL, val;
11423 + int ret = 0;
11424 +
11425 + osh = sb_osh(sbh);
11426 +
11427 + /*
11428 + * Ignore write attempt when:
11429 + * flag 'pci_disabled' is true;
11430 + * value of 'addr' is zero;
11431 + * REG_MAP() fails;
11432 + * BUSPROBE() fails;
11433 + */
11434 + if (pci_disabled)
11435 + return 0;
11436 + else if (bus == 1 && dev == pci_hbslot && func == 0 &&
11437 + sb_pcihb_read_config(sbh, bus, dev, func, off, &reg, &val))
11438 + ;
11439 + else if (((addr = config_cmd(sbh, bus, dev, func, off)) == 0) ||
11440 + ((reg = (uint32 *) REG_MAP(addr, len)) == 0) ||
11441 + (BUSPROBE(val, reg) != 0))
11442 + goto done;
11443 +
11444 + if (len == 4)
11445 + val = *((uint32 *) buf);
11446 + else if (len == 2) {
11447 + val &= ~(0xffff << (8 * (off & 3)));
11448 + val |= *((uint16 *) buf) << (8 * (off & 3));
11449 + } else if (len == 1) {
11450 + val &= ~(0xff << (8 * (off & 3)));
11451 + val |= *((uint8 *) buf) << (8 * (off & 3));
11452 + } else {
11453 + ret = -1;
11454 + goto done;
11455 + }
11456 +
11457 + PCI_MSG(("%s: 0x%x => 0x%p\n", __FUNCTION__, val, reg));
11458 +
11459 + W_REG(osh, reg, val);
11460 +
11461 +done:
11462 + if (reg && addr)
11463 + REG_UNMAP(reg);
11464 +
11465 + return ret;
11466 +}
11467 +
11468 +/*
11469 + * Must access emulated PCI configuration at these locations even when
11470 + * the real PCI config space exists and is accessible.
11471 + *
11472 + * PCI_CFG_VID (0x00)
11473 + * PCI_CFG_DID (0x02)
11474 + * PCI_CFG_PROGIF (0x09)
11475 + * PCI_CFG_SUBCL (0x0a)
11476 + * PCI_CFG_BASECL (0x0b)
11477 + * PCI_CFG_HDR (0x0e)
11478 + * PCI_CFG_INT (0x3c)
11479 + * PCI_CFG_PIN (0x3d)
11480 + */
11481 +#define FORCE_EMUCFG(off, len) \
11482 + ((off == PCI_CFG_VID) || (off == PCI_CFG_DID) || \
11483 + (off == PCI_CFG_PROGIF) || \
11484 + (off == PCI_CFG_SUBCL) || (off == PCI_CFG_BASECL) || \
11485 + (off == PCI_CFG_HDR) || \
11486 + (off == PCI_CFG_INT) || (off == PCI_CFG_PIN))
11487 +
11488 +/* Sync the emulation registers and the real PCI config registers. */
11489 +static void
11490 +sb_pcid_read_config(sb_t *sbh, uint coreidx, sb_pci_cfg_t *cfg,
11491 + uint off, uint len)
11492 +{
11493 + osl_t *osh;
11494 + uint oldidx;
11495 +
11496 + ASSERT(cfg);
11497 + ASSERT(cfg->emu);
11498 + ASSERT(cfg->pci);
11499 +
11500 + /* decide if real PCI config register access is necessary */
11501 + if (FORCE_EMUCFG(off, len))
11502 + return;
11503 +
11504 + osh = sb_osh(sbh);
11505 +
11506 + /* access to the real pci config space only when the core is up */
11507 + oldidx = sb_coreidx(sbh);
11508 + sb_setcoreidx(sbh, coreidx);
11509 + if (sb_iscoreup(sbh)) {
11510 + if (len == 4)
11511 + *(uint32 *)((ulong)cfg->emu + off) =
11512 + htol32(R_REG(osh, (uint32 *)((ulong)cfg->pci + off)));
11513 + else if (len == 2)
11514 + *(uint16 *)((ulong)cfg->emu + off) =
11515 + htol16(R_REG(osh, (uint16 *)((ulong)cfg->pci + off)));
11516 + else if (len == 1)
11517 + *(uint8 *)((ulong)cfg->emu + off) =
11518 + R_REG(osh, (uint8 *)((ulong)cfg->pci + off));
11519 + }
11520 + sb_setcoreidx(sbh, oldidx);
11521 +}
11522 +
11523 +static void
11524 +sb_pcid_write_config(sb_t *sbh, uint coreidx, sb_pci_cfg_t *cfg,
11525 + uint off, uint len)
11526 +{
11527 + osl_t *osh;
11528 + uint oldidx;
11529 +
11530 + ASSERT(cfg);
11531 + ASSERT(cfg->emu);
11532 + ASSERT(cfg->pci);
11533 +
11534 + osh = sb_osh(sbh);
11535 +
11536 + /* decide if real PCI config register access is necessary */
11537 + if (FORCE_EMUCFG(off, len))
11538 + return;
11539 +
11540 + /* access to the real pci config space only when the core is up */
11541 + oldidx = sb_coreidx(sbh);
11542 + sb_setcoreidx(sbh, coreidx);
11543 + if (sb_iscoreup(sbh)) {
11544 + if (len == 4)
11545 + W_REG(osh, (uint32 *)((ulong)cfg->pci + off),
11546 + ltoh32(*(uint32 *)((ulong)cfg->emu + off)));
11547 + else if (len == 2)
11548 + W_REG(osh, (uint16 *)((ulong)cfg->pci + off),
11549 + ltoh16(*(uint16 *)((ulong)cfg->emu + off)));
11550 + else if (len == 1)
11551 + W_REG(osh, (uint8 *)((ulong)cfg->pci + off),
11552 + *(uint8 *)((ulong)cfg->emu + off));
11553 + }
11554 + sb_setcoreidx(sbh, oldidx);
11555 +}
11556 +
11557 +/*
11558 + * Functions for accessing translated SB configuration space
11559 + */
11560 +static int
11561 +sb_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
11562 +{
11563 + pci_config_regs *cfg;
11564 +
11565 + if (dev >= SB_MAXCORES || func >= MAXFUNCS || (off + len) > sizeof(pci_config_regs))
11566 + return -1;
11567 + cfg = sb_pci_cfg[dev][func].emu;
11568 +
11569 + ASSERT(ISALIGNED(off, len));
11570 + ASSERT(ISALIGNED((uintptr)buf, len));
11571 +
11572 + /* use special config space if the device does not exist */
11573 + if (!cfg)
11574 + cfg = &sb_pci_null;
11575 + /* sync emulation with real PCI config if necessary */
11576 + else if (sb_pci_cfg[dev][func].pci)
11577 + sb_pcid_read_config(sbh, dev, &sb_pci_cfg[dev][func], off, len);
11578 +
11579 + if (len == 4)
11580 + *((uint32 *) buf) = ltoh32(*((uint32 *)((ulong) cfg + off)));
11581 + else if (len == 2)
11582 + *((uint16 *) buf) = ltoh16(*((uint16 *)((ulong) cfg + off)));
11583 + else if (len == 1)
11584 + *((uint8 *) buf) = *((uint8 *)((ulong) cfg + off));
11585 + else
11586 + return -1;
11587 +
11588 + return 0;
11589 +}
11590 +
11591 +static int
11592 +sb_write_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
11593 +{
11594 + uint coreidx;
11595 + void *regs;
11596 + pci_config_regs *cfg;
11597 + osl_t *osh;
11598 + sb_bar_cfg_t *bar;
11599 +
11600 + if (dev >= SB_MAXCORES || func >= MAXFUNCS || (off + len) > sizeof(pci_config_regs))
11601 + return -1;
11602 + cfg = sb_pci_cfg[dev][func].emu;
11603 + if (!cfg)
11604 + return -1;
11605 +
11606 + ASSERT(ISALIGNED(off, len));
11607 + ASSERT(ISALIGNED((uintptr)buf, len));
11608 +
11609 + osh = sb_osh(sbh);
11610 +
11611 + /* Emulate BAR sizing */
11612 + if (off >= OFFSETOF(pci_config_regs, base[0]) &&
11613 + off <= OFFSETOF(pci_config_regs, base[3]) &&
11614 + len == 4 && *((uint32 *) buf) == ~0) {
11615 + coreidx = sb_coreidx(sbh);
11616 + if ((regs = sb_setcoreidx(sbh, dev))) {
11617 + bar = sb_pci_cfg[dev][func].bar;
11618 + /* Highest numbered address match register */
11619 + if (off == OFFSETOF(pci_config_regs, base[0]))
11620 + cfg->base[0] = ~(bar->size0 - 1);
11621 + else if (off == OFFSETOF(pci_config_regs, base[1]) && bar->n >= 1)
11622 + cfg->base[1] = ~(bar->size1 - 1);
11623 + else if (off == OFFSETOF(pci_config_regs, base[2]) && bar->n >= 2)
11624 + cfg->base[2] = ~(bar->size2 - 1);
11625 + else if (off == OFFSETOF(pci_config_regs, base[3]) && bar->n >= 3)
11626 + cfg->base[3] = ~(bar->size3 - 1);
11627 + }
11628 + sb_setcoreidx(sbh, coreidx);
11629 + }
11630 + else if (len == 4)
11631 + *((uint32 *)((ulong) cfg + off)) = htol32(*((uint32 *) buf));
11632 + else if (len == 2)
11633 + *((uint16 *)((ulong) cfg + off)) = htol16(*((uint16 *) buf));
11634 + else if (len == 1)
11635 + *((uint8 *)((ulong) cfg + off)) = *((uint8 *) buf);
11636 + else
11637 + return -1;
11638 +
11639 + /* sync emulation with real PCI config if necessary */
11640 + if (sb_pci_cfg[dev][func].pci)
11641 + sb_pcid_write_config(sbh, dev, &sb_pci_cfg[dev][func], off, len);
11642 +
11643 + return 0;
11644 +}
11645 +
11646 +int
11647 +sbpci_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
11648 +{
11649 + if (bus == 0)
11650 + return sb_read_config(sbh, bus, dev, func, off, buf, len);
11651 + else
11652 + return extpci_read_config(sbh, bus, dev, func, off, buf, len);
11653 +}
11654 +
11655 +int
11656 +sbpci_write_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
11657 +{
11658 + if (bus == 0)
11659 + return sb_write_config(sbh, bus, dev, func, off, buf, len);
11660 + else
11661 + return extpci_write_config(sbh, bus, dev, func, off, buf, len);
11662 +}
11663 +
11664 +void
11665 +sbpci_ban(uint16 core)
11666 +{
11667 + if (pci_banned < ARRAYSIZE(pci_ban))
11668 + pci_ban[pci_banned++] = core;
11669 +}
11670 +
11671 +/*
11672 + * Initiliaze PCI core. Return 0 after a successful initialization.
11673 + * Otherwise return -1 to indicate there is no PCI core and return 1
11674 + * to indicate PCI core is disabled.
11675 + */
11676 +int __init
11677 +sbpci_init_pci(sb_t *sbh)
11678 +{
11679 + uint chip, chiprev, chippkg, host;
11680 + uint32 boardflags;
11681 + sbpciregs_t *pci;
11682 + sbconfig_t *sb;
11683 + uint32 val;
11684 + int ret = 0;
11685 + char *hbslot;
11686 + osl_t *osh;
11687 +
11688 + chip = sb_chip(sbh);
11689 + chiprev = sb_chiprev(sbh);
11690 + chippkg = sb_chippkg(sbh);
11691 +
11692 + osh = sb_osh(sbh);
11693 +
11694 + if (!(pci = (sbpciregs_t *) sb_setcore(sbh, SB_PCI, 0))) {
11695 + printk("PCI: no core\n");
11696 + pci_disabled = TRUE;
11697 + return -1;
11698 + }
11699 +
11700 + if ((chip == 0x4310) && (chiprev == 0))
11701 + pci_disabled = TRUE;
11702 +
11703 + sb = (sbconfig_t *)((ulong) pci + SBCONFIGOFF);
11704 +
11705 + boardflags = (uint32) getintvar(NULL, "boardflags");
11706 +
11707 + /*
11708 + * The 200-pin BCM4712 package does not bond out PCI. Even when
11709 + * PCI is bonded out, some boards may leave the pins
11710 + * floating.
11711 + */
11712 + if (((chip == BCM4712_CHIP_ID) &&
11713 + ((chippkg == BCM4712SMALL_PKG_ID) ||
11714 + (chippkg == BCM4712MID_PKG_ID))) ||
11715 + (boardflags & BFL_NOPCI))
11716 + pci_disabled = TRUE;
11717 +
11718 + /* Enable the core */
11719 + sb_core_reset(sbh, 0, 0);
11720 +
11721 + /*
11722 + * If the PCI core should not be touched (disabled, not bonded
11723 + * out, or pins floating), do not even attempt to access core
11724 + * registers. Otherwise, try to determine if it is in host
11725 + * mode.
11726 + */
11727 + if (pci_disabled)
11728 + host = 0;
11729 + else
11730 + host = !BUSPROBE(val, &pci->control);
11731 +
11732 + if (!host) {
11733 + ret = 1;
11734 +
11735 + /* Disable PCI interrupts in client mode */
11736 + W_REG(osh, &sb->sbintvec, 0);
11737 +
11738 + /* Disable the PCI bridge in client mode */
11739 + sbpci_ban(SB_PCI);
11740 + sb_core_disable(sbh, 0);
11741 +
11742 + printk("PCI: Disabled\n");
11743 + } else {
11744 + printk("PCI: Initializing host\n");
11745 +
11746 + /* Disable PCI SBReqeustTimeout for BCM4785 */
11747 + if (chip == BCM4785_CHIP_ID) {
11748 + AND_REG(osh, &sb->sbimconfiglow, ~0x00000070);
11749 + sb_commit(sbh);
11750 + }
11751 +
11752 + /* Reset the external PCI bus and enable the clock */
11753 + W_REG(osh, &pci->control, 0x5); /* enable the tristate drivers */
11754 + W_REG(osh, &pci->control, 0xd); /* enable the PCI clock */
11755 + OSL_DELAY(150); /* delay > 100 us */
11756 + W_REG(osh, &pci->control, 0xf); /* deassert PCI reset */
11757 + /* Use internal arbiter and park REQ/GRNT at external master 0 */
11758 + W_REG(osh, &pci->arbcontrol, PCI_INT_ARB);
11759 + OSL_DELAY(1); /* delay 1 us */
11760 + if (sb_corerev(sbh) >= 8) {
11761 + val = getintvar(NULL, "parkid");
11762 + ASSERT(val <= PCI_PARKID_LAST);
11763 + OR_REG(osh, &pci->arbcontrol, val << PCI_PARKID_SHIFT);
11764 + OSL_DELAY(1);
11765 + }
11766 +
11767 + /* Enable CardBusMode */
11768 + cardbus = getintvar(NULL, "cardbus") == 1;
11769 + if (cardbus) {
11770 + printk("PCI: Enabling CardBus\n");
11771 + /* GPIO 1 resets the CardBus device on bcm94710ap */
11772 + sb_gpioout(sbh, 1, 1, GPIO_DRV_PRIORITY);
11773 + sb_gpioouten(sbh, 1, 1, GPIO_DRV_PRIORITY);
11774 + W_REG(osh, &pci->sprom[0], R_REG(osh, &pci->sprom[0]) | 0x400);
11775 + }
11776 +
11777 + /* 64 MB I/O access window */
11778 + W_REG(osh, &pci->sbtopci0, SBTOPCI_IO);
11779 + /* 64 MB configuration access window */
11780 + W_REG(osh, &pci->sbtopci1, SBTOPCI_CFG0);
11781 + /* 1 GB memory access window */
11782 + W_REG(osh, &pci->sbtopci2, SBTOPCI_MEM | SB_PCI_DMA);
11783 +
11784 + /* Host bridge slot # nvram overwrite */
11785 + if ((hbslot = nvram_get("pcihbslot"))) {
11786 + pci_hbslot = bcm_strtoul(hbslot, NULL, 0);
11787 + ASSERT(pci_hbslot < PCI_MAX_DEVICES);
11788 + }
11789 +
11790 + /* Enable PCI bridge BAR0 prefetch and burst */
11791 + val = 6;
11792 + sbpci_write_config(sbh, 1, pci_hbslot, 0, PCI_CFG_CMD, &val, sizeof(val));
11793 +
11794 + /* Enable PCI interrupts */
11795 + W_REG(osh, &pci->intmask, PCI_INTA);
11796 + }
11797 +
11798 + return ret;
11799 +}
11800 +
11801 +/*
11802 + * Get the PCI region address and size information.
11803 + */
11804 +static void __init
11805 +sbpci_init_regions(sb_t *sbh, uint func, pci_config_regs *cfg, sb_bar_cfg_t *bar)
11806 +{
11807 + osl_t *osh;
11808 + uint16 coreid;
11809 + void *regs;
11810 + sbconfig_t *sb;
11811 + uint32 base;
11812 +
11813 + osh = sb_osh(sbh);
11814 + coreid = sb_coreid(sbh);
11815 + regs = sb_coreregs(sbh);
11816 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
11817 +
11818 + switch (coreid) {
11819 + case SB_USB20H:
11820 + base = htol32(sb_base(R_REG(osh, &sb->sbadmatch0)));
11821 +
11822 + cfg->base[0] = func == 0 ? base : base + 0x800; /* OHCI/EHCI */
11823 + cfg->base[1] = 0;
11824 + cfg->base[2] = 0;
11825 + cfg->base[3] = 0;
11826 + cfg->base[4] = 0;
11827 + cfg->base[5] = 0;
11828 + bar->n = 1;
11829 + bar->size0 = func == 0 ? 0x200 : 0x100; /* OHCI/EHCI */
11830 + bar->size1 = 0;
11831 + bar->size2 = 0;
11832 + bar->size3 = 0;
11833 + break;
11834 + default:
11835 + cfg->base[0] = htol32(sb_base(R_REG(osh, &sb->sbadmatch0)));
11836 + cfg->base[1] = htol32(sb_base(R_REG(osh, &sb->sbadmatch1)));
11837 + cfg->base[2] = htol32(sb_base(R_REG(osh, &sb->sbadmatch2)));
11838 + cfg->base[3] = htol32(sb_base(R_REG(osh, &sb->sbadmatch3)));
11839 + cfg->base[4] = 0;
11840 + cfg->base[5] = 0;
11841 + bar->n = (R_REG(osh, &sb->sbidlow) & SBIDL_AR_MASK) >> SBIDL_AR_SHIFT;
11842 + bar->size0 = sb_size(R_REG(osh, &sb->sbadmatch0));
11843 + bar->size1 = sb_size(R_REG(osh, &sb->sbadmatch1));
11844 + bar->size2 = sb_size(R_REG(osh, &sb->sbadmatch2));
11845 + bar->size3 = sb_size(R_REG(osh, &sb->sbadmatch3));
11846 + break;
11847 + }
11848 +}
11849 +
11850 +/*
11851 + * Construct PCI config spaces for SB cores so that they
11852 + * can be accessed as if they were PCI devices.
11853 + */
11854 +static void __init
11855 +sbpci_init_cores(sb_t *sbh)
11856 +{
11857 + uint chiprev, coreidx, i;
11858 + sbconfig_t *sb;
11859 + pci_config_regs *cfg, *pci;
11860 + sb_bar_cfg_t *bar;
11861 + void *regs;
11862 + osl_t *osh;
11863 + uint16 vendor, device;
11864 + uint16 coreid;
11865 + uint8 class, subclass, progif;
11866 + uint dev;
11867 + uint8 header;
11868 + uint func;
11869 +
11870 + chiprev = sb_chiprev(sbh);
11871 + coreidx = sb_coreidx(sbh);
11872 +
11873 + osh = sb_osh(sbh);
11874 +
11875 + /* Scan the SB bus */
11876 + bzero(sb_config_regs, sizeof(sb_config_regs));
11877 + bzero(sb_bar_cfg, sizeof(sb_bar_cfg));
11878 + bzero(sb_pci_cfg, sizeof(sb_pci_cfg));
11879 + memset(&sb_pci_null, -1, sizeof(sb_pci_null));
11880 + cfg = sb_config_regs;
11881 + bar = sb_bar_cfg;
11882 + for (dev = 0; dev < SB_MAXCORES; dev ++) {
11883 + /* Check if the core exists */
11884 + if (!(regs = sb_setcoreidx(sbh, dev)))
11885 + continue;
11886 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
11887 +
11888 + /* Check if this core is banned */
11889 + coreid = sb_coreid(sbh);
11890 + for (i = 0; i < pci_banned; i++)
11891 + if (coreid == pci_ban[i])
11892 + break;
11893 + if (i < pci_banned)
11894 + continue;
11895 +
11896 + for (func = 0; func < MAXFUNCS; ++func) {
11897 + /* Make sure we won't go beyond the limit */
11898 + if (cfg >= &sb_config_regs[SB_MAXCORES]) {
11899 + printk("PCI: too many emulated devices\n");
11900 + goto done;
11901 + }
11902 +
11903 + /* Convert core id to pci id */
11904 + if (sb_corepciid(sbh, func, &vendor, &device, &class, &subclass,
11905 + &progif, &header))
11906 + continue;
11907 +
11908 + /*
11909 + * Differentiate real PCI config from emulated.
11910 + * non zero 'pci' indicate there is a real PCI config space
11911 + * for this device.
11912 + */
11913 + switch (device) {
11914 + case BCM47XX_GIGETH_ID:
11915 + pci = (pci_config_regs *)((uint32)regs + 0x800);
11916 + break;
11917 + case BCM47XX_SATAXOR_ID:
11918 + pci = (pci_config_regs *)((uint32)regs + 0x400);
11919 + break;
11920 + case BCM47XX_ATA100_ID:
11921 + pci = (pci_config_regs *)((uint32)regs + 0x800);
11922 + break;
11923 + default:
11924 + pci = NULL;
11925 + break;
11926 + }
11927 + /* Supported translations */
11928 + cfg->vendor = htol16(vendor);
11929 + cfg->device = htol16(device);
11930 + cfg->rev_id = chiprev;
11931 + cfg->prog_if = progif;
11932 + cfg->sub_class = subclass;
11933 + cfg->base_class = class;
11934 + cfg->header_type = header;
11935 + sbpci_init_regions(sbh, func, cfg, bar);
11936 + /* Save core interrupt flag */
11937 + cfg->int_pin = R_REG(osh, &sb->sbtpsflag) & SBTPS_NUM0_MASK;
11938 + /* Save core interrupt assignment */
11939 + cfg->int_line = sb_irq(sbh);
11940 + /* Indicate there is no SROM */
11941 + *((uint32 *) &cfg->sprom_control) = 0xffffffff;
11942 +
11943 + /* Point to the PCI config spaces */
11944 + sb_pci_cfg[dev][func].emu = cfg;
11945 + sb_pci_cfg[dev][func].pci = pci;
11946 + sb_pci_cfg[dev][func].bar = bar;
11947 + cfg ++;
11948 + bar ++;
11949 + }
11950 + }
11951 +
11952 +done:
11953 + sb_setcoreidx(sbh, coreidx);
11954 +}
11955 +
11956 +/*
11957 + * Initialize PCI core and construct PCI config spaces for SB cores.
11958 + * Must propagate sbpci_init_pci() return value to the caller to let
11959 + * them know the PCI core initialization status.
11960 + */
11961 +int __init
11962 +sbpci_init(sb_t *sbh)
11963 +{
11964 + int status = sbpci_init_pci(sbh);
11965 + sbpci_init_cores(sbh);
11966 + return status;
11967 +}
11968 +
11969 diff -urN linux.old/arch/mips/bcm947xx/sbutils.c linux.dev/arch/mips/bcm947xx/sbutils.c
11970 --- linux.old/arch/mips/bcm947xx/sbutils.c 1970-01-01 01:00:00.000000000 +0100
11971 +++ linux.dev/arch/mips/bcm947xx/sbutils.c 2006-10-02 21:19:59.000000000 +0200
11972 @@ -0,0 +1,3103 @@
11973 +/*
11974 + * Misc utility routines for accessing chip-specific features
11975 + * of the SiliconBackplane-based Broadcom chips.
11976 + *
11977 + * Copyright 2006, Broadcom Corporation
11978 + * All Rights Reserved.
11979 + *
11980 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
11981 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
11982 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
11983 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
11984 + * $Id: sbutils.c,v 1.10 2006/04/08 07:12:42 honor Exp $
11985 + */
11986 +
11987 +#include <typedefs.h>
11988 +#include <bcmdefs.h>
11989 +#include <osl.h>
11990 +#include <bcmutils.h>
11991 +#include <sbutils.h>
11992 +#include <bcmdevs.h>
11993 +#include <sbconfig.h>
11994 +#include <sbchipc.h>
11995 +#include <sbpci.h>
11996 +#include <sbpcie.h>
11997 +#include <pcicfg.h>
11998 +#include <sbpcmcia.h>
11999 +#include <sbextif.h>
12000 +#include <sbsocram.h>
12001 +#include <bcmsrom.h>
12002 +#ifdef __mips__
12003 +#include <mipsinc.h>
12004 +#endif /* __mips__ */
12005 +
12006 +/* debug/trace */
12007 +#define SB_ERROR(args)
12008 +
12009 +typedef uint32 (*sb_intrsoff_t)(void *intr_arg);
12010 +typedef void (*sb_intrsrestore_t)(void *intr_arg, uint32 arg);
12011 +typedef bool (*sb_intrsenabled_t)(void *intr_arg);
12012 +
12013 +/* misc sb info needed by some of the routines */
12014 +typedef struct sb_info {
12015 +
12016 + struct sb_pub sb; /* back plane public state (must be first field) */
12017 +
12018 + void *osh; /* osl os handle */
12019 + void *sdh; /* bcmsdh handle */
12020 +
12021 + void *curmap; /* current regs va */
12022 + void *regs[SB_MAXCORES]; /* other regs va */
12023 +
12024 + uint curidx; /* current core index */
12025 + uint dev_coreid; /* the core provides driver functions */
12026 +
12027 + bool memseg; /* flag to toggle MEM_SEG register */
12028 +
12029 + uint gpioidx; /* gpio control core index */
12030 + uint gpioid; /* gpio control coretype */
12031 +
12032 + uint numcores; /* # discovered cores */
12033 + uint coreid[SB_MAXCORES]; /* id of each core */
12034 +
12035 + void *intr_arg; /* interrupt callback function arg */
12036 + sb_intrsoff_t intrsoff_fn; /* turns chip interrupts off */
12037 + sb_intrsrestore_t intrsrestore_fn; /* restore chip interrupts */
12038 + sb_intrsenabled_t intrsenabled_fn; /* check if interrupts are enabled */
12039 +
12040 +} sb_info_t;
12041 +
12042 +/* local prototypes */
12043 +static sb_info_t * sb_doattach(sb_info_t *si, uint devid, osl_t *osh, void *regs,
12044 + uint bustype, void *sdh, char **vars, uint *varsz);
12045 +static void sb_scan(sb_info_t *si);
12046 +static uint sb_corereg(sb_info_t *si, uint coreidx, uint regoff, uint mask, uint val);
12047 +static uint _sb_coreidx(sb_info_t *si);
12048 +static uint sb_findcoreidx(sb_info_t *si, uint coreid, uint coreunit);
12049 +static uint sb_pcidev2chip(uint pcidev);
12050 +static uint sb_chip2numcores(uint chip);
12051 +static bool sb_ispcie(sb_info_t *si);
12052 +static bool sb_find_pci_capability(sb_info_t *si, uint8 req_cap_id, uchar *buf, uint32 *buflen);
12053 +static int sb_pci_fixcfg(sb_info_t *si);
12054 +
12055 +/* routines to access mdio slave device registers */
12056 +static int sb_pcie_mdiowrite(sb_info_t *si, uint physmedia, uint readdr, uint val);
12057 +static void sb_war30841(sb_info_t *si);
12058 +
12059 +/* delay needed between the mdio control/ mdiodata register data access */
12060 +#define PR28829_DELAY() OSL_DELAY(10)
12061 +
12062 +/* size that can take bitfielddump */
12063 +#define BITFIELD_DUMP_SIZE 32
12064 +
12065 +/* global variable to indicate reservation/release of gpio's */
12066 +static uint32 sb_gpioreservation = 0;
12067 +
12068 +#define SB_INFO(sbh) (sb_info_t*)sbh
12069 +#define SET_SBREG(si, r, mask, val) \
12070 + W_SBREG((si), (r), ((R_SBREG((si), (r)) & ~(mask)) | (val)))
12071 +#define GOODCOREADDR(x) (((x) >= SB_ENUM_BASE) && ((x) <= SB_ENUM_LIM) && \
12072 + ISALIGNED((x), SB_CORE_SIZE))
12073 +#define GOODREGS(regs) ((regs) && ISALIGNED((uintptr)(regs), SB_CORE_SIZE))
12074 +#define REGS2SB(va) (sbconfig_t*) ((int8*)(va) + SBCONFIGOFF)
12075 +#define GOODIDX(idx) (((uint)idx) < SB_MAXCORES)
12076 +#define BADIDX (SB_MAXCORES+1)
12077 +#define NOREV -1 /* Invalid rev */
12078 +
12079 +#define PCI(si) ((BUSTYPE(si->sb.bustype) == PCI_BUS) && (si->sb.buscoretype == SB_PCI))
12080 +#define PCIE(si) ((BUSTYPE(si->sb.bustype) == PCI_BUS) && (si->sb.buscoretype == SB_PCIE))
12081 +
12082 +/* sonicsrev */
12083 +#define SONICS_2_2 (SBIDL_RV_2_2 >> SBIDL_RV_SHIFT)
12084 +#define SONICS_2_3 (SBIDL_RV_2_3 >> SBIDL_RV_SHIFT)
12085 +
12086 +#define R_SBREG(si, sbr) sb_read_sbreg((si), (sbr))
12087 +#define W_SBREG(si, sbr, v) sb_write_sbreg((si), (sbr), (v))
12088 +#define AND_SBREG(si, sbr, v) W_SBREG((si), (sbr), (R_SBREG((si), (sbr)) & (v)))
12089 +#define OR_SBREG(si, sbr, v) W_SBREG((si), (sbr), (R_SBREG((si), (sbr)) | (v)))
12090 +
12091 +/*
12092 + * Macros to disable/restore function core(D11, ENET, ILINE20, etc) interrupts before/
12093 + * after core switching to avoid invalid register accesss inside ISR.
12094 + */
12095 +#define INTR_OFF(si, intr_val) \
12096 + if ((si)->intrsoff_fn && (si)->coreid[(si)->curidx] == (si)->dev_coreid) { \
12097 + intr_val = (*(si)->intrsoff_fn)((si)->intr_arg); }
12098 +#define INTR_RESTORE(si, intr_val) \
12099 + if ((si)->intrsrestore_fn && (si)->coreid[(si)->curidx] == (si)->dev_coreid) { \
12100 + (*(si)->intrsrestore_fn)((si)->intr_arg, intr_val); }
12101 +
12102 +/* dynamic clock control defines */
12103 +#define LPOMINFREQ 25000 /* low power oscillator min */
12104 +#define LPOMAXFREQ 43000 /* low power oscillator max */
12105 +#define XTALMINFREQ 19800000 /* 20 MHz - 1% */
12106 +#define XTALMAXFREQ 20200000 /* 20 MHz + 1% */
12107 +#define PCIMINFREQ 25000000 /* 25 MHz */
12108 +#define PCIMAXFREQ 34000000 /* 33 MHz + fudge */
12109 +
12110 +#define ILP_DIV_5MHZ 0 /* ILP = 5 MHz */
12111 +#define ILP_DIV_1MHZ 4 /* ILP = 1 MHz */
12112 +
12113 +/* different register spaces to access thr'u pcie indirect access */
12114 +#define PCIE_CONFIGREGS 1 /* Access to config space */
12115 +#define PCIE_PCIEREGS 2 /* Access to pcie registers */
12116 +
12117 +/* force HT war check */
12118 +#define FORCEHT_WAR32414(si) \
12119 + ((PCIE(si)) && (((si->sb.chip == BCM4311_CHIP_ID) && (si->sb.chiprev == 1)) || \
12120 + ((si->sb.chip == BCM4321_CHIP_ID) && (si->sb.chiprev <= 3))))
12121 +
12122 +/* GPIO Based LED powersave defines */
12123 +#define DEFAULT_GPIO_ONTIME 10 /* Default: 10% on */
12124 +#define DEFAULT_GPIO_OFFTIME 90 /* Default: 10% on */
12125 +
12126 +#define DEFAULT_GPIOTIMERVAL ((DEFAULT_GPIO_ONTIME << GPIO_ONTIME_SHIFT) | DEFAULT_GPIO_OFFTIME)
12127 +
12128 +static uint32
12129 +sb_read_sbreg(sb_info_t *si, volatile uint32 *sbr)
12130 +{
12131 + uint8 tmp;
12132 + uint32 val, intr_val = 0;
12133 +
12134 +
12135 + /*
12136 + * compact flash only has 11 bits address, while we needs 12 bits address.
12137 + * MEM_SEG will be OR'd with other 11 bits address in hardware,
12138 + * so we program MEM_SEG with 12th bit when necessary(access sb regsiters).
12139 + * For normal PCMCIA bus(CFTable_regwinsz > 2k), do nothing special
12140 + */
12141 + if (si->memseg) {
12142 + INTR_OFF(si, intr_val);
12143 + tmp = 1;
12144 + OSL_PCMCIA_WRITE_ATTR(si->osh, MEM_SEG, &tmp, 1);
12145 + sbr = (volatile uint32 *)((uintptr)sbr & ~(1 << 11)); /* mask out bit 11 */
12146 + }
12147 +
12148 + val = R_REG(si->osh, sbr);
12149 +
12150 + if (si->memseg) {
12151 + tmp = 0;
12152 + OSL_PCMCIA_WRITE_ATTR(si->osh, MEM_SEG, &tmp, 1);
12153 + INTR_RESTORE(si, intr_val);
12154 + }
12155 +
12156 + return (val);
12157 +}
12158 +
12159 +static void
12160 +sb_write_sbreg(sb_info_t *si, volatile uint32 *sbr, uint32 v)
12161 +{
12162 + uint8 tmp;
12163 + volatile uint32 dummy;
12164 + uint32 intr_val = 0;
12165 +
12166 +
12167 + /*
12168 + * compact flash only has 11 bits address, while we needs 12 bits address.
12169 + * MEM_SEG will be OR'd with other 11 bits address in hardware,
12170 + * so we program MEM_SEG with 12th bit when necessary(access sb regsiters).
12171 + * For normal PCMCIA bus(CFTable_regwinsz > 2k), do nothing special
12172 + */
12173 + if (si->memseg) {
12174 + INTR_OFF(si, intr_val);
12175 + tmp = 1;
12176 + OSL_PCMCIA_WRITE_ATTR(si->osh, MEM_SEG, &tmp, 1);
12177 + sbr = (volatile uint32 *)((uintptr)sbr & ~(1 << 11)); /* mask out bit 11 */
12178 + }
12179 +
12180 + if (BUSTYPE(si->sb.bustype) == PCMCIA_BUS) {
12181 +#ifdef IL_BIGENDIAN
12182 + dummy = R_REG(si->osh, sbr);
12183 + W_REG(si->osh, ((volatile uint16 *)sbr + 1), (uint16)((v >> 16) & 0xffff));
12184 + dummy = R_REG(si->osh, sbr);
12185 + W_REG(si->osh, (volatile uint16 *)sbr, (uint16)(v & 0xffff));
12186 +#else
12187 + dummy = R_REG(si->osh, sbr);
12188 + W_REG(si->osh, (volatile uint16 *)sbr, (uint16)(v & 0xffff));
12189 + dummy = R_REG(si->osh, sbr);
12190 + W_REG(si->osh, ((volatile uint16 *)sbr + 1), (uint16)((v >> 16) & 0xffff));
12191 +#endif /* IL_BIGENDIAN */
12192 + } else
12193 + W_REG(si->osh, sbr, v);
12194 +
12195 + if (si->memseg) {
12196 + tmp = 0;
12197 + OSL_PCMCIA_WRITE_ATTR(si->osh, MEM_SEG, &tmp, 1);
12198 + INTR_RESTORE(si, intr_val);
12199 + }
12200 +}
12201 +
12202 +/*
12203 + * Allocate a sb handle.
12204 + * devid - pci device id (used to determine chip#)
12205 + * osh - opaque OS handle
12206 + * regs - virtual address of initial core registers
12207 + * bustype - pci/pcmcia/sb/sdio/etc
12208 + * vars - pointer to a pointer area for "environment" variables
12209 + * varsz - pointer to int to return the size of the vars
12210 + */
12211 +sb_t *
12212 +BCMINITFN(sb_attach)(uint devid, osl_t *osh, void *regs,
12213 + uint bustype, void *sdh, char **vars, uint *varsz)
12214 +{
12215 + sb_info_t *si;
12216 +
12217 + /* alloc sb_info_t */
12218 + if ((si = MALLOC(osh, sizeof (sb_info_t))) == NULL) {
12219 + SB_ERROR(("sb_attach: malloc failed! malloced %d bytes\n", MALLOCED(osh)));
12220 + return (NULL);
12221 + }
12222 +
12223 + if (sb_doattach(si, devid, osh, regs, bustype, sdh, vars, (uint*)varsz) == NULL) {
12224 + MFREE(osh, si, sizeof(sb_info_t));
12225 + return (NULL);
12226 + }
12227 +
12228 + return (sb_t *)si;
12229 +}
12230 +
12231 +/* Using sb_kattach depends on SB_BUS support, either implicit */
12232 +/* no limiting BCMBUSTYPE value) or explicit (value is SB_BUS). */
12233 +#if !defined(BCMBUSTYPE) || (BCMBUSTYPE == SB_BUS)
12234 +
12235 +/* global kernel resource */
12236 +static sb_info_t ksi;
12237 +static bool ksi_attached = FALSE;
12238 +
12239 +/* generic kernel variant of sb_attach() */
12240 +sb_t *
12241 +BCMINITFN(sb_kattach)(void)
12242 +{
12243 + osl_t *osh = NULL;
12244 + uint32 *regs;
12245 +
12246 + if (!ksi_attached) {
12247 + uint32 cid;
12248 +
12249 + regs = (uint32 *)REG_MAP(SB_ENUM_BASE, SB_CORE_SIZE);
12250 + cid = R_REG(osh, (uint32 *)regs);
12251 + if (((cid & CID_ID_MASK) == BCM4712_CHIP_ID) &&
12252 + ((cid & CID_PKG_MASK) != BCM4712LARGE_PKG_ID) &&
12253 + ((cid & CID_REV_MASK) <= (3 << CID_REV_SHIFT))) {
12254 + uint32 *scc, val;
12255 +
12256 + scc = (uint32 *)((uchar*)regs + OFFSETOF(chipcregs_t, slow_clk_ctl));
12257 + val = R_REG(osh, scc);
12258 + SB_ERROR((" initial scc = 0x%x\n", val));
12259 + val |= SCC_SS_XTAL;
12260 + W_REG(osh, scc, val);
12261 + }
12262 +
12263 + if (sb_doattach(&ksi, BCM4710_DEVICE_ID, osh, (void*)regs,
12264 + SB_BUS, NULL, NULL, NULL) == NULL) {
12265 + return NULL;
12266 + }
12267 + else
12268 + ksi_attached = TRUE;
12269 + }
12270 +
12271 + return (sb_t *)&ksi;
12272 +}
12273 +#endif /* !BCMBUSTYPE || (BCMBUSTYPE == SB_BUS) */
12274 +
12275 +void
12276 +BCMINITFN(sb_war32414_forceHT)(sb_t *sbh, bool forceHT)
12277 +{
12278 + sb_info_t *si;
12279 +
12280 + si = SB_INFO(sbh);
12281 +
12282 +
12283 + if (FORCEHT_WAR32414(si)) {
12284 + uint32 val = 0;
12285 + if (forceHT)
12286 + val = SYCC_HR;
12287 + sb_corereg((void*)si, SB_CC_IDX, OFFSETOF(chipcregs_t, system_clk_ctl),
12288 + SYCC_HR, val);
12289 + }
12290 +}
12291 +
12292 +static sb_info_t *
12293 +BCMINITFN(sb_doattach)(sb_info_t *si, uint devid, osl_t *osh, void *regs,
12294 + uint bustype, void *sdh, char **vars, uint *varsz)
12295 +{
12296 + uint origidx;
12297 + chipcregs_t *cc;
12298 + sbconfig_t *sb;
12299 + uint32 w;
12300 +
12301 + ASSERT(GOODREGS(regs));
12302 +
12303 + bzero((uchar*)si, sizeof(sb_info_t));
12304 +
12305 + si->sb.buscoreidx = si->gpioidx = BADIDX;
12306 +
12307 + si->curmap = regs;
12308 + si->sdh = sdh;
12309 + si->osh = osh;
12310 +
12311 + /* check to see if we are a sb core mimic'ing a pci core */
12312 + if (bustype == PCI_BUS) {
12313 + if (OSL_PCI_READ_CONFIG(si->osh, PCI_SPROM_CONTROL, sizeof(uint32)) == 0xffffffff) {
12314 + SB_ERROR(("%s: incoming bus is PCI but it's a lie, switching to SB "
12315 + "devid:0x%x\n", __FUNCTION__, devid));
12316 + bustype = SB_BUS;
12317 + }
12318 + }
12319 +
12320 + si->sb.bustype = bustype;
12321 + if (si->sb.bustype != BUSTYPE(si->sb.bustype)) {
12322 + SB_ERROR(("sb_doattach: bus type %d does not match configured bus type %d\n",
12323 + si->sb.bustype, BUSTYPE(si->sb.bustype)));
12324 + return NULL;
12325 + }
12326 +
12327 + /* need to set memseg flag for CF card first before any sb registers access */
12328 + if (BUSTYPE(si->sb.bustype) == PCMCIA_BUS)
12329 + si->memseg = TRUE;
12330 +
12331 + /* kludge to enable the clock on the 4306 which lacks a slowclock */
12332 + if (BUSTYPE(si->sb.bustype) == PCI_BUS)
12333 + sb_clkctl_xtal(&si->sb, XTAL|PLL, ON);
12334 +
12335 + if (BUSTYPE(si->sb.bustype) == PCI_BUS) {
12336 + w = OSL_PCI_READ_CONFIG(si->osh, PCI_BAR0_WIN, sizeof(uint32));
12337 + if (!GOODCOREADDR(w))
12338 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_BAR0_WIN, sizeof(uint32), SB_ENUM_BASE);
12339 + }
12340 +
12341 + /* initialize current core index value */
12342 + si->curidx = _sb_coreidx(si);
12343 +
12344 + if (si->curidx == BADIDX) {
12345 + SB_ERROR(("sb_doattach: bad core index\n"));
12346 + return NULL;
12347 + }
12348 +
12349 + /* get sonics backplane revision */
12350 + sb = REGS2SB(si->curmap);
12351 + si->sb.sonicsrev = (R_SBREG(si, &sb->sbidlow) & SBIDL_RV_MASK) >> SBIDL_RV_SHIFT;
12352 +
12353 + /* keep and reuse the initial register mapping */
12354 + origidx = si->curidx;
12355 + if (BUSTYPE(si->sb.bustype) == SB_BUS)
12356 + si->regs[origidx] = regs;
12357 +
12358 + /* is core-0 a chipcommon core? */
12359 + si->numcores = 1;
12360 + cc = (chipcregs_t*) sb_setcoreidx(&si->sb, 0);
12361 + if (sb_coreid(&si->sb) != SB_CC)
12362 + cc = NULL;
12363 +
12364 + /* determine chip id and rev */
12365 + if (cc) {
12366 + /* chip common core found! */
12367 + si->sb.chip = R_REG(si->osh, &cc->chipid) & CID_ID_MASK;
12368 + si->sb.chiprev = (R_REG(si->osh, &cc->chipid) & CID_REV_MASK) >> CID_REV_SHIFT;
12369 + si->sb.chippkg = (R_REG(si->osh, &cc->chipid) & CID_PKG_MASK) >> CID_PKG_SHIFT;
12370 + } else {
12371 + /* no chip common core -- must convert device id to chip id */
12372 + if ((si->sb.chip = sb_pcidev2chip(devid)) == 0) {
12373 + SB_ERROR(("sb_doattach: unrecognized device id 0x%04x\n", devid));
12374 + sb_setcoreidx(&si->sb, origidx);
12375 + return NULL;
12376 + }
12377 + }
12378 +
12379 + /* get chipcommon rev */
12380 + si->sb.ccrev = cc ? (int)sb_corerev(&si->sb) : NOREV;
12381 +
12382 + /* determine numcores */
12383 + if (cc && ((si->sb.ccrev == 4) || (si->sb.ccrev >= 6)))
12384 + si->numcores = (R_REG(si->osh, &cc->chipid) & CID_CC_MASK) >> CID_CC_SHIFT;
12385 + else
12386 + si->numcores = sb_chip2numcores(si->sb.chip);
12387 +
12388 + /* return to original core */
12389 + sb_setcoreidx(&si->sb, origidx);
12390 +
12391 + /* sanity checks */
12392 + ASSERT(si->sb.chip);
12393 +
12394 + /* scan for cores */
12395 + sb_scan(si);
12396 +
12397 + /* fixup necessary chip/core configurations */
12398 + if (BUSTYPE(si->sb.bustype) == PCI_BUS) {
12399 + if (sb_pci_fixcfg(si)) {
12400 + SB_ERROR(("sb_doattach: sb_pci_fixcfg failed\n"));
12401 + return NULL;
12402 + }
12403 + }
12404 +
12405 + /* srom_var_init() depends on sb_scan() info */
12406 + if (srom_var_init(si, si->sb.bustype, si->curmap, si->osh, vars, varsz)) {
12407 + SB_ERROR(("sb_doattach: srom_var_init failed: bad srom\n"));
12408 + return (NULL);
12409 + }
12410 +
12411 + if (cc == NULL) {
12412 + /*
12413 + * The chip revision number is hardwired into all
12414 + * of the pci function config rev fields and is
12415 + * independent from the individual core revision numbers.
12416 + * For example, the "A0" silicon of each chip is chip rev 0.
12417 + * For PCMCIA we get it from the CIS instead.
12418 + */
12419 + if (BUSTYPE(si->sb.bustype) == PCMCIA_BUS) {
12420 + ASSERT(vars);
12421 + si->sb.chiprev = getintvar(*vars, "chiprev");
12422 + } else if (BUSTYPE(si->sb.bustype) == PCI_BUS) {
12423 + w = OSL_PCI_READ_CONFIG(si->osh, PCI_CFG_REV, sizeof(uint32));
12424 + si->sb.chiprev = w & 0xff;
12425 + } else
12426 + si->sb.chiprev = 0;
12427 + }
12428 +
12429 + if (BUSTYPE(si->sb.bustype) == PCMCIA_BUS) {
12430 + w = getintvar(*vars, "regwindowsz");
12431 + si->memseg = (w <= CFTABLE_REGWIN_2K) ? TRUE : FALSE;
12432 + }
12433 +
12434 + /* gpio control core is required */
12435 + if (!GOODIDX(si->gpioidx)) {
12436 + SB_ERROR(("sb_doattach: gpio control core not found\n"));
12437 + return NULL;
12438 + }
12439 +
12440 + /* get boardtype and boardrev */
12441 + switch (BUSTYPE(si->sb.bustype)) {
12442 + case PCI_BUS:
12443 + /* do a pci config read to get subsystem id and subvendor id */
12444 + w = OSL_PCI_READ_CONFIG(si->osh, PCI_CFG_SVID, sizeof(uint32));
12445 + si->sb.boardvendor = w & 0xffff;
12446 + si->sb.boardtype = (w >> 16) & 0xffff;
12447 + break;
12448 +
12449 + case PCMCIA_BUS:
12450 + case SDIO_BUS:
12451 + si->sb.boardvendor = getintvar(*vars, "manfid");
12452 + si->sb.boardtype = getintvar(*vars, "prodid");
12453 + break;
12454 +
12455 + case SB_BUS:
12456 + case JTAG_BUS:
12457 + si->sb.boardvendor = VENDOR_BROADCOM;
12458 + if ((si->sb.boardtype = getintvar(NULL, "boardtype")) == 0)
12459 + si->sb.boardtype = 0xffff;
12460 + break;
12461 + }
12462 +
12463 + if (si->sb.boardtype == 0) {
12464 + SB_ERROR(("sb_doattach: unknown board type\n"));
12465 + ASSERT(si->sb.boardtype);
12466 + }
12467 +
12468 + /* setup the GPIO based LED powersave register */
12469 + if (si->sb.ccrev >= 16) {
12470 + if ((vars == NULL) || ((w = getintvar(*vars, "leddc")) == 0))
12471 + w = DEFAULT_GPIOTIMERVAL;
12472 + sb_corereg(si, 0, OFFSETOF(chipcregs_t, gpiotimerval), ~0, w);
12473 + }
12474 + if (FORCEHT_WAR32414(si)) {
12475 + /* set proper clk setup delays before forcing HT */
12476 + sb_clkctl_init((void *)si);
12477 + sb_war32414_forceHT((void *)si, 1);
12478 + }
12479 +
12480 +
12481 + return (si);
12482 +}
12483 +
12484 +
12485 +uint
12486 +sb_coreid(sb_t *sbh)
12487 +{
12488 + sb_info_t *si;
12489 + sbconfig_t *sb;
12490 +
12491 + si = SB_INFO(sbh);
12492 + sb = REGS2SB(si->curmap);
12493 +
12494 + return ((R_SBREG(si, &sb->sbidhigh) & SBIDH_CC_MASK) >> SBIDH_CC_SHIFT);
12495 +}
12496 +
12497 +uint
12498 +sb_coreidx(sb_t *sbh)
12499 +{
12500 + sb_info_t *si;
12501 +
12502 + si = SB_INFO(sbh);
12503 + return (si->curidx);
12504 +}
12505 +
12506 +/* return current index of core */
12507 +static uint
12508 +_sb_coreidx(sb_info_t *si)
12509 +{
12510 + sbconfig_t *sb;
12511 + uint32 sbaddr = 0;
12512 +
12513 + ASSERT(si);
12514 +
12515 + switch (BUSTYPE(si->sb.bustype)) {
12516 + case SB_BUS:
12517 + sb = REGS2SB(si->curmap);
12518 + sbaddr = sb_base(R_SBREG(si, &sb->sbadmatch0));
12519 + break;
12520 +
12521 + case PCI_BUS:
12522 + sbaddr = OSL_PCI_READ_CONFIG(si->osh, PCI_BAR0_WIN, sizeof(uint32));
12523 + break;
12524 +
12525 + case PCMCIA_BUS: {
12526 + uint8 tmp = 0;
12527 +
12528 + OSL_PCMCIA_READ_ATTR(si->osh, PCMCIA_ADDR0, &tmp, 1);
12529 + sbaddr = (uint)tmp << 12;
12530 + OSL_PCMCIA_READ_ATTR(si->osh, PCMCIA_ADDR1, &tmp, 1);
12531 + sbaddr |= (uint)tmp << 16;
12532 + OSL_PCMCIA_READ_ATTR(si->osh, PCMCIA_ADDR2, &tmp, 1);
12533 + sbaddr |= (uint)tmp << 24;
12534 + break;
12535 + }
12536 +
12537 +#ifdef BCMJTAG
12538 + case JTAG_BUS:
12539 + sbaddr = (uint32)si->curmap;
12540 + break;
12541 +#endif /* BCMJTAG */
12542 +
12543 + default:
12544 + ASSERT(0);
12545 + }
12546 +
12547 + if (!GOODCOREADDR(sbaddr))
12548 + return BADIDX;
12549 +
12550 + return ((sbaddr - SB_ENUM_BASE) / SB_CORE_SIZE);
12551 +}
12552 +
12553 +uint
12554 +sb_corevendor(sb_t *sbh)
12555 +{
12556 + sb_info_t *si;
12557 + sbconfig_t *sb;
12558 +
12559 + si = SB_INFO(sbh);
12560 + sb = REGS2SB(si->curmap);
12561 +
12562 + return ((R_SBREG(si, &sb->sbidhigh) & SBIDH_VC_MASK) >> SBIDH_VC_SHIFT);
12563 +}
12564 +
12565 +uint
12566 +sb_corerev(sb_t *sbh)
12567 +{
12568 + sb_info_t *si;
12569 + sbconfig_t *sb;
12570 + uint sbidh;
12571 +
12572 + si = SB_INFO(sbh);
12573 + sb = REGS2SB(si->curmap);
12574 + sbidh = R_SBREG(si, &sb->sbidhigh);
12575 +
12576 + return (SBCOREREV(sbidh));
12577 +}
12578 +
12579 +void *
12580 +sb_osh(sb_t *sbh)
12581 +{
12582 + sb_info_t *si;
12583 +
12584 + si = SB_INFO(sbh);
12585 + return si->osh;
12586 +}
12587 +
12588 +void
12589 +sb_setosh(sb_t *sbh, osl_t *osh)
12590 +{
12591 + sb_info_t *si;
12592 +
12593 + si = SB_INFO(sbh);
12594 + if (si->osh != NULL) {
12595 + SB_ERROR(("osh is already set....\n"));
12596 + ASSERT(!si->osh);
12597 + }
12598 + si->osh = osh;
12599 +}
12600 +
12601 +/* set/clear sbtmstatelow core-specific flags */
12602 +uint32
12603 +sb_coreflags(sb_t *sbh, uint32 mask, uint32 val)
12604 +{
12605 + sb_info_t *si;
12606 + sbconfig_t *sb;
12607 + uint32 w;
12608 +
12609 + si = SB_INFO(sbh);
12610 + sb = REGS2SB(si->curmap);
12611 +
12612 + ASSERT((val & ~mask) == 0);
12613 +
12614 + /* mask and set */
12615 + if (mask || val) {
12616 + w = (R_SBREG(si, &sb->sbtmstatelow) & ~mask) | val;
12617 + W_SBREG(si, &sb->sbtmstatelow, w);
12618 + }
12619 +
12620 + /* return the new value */
12621 + return (R_SBREG(si, &sb->sbtmstatelow));
12622 +}
12623 +
12624 +/* set/clear sbtmstatehigh core-specific flags */
12625 +uint32
12626 +sb_coreflagshi(sb_t *sbh, uint32 mask, uint32 val)
12627 +{
12628 + sb_info_t *si;
12629 + sbconfig_t *sb;
12630 + uint32 w;
12631 +
12632 + si = SB_INFO(sbh);
12633 + sb = REGS2SB(si->curmap);
12634 +
12635 + ASSERT((val & ~mask) == 0);
12636 + ASSERT((mask & ~SBTMH_FL_MASK) == 0);
12637 +
12638 + /* mask and set */
12639 + if (mask || val) {
12640 + w = (R_SBREG(si, &sb->sbtmstatehigh) & ~mask) | val;
12641 + W_SBREG(si, &sb->sbtmstatehigh, w);
12642 + }
12643 +
12644 + /* return the new value */
12645 + return (R_SBREG(si, &sb->sbtmstatehigh) & SBTMH_FL_MASK);
12646 +}
12647 +
12648 +/* Run bist on current core. Caller needs to take care of core-specific bist hazards */
12649 +int
12650 +sb_corebist(sb_t *sbh)
12651 +{
12652 + uint32 sblo;
12653 + sb_info_t *si;
12654 + sbconfig_t *sb;
12655 + int result = 0;
12656 +
12657 + si = SB_INFO(sbh);
12658 + sb = REGS2SB(si->curmap);
12659 +
12660 + sblo = R_SBREG(si, &sb->sbtmstatelow);
12661 + W_SBREG(si, &sb->sbtmstatelow, (sblo | SBTML_FGC | SBTML_BE));
12662 +
12663 + SPINWAIT(((R_SBREG(si, &sb->sbtmstatehigh) & SBTMH_BISTD) == 0), 100000);
12664 +
12665 + if (R_SBREG(si, &sb->sbtmstatehigh) & SBTMH_BISTF)
12666 + result = BCME_ERROR;
12667 +
12668 + W_SBREG(si, &sb->sbtmstatelow, sblo);
12669 +
12670 + return result;
12671 +}
12672 +
12673 +bool
12674 +sb_iscoreup(sb_t *sbh)
12675 +{
12676 + sb_info_t *si;
12677 + sbconfig_t *sb;
12678 +
12679 + si = SB_INFO(sbh);
12680 + sb = REGS2SB(si->curmap);
12681 +
12682 + return ((R_SBREG(si, &sb->sbtmstatelow) &
12683 + (SBTML_RESET | SBTML_REJ_MASK | SBTML_CLK)) == SBTML_CLK);
12684 +}
12685 +
12686 +/*
12687 + * Switch to 'coreidx', issue a single arbitrary 32bit register mask&set operation,
12688 + * switch back to the original core, and return the new value.
12689 + *
12690 + * When using the silicon backplane, no fidleing with interrupts or core switches are needed.
12691 + *
12692 + * Also, when using pci/pcie, we can optimize away the core switching for pci registers
12693 + * and (on newer pci cores) chipcommon registers.
12694 + */
12695 +static uint
12696 +sb_corereg(sb_info_t *si, uint coreidx, uint regoff, uint mask, uint val)
12697 +{
12698 + uint origidx = 0;
12699 + uint32 *r = NULL;
12700 + uint w;
12701 + uint intr_val = 0;
12702 + bool fast = FALSE;
12703 +
12704 + ASSERT(GOODIDX(coreidx));
12705 + ASSERT(regoff < SB_CORE_SIZE);
12706 + ASSERT((val & ~mask) == 0);
12707 +
12708 +#ifdef notyet
12709 + if (si->sb.bustype == SB_BUS) {
12710 + /* If internal bus, we can always get at everything */
12711 + fast = TRUE;
12712 + r = (uint32 *)((uchar *)si->regs[coreidx] + regoff);
12713 + } else if (si->sb.bustype == PCI_BUS) {
12714 + /* If pci/pcie, we can get at pci/pcie regs and on newer cores to chipc */
12715 +
12716 + if ((si->coreid[coreidx] == SB_CC) &&
12717 + ((si->sb.buscoretype == SB_PCIE) ||
12718 + (si->sb.buscorerev >= 13))) {
12719 + /* Chipc registers are mapped at 12KB */
12720 +
12721 + fast = TRUE;
12722 + r = (uint32 *)((char *)si->curmap + PCI_16KB0_CCREGS_OFFSET + regoff);
12723 + } else if (si->sb.buscoreidx == coreidx) {
12724 + /* pci registers are at either in the last 2KB of an 8KB window
12725 + * or, in pcie and pci rev 13 at 8KB
12726 + */
12727 + fast = TRUE;
12728 + if ((si->sb.buscoretype == SB_PCIE) ||
12729 + (si->sb.buscorerev >= 13))
12730 + r = (uint32 *)((char *)si->curmap +
12731 + PCI_16KB0_PCIREGS_OFFSET + regoff);
12732 + else
12733 + r = (uint32 *)((char *)si->curmap +
12734 + ((regoff >= SBCONFIGOFF) ?
12735 + PCI_BAR0_PCISBR_OFFSET : PCI_BAR0_PCIREGS_OFFSET) +
12736 + regoff);
12737 + }
12738 + }
12739 +#endif /* notyet */
12740 +
12741 + if (!fast) {
12742 + INTR_OFF(si, intr_val);
12743 +
12744 + /* save current core index */
12745 + origidx = sb_coreidx(&si->sb);
12746 +
12747 + /* switch core */
12748 + r = (uint32*) ((uchar*) sb_setcoreidx(&si->sb, coreidx) + regoff);
12749 + }
12750 + ASSERT(r);
12751 +
12752 + /* mask and set */
12753 + if (mask || val) {
12754 + if (regoff >= SBCONFIGOFF) {
12755 + w = (R_SBREG(si, r) & ~mask) | val;
12756 + W_SBREG(si, r, w);
12757 + } else {
12758 + w = (R_REG(si->osh, r) & ~mask) | val;
12759 + W_REG(si->osh, r, w);
12760 + }
12761 + }
12762 +
12763 + /* readback */
12764 + if (regoff >= SBCONFIGOFF)
12765 + w = R_SBREG(si, r);
12766 + else
12767 + w = R_REG(si->osh, r);
12768 +
12769 + if (!fast) {
12770 + /* restore core index */
12771 + if (origidx != coreidx)
12772 + sb_setcoreidx(&si->sb, origidx);
12773 +
12774 + INTR_RESTORE(si, intr_val);
12775 + }
12776 +
12777 + return (w);
12778 +}
12779 +
12780 +#define DWORD_ALIGN(x) (x & ~(0x03))
12781 +#define BYTE_POS(x) (x & 0x3)
12782 +#define WORD_POS(x) (x & 0x1)
12783 +
12784 +#define BYTE_SHIFT(x) (8 * BYTE_POS(x))
12785 +#define WORD_SHIFT(x) (16 * WORD_POS(x))
12786 +
12787 +#define BYTE_VAL(a, x) ((a >> BYTE_SHIFT(x)) & 0xFF)
12788 +#define WORD_VAL(a, x) ((a >> WORD_SHIFT(x)) & 0xFFFF)
12789 +
12790 +#define read_pci_cfg_byte(a) \
12791 + (BYTE_VAL(OSL_PCI_READ_CONFIG(si->osh, DWORD_ALIGN(a), 4), a) & 0xff)
12792 +
12793 +#define read_pci_cfg_word(a) \
12794 + (WORD_VAL(OSL_PCI_READ_CONFIG(si->osh, DWORD_ALIGN(a), 4), a) & 0xffff)
12795 +
12796 +
12797 +/* return TRUE if requested capability exists in the PCI config space */
12798 +static bool
12799 +sb_find_pci_capability(sb_info_t *si, uint8 req_cap_id, uchar *buf, uint32 *buflen)
12800 +{
12801 + uint8 cap_id;
12802 + uint8 cap_ptr;
12803 + uint32 bufsize;
12804 + uint8 byte_val;
12805 +
12806 + if (BUSTYPE(si->sb.bustype) != PCI_BUS)
12807 + return FALSE;
12808 +
12809 + /* check for Header type 0 */
12810 + byte_val = read_pci_cfg_byte(PCI_CFG_HDR);
12811 + if ((byte_val & 0x7f) != PCI_HEADER_NORMAL)
12812 + return FALSE;
12813 +
12814 + /* check if the capability pointer field exists */
12815 + byte_val = read_pci_cfg_byte(PCI_CFG_STAT);
12816 + if (!(byte_val & PCI_CAPPTR_PRESENT))
12817 + return FALSE;
12818 +
12819 + cap_ptr = read_pci_cfg_byte(PCI_CFG_CAPPTR);
12820 + /* check if the capability pointer is 0x00 */
12821 + if (cap_ptr == 0x00)
12822 + return FALSE;
12823 +
12824 +
12825 + /* loop thr'u the capability list and see if the pcie capabilty exists */
12826 +
12827 + cap_id = read_pci_cfg_byte(cap_ptr);
12828 +
12829 + while (cap_id != req_cap_id) {
12830 + cap_ptr = read_pci_cfg_byte((cap_ptr+1));
12831 + if (cap_ptr == 0x00) break;
12832 + cap_id = read_pci_cfg_byte(cap_ptr);
12833 + }
12834 + if (cap_id != req_cap_id) {
12835 + return FALSE;
12836 + }
12837 + /* found the caller requested capability */
12838 + if ((buf != NULL) && (buflen != NULL)) {
12839 + bufsize = *buflen;
12840 + if (!bufsize) goto end;
12841 + *buflen = 0;
12842 + /* copy the cpability data excluding cap ID and next ptr */
12843 + cap_ptr += 2;
12844 + if ((bufsize + cap_ptr) > SZPCR)
12845 + bufsize = SZPCR - cap_ptr;
12846 + *buflen = bufsize;
12847 + while (bufsize--) {
12848 + *buf = read_pci_cfg_byte(cap_ptr);
12849 + cap_ptr++;
12850 + buf++;
12851 + }
12852 + }
12853 +end:
12854 + return TRUE;
12855 +}
12856 +
12857 +/* return TRUE if PCIE capability exists the pci config space */
12858 +static inline bool
12859 +sb_ispcie(sb_info_t *si)
12860 +{
12861 + return (sb_find_pci_capability(si, PCI_CAP_PCIECAP_ID, NULL, NULL));
12862 +}
12863 +
12864 +/* scan the sb enumerated space to identify all cores */
12865 +static void
12866 +BCMINITFN(sb_scan)(sb_info_t *si)
12867 +{
12868 + uint origidx;
12869 + uint i;
12870 + bool pci;
12871 + bool pcie;
12872 + uint pciidx;
12873 + uint pcieidx;
12874 + uint pcirev;
12875 + uint pcierev;
12876 +
12877 +
12878 + /* numcores should already be set */
12879 + ASSERT((si->numcores > 0) && (si->numcores <= SB_MAXCORES));
12880 +
12881 + /* save current core index */
12882 + origidx = sb_coreidx(&si->sb);
12883 +
12884 + si->sb.buscorerev = NOREV;
12885 + si->sb.buscoreidx = BADIDX;
12886 +
12887 + si->gpioidx = BADIDX;
12888 +
12889 + pci = pcie = FALSE;
12890 + pcirev = pcierev = NOREV;
12891 + pciidx = pcieidx = BADIDX;
12892 +
12893 + for (i = 0; i < si->numcores; i++) {
12894 + sb_setcoreidx(&si->sb, i);
12895 + si->coreid[i] = sb_coreid(&si->sb);
12896 +
12897 + if (si->coreid[i] == SB_PCI) {
12898 + pciidx = i;
12899 + pcirev = sb_corerev(&si->sb);
12900 + pci = TRUE;
12901 + } else if (si->coreid[i] == SB_PCIE) {
12902 + pcieidx = i;
12903 + pcierev = sb_corerev(&si->sb);
12904 + pcie = TRUE;
12905 + } else if (si->coreid[i] == SB_PCMCIA) {
12906 + si->sb.buscorerev = sb_corerev(&si->sb);
12907 + si->sb.buscoretype = si->coreid[i];
12908 + si->sb.buscoreidx = i;
12909 + }
12910 + }
12911 + if (pci && pcie) {
12912 + if (sb_ispcie(si))
12913 + pci = FALSE;
12914 + else
12915 + pcie = FALSE;
12916 + }
12917 + if (pci) {
12918 + si->sb.buscoretype = SB_PCI;
12919 + si->sb.buscorerev = pcirev;
12920 + si->sb.buscoreidx = pciidx;
12921 + } else if (pcie) {
12922 + si->sb.buscoretype = SB_PCIE;
12923 + si->sb.buscorerev = pcierev;
12924 + si->sb.buscoreidx = pcieidx;
12925 + }
12926 +
12927 + /*
12928 + * Find the gpio "controlling core" type and index.
12929 + * Precedence:
12930 + * - if there's a chip common core - use that
12931 + * - else if there's a pci core (rev >= 2) - use that
12932 + * - else there had better be an extif core (4710 only)
12933 + */
12934 + if (GOODIDX(sb_findcoreidx(si, SB_CC, 0))) {
12935 + si->gpioidx = sb_findcoreidx(si, SB_CC, 0);
12936 + si->gpioid = SB_CC;
12937 + } else if (PCI(si) && (si->sb.buscorerev >= 2)) {
12938 + si->gpioidx = si->sb.buscoreidx;
12939 + si->gpioid = SB_PCI;
12940 + } else if (sb_findcoreidx(si, SB_EXTIF, 0)) {
12941 + si->gpioidx = sb_findcoreidx(si, SB_EXTIF, 0);
12942 + si->gpioid = SB_EXTIF;
12943 + } else
12944 + ASSERT(si->gpioidx != BADIDX);
12945 +
12946 + /* return to original core index */
12947 + sb_setcoreidx(&si->sb, origidx);
12948 +}
12949 +
12950 +/* may be called with core in reset */
12951 +void
12952 +sb_detach(sb_t *sbh)
12953 +{
12954 + sb_info_t *si;
12955 + uint idx;
12956 +
12957 + si = SB_INFO(sbh);
12958 +
12959 + if (si == NULL)
12960 + return;
12961 +
12962 + if (BUSTYPE(si->sb.bustype) == SB_BUS)
12963 + for (idx = 0; idx < SB_MAXCORES; idx++)
12964 + if (si->regs[idx]) {
12965 + REG_UNMAP(si->regs[idx]);
12966 + si->regs[idx] = NULL;
12967 + }
12968 +#if !defined(BCMBUSTYPE) || (BCMBUSTYPE == SB_BUS)
12969 + if (si != &ksi)
12970 +#endif /* !BCMBUSTYPE || (BCMBUSTYPE == SB_BUS) */
12971 + MFREE(si->osh, si, sizeof(sb_info_t));
12972 +
12973 +}
12974 +
12975 +/* use pci dev id to determine chip id for chips not having a chipcommon core */
12976 +static uint
12977 +BCMINITFN(sb_pcidev2chip)(uint pcidev)
12978 +{
12979 + if ((pcidev >= BCM4710_DEVICE_ID) && (pcidev <= BCM47XX_USB_ID))
12980 + return (BCM4710_CHIP_ID);
12981 + if ((pcidev >= BCM4402_ENET_ID) && (pcidev <= BCM4402_V90_ID))
12982 + return (BCM4402_CHIP_ID);
12983 + if (pcidev == BCM4401_ENET_ID)
12984 + return (BCM4402_CHIP_ID);
12985 +
12986 + return (0);
12987 +}
12988 +
12989 +/* convert chip number to number of i/o cores */
12990 +static uint
12991 +BCMINITFN(sb_chip2numcores)(uint chip)
12992 +{
12993 + if (chip == BCM4710_CHIP_ID)
12994 + return (9);
12995 + if (chip == BCM4402_CHIP_ID)
12996 + return (3);
12997 + if (chip == BCM4306_CHIP_ID) /* < 4306c0 */
12998 + return (6);
12999 + if (chip == BCM4704_CHIP_ID)
13000 + return (9);
13001 + if (chip == BCM5365_CHIP_ID)
13002 + return (7);
13003 +
13004 + SB_ERROR(("sb_chip2numcores: unsupported chip 0x%x\n", chip));
13005 + ASSERT(0);
13006 + return (1);
13007 +}
13008 +
13009 +/* return index of coreid or BADIDX if not found */
13010 +static uint
13011 +sb_findcoreidx(sb_info_t *si, uint coreid, uint coreunit)
13012 +{
13013 + uint found;
13014 + uint i;
13015 +
13016 + found = 0;
13017 +
13018 + for (i = 0; i < si->numcores; i++)
13019 + if (si->coreid[i] == coreid) {
13020 + if (found == coreunit)
13021 + return (i);
13022 + found++;
13023 + }
13024 +
13025 + return (BADIDX);
13026 +}
13027 +
13028 +/*
13029 + * this function changes logical "focus" to the indiciated core,
13030 + * must be called with interrupt off.
13031 + * Moreover, callers should keep interrupts off during switching out of and back to d11 core
13032 + */
13033 +void*
13034 +sb_setcoreidx(sb_t *sbh, uint coreidx)
13035 +{
13036 + sb_info_t *si;
13037 + uint32 sbaddr;
13038 + uint8 tmp;
13039 +
13040 + si = SB_INFO(sbh);
13041 +
13042 + if (coreidx >= si->numcores)
13043 + return (NULL);
13044 +
13045 + /*
13046 + * If the user has provided an interrupt mask enabled function,
13047 + * then assert interrupts are disabled before switching the core.
13048 + */
13049 + ASSERT((si->intrsenabled_fn == NULL) || !(*(si)->intrsenabled_fn)((si)->intr_arg));
13050 +
13051 + sbaddr = SB_ENUM_BASE + (coreidx * SB_CORE_SIZE);
13052 +
13053 + switch (BUSTYPE(si->sb.bustype)) {
13054 + case SB_BUS:
13055 + /* map new one */
13056 + if (!si->regs[coreidx]) {
13057 + si->regs[coreidx] = (void*)REG_MAP(sbaddr, SB_CORE_SIZE);
13058 + ASSERT(GOODREGS(si->regs[coreidx]));
13059 + }
13060 + si->curmap = si->regs[coreidx];
13061 + break;
13062 +
13063 + case PCI_BUS:
13064 + /* point bar0 window */
13065 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_BAR0_WIN, 4, sbaddr);
13066 + break;
13067 +
13068 + case PCMCIA_BUS:
13069 + tmp = (sbaddr >> 12) & 0x0f;
13070 + OSL_PCMCIA_WRITE_ATTR(si->osh, PCMCIA_ADDR0, &tmp, 1);
13071 + tmp = (sbaddr >> 16) & 0xff;
13072 + OSL_PCMCIA_WRITE_ATTR(si->osh, PCMCIA_ADDR1, &tmp, 1);
13073 + tmp = (sbaddr >> 24) & 0xff;
13074 + OSL_PCMCIA_WRITE_ATTR(si->osh, PCMCIA_ADDR2, &tmp, 1);
13075 + break;
13076 +#ifdef BCMJTAG
13077 + case JTAG_BUS:
13078 + /* map new one */
13079 + if (!si->regs[coreidx]) {
13080 + si->regs[coreidx] = (void *)sbaddr;
13081 + ASSERT(GOODREGS(si->regs[coreidx]));
13082 + }
13083 + si->curmap = si->regs[coreidx];
13084 + break;
13085 +#endif /* BCMJTAG */
13086 + }
13087 +
13088 + si->curidx = coreidx;
13089 +
13090 + return (si->curmap);
13091 +}
13092 +
13093 +/*
13094 + * this function changes logical "focus" to the indiciated core,
13095 + * must be called with interrupt off.
13096 + * Moreover, callers should keep interrupts off during switching out of and back to d11 core
13097 + */
13098 +void*
13099 +sb_setcore(sb_t *sbh, uint coreid, uint coreunit)
13100 +{
13101 + sb_info_t *si;
13102 + uint idx;
13103 +
13104 + si = SB_INFO(sbh);
13105 + idx = sb_findcoreidx(si, coreid, coreunit);
13106 + if (!GOODIDX(idx))
13107 + return (NULL);
13108 +
13109 + return (sb_setcoreidx(sbh, idx));
13110 +}
13111 +
13112 +/* return chip number */
13113 +uint
13114 +sb_chip(sb_t *sbh)
13115 +{
13116 + sb_info_t *si;
13117 +
13118 + si = SB_INFO(sbh);
13119 + return (si->sb.chip);
13120 +}
13121 +
13122 +/* return chip revision number */
13123 +uint
13124 +sb_chiprev(sb_t *sbh)
13125 +{
13126 + sb_info_t *si;
13127 +
13128 + si = SB_INFO(sbh);
13129 + return (si->sb.chiprev);
13130 +}
13131 +
13132 +/* return chip common revision number */
13133 +uint
13134 +sb_chipcrev(sb_t *sbh)
13135 +{
13136 + sb_info_t *si;
13137 +
13138 + si = SB_INFO(sbh);
13139 + return (si->sb.ccrev);
13140 +}
13141 +
13142 +/* return chip package option */
13143 +uint
13144 +sb_chippkg(sb_t *sbh)
13145 +{
13146 + sb_info_t *si;
13147 +
13148 + si = SB_INFO(sbh);
13149 + return (si->sb.chippkg);
13150 +}
13151 +
13152 +/* return PCI core rev. */
13153 +uint
13154 +sb_pcirev(sb_t *sbh)
13155 +{
13156 + sb_info_t *si;
13157 +
13158 + si = SB_INFO(sbh);
13159 + return (si->sb.buscorerev);
13160 +}
13161 +
13162 +bool
13163 +BCMINITFN(sb_war16165)(sb_t *sbh)
13164 +{
13165 + sb_info_t *si;
13166 +
13167 + si = SB_INFO(sbh);
13168 +
13169 + return (PCI(si) && (si->sb.buscorerev <= 10));
13170 +}
13171 +
13172 +static void
13173 +BCMINITFN(sb_war30841)(sb_info_t *si)
13174 +{
13175 + sb_pcie_mdiowrite(si, MDIODATA_DEV_RX, SERDES_RX_TIMER1, 0x8128);
13176 + sb_pcie_mdiowrite(si, MDIODATA_DEV_RX, SERDES_RX_CDR, 0x0100);
13177 + sb_pcie_mdiowrite(si, MDIODATA_DEV_RX, SERDES_RX_CDRBW, 0x1466);
13178 +}
13179 +
13180 +/* return PCMCIA core rev. */
13181 +uint
13182 +BCMINITFN(sb_pcmciarev)(sb_t *sbh)
13183 +{
13184 + sb_info_t *si;
13185 +
13186 + si = SB_INFO(sbh);
13187 + return (si->sb.buscorerev);
13188 +}
13189 +
13190 +/* return board vendor id */
13191 +uint
13192 +sb_boardvendor(sb_t *sbh)
13193 +{
13194 + sb_info_t *si;
13195 +
13196 + si = SB_INFO(sbh);
13197 + return (si->sb.boardvendor);
13198 +}
13199 +
13200 +/* return boardtype */
13201 +uint
13202 +sb_boardtype(sb_t *sbh)
13203 +{
13204 + sb_info_t *si;
13205 + char *var;
13206 +
13207 + si = SB_INFO(sbh);
13208 +
13209 + if (BUSTYPE(si->sb.bustype) == SB_BUS && si->sb.boardtype == 0xffff) {
13210 + /* boardtype format is a hex string */
13211 + si->sb.boardtype = getintvar(NULL, "boardtype");
13212 +
13213 + /* backward compatibility for older boardtype string format */
13214 + if ((si->sb.boardtype == 0) && (var = getvar(NULL, "boardtype"))) {
13215 + if (!strcmp(var, "bcm94710dev"))
13216 + si->sb.boardtype = BCM94710D_BOARD;
13217 + else if (!strcmp(var, "bcm94710ap"))
13218 + si->sb.boardtype = BCM94710AP_BOARD;
13219 + else if (!strcmp(var, "bu4710"))
13220 + si->sb.boardtype = BU4710_BOARD;
13221 + else if (!strcmp(var, "bcm94702mn"))
13222 + si->sb.boardtype = BCM94702MN_BOARD;
13223 + else if (!strcmp(var, "bcm94710r1"))
13224 + si->sb.boardtype = BCM94710R1_BOARD;
13225 + else if (!strcmp(var, "bcm94710r4"))
13226 + si->sb.boardtype = BCM94710R4_BOARD;
13227 + else if (!strcmp(var, "bcm94702cpci"))
13228 + si->sb.boardtype = BCM94702CPCI_BOARD;
13229 + else if (!strcmp(var, "bcm95380_rr"))
13230 + si->sb.boardtype = BCM95380RR_BOARD;
13231 + }
13232 + }
13233 +
13234 + return (si->sb.boardtype);
13235 +}
13236 +
13237 +/* return bus type of sbh device */
13238 +uint
13239 +sb_bus(sb_t *sbh)
13240 +{
13241 + sb_info_t *si;
13242 +
13243 + si = SB_INFO(sbh);
13244 + return (si->sb.bustype);
13245 +}
13246 +
13247 +/* return bus core type */
13248 +uint
13249 +sb_buscoretype(sb_t *sbh)
13250 +{
13251 + sb_info_t *si;
13252 +
13253 + si = SB_INFO(sbh);
13254 +
13255 + return (si->sb.buscoretype);
13256 +}
13257 +
13258 +/* return bus core revision */
13259 +uint
13260 +sb_buscorerev(sb_t *sbh)
13261 +{
13262 + sb_info_t *si;
13263 + si = SB_INFO(sbh);
13264 +
13265 + return (si->sb.buscorerev);
13266 +}
13267 +
13268 +/* return list of found cores */
13269 +uint
13270 +sb_corelist(sb_t *sbh, uint coreid[])
13271 +{
13272 + sb_info_t *si;
13273 +
13274 + si = SB_INFO(sbh);
13275 +
13276 + bcopy((uchar*)si->coreid, (uchar*)coreid, (si->numcores * sizeof(uint)));
13277 + return (si->numcores);
13278 +}
13279 +
13280 +/* return current register mapping */
13281 +void *
13282 +sb_coreregs(sb_t *sbh)
13283 +{
13284 + sb_info_t *si;
13285 +
13286 + si = SB_INFO(sbh);
13287 + ASSERT(GOODREGS(si->curmap));
13288 +
13289 + return (si->curmap);
13290 +}
13291 +
13292 +
13293 +/* do buffered registers update */
13294 +void
13295 +sb_commit(sb_t *sbh)
13296 +{
13297 + sb_info_t *si;
13298 + uint origidx;
13299 + uint intr_val = 0;
13300 +
13301 + si = SB_INFO(sbh);
13302 +
13303 + origidx = si->curidx;
13304 + ASSERT(GOODIDX(origidx));
13305 +
13306 + INTR_OFF(si, intr_val);
13307 +
13308 + /* switch over to chipcommon core if there is one, else use pci */
13309 + if (si->sb.ccrev != NOREV) {
13310 + chipcregs_t *ccregs = (chipcregs_t *)sb_setcore(sbh, SB_CC, 0);
13311 +
13312 + /* do the buffer registers update */
13313 + W_REG(si->osh, &ccregs->broadcastaddress, SB_COMMIT);
13314 + W_REG(si->osh, &ccregs->broadcastdata, 0x0);
13315 + } else if (PCI(si)) {
13316 + sbpciregs_t *pciregs = (sbpciregs_t *)sb_setcore(sbh, SB_PCI, 0);
13317 +
13318 + /* do the buffer registers update */
13319 + W_REG(si->osh, &pciregs->bcastaddr, SB_COMMIT);
13320 + W_REG(si->osh, &pciregs->bcastdata, 0x0);
13321 + } else
13322 + ASSERT(0);
13323 +
13324 + /* restore core index */
13325 + sb_setcoreidx(sbh, origidx);
13326 + INTR_RESTORE(si, intr_val);
13327 +}
13328 +
13329 +/* reset and re-enable a core
13330 + * inputs:
13331 + * bits - core specific bits that are set during and after reset sequence
13332 + * resetbits - core specific bits that are set only during reset sequence
13333 + */
13334 +void
13335 +sb_core_reset(sb_t *sbh, uint32 bits, uint32 resetbits)
13336 +{
13337 + sb_info_t *si;
13338 + sbconfig_t *sb;
13339 + volatile uint32 dummy;
13340 +
13341 + si = SB_INFO(sbh);
13342 + ASSERT(GOODREGS(si->curmap));
13343 + sb = REGS2SB(si->curmap);
13344 +
13345 + /*
13346 + * Must do the disable sequence first to work for arbitrary current core state.
13347 + */
13348 + sb_core_disable(sbh, (bits | resetbits));
13349 +
13350 + /*
13351 + * Now do the initialization sequence.
13352 + */
13353 +
13354 + /* set reset while enabling the clock and forcing them on throughout the core */
13355 + W_SBREG(si, &sb->sbtmstatelow, (SBTML_FGC | SBTML_CLK | SBTML_RESET | bits | resetbits));
13356 + dummy = R_SBREG(si, &sb->sbtmstatelow);
13357 + OSL_DELAY(1);
13358 +
13359 + if (R_SBREG(si, &sb->sbtmstatehigh) & SBTMH_SERR) {
13360 + W_SBREG(si, &sb->sbtmstatehigh, 0);
13361 + }
13362 + if ((dummy = R_SBREG(si, &sb->sbimstate)) & (SBIM_IBE | SBIM_TO)) {
13363 + AND_SBREG(si, &sb->sbimstate, ~(SBIM_IBE | SBIM_TO));
13364 + }
13365 +
13366 + /* clear reset and allow it to propagate throughout the core */
13367 + W_SBREG(si, &sb->sbtmstatelow, (SBTML_FGC | SBTML_CLK | bits));
13368 + dummy = R_SBREG(si, &sb->sbtmstatelow);
13369 + OSL_DELAY(1);
13370 +
13371 + /* leave clock enabled */
13372 + W_SBREG(si, &sb->sbtmstatelow, (SBTML_CLK | bits));
13373 + dummy = R_SBREG(si, &sb->sbtmstatelow);
13374 + OSL_DELAY(1);
13375 +}
13376 +
13377 +void
13378 +sb_core_tofixup(sb_t *sbh)
13379 +{
13380 + sb_info_t *si;
13381 + sbconfig_t *sb;
13382 +
13383 + si = SB_INFO(sbh);
13384 +
13385 + if ((BUSTYPE(si->sb.bustype) != PCI_BUS) || PCIE(si) ||
13386 + (PCI(si) && (si->sb.buscorerev >= 5)))
13387 + return;
13388 +
13389 + ASSERT(GOODREGS(si->curmap));
13390 + sb = REGS2SB(si->curmap);
13391 +
13392 + if (BUSTYPE(si->sb.bustype) == SB_BUS) {
13393 + SET_SBREG(si, &sb->sbimconfiglow,
13394 + SBIMCL_RTO_MASK | SBIMCL_STO_MASK,
13395 + (0x5 << SBIMCL_RTO_SHIFT) | 0x3);
13396 + } else {
13397 + if (sb_coreid(sbh) == SB_PCI) {
13398 + SET_SBREG(si, &sb->sbimconfiglow,
13399 + SBIMCL_RTO_MASK | SBIMCL_STO_MASK,
13400 + (0x3 << SBIMCL_RTO_SHIFT) | 0x2);
13401 + } else {
13402 + SET_SBREG(si, &sb->sbimconfiglow, (SBIMCL_RTO_MASK | SBIMCL_STO_MASK), 0);
13403 + }
13404 + }
13405 +
13406 + sb_commit(sbh);
13407 +}
13408 +
13409 +/*
13410 + * Set the initiator timeout for the "master core".
13411 + * The master core is defined to be the core in control
13412 + * of the chip and so it issues accesses to non-memory
13413 + * locations (Because of dma *any* core can access memeory).
13414 + *
13415 + * The routine uses the bus to decide who is the master:
13416 + * SB_BUS => mips
13417 + * JTAG_BUS => chipc
13418 + * PCI_BUS => pci or pcie
13419 + * PCMCIA_BUS => pcmcia
13420 + * SDIO_BUS => pcmcia
13421 + *
13422 + * This routine exists so callers can disable initiator
13423 + * timeouts so accesses to very slow devices like otp
13424 + * won't cause an abort. The routine allows arbitrary
13425 + * settings of the service and request timeouts, though.
13426 + *
13427 + * Returns the timeout state before changing it or -1
13428 + * on error.
13429 + */
13430 +
13431 +#define TO_MASK (SBIMCL_RTO_MASK | SBIMCL_STO_MASK)
13432 +
13433 +uint32
13434 +sb_set_initiator_to(sb_t *sbh, uint32 to)
13435 +{
13436 + sb_info_t *si;
13437 + uint origidx, idx;
13438 + uint intr_val = 0;
13439 + uint32 tmp, ret = 0xffffffff;
13440 + sbconfig_t *sb;
13441 +
13442 + si = SB_INFO(sbh);
13443 +
13444 + if ((to & ~TO_MASK) != 0)
13445 + return ret;
13446 +
13447 + /* Figure out the master core */
13448 + idx = BADIDX;
13449 + switch (BUSTYPE(si->sb.bustype)) {
13450 + case PCI_BUS:
13451 + idx = si->sb.buscoreidx;
13452 + break;
13453 + case JTAG_BUS:
13454 + idx = SB_CC_IDX;
13455 + break;
13456 + case PCMCIA_BUS:
13457 + case SDIO_BUS:
13458 + idx = sb_findcoreidx(si, SB_PCMCIA, 0);
13459 + break;
13460 + case SB_BUS:
13461 + if ((idx = sb_findcoreidx(si, SB_MIPS33, 0)) == BADIDX)
13462 + idx = sb_findcoreidx(si, SB_MIPS, 0);
13463 + break;
13464 + default:
13465 + ASSERT(0);
13466 + }
13467 + if (idx == BADIDX)
13468 + return ret;
13469 +
13470 + INTR_OFF(si, intr_val);
13471 + origidx = sb_coreidx(sbh);
13472 +
13473 + sb = REGS2SB(sb_setcoreidx(sbh, idx));
13474 +
13475 + tmp = R_SBREG(si, &sb->sbimconfiglow);
13476 + ret = tmp & TO_MASK;
13477 + W_SBREG(si, &sb->sbimconfiglow, (tmp & ~TO_MASK) | to);
13478 +
13479 + sb_commit(sbh);
13480 + sb_setcoreidx(sbh, origidx);
13481 + INTR_RESTORE(si, intr_val);
13482 + return ret;
13483 +}
13484 +
13485 +void
13486 +sb_core_disable(sb_t *sbh, uint32 bits)
13487 +{
13488 + sb_info_t *si;
13489 + volatile uint32 dummy;
13490 + uint32 rej;
13491 + sbconfig_t *sb;
13492 +
13493 + si = SB_INFO(sbh);
13494 +
13495 + ASSERT(GOODREGS(si->curmap));
13496 + sb = REGS2SB(si->curmap);
13497 +
13498 + /* if core is already in reset, just return */
13499 + if (R_SBREG(si, &sb->sbtmstatelow) & SBTML_RESET)
13500 + return;
13501 +
13502 + /* reject value changed between sonics 2.2 and 2.3 */
13503 + if (si->sb.sonicsrev == SONICS_2_2)
13504 + rej = (1 << SBTML_REJ_SHIFT);
13505 + else
13506 + rej = (2 << SBTML_REJ_SHIFT);
13507 +
13508 + /* if clocks are not enabled, put into reset and return */
13509 + if ((R_SBREG(si, &sb->sbtmstatelow) & SBTML_CLK) == 0)
13510 + goto disable;
13511 +
13512 + /* set target reject and spin until busy is clear (preserve core-specific bits) */
13513 + OR_SBREG(si, &sb->sbtmstatelow, rej);
13514 + dummy = R_SBREG(si, &sb->sbtmstatelow);
13515 + OSL_DELAY(1);
13516 + SPINWAIT((R_SBREG(si, &sb->sbtmstatehigh) & SBTMH_BUSY), 100000);
13517 + if (R_SBREG(si, &sb->sbtmstatehigh) & SBTMH_BUSY)
13518 + SB_ERROR(("%s: target state still busy\n", __FUNCTION__));
13519 +
13520 + if (R_SBREG(si, &sb->sbidlow) & SBIDL_INIT) {
13521 + OR_SBREG(si, &sb->sbimstate, SBIM_RJ);
13522 + dummy = R_SBREG(si, &sb->sbimstate);
13523 + OSL_DELAY(1);
13524 + SPINWAIT((R_SBREG(si, &sb->sbimstate) & SBIM_BY), 100000);
13525 + }
13526 +
13527 + /* set reset and reject while enabling the clocks */
13528 + W_SBREG(si, &sb->sbtmstatelow, (bits | SBTML_FGC | SBTML_CLK | rej | SBTML_RESET));
13529 + dummy = R_SBREG(si, &sb->sbtmstatelow);
13530 + OSL_DELAY(10);
13531 +
13532 + /* don't forget to clear the initiator reject bit */
13533 + if (R_SBREG(si, &sb->sbidlow) & SBIDL_INIT)
13534 + AND_SBREG(si, &sb->sbimstate, ~SBIM_RJ);
13535 +
13536 +disable:
13537 + /* leave reset and reject asserted */
13538 + W_SBREG(si, &sb->sbtmstatelow, (bits | rej | SBTML_RESET));
13539 + OSL_DELAY(1);
13540 +}
13541 +
13542 +/* set chip watchdog reset timer to fire in 'ticks' backplane cycles */
13543 +void
13544 +sb_watchdog(sb_t *sbh, uint ticks)
13545 +{
13546 + sb_info_t *si = SB_INFO(sbh);
13547 +
13548 + /* make sure we come up in fast clock mode */
13549 + sb_clkctl_clk(sbh, CLK_FAST);
13550 +
13551 + /* instant NMI */
13552 + switch (si->gpioid) {
13553 + case SB_CC:
13554 +#ifdef __mips__
13555 + if (sb_chip(sbh) == BCM4785_CHIP_ID && ticks <= 1)
13556 + MTC0(C0_BROADCOM, 4, (1 << 22));
13557 +#endif /* __mips__ */
13558 + sb_corereg(si, 0, OFFSETOF(chipcregs_t, watchdog), ~0, ticks);
13559 +#ifdef __mips__
13560 + if (sb_chip(sbh) == BCM4785_CHIP_ID && ticks <= 1) {
13561 + __asm__ __volatile__ (
13562 + ".set\tmips3\n\t"
13563 + "sync\n\t"
13564 + "wait\n\t"
13565 + ".set\tmips0"
13566 + );
13567 + while (1);
13568 + }
13569 +#endif /* __mips__ */
13570 + break;
13571 + case SB_EXTIF:
13572 + sb_corereg(si, si->gpioidx, OFFSETOF(extifregs_t, watchdog), ~0, ticks);
13573 + break;
13574 + }
13575 +}
13576 +
13577 +/* initialize the pcmcia core */
13578 +void
13579 +sb_pcmcia_init(sb_t *sbh)
13580 +{
13581 + sb_info_t *si;
13582 + uint8 cor = 0;
13583 +
13584 + si = SB_INFO(sbh);
13585 +
13586 + /* enable d11 mac interrupts */
13587 + OSL_PCMCIA_READ_ATTR(si->osh, PCMCIA_FCR0 + PCMCIA_COR, &cor, 1);
13588 + cor |= COR_IRQEN | COR_FUNEN;
13589 + OSL_PCMCIA_WRITE_ATTR(si->osh, PCMCIA_FCR0 + PCMCIA_COR, &cor, 1);
13590 +
13591 +}
13592 +
13593 +
13594 +/*
13595 + * Configure the pci core for pci client (NIC) action
13596 + * coremask is the bitvec of cores by index to be enabled.
13597 + */
13598 +void
13599 +BCMINITFN(sb_pci_setup)(sb_t *sbh, uint coremask)
13600 +{
13601 + sb_info_t *si;
13602 + sbconfig_t *sb;
13603 + sbpciregs_t *pciregs;
13604 + uint32 sbflag;
13605 + uint32 w;
13606 + uint idx;
13607 + int reg_val;
13608 +
13609 + si = SB_INFO(sbh);
13610 +
13611 + /* if not pci bus, we're done */
13612 + if (BUSTYPE(si->sb.bustype) != PCI_BUS)
13613 + return;
13614 +
13615 + ASSERT(PCI(si) || PCIE(si));
13616 + ASSERT(si->sb.buscoreidx != BADIDX);
13617 +
13618 + /* get current core index */
13619 + idx = si->curidx;
13620 +
13621 + /* we interrupt on this backplane flag number */
13622 + ASSERT(GOODREGS(si->curmap));
13623 + sb = REGS2SB(si->curmap);
13624 + sbflag = R_SBREG(si, &sb->sbtpsflag) & SBTPS_NUM0_MASK;
13625 +
13626 + /* switch over to pci core */
13627 + pciregs = (sbpciregs_t*) sb_setcoreidx(sbh, si->sb.buscoreidx);
13628 + sb = REGS2SB(pciregs);
13629 +
13630 + /*
13631 + * Enable sb->pci interrupts. Assume
13632 + * PCI rev 2.3 support was added in pci core rev 6 and things changed..
13633 + */
13634 + if (PCIE(si) || (PCI(si) && ((si->sb.buscorerev) >= 6))) {
13635 + /* pci config write to set this core bit in PCIIntMask */
13636 + w = OSL_PCI_READ_CONFIG(si->osh, PCI_INT_MASK, sizeof(uint32));
13637 + w |= (coremask << PCI_SBIM_SHIFT);
13638 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_INT_MASK, sizeof(uint32), w);
13639 + } else {
13640 + /* set sbintvec bit for our flag number */
13641 + OR_SBREG(si, &sb->sbintvec, (1 << sbflag));
13642 + }
13643 +
13644 + if (PCI(si)) {
13645 + OR_REG(si->osh, &pciregs->sbtopci2, (SBTOPCI_PREF|SBTOPCI_BURST));
13646 + if (si->sb.buscorerev >= 11)
13647 + OR_REG(si->osh, &pciregs->sbtopci2, SBTOPCI_RC_READMULTI);
13648 + if (si->sb.buscorerev < 5) {
13649 + SET_SBREG(si, &sb->sbimconfiglow, SBIMCL_RTO_MASK | SBIMCL_STO_MASK,
13650 + (0x3 << SBIMCL_RTO_SHIFT) | 0x2);
13651 + sb_commit(sbh);
13652 + }
13653 + }
13654 +
13655 +#ifdef PCIE_SUPPOER
13656 + /* PCIE workarounds */
13657 + if (PCIE(si)) {
13658 + if ((si->sb.buscorerev == 0) || (si->sb.buscorerev == 1)) {
13659 + reg_val = sb_pcie_readreg((void *)sbh, (void *)PCIE_PCIEREGS,
13660 + PCIE_TLP_WORKAROUNDSREG);
13661 + reg_val |= 0x8;
13662 + sb_pcie_writereg((void *)sbh, (void *)PCIE_PCIEREGS,
13663 + PCIE_TLP_WORKAROUNDSREG, reg_val);
13664 + }
13665 +
13666 + if (si->sb.buscorerev == 1) {
13667 + reg_val = sb_pcie_readreg((void *)sbh, (void *)PCIE_PCIEREGS,
13668 + PCIE_DLLP_LCREG);
13669 + reg_val |= (0x40);
13670 + sb_pcie_writereg(sbh, (void *)PCIE_PCIEREGS, PCIE_DLLP_LCREG, reg_val);
13671 + }
13672 +
13673 + if (si->sb.buscorerev == 0)
13674 + sb_war30841(si);
13675 + }
13676 +#endif
13677 +
13678 + /* switch back to previous core */
13679 + sb_setcoreidx(sbh, idx);
13680 +}
13681 +
13682 +uint32
13683 +sb_base(uint32 admatch)
13684 +{
13685 + uint32 base;
13686 + uint type;
13687 +
13688 + type = admatch & SBAM_TYPE_MASK;
13689 + ASSERT(type < 3);
13690 +
13691 + base = 0;
13692 +
13693 + if (type == 0) {
13694 + base = admatch & SBAM_BASE0_MASK;
13695 + } else if (type == 1) {
13696 + ASSERT(!(admatch & SBAM_ADNEG)); /* neg not supported */
13697 + base = admatch & SBAM_BASE1_MASK;
13698 + } else if (type == 2) {
13699 + ASSERT(!(admatch & SBAM_ADNEG)); /* neg not supported */
13700 + base = admatch & SBAM_BASE2_MASK;
13701 + }
13702 +
13703 + return (base);
13704 +}
13705 +
13706 +uint32
13707 +sb_size(uint32 admatch)
13708 +{
13709 + uint32 size;
13710 + uint type;
13711 +
13712 + type = admatch & SBAM_TYPE_MASK;
13713 + ASSERT(type < 3);
13714 +
13715 + size = 0;
13716 +
13717 + if (type == 0) {
13718 + size = 1 << (((admatch & SBAM_ADINT0_MASK) >> SBAM_ADINT0_SHIFT) + 1);
13719 + } else if (type == 1) {
13720 + ASSERT(!(admatch & SBAM_ADNEG)); /* neg not supported */
13721 + size = 1 << (((admatch & SBAM_ADINT1_MASK) >> SBAM_ADINT1_SHIFT) + 1);
13722 + } else if (type == 2) {
13723 + ASSERT(!(admatch & SBAM_ADNEG)); /* neg not supported */
13724 + size = 1 << (((admatch & SBAM_ADINT2_MASK) >> SBAM_ADINT2_SHIFT) + 1);
13725 + }
13726 +
13727 + return (size);
13728 +}
13729 +
13730 +/* return the core-type instantiation # of the current core */
13731 +uint
13732 +sb_coreunit(sb_t *sbh)
13733 +{
13734 + sb_info_t *si;
13735 + uint idx;
13736 + uint coreid;
13737 + uint coreunit;
13738 + uint i;
13739 +
13740 + si = SB_INFO(sbh);
13741 + coreunit = 0;
13742 +
13743 + idx = si->curidx;
13744 +
13745 + ASSERT(GOODREGS(si->curmap));
13746 + coreid = sb_coreid(sbh);
13747 +
13748 + /* count the cores of our type */
13749 + for (i = 0; i < idx; i++)
13750 + if (si->coreid[i] == coreid)
13751 + coreunit++;
13752 +
13753 + return (coreunit);
13754 +}
13755 +
13756 +static INLINE uint32
13757 +factor6(uint32 x)
13758 +{
13759 + switch (x) {
13760 + case CC_F6_2: return 2;
13761 + case CC_F6_3: return 3;
13762 + case CC_F6_4: return 4;
13763 + case CC_F6_5: return 5;
13764 + case CC_F6_6: return 6;
13765 + case CC_F6_7: return 7;
13766 + default: return 0;
13767 + }
13768 +}
13769 +
13770 +/* calculate the speed the SB would run at given a set of clockcontrol values */
13771 +uint32
13772 +sb_clock_rate(uint32 pll_type, uint32 n, uint32 m)
13773 +{
13774 + uint32 n1, n2, clock, m1, m2, m3, mc;
13775 +
13776 + n1 = n & CN_N1_MASK;
13777 + n2 = (n & CN_N2_MASK) >> CN_N2_SHIFT;
13778 +
13779 + if (pll_type == PLL_TYPE6) {
13780 + if (m & CC_T6_MMASK)
13781 + return CC_T6_M1;
13782 + else
13783 + return CC_T6_M0;
13784 + } else if ((pll_type == PLL_TYPE1) ||
13785 + (pll_type == PLL_TYPE3) ||
13786 + (pll_type == PLL_TYPE4) ||
13787 + (pll_type == PLL_TYPE7)) {
13788 + n1 = factor6(n1);
13789 + n2 += CC_F5_BIAS;
13790 + } else if (pll_type == PLL_TYPE2) {
13791 + n1 += CC_T2_BIAS;
13792 + n2 += CC_T2_BIAS;
13793 + ASSERT((n1 >= 2) && (n1 <= 7));
13794 + ASSERT((n2 >= 5) && (n2 <= 23));
13795 + } else if (pll_type == PLL_TYPE5) {
13796 + return (100000000);
13797 + } else
13798 + ASSERT(0);
13799 + /* PLL types 3 and 7 use BASE2 (25Mhz) */
13800 + if ((pll_type == PLL_TYPE3) ||
13801 + (pll_type == PLL_TYPE7)) {
13802 + clock = CC_CLOCK_BASE2 * n1 * n2;
13803 + } else
13804 + clock = CC_CLOCK_BASE1 * n1 * n2;
13805 +
13806 + if (clock == 0)
13807 + return 0;
13808 +
13809 + m1 = m & CC_M1_MASK;
13810 + m2 = (m & CC_M2_MASK) >> CC_M2_SHIFT;
13811 + m3 = (m & CC_M3_MASK) >> CC_M3_SHIFT;
13812 + mc = (m & CC_MC_MASK) >> CC_MC_SHIFT;
13813 +
13814 + if ((pll_type == PLL_TYPE1) ||
13815 + (pll_type == PLL_TYPE3) ||
13816 + (pll_type == PLL_TYPE4) ||
13817 + (pll_type == PLL_TYPE7)) {
13818 + m1 = factor6(m1);
13819 + if ((pll_type == PLL_TYPE1) || (pll_type == PLL_TYPE3))
13820 + m2 += CC_F5_BIAS;
13821 + else
13822 + m2 = factor6(m2);
13823 + m3 = factor6(m3);
13824 +
13825 + switch (mc) {
13826 + case CC_MC_BYPASS: return (clock);
13827 + case CC_MC_M1: return (clock / m1);
13828 + case CC_MC_M1M2: return (clock / (m1 * m2));
13829 + case CC_MC_M1M2M3: return (clock / (m1 * m2 * m3));
13830 + case CC_MC_M1M3: return (clock / (m1 * m3));
13831 + default: return (0);
13832 + }
13833 + } else {
13834 + ASSERT(pll_type == PLL_TYPE2);
13835 +
13836 + m1 += CC_T2_BIAS;
13837 + m2 += CC_T2M2_BIAS;
13838 + m3 += CC_T2_BIAS;
13839 + ASSERT((m1 >= 2) && (m1 <= 7));
13840 + ASSERT((m2 >= 3) && (m2 <= 10));
13841 + ASSERT((m3 >= 2) && (m3 <= 7));
13842 +
13843 + if ((mc & CC_T2MC_M1BYP) == 0)
13844 + clock /= m1;
13845 + if ((mc & CC_T2MC_M2BYP) == 0)
13846 + clock /= m2;
13847 + if ((mc & CC_T2MC_M3BYP) == 0)
13848 + clock /= m3;
13849 +
13850 + return (clock);
13851 + }
13852 +}
13853 +
13854 +/* returns the current speed the SB is running at */
13855 +uint32
13856 +sb_clock(sb_t *sbh)
13857 +{
13858 + sb_info_t *si;
13859 + extifregs_t *eir;
13860 + chipcregs_t *cc;
13861 + uint32 n, m;
13862 + uint idx;
13863 + uint32 pll_type, rate;
13864 + uint intr_val = 0;
13865 +
13866 + si = SB_INFO(sbh);
13867 + idx = si->curidx;
13868 + pll_type = PLL_TYPE1;
13869 +
13870 + INTR_OFF(si, intr_val);
13871 +
13872 + /* switch to extif or chipc core */
13873 + if ((eir = (extifregs_t *) sb_setcore(sbh, SB_EXTIF, 0))) {
13874 + n = R_REG(si->osh, &eir->clockcontrol_n);
13875 + m = R_REG(si->osh, &eir->clockcontrol_sb);
13876 + } else if ((cc = (chipcregs_t *) sb_setcore(sbh, SB_CC, 0))) {
13877 + pll_type = R_REG(si->osh, &cc->capabilities) & CAP_PLL_MASK;
13878 + if (pll_type == PLL_NONE) {
13879 + INTR_RESTORE(si, intr_val);
13880 + return 80000000;
13881 + }
13882 + n = R_REG(si->osh, &cc->clockcontrol_n);
13883 + if (pll_type == PLL_TYPE6)
13884 + m = R_REG(si->osh, &cc->clockcontrol_m3);
13885 + else if ((pll_type == PLL_TYPE3) && !(BCMINIT(sb_chip)(sbh) == 0x5365))
13886 + m = R_REG(si->osh, &cc->clockcontrol_m2);
13887 + else
13888 + m = R_REG(si->osh, &cc->clockcontrol_sb);
13889 + } else {
13890 + INTR_RESTORE(si, intr_val);
13891 + return 0;
13892 + }
13893 +
13894 + /* calculate rate */
13895 + if (BCMINIT(sb_chip)(sbh) == 0x5365)
13896 + rate = 100000000;
13897 + else {
13898 + rate = sb_clock_rate(pll_type, n, m);
13899 +
13900 + if (pll_type == PLL_TYPE3)
13901 + rate = rate / 2;
13902 + }
13903 +
13904 + /* switch back to previous core */
13905 + sb_setcoreidx(sbh, idx);
13906 +
13907 + INTR_RESTORE(si, intr_val);
13908 +
13909 + return rate;
13910 +}
13911 +
13912 +/* change logical "focus" to the gpio core for optimized access */
13913 +void*
13914 +sb_gpiosetcore(sb_t *sbh)
13915 +{
13916 + sb_info_t *si;
13917 +
13918 + si = SB_INFO(sbh);
13919 +
13920 + return (sb_setcoreidx(sbh, si->gpioidx));
13921 +}
13922 +
13923 +/* mask&set gpiocontrol bits */
13924 +uint32
13925 +sb_gpiocontrol(sb_t *sbh, uint32 mask, uint32 val, uint8 priority)
13926 +{
13927 + sb_info_t *si;
13928 + uint regoff;
13929 +
13930 + si = SB_INFO(sbh);
13931 + regoff = 0;
13932 +
13933 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
13934 +
13935 + /* gpios could be shared on router platforms */
13936 + if ((BUSTYPE(si->sb.bustype) == SB_BUS) && (val || mask)) {
13937 + mask = priority ? (sb_gpioreservation & mask) :
13938 + ((sb_gpioreservation | mask) & ~(sb_gpioreservation));
13939 + val &= mask;
13940 + }
13941 +
13942 + switch (si->gpioid) {
13943 + case SB_CC:
13944 + regoff = OFFSETOF(chipcregs_t, gpiocontrol);
13945 + break;
13946 +
13947 + case SB_PCI:
13948 + regoff = OFFSETOF(sbpciregs_t, gpiocontrol);
13949 + break;
13950 +
13951 + case SB_EXTIF:
13952 + return (0);
13953 + }
13954 +
13955 + return (sb_corereg(si, si->gpioidx, regoff, mask, val));
13956 +}
13957 +
13958 +/* mask&set gpio output enable bits */
13959 +uint32
13960 +sb_gpioouten(sb_t *sbh, uint32 mask, uint32 val, uint8 priority)
13961 +{
13962 + sb_info_t *si;
13963 + uint regoff;
13964 +
13965 + si = SB_INFO(sbh);
13966 + regoff = 0;
13967 +
13968 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
13969 +
13970 + /* gpios could be shared on router platforms */
13971 + if ((BUSTYPE(si->sb.bustype) == SB_BUS) && (val || mask)) {
13972 + mask = priority ? (sb_gpioreservation & mask) :
13973 + ((sb_gpioreservation | mask) & ~(sb_gpioreservation));
13974 + val &= mask;
13975 + }
13976 +
13977 + switch (si->gpioid) {
13978 + case SB_CC:
13979 + regoff = OFFSETOF(chipcregs_t, gpioouten);
13980 + break;
13981 +
13982 + case SB_PCI:
13983 + regoff = OFFSETOF(sbpciregs_t, gpioouten);
13984 + break;
13985 +
13986 + case SB_EXTIF:
13987 + regoff = OFFSETOF(extifregs_t, gpio[0].outen);
13988 + break;
13989 + }
13990 +
13991 + return (sb_corereg(si, si->gpioidx, regoff, mask, val));
13992 +}
13993 +
13994 +/* mask&set gpio output bits */
13995 +uint32
13996 +sb_gpioout(sb_t *sbh, uint32 mask, uint32 val, uint8 priority)
13997 +{
13998 + sb_info_t *si;
13999 + uint regoff;
14000 +
14001 + si = SB_INFO(sbh);
14002 + regoff = 0;
14003 +
14004 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
14005 +
14006 + /* gpios could be shared on router platforms */
14007 + if ((BUSTYPE(si->sb.bustype) == SB_BUS) && (val || mask)) {
14008 + mask = priority ? (sb_gpioreservation & mask) :
14009 + ((sb_gpioreservation | mask) & ~(sb_gpioreservation));
14010 + val &= mask;
14011 + }
14012 +
14013 + switch (si->gpioid) {
14014 + case SB_CC:
14015 + regoff = OFFSETOF(chipcregs_t, gpioout);
14016 + break;
14017 +
14018 + case SB_PCI:
14019 + regoff = OFFSETOF(sbpciregs_t, gpioout);
14020 + break;
14021 +
14022 + case SB_EXTIF:
14023 + regoff = OFFSETOF(extifregs_t, gpio[0].out);
14024 + break;
14025 + }
14026 +
14027 + return (sb_corereg(si, si->gpioidx, regoff, mask, val));
14028 +}
14029 +
14030 +/* reserve one gpio */
14031 +uint32
14032 +sb_gpioreserve(sb_t *sbh, uint32 gpio_bitmask, uint8 priority)
14033 +{
14034 + sb_info_t *si;
14035 +
14036 + si = SB_INFO(sbh);
14037 +
14038 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
14039 +
14040 + /* only cores on SB_BUS share GPIO's and only applcation users need to
14041 + * reserve/release GPIO
14042 + */
14043 + if ((BUSTYPE(si->sb.bustype) != SB_BUS) || (!priority)) {
14044 + ASSERT((BUSTYPE(si->sb.bustype) == SB_BUS) && (priority));
14045 + return -1;
14046 + }
14047 + /* make sure only one bit is set */
14048 + if ((!gpio_bitmask) || ((gpio_bitmask) & (gpio_bitmask - 1))) {
14049 + ASSERT((gpio_bitmask) && !((gpio_bitmask) & (gpio_bitmask - 1)));
14050 + return -1;
14051 + }
14052 +
14053 + /* already reserved */
14054 + if (sb_gpioreservation & gpio_bitmask)
14055 + return -1;
14056 + /* set reservation */
14057 + sb_gpioreservation |= gpio_bitmask;
14058 +
14059 + return sb_gpioreservation;
14060 +}
14061 +
14062 +/* release one gpio */
14063 +/*
14064 + * releasing the gpio doesn't change the current value on the GPIO last write value
14065 + * persists till some one overwrites it
14066 +*/
14067 +
14068 +uint32
14069 +sb_gpiorelease(sb_t *sbh, uint32 gpio_bitmask, uint8 priority)
14070 +{
14071 + sb_info_t *si;
14072 +
14073 + si = SB_INFO(sbh);
14074 +
14075 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
14076 +
14077 + /* only cores on SB_BUS share GPIO's and only applcation users need to
14078 + * reserve/release GPIO
14079 + */
14080 + if ((BUSTYPE(si->sb.bustype) != SB_BUS) || (!priority)) {
14081 + ASSERT((BUSTYPE(si->sb.bustype) == SB_BUS) && (priority));
14082 + return -1;
14083 + }
14084 + /* make sure only one bit is set */
14085 + if ((!gpio_bitmask) || ((gpio_bitmask) & (gpio_bitmask - 1))) {
14086 + ASSERT((gpio_bitmask) && !((gpio_bitmask) & (gpio_bitmask - 1)));
14087 + return -1;
14088 + }
14089 +
14090 + /* already released */
14091 + if (!(sb_gpioreservation & gpio_bitmask))
14092 + return -1;
14093 +
14094 + /* clear reservation */
14095 + sb_gpioreservation &= ~gpio_bitmask;
14096 +
14097 + return sb_gpioreservation;
14098 +}
14099 +
14100 +/* return the current gpioin register value */
14101 +uint32
14102 +sb_gpioin(sb_t *sbh)
14103 +{
14104 + sb_info_t *si;
14105 + uint regoff;
14106 +
14107 + si = SB_INFO(sbh);
14108 + regoff = 0;
14109 +
14110 + switch (si->gpioid) {
14111 + case SB_CC:
14112 + regoff = OFFSETOF(chipcregs_t, gpioin);
14113 + break;
14114 +
14115 + case SB_PCI:
14116 + regoff = OFFSETOF(sbpciregs_t, gpioin);
14117 + break;
14118 +
14119 + case SB_EXTIF:
14120 + regoff = OFFSETOF(extifregs_t, gpioin);
14121 + break;
14122 + }
14123 +
14124 + return (sb_corereg(si, si->gpioidx, regoff, 0, 0));
14125 +}
14126 +
14127 +/* mask&set gpio interrupt polarity bits */
14128 +uint32
14129 +sb_gpiointpolarity(sb_t *sbh, uint32 mask, uint32 val, uint8 priority)
14130 +{
14131 + sb_info_t *si;
14132 + uint regoff;
14133 +
14134 + si = SB_INFO(sbh);
14135 + regoff = 0;
14136 +
14137 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
14138 +
14139 + /* gpios could be shared on router platforms */
14140 + if ((BUSTYPE(si->sb.bustype) == SB_BUS) && (val || mask)) {
14141 + mask = priority ? (sb_gpioreservation & mask) :
14142 + ((sb_gpioreservation | mask) & ~(sb_gpioreservation));
14143 + val &= mask;
14144 + }
14145 +
14146 + switch (si->gpioid) {
14147 + case SB_CC:
14148 + regoff = OFFSETOF(chipcregs_t, gpiointpolarity);
14149 + break;
14150 +
14151 + case SB_PCI:
14152 + /* pci gpio implementation does not support interrupt polarity */
14153 + ASSERT(0);
14154 + break;
14155 +
14156 + case SB_EXTIF:
14157 + regoff = OFFSETOF(extifregs_t, gpiointpolarity);
14158 + break;
14159 + }
14160 +
14161 + return (sb_corereg(si, si->gpioidx, regoff, mask, val));
14162 +}
14163 +
14164 +/* mask&set gpio interrupt mask bits */
14165 +uint32
14166 +sb_gpiointmask(sb_t *sbh, uint32 mask, uint32 val, uint8 priority)
14167 +{
14168 + sb_info_t *si;
14169 + uint regoff;
14170 +
14171 + si = SB_INFO(sbh);
14172 + regoff = 0;
14173 +
14174 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
14175 +
14176 + /* gpios could be shared on router platforms */
14177 + if ((BUSTYPE(si->sb.bustype) == SB_BUS) && (val || mask)) {
14178 + mask = priority ? (sb_gpioreservation & mask) :
14179 + ((sb_gpioreservation | mask) & ~(sb_gpioreservation));
14180 + val &= mask;
14181 + }
14182 +
14183 + switch (si->gpioid) {
14184 + case SB_CC:
14185 + regoff = OFFSETOF(chipcregs_t, gpiointmask);
14186 + break;
14187 +
14188 + case SB_PCI:
14189 + /* pci gpio implementation does not support interrupt mask */
14190 + ASSERT(0);
14191 + break;
14192 +
14193 + case SB_EXTIF:
14194 + regoff = OFFSETOF(extifregs_t, gpiointmask);
14195 + break;
14196 + }
14197 +
14198 + return (sb_corereg(si, si->gpioidx, regoff, mask, val));
14199 +}
14200 +
14201 +/* assign the gpio to an led */
14202 +uint32
14203 +sb_gpioled(sb_t *sbh, uint32 mask, uint32 val)
14204 +{
14205 + sb_info_t *si;
14206 +
14207 + si = SB_INFO(sbh);
14208 + if (si->sb.ccrev < 16)
14209 + return -1;
14210 +
14211 + /* gpio led powersave reg */
14212 + return (sb_corereg(si, 0, OFFSETOF(chipcregs_t, gpiotimeroutmask), mask, val));
14213 +}
14214 +
14215 +/* mask & set gpio timer val */
14216 +uint32
14217 +sb_gpiotimerval(sb_t *sbh, uint32 mask, uint32 gpiotimerval)
14218 +{
14219 + sb_info_t *si;
14220 + si = SB_INFO(sbh);
14221 +
14222 + if (si->sb.ccrev < 16)
14223 + return -1;
14224 +
14225 + return (sb_corereg(si, 0, OFFSETOF(chipcregs_t, gpiotimerval), mask, gpiotimerval));
14226 +}
14227 +
14228 +
14229 +/* return the slow clock source - LPO, XTAL, or PCI */
14230 +static uint
14231 +sb_slowclk_src(sb_info_t *si)
14232 +{
14233 + chipcregs_t *cc;
14234 +
14235 +
14236 + ASSERT(sb_coreid(&si->sb) == SB_CC);
14237 +
14238 + if (si->sb.ccrev < 6) {
14239 + if ((BUSTYPE(si->sb.bustype) == PCI_BUS) &&
14240 + (OSL_PCI_READ_CONFIG(si->osh, PCI_GPIO_OUT, sizeof(uint32)) &
14241 + PCI_CFG_GPIO_SCS))
14242 + return (SCC_SS_PCI);
14243 + else
14244 + return (SCC_SS_XTAL);
14245 + } else if (si->sb.ccrev < 10) {
14246 + cc = (chipcregs_t*) sb_setcoreidx(&si->sb, si->curidx);
14247 + return (R_REG(si->osh, &cc->slow_clk_ctl) & SCC_SS_MASK);
14248 + } else /* Insta-clock */
14249 + return (SCC_SS_XTAL);
14250 +}
14251 +
14252 +/* return the ILP (slowclock) min or max frequency */
14253 +static uint
14254 +sb_slowclk_freq(sb_info_t *si, bool max)
14255 +{
14256 + chipcregs_t *cc;
14257 + uint32 slowclk;
14258 + uint div;
14259 +
14260 +
14261 + ASSERT(sb_coreid(&si->sb) == SB_CC);
14262 +
14263 + cc = (chipcregs_t*) sb_setcoreidx(&si->sb, si->curidx);
14264 +
14265 + /* shouldn't be here unless we've established the chip has dynamic clk control */
14266 + ASSERT(R_REG(si->osh, &cc->capabilities) & CAP_PWR_CTL);
14267 +
14268 + slowclk = sb_slowclk_src(si);
14269 + if (si->sb.ccrev < 6) {
14270 + if (slowclk == SCC_SS_PCI)
14271 + return (max? (PCIMAXFREQ/64) : (PCIMINFREQ/64));
14272 + else
14273 + return (max? (XTALMAXFREQ/32) : (XTALMINFREQ/32));
14274 + } else if (si->sb.ccrev < 10) {
14275 + div = 4 * (((R_REG(si->osh, &cc->slow_clk_ctl) & SCC_CD_MASK) >> SCC_CD_SHIFT) + 1);
14276 + if (slowclk == SCC_SS_LPO)
14277 + return (max? LPOMAXFREQ : LPOMINFREQ);
14278 + else if (slowclk == SCC_SS_XTAL)
14279 + return (max? (XTALMAXFREQ/div) : (XTALMINFREQ/div));
14280 + else if (slowclk == SCC_SS_PCI)
14281 + return (max? (PCIMAXFREQ/div) : (PCIMINFREQ/div));
14282 + else
14283 + ASSERT(0);
14284 + } else {
14285 + /* Chipc rev 10 is InstaClock */
14286 + div = R_REG(si->osh, &cc->system_clk_ctl) >> SYCC_CD_SHIFT;
14287 + div = 4 * (div + 1);
14288 + return (max ? XTALMAXFREQ : (XTALMINFREQ/div));
14289 + }
14290 + return (0);
14291 +}
14292 +
14293 +static void
14294 +BCMINITFN(sb_clkctl_setdelay)(sb_info_t *si, void *chipcregs)
14295 +{
14296 + chipcregs_t * cc;
14297 + uint slowmaxfreq, pll_delay, slowclk;
14298 + uint pll_on_delay, fref_sel_delay;
14299 +
14300 + pll_delay = PLL_DELAY;
14301 +
14302 + /* If the slow clock is not sourced by the xtal then add the xtal_on_delay
14303 + * since the xtal will also be powered down by dynamic clk control logic.
14304 + */
14305 +
14306 + slowclk = sb_slowclk_src(si);
14307 + if (slowclk != SCC_SS_XTAL)
14308 + pll_delay += XTAL_ON_DELAY;
14309 +
14310 + /* Starting with 4318 it is ILP that is used for the delays */
14311 + slowmaxfreq = sb_slowclk_freq(si, (si->sb.ccrev >= 10) ? FALSE : TRUE);
14312 +
14313 + pll_on_delay = ((slowmaxfreq * pll_delay) + 999999) / 1000000;
14314 + fref_sel_delay = ((slowmaxfreq * FREF_DELAY) + 999999) / 1000000;
14315 +
14316 + cc = (chipcregs_t *)chipcregs;
14317 + W_REG(si->osh, &cc->pll_on_delay, pll_on_delay);
14318 + W_REG(si->osh, &cc->fref_sel_delay, fref_sel_delay);
14319 +}
14320 +
14321 +/* initialize power control delay registers */
14322 +void
14323 +BCMINITFN(sb_clkctl_init)(sb_t *sbh)
14324 +{
14325 + sb_info_t *si;
14326 + uint origidx;
14327 + chipcregs_t *cc;
14328 +
14329 + si = SB_INFO(sbh);
14330 +
14331 + origidx = si->curidx;
14332 +
14333 + if ((cc = (chipcregs_t*) sb_setcore(sbh, SB_CC, 0)) == NULL)
14334 + return;
14335 +
14336 + if ((si->sb.chip == BCM4321_CHIP_ID) && (si->sb.chiprev < 2))
14337 + W_REG(si->osh, &cc->chipcontrol,
14338 + (si->sb.chiprev == 0) ? CHIPCTRL_4321A0_DEFAULT : CHIPCTRL_4321A1_DEFAULT);
14339 +
14340 + if (!(R_REG(si->osh, &cc->capabilities) & CAP_PWR_CTL))
14341 + goto done;
14342 +
14343 + /* set all Instaclk chip ILP to 1 MHz */
14344 + else if (si->sb.ccrev >= 10)
14345 + SET_REG(si->osh, &cc->system_clk_ctl, SYCC_CD_MASK,
14346 + (ILP_DIV_1MHZ << SYCC_CD_SHIFT));
14347 +
14348 + sb_clkctl_setdelay(si, (void *)cc);
14349 +
14350 +done:
14351 + sb_setcoreidx(sbh, origidx);
14352 +}
14353 +
14354 +/* return the value suitable for writing to the dot11 core FAST_PWRUP_DELAY register */
14355 +uint16
14356 +sb_clkctl_fast_pwrup_delay(sb_t *sbh)
14357 +{
14358 + sb_info_t *si;
14359 + uint origidx;
14360 + chipcregs_t *cc;
14361 + uint slowminfreq;
14362 + uint16 fpdelay;
14363 + uint intr_val = 0;
14364 +
14365 + si = SB_INFO(sbh);
14366 + fpdelay = 0;
14367 + origidx = si->curidx;
14368 +
14369 + INTR_OFF(si, intr_val);
14370 +
14371 + if ((cc = (chipcregs_t*) sb_setcore(sbh, SB_CC, 0)) == NULL)
14372 + goto done;
14373 +
14374 + if (!(R_REG(si->osh, &cc->capabilities) & CAP_PWR_CTL))
14375 + goto done;
14376 +
14377 + slowminfreq = sb_slowclk_freq(si, FALSE);
14378 + fpdelay = (((R_REG(si->osh, &cc->pll_on_delay) + 2) * 1000000) +
14379 + (slowminfreq - 1)) / slowminfreq;
14380 +
14381 +done:
14382 + sb_setcoreidx(sbh, origidx);
14383 + INTR_RESTORE(si, intr_val);
14384 + return (fpdelay);
14385 +}
14386 +
14387 +/* turn primary xtal and/or pll off/on */
14388 +int
14389 +sb_clkctl_xtal(sb_t *sbh, uint what, bool on)
14390 +{
14391 + sb_info_t *si;
14392 + uint32 in, out, outen;
14393 +
14394 + si = SB_INFO(sbh);
14395 +
14396 + switch (BUSTYPE(si->sb.bustype)) {
14397 +
14398 +
14399 + case PCMCIA_BUS:
14400 + return (0);
14401 +
14402 +
14403 + case PCI_BUS:
14404 +
14405 + /* pcie core doesn't have any mapping to control the xtal pu */
14406 + if (PCIE(si))
14407 + return -1;
14408 +
14409 + in = OSL_PCI_READ_CONFIG(si->osh, PCI_GPIO_IN, sizeof(uint32));
14410 + out = OSL_PCI_READ_CONFIG(si->osh, PCI_GPIO_OUT, sizeof(uint32));
14411 + outen = OSL_PCI_READ_CONFIG(si->osh, PCI_GPIO_OUTEN, sizeof(uint32));
14412 +
14413 + /*
14414 + * Avoid glitching the clock if GPRS is already using it.
14415 + * We can't actually read the state of the PLLPD so we infer it
14416 + * by the value of XTAL_PU which *is* readable via gpioin.
14417 + */
14418 + if (on && (in & PCI_CFG_GPIO_XTAL))
14419 + return (0);
14420 +
14421 + if (what & XTAL)
14422 + outen |= PCI_CFG_GPIO_XTAL;
14423 + if (what & PLL)
14424 + outen |= PCI_CFG_GPIO_PLL;
14425 +
14426 + if (on) {
14427 + /* turn primary xtal on */
14428 + if (what & XTAL) {
14429 + out |= PCI_CFG_GPIO_XTAL;
14430 + if (what & PLL)
14431 + out |= PCI_CFG_GPIO_PLL;
14432 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUT,
14433 + sizeof(uint32), out);
14434 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUTEN,
14435 + sizeof(uint32), outen);
14436 + OSL_DELAY(XTAL_ON_DELAY);
14437 + }
14438 +
14439 + /* turn pll on */
14440 + if (what & PLL) {
14441 + out &= ~PCI_CFG_GPIO_PLL;
14442 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUT,
14443 + sizeof(uint32), out);
14444 + OSL_DELAY(2000);
14445 + }
14446 + } else {
14447 + if (what & XTAL)
14448 + out &= ~PCI_CFG_GPIO_XTAL;
14449 + if (what & PLL)
14450 + out |= PCI_CFG_GPIO_PLL;
14451 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUT, sizeof(uint32), out);
14452 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUTEN, sizeof(uint32),
14453 + outen);
14454 + }
14455 +
14456 + default:
14457 + return (-1);
14458 + }
14459 +
14460 + return (0);
14461 +}
14462 +
14463 +/* set dynamic clk control mode (forceslow, forcefast, dynamic) */
14464 +/* returns true if we are forcing fast clock */
14465 +bool
14466 +sb_clkctl_clk(sb_t *sbh, uint mode)
14467 +{
14468 + sb_info_t *si;
14469 + uint origidx;
14470 + chipcregs_t *cc;
14471 + uint32 scc;
14472 + uint intr_val = 0;
14473 +
14474 + si = SB_INFO(sbh);
14475 +
14476 + /* chipcommon cores prior to rev6 don't support dynamic clock control */
14477 + if (si->sb.ccrev < 6)
14478 + return (FALSE);
14479 +
14480 +
14481 + /* Chips with ccrev 10 are EOL and they don't have SYCC_HR which we use below */
14482 + ASSERT(si->sb.ccrev != 10);
14483 +
14484 + INTR_OFF(si, intr_val);
14485 +
14486 + origidx = si->curidx;
14487 +
14488 + if (sb_setcore(sbh, SB_MIPS33, 0) && (sb_corerev(&si->sb) <= 7) &&
14489 + (BUSTYPE(si->sb.bustype) == SB_BUS) && (si->sb.ccrev >= 10))
14490 + goto done;
14491 +
14492 + /* PR32414WAR "Force HT clock on" all the time, no dynamic clk ctl */
14493 + if ((si->sb.chip == BCM4311_CHIP_ID) && (si->sb.chiprev <= 1))
14494 + goto done;
14495 +
14496 + cc = (chipcregs_t*) sb_setcore(sbh, SB_CC, 0);
14497 + ASSERT(cc != NULL);
14498 +
14499 + if (!(R_REG(si->osh, &cc->capabilities) & CAP_PWR_CTL))
14500 + goto done;
14501 +
14502 + switch (mode) {
14503 + case CLK_FAST: /* force fast (pll) clock */
14504 + if (si->sb.ccrev < 10) {
14505 + /* don't forget to force xtal back on before we clear SCC_DYN_XTAL.. */
14506 + sb_clkctl_xtal(&si->sb, XTAL, ON);
14507 +
14508 + SET_REG(si->osh, &cc->slow_clk_ctl, (SCC_XC | SCC_FS | SCC_IP), SCC_IP);
14509 + } else
14510 + OR_REG(si->osh, &cc->system_clk_ctl, SYCC_HR);
14511 + /* wait for the PLL */
14512 + OSL_DELAY(PLL_DELAY);
14513 + break;
14514 +
14515 + case CLK_DYNAMIC: /* enable dynamic clock control */
14516 +
14517 + if (si->sb.ccrev < 10) {
14518 + scc = R_REG(si->osh, &cc->slow_clk_ctl);
14519 + scc &= ~(SCC_FS | SCC_IP | SCC_XC);
14520 + if ((scc & SCC_SS_MASK) != SCC_SS_XTAL)
14521 + scc |= SCC_XC;
14522 + W_REG(si->osh, &cc->slow_clk_ctl, scc);
14523 +
14524 + /* for dynamic control, we have to release our xtal_pu "force on" */
14525 + if (scc & SCC_XC)
14526 + sb_clkctl_xtal(&si->sb, XTAL, OFF);
14527 + } else {
14528 + /* Instaclock */
14529 + AND_REG(si->osh, &cc->system_clk_ctl, ~SYCC_HR);
14530 + }
14531 + break;
14532 +
14533 + default:
14534 + ASSERT(0);
14535 + }
14536 +
14537 +done:
14538 + sb_setcoreidx(sbh, origidx);
14539 + INTR_RESTORE(si, intr_val);
14540 + return (mode == CLK_FAST);
14541 +}
14542 +
14543 +/* register driver interrupt disabling and restoring callback functions */
14544 +void
14545 +sb_register_intr_callback(sb_t *sbh, void *intrsoff_fn, void *intrsrestore_fn,
14546 + void *intrsenabled_fn, void *intr_arg)
14547 +{
14548 + sb_info_t *si;
14549 +
14550 + si = SB_INFO(sbh);
14551 + si->intr_arg = intr_arg;
14552 + si->intrsoff_fn = (sb_intrsoff_t)intrsoff_fn;
14553 + si->intrsrestore_fn = (sb_intrsrestore_t)intrsrestore_fn;
14554 + si->intrsenabled_fn = (sb_intrsenabled_t)intrsenabled_fn;
14555 + /* save current core id. when this function called, the current core
14556 + * must be the core which provides driver functions(il, et, wl, etc.)
14557 + */
14558 + si->dev_coreid = si->coreid[si->curidx];
14559 +}
14560 +
14561 +
14562 +int
14563 +sb_corepciid(sb_t *sbh, uint func, uint16 *pcivendor, uint16 *pcidevice,
14564 + uint8 *pciclass, uint8 *pcisubclass, uint8 *pciprogif,
14565 + uint8 *pciheader)
14566 +{
14567 + uint16 vendor = 0xffff, device = 0xffff;
14568 + uint core, unit;
14569 + uint chip, chippkg;
14570 + uint nfunc;
14571 + char varname[SB_DEVPATH_BUFSZ + 8];
14572 + uint8 class, subclass, progif;
14573 + char devpath[SB_DEVPATH_BUFSZ];
14574 + uint8 header;
14575 +
14576 + core = sb_coreid(sbh);
14577 + unit = sb_coreunit(sbh);
14578 +
14579 + chip = sb_chip(sbh);
14580 + chippkg = sb_chippkg(sbh);
14581 +
14582 + progif = 0;
14583 + header = PCI_HEADER_NORMAL;
14584 +
14585 + /* Verify whether the function exists for the core */
14586 + nfunc = (core == SB_USB20H) ? 2 : 1;
14587 + if (func >= nfunc)
14588 + return BCME_ERROR;
14589 +
14590 + /* Known vendor translations */
14591 + switch (sb_corevendor(sbh)) {
14592 + case SB_VEND_BCM:
14593 + vendor = VENDOR_BROADCOM;
14594 + break;
14595 + default:
14596 + return BCME_ERROR;
14597 + }
14598 +
14599 + /* Determine class based on known core codes */
14600 + switch (core) {
14601 + case SB_ILINE20:
14602 + class = PCI_CLASS_NET;
14603 + subclass = PCI_NET_ETHER;
14604 + device = BCM47XX_ILINE_ID;
14605 + break;
14606 + case SB_ENET:
14607 + class = PCI_CLASS_NET;
14608 + subclass = PCI_NET_ETHER;
14609 + device = BCM47XX_ENET_ID;
14610 + break;
14611 + case SB_GIGETH:
14612 + class = PCI_CLASS_NET;
14613 + subclass = PCI_NET_ETHER;
14614 + device = BCM47XX_GIGETH_ID;
14615 + break;
14616 + case SB_SDRAM:
14617 + case SB_MEMC:
14618 + class = PCI_CLASS_MEMORY;
14619 + subclass = PCI_MEMORY_RAM;
14620 + device = (uint16)core;
14621 + break;
14622 + case SB_PCI:
14623 + case SB_PCIE:
14624 + class = PCI_CLASS_BRIDGE;
14625 + subclass = PCI_BRIDGE_PCI;
14626 + device = (uint16)core;
14627 + header = PCI_HEADER_BRIDGE;
14628 + break;
14629 + case SB_MIPS:
14630 + case SB_MIPS33:
14631 + class = PCI_CLASS_CPU;
14632 + subclass = PCI_CPU_MIPS;
14633 + device = (uint16)core;
14634 + break;
14635 + case SB_CODEC:
14636 + class = PCI_CLASS_COMM;
14637 + subclass = PCI_COMM_MODEM;
14638 + device = BCM47XX_V90_ID;
14639 + break;
14640 + case SB_USB:
14641 + class = PCI_CLASS_SERIAL;
14642 + subclass = PCI_SERIAL_USB;
14643 + progif = 0x10; /* OHCI */
14644 + device = BCM47XX_USB_ID;
14645 + break;
14646 + case SB_USB11H:
14647 + class = PCI_CLASS_SERIAL;
14648 + subclass = PCI_SERIAL_USB;
14649 + progif = 0x10; /* OHCI */
14650 + device = BCM47XX_USBH_ID;
14651 + break;
14652 + case SB_USB20H:
14653 + class = PCI_CLASS_SERIAL;
14654 + subclass = PCI_SERIAL_USB;
14655 + progif = func == 0 ? 0x10 : 0x20; /* OHCI/EHCI */
14656 + device = BCM47XX_USB20H_ID;
14657 + header = 0x80; /* multifunction */
14658 + break;
14659 + case SB_USB11D:
14660 + class = PCI_CLASS_SERIAL;
14661 + subclass = PCI_SERIAL_USB;
14662 + device = BCM47XX_USBD_ID;
14663 + break;
14664 + case SB_USB20D:
14665 + class = PCI_CLASS_SERIAL;
14666 + subclass = PCI_SERIAL_USB;
14667 + device = BCM47XX_USB20D_ID;
14668 + break;
14669 + case SB_IPSEC:
14670 + class = PCI_CLASS_CRYPT;
14671 + subclass = PCI_CRYPT_NETWORK;
14672 + device = BCM47XX_IPSEC_ID;
14673 + break;
14674 + case SB_ROBO:
14675 + class = PCI_CLASS_NET;
14676 + subclass = PCI_NET_OTHER;
14677 + device = BCM47XX_ROBO_ID;
14678 + break;
14679 + case SB_EXTIF:
14680 + case SB_CC:
14681 + class = PCI_CLASS_MEMORY;
14682 + subclass = PCI_MEMORY_FLASH;
14683 + device = (uint16)core;
14684 + break;
14685 + case SB_D11:
14686 + class = PCI_CLASS_NET;
14687 + subclass = PCI_NET_OTHER;
14688 + /* Let nvram variable override core ID */
14689 + sb_devpath(sbh, devpath, sizeof(devpath));
14690 + sprintf(varname, "%sdevid", devpath);
14691 + if ((device = (uint16)getintvar(NULL, varname)))
14692 + break;
14693 + /*
14694 + * no longer support wl%did, but keep the code
14695 + * here for backward compatibility.
14696 + */
14697 + sprintf(varname, "wl%did", unit);
14698 + if ((device = (uint16)getintvar(NULL, varname)))
14699 + break;
14700 + /* Chip specific conversion */
14701 + if (chip == BCM4712_CHIP_ID) {
14702 + if (chippkg == BCM4712SMALL_PKG_ID)
14703 + device = BCM4306_D11G_ID;
14704 + else
14705 + device = BCM4306_D11DUAL_ID;
14706 + break;
14707 + }
14708 + /* ignore it */
14709 + device = 0xffff;
14710 + break;
14711 + case SB_SATAXOR:
14712 + class = PCI_CLASS_XOR;
14713 + subclass = PCI_XOR_QDMA;
14714 + device = BCM47XX_SATAXOR_ID;
14715 + break;
14716 + case SB_ATA100:
14717 + class = PCI_CLASS_DASDI;
14718 + subclass = PCI_DASDI_IDE;
14719 + device = BCM47XX_ATA100_ID;
14720 + break;
14721 +
14722 + default:
14723 + class = subclass = progif = 0xff;
14724 + device = (uint16)core;
14725 + break;
14726 + }
14727 +
14728 + *pcivendor = vendor;
14729 + *pcidevice = device;
14730 + *pciclass = class;
14731 + *pcisubclass = subclass;
14732 + *pciprogif = progif;
14733 + *pciheader = header;
14734 +
14735 + return 0;
14736 +}
14737 +
14738 +
14739 +
14740 +/* use the mdio interface to write to mdio slaves */
14741 +static int
14742 +sb_pcie_mdiowrite(sb_info_t *si, uint physmedia, uint regaddr, uint val)
14743 +{
14744 + uint mdiodata;
14745 + uint i = 0;
14746 + sbpcieregs_t *pcieregs;
14747 +
14748 + pcieregs = (sbpcieregs_t*) sb_setcoreidx(&si->sb, si->sb.buscoreidx);
14749 + ASSERT(pcieregs);
14750 +
14751 + /* enable mdio access to SERDES */
14752 + W_REG(si->osh, (&pcieregs->mdiocontrol), MDIOCTL_PREAM_EN | MDIOCTL_DIVISOR_VAL);
14753 +
14754 + mdiodata = MDIODATA_START | MDIODATA_WRITE |
14755 + (physmedia << MDIODATA_DEVADDR_SHF) |
14756 + (regaddr << MDIODATA_REGADDR_SHF) | MDIODATA_TA | val;
14757 +
14758 + W_REG(si->osh, (&pcieregs->mdiodata), mdiodata);
14759 +
14760 + PR28829_DELAY();
14761 +
14762 + /* retry till the transaction is complete */
14763 + while (i < 10) {
14764 + if (R_REG(si->osh, &(pcieregs->mdiocontrol)) & MDIOCTL_ACCESS_DONE) {
14765 + /* Disable mdio access to SERDES */
14766 + W_REG(si->osh, (&pcieregs->mdiocontrol), 0);
14767 + return 0;
14768 + }
14769 + OSL_DELAY(1000);
14770 + i++;
14771 + }
14772 +
14773 + SB_ERROR(("sb_pcie_mdiowrite: timed out\n"));
14774 + /* Disable mdio access to SERDES */
14775 + W_REG(si->osh, (&pcieregs->mdiocontrol), 0);
14776 + ASSERT(0);
14777 + return 1;
14778 +
14779 +}
14780 +
14781 +/* indirect way to read pcie config regs */
14782 +uint
14783 +sb_pcie_readreg(void *sb, void* arg1, uint offset)
14784 +{
14785 + sb_info_t *si;
14786 + sb_t *sbh;
14787 + uint retval = 0xFFFFFFFF;
14788 + sbpcieregs_t *pcieregs;
14789 + uint addrtype;
14790 +
14791 + sbh = (sb_t *)sb;
14792 + si = SB_INFO(sbh);
14793 + ASSERT(PCIE(si));
14794 +
14795 + pcieregs = (sbpcieregs_t *)sb_setcore(sbh, SB_PCIE, 0);
14796 + ASSERT(pcieregs);
14797 +
14798 + addrtype = (uint)((uintptr)arg1);
14799 + switch (addrtype) {
14800 + case PCIE_CONFIGREGS:
14801 + W_REG(si->osh, (&pcieregs->configaddr), offset);
14802 + retval = R_REG(si->osh, &(pcieregs->configdata));
14803 + break;
14804 + case PCIE_PCIEREGS:
14805 + W_REG(si->osh, &(pcieregs->pcieaddr), offset);
14806 + retval = R_REG(si->osh, &(pcieregs->pciedata));
14807 + break;
14808 + default:
14809 + ASSERT(0);
14810 + break;
14811 + }
14812 + return retval;
14813 +}
14814 +
14815 +/* indirect way to write pcie config/mdio/pciecore regs */
14816 +uint
14817 +sb_pcie_writereg(sb_t *sbh, void *arg1, uint offset, uint val)
14818 +{
14819 + sb_info_t *si;
14820 + sbpcieregs_t *pcieregs;
14821 + uint addrtype;
14822 +
14823 + si = SB_INFO(sbh);
14824 + ASSERT(PCIE(si));
14825 +
14826 + pcieregs = (sbpcieregs_t *)sb_setcore(sbh, SB_PCIE, 0);
14827 + ASSERT(pcieregs);
14828 +
14829 + addrtype = (uint)((uintptr)arg1);
14830 +
14831 + switch (addrtype) {
14832 + case PCIE_CONFIGREGS:
14833 + W_REG(si->osh, (&pcieregs->configaddr), offset);
14834 + W_REG(si->osh, (&pcieregs->configdata), val);
14835 + break;
14836 + case PCIE_PCIEREGS:
14837 + W_REG(si->osh, (&pcieregs->pcieaddr), offset);
14838 + W_REG(si->osh, (&pcieregs->pciedata), val);
14839 + break;
14840 + default:
14841 + ASSERT(0);
14842 + break;
14843 + }
14844 + return 0;
14845 +}
14846 +
14847 +/* Build device path. Support SB, PCI, and JTAG for now. */
14848 +int
14849 +sb_devpath(sb_t *sbh, char *path, int size)
14850 +{
14851 + ASSERT(path);
14852 + ASSERT(size >= SB_DEVPATH_BUFSZ);
14853 +
14854 + switch (BUSTYPE((SB_INFO(sbh))->sb.bustype)) {
14855 + case SB_BUS:
14856 + case JTAG_BUS:
14857 + sprintf(path, "sb/%u/", sb_coreidx(sbh));
14858 + break;
14859 + case PCI_BUS:
14860 + ASSERT((SB_INFO(sbh))->osh);
14861 + sprintf(path, "pci/%u/%u/", OSL_PCI_BUS((SB_INFO(sbh))->osh),
14862 + OSL_PCI_SLOT((SB_INFO(sbh))->osh));
14863 + break;
14864 + case PCMCIA_BUS:
14865 + SB_ERROR(("sb_devpath: OSL_PCMCIA_BUS() not implemented, bus 1 assumed\n"));
14866 + SB_ERROR(("sb_devpath: OSL_PCMCIA_SLOT() not implemented, slot 1 assumed\n"));
14867 + sprintf(path, "pc/%u/%u/", 1, 1);
14868 + break;
14869 + case SDIO_BUS:
14870 + SB_ERROR(("sb_devpath: device 0 assumed\n"));
14871 + sprintf(path, "sd/%u/", sb_coreidx(sbh));
14872 + break;
14873 + default:
14874 + ASSERT(0);
14875 + break;
14876 + }
14877 +
14878 + return 0;
14879 +}
14880 +
14881 +/*
14882 + * Fixup SROMless PCI device's configuration.
14883 + * The current core may be changed upon return.
14884 + */
14885 +static int
14886 +sb_pci_fixcfg(sb_info_t *si)
14887 +{
14888 + uint origidx, pciidx;
14889 + sbpciregs_t *pciregs;
14890 + sbpcieregs_t *pcieregs;
14891 + uint16 val16, *reg16;
14892 + char name[SB_DEVPATH_BUFSZ+16], *value;
14893 + char devpath[SB_DEVPATH_BUFSZ];
14894 +
14895 + ASSERT(BUSTYPE(si->sb.bustype) == PCI_BUS);
14896 +
14897 + /* Fixup PI in SROM shadow area to enable the correct PCI core access */
14898 + /* save the current index */
14899 + origidx = sb_coreidx(&si->sb);
14900 +
14901 + /* check 'pi' is correct and fix it if not */
14902 + if (si->sb.buscoretype == SB_PCIE) {
14903 + pcieregs = (sbpcieregs_t *)sb_setcore(&si->sb, SB_PCIE, 0);
14904 + ASSERT(pcieregs);
14905 + reg16 = &pcieregs->sprom[SRSH_PI_OFFSET];
14906 + } else if (si->sb.buscoretype == SB_PCI) {
14907 + pciregs = (sbpciregs_t *)sb_setcore(&si->sb, SB_PCI, 0);
14908 + ASSERT(pciregs);
14909 + reg16 = &pciregs->sprom[SRSH_PI_OFFSET];
14910 + } else {
14911 + ASSERT(0);
14912 + return -1;
14913 + }
14914 + pciidx = sb_coreidx(&si->sb);
14915 + val16 = R_REG(si->osh, reg16);
14916 + if (((val16 & SRSH_PI_MASK) >> SRSH_PI_SHIFT) != (uint16)pciidx) {
14917 + val16 = (uint16)(pciidx << SRSH_PI_SHIFT) | (val16 & ~SRSH_PI_MASK);
14918 + W_REG(si->osh, reg16, val16);
14919 + }
14920 +
14921 + /* restore the original index */
14922 + sb_setcoreidx(&si->sb, origidx);
14923 +
14924 + /*
14925 + * Fixup bar0window in PCI config space to make the core indicated
14926 + * by the nvram variable the current core.
14927 + * !Do it last, it may change the current core!
14928 + */
14929 + if (sb_devpath(&si->sb, devpath, sizeof(devpath)))
14930 + return -1;
14931 + sprintf(name, "%sb0w", devpath);
14932 + if ((value = getvar(NULL, name))) {
14933 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_BAR0_WIN, sizeof(uint32),
14934 + bcm_strtoul(value, NULL, 16));
14935 + /* update curidx since the current core is changed */
14936 + si->curidx = _sb_coreidx(si);
14937 + if (si->curidx == BADIDX) {
14938 + SB_ERROR(("sb_pci_fixcfg: bad core index\n"));
14939 + return -1;
14940 + }
14941 + }
14942 +
14943 + return 0;
14944 +}
14945 +
14946 +static uint
14947 +sb_chipc_capability(sb_t *sbh)
14948 +{
14949 + sb_info_t *si;
14950 +
14951 + si = SB_INFO(sbh);
14952 +
14953 + /* Make sure that there is ChipCommon core present */
14954 + if (si->coreid[SB_CC_IDX] == SB_CC)
14955 + return (sb_corereg(si, SB_CC_IDX, OFFSETOF(chipcregs_t, capabilities),
14956 + 0, 0));
14957 + return 0;
14958 +}
14959 +
14960 +/* Return ADDR64 capability of the backplane */
14961 +bool
14962 +sb_backplane64(sb_t *sbh)
14963 +{
14964 + return ((sb_chipc_capability(sbh) & CAP_BKPLN64) != 0);
14965 +}
14966 +
14967 +void
14968 +sb_btcgpiowar(sb_t *sbh)
14969 +{
14970 + sb_info_t *si;
14971 + uint origidx;
14972 + uint intr_val = 0;
14973 + chipcregs_t *cc;
14974 + si = SB_INFO(sbh);
14975 +
14976 + /* Make sure that there is ChipCommon core present &&
14977 + * UART_TX is strapped to 1
14978 + */
14979 + if (!(sb_chipc_capability(sbh) & CAP_UARTGPIO))
14980 + return;
14981 +
14982 + /* sb_corereg cannot be used as we have to guarantee 8-bit read/writes */
14983 + INTR_OFF(si, intr_val);
14984 +
14985 + origidx = sb_coreidx(sbh);
14986 +
14987 + cc = (chipcregs_t *)sb_setcore(sbh, SB_CC, 0);
14988 + if (cc == NULL)
14989 + goto end;
14990 +
14991 + W_REG(si->osh, &cc->uart0mcr, R_REG(si->osh, &cc->uart0mcr) | 0x04);
14992 +
14993 +end:
14994 + /* restore the original index */
14995 + sb_setcoreidx(sbh, origidx);
14996 +
14997 + INTR_RESTORE(si, intr_val);
14998 +}
14999 +
15000 +/* check if the device is removed */
15001 +bool
15002 +sb_deviceremoved(sb_t *sbh)
15003 +{
15004 + uint32 w;
15005 + sb_info_t *si;
15006 +
15007 + si = SB_INFO(sbh);
15008 +
15009 + switch (BUSTYPE(si->sb.bustype)) {
15010 + case PCI_BUS:
15011 + ASSERT(si->osh);
15012 + w = OSL_PCI_READ_CONFIG(si->osh, PCI_CFG_VID, sizeof(uint32));
15013 + if ((w & 0xFFFF) != VENDOR_BROADCOM)
15014 + return TRUE;
15015 + else
15016 + return FALSE;
15017 + default:
15018 + return FALSE;
15019 + }
15020 + return FALSE;
15021 +}
15022 +
15023 +/* Return the RAM size of the SOCRAM core */
15024 +uint32
15025 +sb_socram_size(sb_t *sbh)
15026 +{
15027 + sb_info_t *si;
15028 + uint origidx;
15029 + uint intr_val = 0;
15030 +
15031 + sbsocramregs_t *regs;
15032 + bool wasup;
15033 + uint corerev;
15034 + uint32 coreinfo;
15035 + uint memsize = 0;
15036 +
15037 + si = SB_INFO(sbh);
15038 + ASSERT(si);
15039 +
15040 + /* Block ints and save current core */
15041 + INTR_OFF(si, intr_val);
15042 + origidx = sb_coreidx(sbh);
15043 +
15044 + /* Switch to SOCRAM core */
15045 + if (!(regs = sb_setcore(sbh, SB_SOCRAM, 0)))
15046 + goto done;
15047 +
15048 + /* Get info for determining size */
15049 + if (!(wasup = sb_iscoreup(sbh)))
15050 + sb_core_reset(sbh, 0, 0);
15051 + corerev = sb_corerev(sbh);
15052 + coreinfo = R_REG(si->osh, &regs->coreinfo);
15053 +
15054 + /* Calculate size from coreinfo based on rev */
15055 + switch (corerev) {
15056 + case 0:
15057 + memsize = 1 << (16 + (coreinfo & SRCI_MS0_MASK));
15058 + break;
15059 + default: /* rev >= 1 */
15060 + memsize = 1 << (SR_BSZ_BASE + (coreinfo & SRCI_SRBSZ_MASK));
15061 + memsize *= (coreinfo & SRCI_SRNB_MASK) >> SRCI_SRNB_SHIFT;
15062 + break;
15063 + }
15064 +
15065 + /* Return to previous state and core */
15066 + if (!wasup)
15067 + sb_core_disable(sbh, 0);
15068 + sb_setcoreidx(sbh, origidx);
15069 +
15070 +done:
15071 + INTR_RESTORE(si, intr_val);
15072 + return memsize;
15073 +}
15074 +
15075 +
15076 diff -urN linux.old/arch/mips/bcm947xx/setup.c linux.dev/arch/mips/bcm947xx/setup.c
15077 --- linux.old/arch/mips/bcm947xx/setup.c 1970-01-01 01:00:00.000000000 +0100
15078 +++ linux.dev/arch/mips/bcm947xx/setup.c 2006-10-02 21:19:59.000000000 +0200
15079 @@ -0,0 +1,241 @@
15080 +/*
15081 + * Generic setup routines for Broadcom MIPS boards
15082 + *
15083 + * Copyright (C) 2005 Felix Fietkau <nbd@openwrt.org>
15084 + *
15085 + * This program is free software; you can redistribute it and/or modify it
15086 + * under the terms of the GNU General Public License as published by the
15087 + * Free Software Foundation; either version 2 of the License, or (at your
15088 + * option) any later version.
15089 + *
15090 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
15091 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
15092 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
15093 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
15094 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
15095 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
15096 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
15097 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
15098 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
15099 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
15100 + *
15101 + * You should have received a copy of the GNU General Public License along
15102 + * with this program; if not, write to the Free Software Foundation, Inc.,
15103 + * 675 Mass Ave, Cambridge, MA 02139, USA.
15104 + *
15105 + *
15106 + * Copyright 2005, Broadcom Corporation
15107 + * All Rights Reserved.
15108 + *
15109 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
15110 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
15111 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
15112 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
15113 + *
15114 + */
15115 +
15116 +#include <linux/config.h>
15117 +#include <linux/init.h>
15118 +#include <linux/kernel.h>
15119 +#include <linux/module.h>
15120 +#include <linux/serialP.h>
15121 +#include <linux/ide.h>
15122 +#include <asm/bootinfo.h>
15123 +#include <asm/cpu.h>
15124 +#include <asm/time.h>
15125 +#include <asm/reboot.h>
15126 +
15127 +#include <typedefs.h>
15128 +#include <osl.h>
15129 +#include <sbutils.h>
15130 +#include <bcmutils.h>
15131 +#include <bcmnvram.h>
15132 +#include <sbhndmips.h>
15133 +#include <hndmips.h>
15134 +#include <trxhdr.h>
15135 +
15136 +/* Virtual IRQ base, after last hw IRQ */
15137 +#define SBMIPS_VIRTIRQ_BASE 6
15138 +
15139 +/* # IRQs, hw and sw IRQs */
15140 +#define SBMIPS_NUMIRQS 8
15141 +
15142 +/* Global SB handle */
15143 +sb_t *bcm947xx_sbh = NULL;
15144 +spinlock_t bcm947xx_sbh_lock = SPIN_LOCK_UNLOCKED;
15145 +
15146 +/* Convenience */
15147 +#define sbh bcm947xx_sbh
15148 +#define sbh_lock bcm947xx_sbh_lock
15149 +
15150 +extern void bcm947xx_time_init(void);
15151 +extern void bcm947xx_timer_setup(struct irqaction *irq);
15152 +
15153 +#ifdef CONFIG_REMOTE_DEBUG
15154 +extern void set_debug_traps(void);
15155 +extern void rs_kgdb_hook(struct serial_state *);
15156 +extern void breakpoint(void);
15157 +#endif
15158 +
15159 +#if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)
15160 +extern struct ide_ops std_ide_ops;
15161 +#endif
15162 +
15163 +/* Kernel command line */
15164 +char arcs_cmdline[CL_SIZE] __initdata = CONFIG_CMDLINE;
15165 +extern void sb_serial_init(sb_t *sbh, void (*add)(void *regs, uint irq, uint baud_base, uint reg_shift));
15166 +
15167 +void
15168 +bcm947xx_machine_restart(char *command)
15169 +{
15170 + printk("Please stand by while rebooting the system...\n");
15171 +
15172 + /* Set the watchdog timer to reset immediately */
15173 + __cli();
15174 + sb_watchdog(sbh, 1);
15175 + while (1);
15176 +}
15177 +
15178 +void
15179 +bcm947xx_machine_halt(void)
15180 +{
15181 + printk("System halted\n");
15182 +
15183 + /* Disable interrupts and watchdog and spin forever */
15184 + __cli();
15185 + sb_watchdog(sbh, 0);
15186 + while (1);
15187 +}
15188 +
15189 +#ifdef CONFIG_SERIAL
15190 +
15191 +static int ser_line = 0;
15192 +
15193 +typedef struct {
15194 + void *regs;
15195 + uint irq;
15196 + uint baud_base;
15197 + uint reg_shift;
15198 +} serial_port;
15199 +
15200 +static serial_port ports[4];
15201 +static int num_ports = 0;
15202 +
15203 +static void
15204 +serial_add(void *regs, uint irq, uint baud_base, uint reg_shift)
15205 +{
15206 + ports[num_ports].regs = regs;
15207 + ports[num_ports].irq = irq;
15208 + ports[num_ports].baud_base = baud_base;
15209 + ports[num_ports].reg_shift = reg_shift;
15210 + num_ports++;
15211 +}
15212 +
15213 +static void
15214 +do_serial_add(serial_port *port)
15215 +{
15216 + void *regs;
15217 + uint irq;
15218 + uint baud_base;
15219 + uint reg_shift;
15220 + struct serial_struct s;
15221 +
15222 + regs = port->regs;
15223 + irq = port->irq;
15224 + baud_base = port->baud_base;
15225 + reg_shift = port->reg_shift;
15226 +
15227 + memset(&s, 0, sizeof(s));
15228 +
15229 + s.line = ser_line++;
15230 + s.iomem_base = regs;
15231 + s.irq = irq + 2;
15232 + s.baud_base = baud_base / 16;
15233 + s.flags = ASYNC_BOOT_AUTOCONF;
15234 + s.io_type = SERIAL_IO_MEM;
15235 + s.iomem_reg_shift = reg_shift;
15236 +
15237 + if (early_serial_setup(&s) != 0) {
15238 + printk(KERN_ERR "Serial setup failed!\n");
15239 + }
15240 +}
15241 +
15242 +#endif /* CONFIG_SERIAL */
15243 +
15244 +void __init
15245 +brcm_setup(void)
15246 +{
15247 + char *s;
15248 + int i;
15249 + char *value;
15250 +
15251 + /* Get global SB handle */
15252 + sbh = sb_kattach();
15253 +
15254 + /* Initialize clocks and interrupts */
15255 + sb_mips_init(sbh, SBMIPS_VIRTIRQ_BASE);
15256 +
15257 + if (BCM330X(current_cpu_data.processor_id) &&
15258 + (read_c0_diag() & BRCM_PFC_AVAIL)) {
15259 + /*
15260 + * Now that the sbh is inited set the proper PFC value
15261 + */
15262 + printk("Setting the PFC to its default value\n");
15263 + enable_pfc(PFC_AUTO);
15264 + }
15265 +
15266 +
15267 +#ifdef CONFIG_SERIAL
15268 + sb_serial_init(sbh, serial_add);
15269 +
15270 + /* reverse serial ports if nvram variable starts with console=ttyS1 */
15271 + /* Initialize UARTs */
15272 + s = nvram_get("kernel_args");
15273 + if (!s) s = "";
15274 + if (!strncmp(s, "console=ttyS1", 13)) {
15275 + for (i = num_ports; i; i--)
15276 + do_serial_add(&ports[i - 1]);
15277 + } else {
15278 + for (i = 0; i < num_ports; i++)
15279 + do_serial_add(&ports[i]);
15280 + }
15281 +#endif
15282 +
15283 +#if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)
15284 + ide_ops = &std_ide_ops;
15285 +#endif
15286 +
15287 + /* Override default command line arguments */
15288 + value = nvram_get("kernel_cmdline");
15289 + if (value && strlen(value) && strncmp(value, "empty", 5))
15290 + strncpy(arcs_cmdline, value, sizeof(arcs_cmdline));
15291 +
15292 +
15293 + /* Generic setup */
15294 + _machine_restart = bcm947xx_machine_restart;
15295 + _machine_halt = bcm947xx_machine_halt;
15296 + _machine_power_off = bcm947xx_machine_halt;
15297 +
15298 + board_time_init = bcm947xx_time_init;
15299 + board_timer_setup = bcm947xx_timer_setup;
15300 +}
15301 +
15302 +const char *
15303 +get_system_type(void)
15304 +{
15305 + static char s[32];
15306 +
15307 + if (bcm947xx_sbh) {
15308 + sprintf(s, "Broadcom BCM%X chip rev %d", sb_chip(bcm947xx_sbh),
15309 + sb_chiprev(bcm947xx_sbh));
15310 + return s;
15311 + }
15312 + else
15313 + return "Broadcom BCM947XX";
15314 +}
15315 +
15316 +void __init
15317 +bus_error_init(void)
15318 +{
15319 +}
15320 +
15321 diff -urN linux.old/arch/mips/bcm947xx/sflash.c linux.dev/arch/mips/bcm947xx/sflash.c
15322 --- linux.old/arch/mips/bcm947xx/sflash.c 1970-01-01 01:00:00.000000000 +0100
15323 +++ linux.dev/arch/mips/bcm947xx/sflash.c 2006-10-02 21:19:59.000000000 +0200
15324 @@ -0,0 +1,422 @@
15325 +/*
15326 + * Broadcom SiliconBackplane chipcommon serial flash interface
15327 + *
15328 + * Copyright 2006, Broadcom Corporation
15329 + * All Rights Reserved.
15330 + *
15331 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
15332 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
15333 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
15334 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
15335 + *
15336 + * $Id: sflash.c,v 1.1.1.13 2006/02/27 03:43:16 honor Exp $
15337 + */
15338 +
15339 +#include <osl.h>
15340 +#include <typedefs.h>
15341 +#include <sbconfig.h>
15342 +#include <sbchipc.h>
15343 +#include <mipsinc.h>
15344 +#include <bcmutils.h>
15345 +#include <bcmdevs.h>
15346 +#include <sflash.h>
15347 +
15348 +/* Private global state */
15349 +static struct sflash sflash;
15350 +
15351 +/* Issue a serial flash command */
15352 +static INLINE void
15353 +sflash_cmd(chipcregs_t *cc, uint opcode)
15354 +{
15355 + W_REG(NULL, &cc->flashcontrol, SFLASH_START | opcode);
15356 + while (R_REG(NULL, &cc->flashcontrol) & SFLASH_BUSY);
15357 +}
15358 +
15359 +/* Initialize serial flash access */
15360 +struct sflash *
15361 +sflash_init(chipcregs_t *cc)
15362 +{
15363 + uint32 id, id2;
15364 +
15365 + bzero(&sflash, sizeof(sflash));
15366 +
15367 + sflash.type = R_REG(NULL, &cc->capabilities) & CAP_FLASH_MASK;
15368 +
15369 + switch (sflash.type) {
15370 + case SFLASH_ST:
15371 + /* Probe for ST chips */
15372 + sflash_cmd(cc, SFLASH_ST_DP);
15373 + sflash_cmd(cc, SFLASH_ST_RES);
15374 + id = R_REG(NULL, &cc->flashdata);
15375 + switch (id) {
15376 + case 0x11:
15377 + /* ST M25P20 2 Mbit Serial Flash */
15378 + sflash.blocksize = 64 * 1024;
15379 + sflash.numblocks = 4;
15380 + break;
15381 + case 0x12:
15382 + /* ST M25P40 4 Mbit Serial Flash */
15383 + sflash.blocksize = 64 * 1024;
15384 + sflash.numblocks = 8;
15385 + break;
15386 + case 0x13:
15387 + /* ST M25P80 8 Mbit Serial Flash */
15388 + sflash.blocksize = 64 * 1024;
15389 + sflash.numblocks = 16;
15390 + break;
15391 + case 0x14:
15392 + /* ST M25P16 16 Mbit Serial Flash */
15393 + sflash.blocksize = 64 * 1024;
15394 + sflash.numblocks = 32;
15395 + break;
15396 + case 0x15:
15397 + /* ST M25P32 32 Mbit Serial Flash */
15398 + sflash.blocksize = 64 * 1024;
15399 + sflash.numblocks = 64;
15400 + break;
15401 + case 0x16:
15402 + /* ST M25P64 64 Mbit Serial Flash */
15403 + sflash.blocksize = 64 * 1024;
15404 + sflash.numblocks = 128;
15405 + break;
15406 + case 0xbf:
15407 + W_REG(NULL, &cc->flashaddress, 1);
15408 + sflash_cmd(cc, SFLASH_ST_RES);
15409 + id2 = R_REG(NULL, &cc->flashdata);
15410 + if (id2 == 0x44) {
15411 + /* SST M25VF80 4 Mbit Serial Flash */
15412 + sflash.blocksize = 64 * 1024;
15413 + sflash.numblocks = 8;
15414 + }
15415 + break;
15416 + }
15417 + break;
15418 +
15419 + case SFLASH_AT:
15420 + /* Probe for Atmel chips */
15421 + sflash_cmd(cc, SFLASH_AT_STATUS);
15422 + id = R_REG(NULL, &cc->flashdata) & 0x3c;
15423 + switch (id) {
15424 + case 0xc:
15425 + /* Atmel AT45DB011 1Mbit Serial Flash */
15426 + sflash.blocksize = 256;
15427 + sflash.numblocks = 512;
15428 + break;
15429 + case 0x14:
15430 + /* Atmel AT45DB021 2Mbit Serial Flash */
15431 + sflash.blocksize = 256;
15432 + sflash.numblocks = 1024;
15433 + break;
15434 + case 0x1c:
15435 + /* Atmel AT45DB041 4Mbit Serial Flash */
15436 + sflash.blocksize = 256;
15437 + sflash.numblocks = 2048;
15438 + break;
15439 + case 0x24:
15440 + /* Atmel AT45DB081 8Mbit Serial Flash */
15441 + sflash.blocksize = 256;
15442 + sflash.numblocks = 4096;
15443 + break;
15444 + case 0x2c:
15445 + /* Atmel AT45DB161 16Mbit Serial Flash */
15446 + sflash.blocksize = 512;
15447 + sflash.numblocks = 4096;
15448 + break;
15449 + case 0x34:
15450 + /* Atmel AT45DB321 32Mbit Serial Flash */
15451 + sflash.blocksize = 512;
15452 + sflash.numblocks = 8192;
15453 + break;
15454 + case 0x3c:
15455 + /* Atmel AT45DB642 64Mbit Serial Flash */
15456 + sflash.blocksize = 1024;
15457 + sflash.numblocks = 8192;
15458 + break;
15459 + }
15460 + break;
15461 + }
15462 +
15463 + sflash.size = sflash.blocksize * sflash.numblocks;
15464 + return sflash.size ? &sflash : NULL;
15465 +}
15466 +
15467 +/* Read len bytes starting at offset into buf. Returns number of bytes read. */
15468 +int
15469 +sflash_read(chipcregs_t *cc, uint offset, uint len, uchar *buf)
15470 +{
15471 + int cnt;
15472 + uint32 *from, *to;
15473 +
15474 + if (!len)
15475 + return 0;
15476 +
15477 + if ((offset + len) > sflash.size)
15478 + return -22;
15479 +
15480 + if ((len >= 4) && (offset & 3))
15481 + cnt = 4 - (offset & 3);
15482 + else if ((len >= 4) && ((uint32)buf & 3))
15483 + cnt = 4 - ((uint32)buf & 3);
15484 + else
15485 + cnt = len;
15486 +
15487 + from = (uint32 *)KSEG1ADDR(SB_FLASH2 + offset);
15488 + to = (uint32 *)buf;
15489 +
15490 + if (cnt < 4) {
15491 + bcopy(from, to, cnt);
15492 + return cnt;
15493 + }
15494 +
15495 + while (cnt >= 4) {
15496 + *to++ = *from++;
15497 + cnt -= 4;
15498 + }
15499 +
15500 + return (len - cnt);
15501 +}
15502 +
15503 +/* Poll for command completion. Returns zero when complete. */
15504 +int
15505 +sflash_poll(chipcregs_t *cc, uint offset)
15506 +{
15507 + if (offset >= sflash.size)
15508 + return -22;
15509 +
15510 + switch (sflash.type) {
15511 + case SFLASH_ST:
15512 + /* Check for ST Write In Progress bit */
15513 + sflash_cmd(cc, SFLASH_ST_RDSR);
15514 + return R_REG(NULL, &cc->flashdata) & SFLASH_ST_WIP;
15515 + case SFLASH_AT:
15516 + /* Check for Atmel Ready bit */
15517 + sflash_cmd(cc, SFLASH_AT_STATUS);
15518 + return !(R_REG(NULL, &cc->flashdata) & SFLASH_AT_READY);
15519 + }
15520 +
15521 + return 0;
15522 +}
15523 +
15524 +/* Write len bytes starting at offset into buf. Returns number of bytes
15525 + * written. Caller should poll for completion.
15526 + */
15527 +int
15528 +sflash_write(chipcregs_t *cc, uint offset, uint len, const uchar *buf)
15529 +{
15530 + struct sflash *sfl;
15531 + int ret = 0;
15532 + bool is4712b0;
15533 + uint32 page, byte, mask;
15534 +
15535 + if (!len)
15536 + return 0;
15537 +
15538 + if ((offset + len) > sflash.size)
15539 + return -22;
15540 +
15541 + sfl = &sflash;
15542 + switch (sfl->type) {
15543 + case SFLASH_ST:
15544 + mask = R_REG(NULL, &cc->chipid);
15545 + is4712b0 = (((mask & CID_ID_MASK) == BCM4712_CHIP_ID) &&
15546 + ((mask & CID_REV_MASK) == (3 << CID_REV_SHIFT)));
15547 + /* Enable writes */
15548 + sflash_cmd(cc, SFLASH_ST_WREN);
15549 + if (is4712b0) {
15550 + mask = 1 << 14;
15551 + W_REG(NULL, &cc->flashaddress, offset);
15552 + W_REG(NULL, &cc->flashdata, *buf++);
15553 + /* Set chip select */
15554 + OR_REG(NULL, &cc->gpioout, mask);
15555 + /* Issue a page program with the first byte */
15556 + sflash_cmd(cc, SFLASH_ST_PP);
15557 + ret = 1;
15558 + offset++;
15559 + len--;
15560 + while (len > 0) {
15561 + if ((offset & 255) == 0) {
15562 + /* Page boundary, drop cs and return */
15563 + AND_REG(NULL, &cc->gpioout, ~mask);
15564 + if (!sflash_poll(cc, offset)) {
15565 + /* Flash rejected command */
15566 + return -11;
15567 + }
15568 + return ret;
15569 + } else {
15570 + /* Write single byte */
15571 + sflash_cmd(cc, *buf++);
15572 + }
15573 + ret++;
15574 + offset++;
15575 + len--;
15576 + }
15577 + /* All done, drop cs if needed */
15578 + if ((offset & 255) != 1) {
15579 + /* Drop cs */
15580 + AND_REG(NULL, &cc->gpioout, ~mask);
15581 + if (!sflash_poll(cc, offset)) {
15582 + /* Flash rejected command */
15583 + return -12;
15584 + }
15585 + }
15586 + } else {
15587 + ret = 1;
15588 + W_REG(NULL, &cc->flashaddress, offset);
15589 + W_REG(NULL, &cc->flashdata, *buf);
15590 + /* Page program */
15591 + sflash_cmd(cc, SFLASH_ST_PP);
15592 + }
15593 + break;
15594 + case SFLASH_AT:
15595 + mask = sfl->blocksize - 1;
15596 + page = (offset & ~mask) << 1;
15597 + byte = offset & mask;
15598 + /* Read main memory page into buffer 1 */
15599 + if (byte || (len < sfl->blocksize)) {
15600 + W_REG(NULL, &cc->flashaddress, page);
15601 + sflash_cmd(cc, SFLASH_AT_BUF1_LOAD);
15602 + /* 250 us for AT45DB321B */
15603 + SPINWAIT(sflash_poll(cc, offset), 1000);
15604 + ASSERT(!sflash_poll(cc, offset));
15605 + }
15606 + /* Write into buffer 1 */
15607 + for (ret = 0; (ret < (int)len) && (byte < sfl->blocksize); ret++) {
15608 + W_REG(NULL, &cc->flashaddress, byte++);
15609 + W_REG(NULL, &cc->flashdata, *buf++);
15610 + sflash_cmd(cc, SFLASH_AT_BUF1_WRITE);
15611 + }
15612 + /* Write buffer 1 into main memory page */
15613 + W_REG(NULL, &cc->flashaddress, page);
15614 + sflash_cmd(cc, SFLASH_AT_BUF1_PROGRAM);
15615 + break;
15616 + }
15617 +
15618 + return ret;
15619 +}
15620 +
15621 +/* Erase a region. Returns number of bytes scheduled for erasure.
15622 + * Caller should poll for completion.
15623 + */
15624 +int
15625 +sflash_erase(chipcregs_t *cc, uint offset)
15626 +{
15627 + struct sflash *sfl;
15628 +
15629 + if (offset >= sflash.size)
15630 + return -22;
15631 +
15632 + sfl = &sflash;
15633 + switch (sfl->type) {
15634 + case SFLASH_ST:
15635 + sflash_cmd(cc, SFLASH_ST_WREN);
15636 + W_REG(NULL, &cc->flashaddress, offset);
15637 + sflash_cmd(cc, SFLASH_ST_SE);
15638 + return sfl->blocksize;
15639 + case SFLASH_AT:
15640 + W_REG(NULL, &cc->flashaddress, offset << 1);
15641 + sflash_cmd(cc, SFLASH_AT_PAGE_ERASE);
15642 + return sfl->blocksize;
15643 + }
15644 +
15645 + return 0;
15646 +}
15647 +
15648 +/*
15649 + * writes the appropriate range of flash, a NULL buf simply erases
15650 + * the region of flash
15651 + */
15652 +int
15653 +sflash_commit(chipcregs_t *cc, uint offset, uint len, const uchar *buf)
15654 +{
15655 + struct sflash *sfl;
15656 + uchar *block = NULL, *cur_ptr, *blk_ptr;
15657 + uint blocksize = 0, mask, cur_offset, cur_length, cur_retlen, remainder;
15658 + uint blk_offset, blk_len, copied;
15659 + int bytes, ret = 0;
15660 +
15661 + /* Check address range */
15662 + if (len <= 0)
15663 + return 0;
15664 +
15665 + sfl = &sflash;
15666 + if ((offset + len) > sfl->size)
15667 + return -1;
15668 +
15669 + blocksize = sfl->blocksize;
15670 + mask = blocksize - 1;
15671 +
15672 + /* Allocate a block of mem */
15673 + if (!(block = MALLOC(NULL, blocksize)))
15674 + return -1;
15675 +
15676 + while (len) {
15677 + /* Align offset */
15678 + cur_offset = offset & ~mask;
15679 + cur_length = blocksize;
15680 + cur_ptr = block;
15681 +
15682 + remainder = blocksize - (offset & mask);
15683 + if (len < remainder)
15684 + cur_retlen = len;
15685 + else
15686 + cur_retlen = remainder;
15687 +
15688 + /* buf == NULL means erase only */
15689 + if (buf) {
15690 + /* Copy existing data into holding block if necessary */
15691 + if ((offset & mask) || (len < blocksize)) {
15692 + blk_offset = cur_offset;
15693 + blk_len = cur_length;
15694 + blk_ptr = cur_ptr;
15695 +
15696 + /* Copy entire block */
15697 + while (blk_len) {
15698 + copied = sflash_read(cc, blk_offset, blk_len, blk_ptr);
15699 + blk_offset += copied;
15700 + blk_len -= copied;
15701 + blk_ptr += copied;
15702 + }
15703 + }
15704 +
15705 + /* Copy input data into holding block */
15706 + memcpy(cur_ptr + (offset & mask), buf, cur_retlen);
15707 + }
15708 +
15709 + /* Erase block */
15710 + if ((ret = sflash_erase(cc, (uint) cur_offset)) < 0)
15711 + goto done;
15712 + while (sflash_poll(cc, (uint) cur_offset));
15713 +
15714 + /* buf == NULL means erase only */
15715 + if (!buf) {
15716 + offset += cur_retlen;
15717 + len -= cur_retlen;
15718 + continue;
15719 + }
15720 +
15721 + /* Write holding block */
15722 + while (cur_length > 0) {
15723 + if ((bytes = sflash_write(cc,
15724 + (uint) cur_offset,
15725 + (uint) cur_length,
15726 + (uchar *) cur_ptr)) < 0) {
15727 + ret = bytes;
15728 + goto done;
15729 + }
15730 + while (sflash_poll(cc, (uint) cur_offset));
15731 + cur_offset += bytes;
15732 + cur_length -= bytes;
15733 + cur_ptr += bytes;
15734 + }
15735 +
15736 + offset += cur_retlen;
15737 + len -= cur_retlen;
15738 + buf += cur_retlen;
15739 + }
15740 +
15741 + ret = len;
15742 +done:
15743 + if (block)
15744 + MFREE(NULL, block, blocksize);
15745 + return ret;
15746 +}
15747 diff -urN linux.old/arch/mips/bcm947xx/time.c linux.dev/arch/mips/bcm947xx/time.c
15748 --- linux.old/arch/mips/bcm947xx/time.c 1970-01-01 01:00:00.000000000 +0100
15749 +++ linux.dev/arch/mips/bcm947xx/time.c 2006-10-02 21:19:59.000000000 +0200
15750 @@ -0,0 +1,104 @@
15751 +/*
15752 + * Copyright 2006, Broadcom Corporation
15753 + * All Rights Reserved.
15754 + *
15755 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
15756 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
15757 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
15758 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
15759 + *
15760 + * $Id: time.c,v 1.1.1.10 2006/02/27 03:42:55 honor Exp $
15761 + */
15762 +#include <linux/config.h>
15763 +#include <linux/init.h>
15764 +#include <linux/kernel.h>
15765 +#include <linux/sched.h>
15766 +#include <linux/serial_reg.h>
15767 +#include <linux/interrupt.h>
15768 +#include <asm/addrspace.h>
15769 +#include <asm/io.h>
15770 +#include <asm/time.h>
15771 +
15772 +#include <typedefs.h>
15773 +#include <osl.h>
15774 +#include <bcmnvram.h>
15775 +#include <sbconfig.h>
15776 +#include <sbextif.h>
15777 +#include <sbutils.h>
15778 +#include <hndmips.h>
15779 +#include <mipsinc.h>
15780 +#include <hndcpu.h>
15781 +
15782 +/* Global SB handle */
15783 +extern void *bcm947xx_sbh;
15784 +extern spinlock_t bcm947xx_sbh_lock;
15785 +
15786 +/* Convenience */
15787 +#define sbh bcm947xx_sbh
15788 +#define sbh_lock bcm947xx_sbh_lock
15789 +
15790 +extern int panic_timeout;
15791 +static int watchdog = 0;
15792 +static u8 *mcr = NULL;
15793 +
15794 +void __init
15795 +bcm947xx_time_init(void)
15796 +{
15797 + unsigned int hz;
15798 + extifregs_t *eir;
15799 +
15800 + /*
15801 + * Use deterministic values for initial counter interrupt
15802 + * so that calibrate delay avoids encountering a counter wrap.
15803 + */
15804 + write_c0_count(0);
15805 + write_c0_compare(0xffff);
15806 +
15807 + if (!(hz = sb_cpu_clock(sbh)))
15808 + hz = 100000000;
15809 +
15810 + printk("CPU: BCM%04x rev %d at %d MHz\n", sb_chip(sbh), sb_chiprev(sbh),
15811 + (hz + 500000) / 1000000);
15812 +
15813 + /* Set MIPS counter frequency for fixed_rate_gettimeoffset() */
15814 + mips_hpt_frequency = hz / 2;
15815 +
15816 + /* Set watchdog interval in ms */
15817 + watchdog = simple_strtoul(nvram_safe_get("watchdog"), NULL, 0);
15818 +
15819 + /* Please set the watchdog to 3 sec if it is less than 3 but not equal to 0 */
15820 + if (watchdog > 0) {
15821 + if (watchdog < 3000)
15822 + watchdog = 3000;
15823 + }
15824 +
15825 + /* Set panic timeout in seconds */
15826 + panic_timeout = watchdog / 1000;
15827 +}
15828 +
15829 +static void
15830 +bcm947xx_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
15831 +{
15832 + /* Generic MIPS timer code */
15833 + timer_interrupt(irq, dev_id, regs);
15834 +
15835 + /* Set the watchdog timer to reset after the specified number of ms */
15836 + if (watchdog > 0)
15837 + sb_watchdog(sbh, WATCHDOG_CLOCK / 1000 * watchdog);
15838 +}
15839 +
15840 +static struct irqaction bcm947xx_timer_irqaction = {
15841 + bcm947xx_timer_interrupt,
15842 + SA_INTERRUPT,
15843 + 0,
15844 + "timer",
15845 + NULL,
15846 + NULL
15847 +};
15848 +
15849 +void __init
15850 +bcm947xx_timer_setup(struct irqaction *irq)
15851 +{
15852 + /* Enable the timer interrupt */
15853 + setup_irq(7, &bcm947xx_timer_irqaction);
15854 +}
15855 diff -urN linux.old/arch/mips/config-shared.in linux.dev/arch/mips/config-shared.in
15856 --- linux.old/arch/mips/config-shared.in 2006-10-02 21:23:10.000000000 +0200
15857 +++ linux.dev/arch/mips/config-shared.in 2006-10-02 21:19:59.000000000 +0200
15858 @@ -208,6 +208,14 @@
15859 fi
15860 define_bool CONFIG_MIPS_RTC y
15861 fi
15862 +dep_bool 'Support for Broadcom MIPS-based boards' CONFIG_MIPS_BRCM $CONFIG_EXPERIMENTAL
15863 +dep_bool 'Support for Broadcom BCM947XX' CONFIG_BCM947XX $CONFIG_MIPS_BRCM
15864 +if [ "$CONFIG_BCM947XX" = "y" ] ; then
15865 + bool ' Support for Broadcom BCM4710' CONFIG_BCM4710
15866 + bool ' Support for Broadcom BCM4310' CONFIG_BCM4310
15867 + bool ' Support for Broadcom BCM4704' CONFIG_BCM4704
15868 + bool ' Support for Broadcom BCM5365' CONFIG_BCM5365
15869 +fi
15870 bool 'Support for SNI RM200 PCI' CONFIG_SNI_RM200_PCI
15871 bool 'Support for TANBAC TB0226 (Mbase)' CONFIG_TANBAC_TB0226
15872 bool 'Support for TANBAC TB0229 (VR4131DIMM)' CONFIG_TANBAC_TB0229
15873 @@ -229,6 +237,11 @@
15874 define_bool CONFIG_RWSEM_XCHGADD_ALGORITHM n
15875
15876 #
15877 +# Provide an option for a default kernel command line
15878 +#
15879 +string 'Default kernel command string' CONFIG_CMDLINE ""
15880 +
15881 +#
15882 # Select some configuration options automatically based on user selections.
15883 #
15884 if [ "$CONFIG_ACER_PICA_61" = "y" ]; then
15885 @@ -554,6 +567,12 @@
15886 define_bool CONFIG_SWAP_IO_SPACE_L y
15887 define_bool CONFIG_BOOT_ELF32 y
15888 fi
15889 +if [ "$CONFIG_BCM947XX" = "y" ] ; then
15890 + define_bool CONFIG_PCI y
15891 + define_bool CONFIG_NONCOHERENT_IO y
15892 + define_bool CONFIG_NEW_TIME_C y
15893 + define_bool CONFIG_NEW_IRQ y
15894 +fi
15895 if [ "$CONFIG_SNI_RM200_PCI" = "y" ]; then
15896 define_bool CONFIG_ARC32 y
15897 define_bool CONFIG_ARC_MEMORY y
15898 @@ -1042,7 +1061,11 @@
15899
15900 bool 'Are you using a crosscompiler' CONFIG_CROSSCOMPILE
15901 bool 'Enable run-time debugging' CONFIG_RUNTIME_DEBUG
15902 -bool 'Remote GDB kernel debugging' CONFIG_KGDB
15903 +if [ "$CONFIG_BCM947XX" = "y" ] ; then
15904 + bool 'Remote GDB kernel debugging' CONFIG_REMOTE_DEBUG
15905 +else
15906 + bool 'Remote GDB kernel debugging' CONFIG_KGDB
15907 +fi
15908 dep_bool ' Console output to GDB' CONFIG_GDB_CONSOLE $CONFIG_KGDB
15909 if [ "$CONFIG_KGDB" = "y" ]; then
15910 define_bool CONFIG_DEBUG_INFO y
15911 diff -urN linux.old/arch/mips/kernel/cpu-probe.c linux.dev/arch/mips/kernel/cpu-probe.c
15912 --- linux.old/arch/mips/kernel/cpu-probe.c 2006-10-02 21:23:10.000000000 +0200
15913 +++ linux.dev/arch/mips/kernel/cpu-probe.c 2006-10-02 21:19:59.000000000 +0200
15914 @@ -162,7 +162,7 @@
15915
15916 static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
15917 {
15918 - switch (c->processor_id & 0xff00) {
15919 + switch (c->processor_id & PRID_IMP_MASK) {
15920 case PRID_IMP_R2000:
15921 c->cputype = CPU_R2000;
15922 c->isa_level = MIPS_CPU_ISA_I;
15923 @@ -172,7 +172,7 @@
15924 c->tlbsize = 64;
15925 break;
15926 case PRID_IMP_R3000:
15927 - if ((c->processor_id & 0xff) == PRID_REV_R3000A)
15928 + if ((c->processor_id & PRID_REV_MASK) == PRID_REV_R3000A)
15929 if (cpu_has_confreg())
15930 c->cputype = CPU_R3081E;
15931 else
15932 @@ -187,12 +187,12 @@
15933 break;
15934 case PRID_IMP_R4000:
15935 if (read_c0_config() & CONF_SC) {
15936 - if ((c->processor_id & 0xff) >= PRID_REV_R4400)
15937 + if ((c->processor_id & PRID_REV_MASK) >= PRID_REV_R4400)
15938 c->cputype = CPU_R4400PC;
15939 else
15940 c->cputype = CPU_R4000PC;
15941 } else {
15942 - if ((c->processor_id & 0xff) >= PRID_REV_R4400)
15943 + if ((c->processor_id & PRID_REV_MASK) >= PRID_REV_R4400)
15944 c->cputype = CPU_R4400SC;
15945 else
15946 c->cputype = CPU_R4000SC;
15947 @@ -438,7 +438,7 @@
15948 static inline void cpu_probe_mips(struct cpuinfo_mips *c)
15949 {
15950 decode_config1(c);
15951 - switch (c->processor_id & 0xff00) {
15952 + switch (c->processor_id & PRID_IMP_MASK) {
15953 case PRID_IMP_4KC:
15954 c->cputype = CPU_4KC;
15955 c->isa_level = MIPS_CPU_ISA_M32;
15956 @@ -479,10 +479,10 @@
15957 {
15958 decode_config1(c);
15959 c->options |= MIPS_CPU_PREFETCH;
15960 - switch (c->processor_id & 0xff00) {
15961 + switch (c->processor_id & PRID_IMP_MASK) {
15962 case PRID_IMP_AU1_REV1:
15963 case PRID_IMP_AU1_REV2:
15964 - switch ((c->processor_id >> 24) & 0xff) {
15965 + switch ((c->processor_id >> 24) & PRID_REV_MASK) {
15966 case 0:
15967 c->cputype = CPU_AU1000;
15968 break;
15969 @@ -510,10 +510,34 @@
15970 }
15971 }
15972
15973 +static inline void cpu_probe_broadcom(struct cpuinfo_mips *c)
15974 +{
15975 + decode_config1(c);
15976 + c->options |= MIPS_CPU_PREFETCH;
15977 + switch (c->processor_id & PRID_IMP_MASK) {
15978 + case PRID_IMP_BCM4710:
15979 + c->cputype = CPU_BCM4710;
15980 + c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
15981 + MIPS_CPU_4KTLB | MIPS_CPU_COUNTER;
15982 + c->scache.flags = MIPS_CACHE_NOT_PRESENT;
15983 + break;
15984 + case PRID_IMP_4KC:
15985 + case PRID_IMP_BCM3302:
15986 + c->cputype = CPU_BCM3302;
15987 + c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
15988 + MIPS_CPU_4KTLB | MIPS_CPU_COUNTER;
15989 + c->scache.flags = MIPS_CACHE_NOT_PRESENT;
15990 + break;
15991 + default:
15992 + c->cputype = CPU_UNKNOWN;
15993 + break;
15994 + }
15995 +}
15996 +
15997 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c)
15998 {
15999 decode_config1(c);
16000 - switch (c->processor_id & 0xff00) {
16001 + switch (c->processor_id & PRID_IMP_MASK) {
16002 case PRID_IMP_SB1:
16003 c->cputype = CPU_SB1;
16004 c->isa_level = MIPS_CPU_ISA_M64;
16005 @@ -535,7 +559,7 @@
16006 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c)
16007 {
16008 decode_config1(c);
16009 - switch (c->processor_id & 0xff00) {
16010 + switch (c->processor_id & PRID_IMP_MASK) {
16011 case PRID_IMP_SR71000:
16012 c->cputype = CPU_SR71000;
16013 c->isa_level = MIPS_CPU_ISA_M64;
16014 @@ -560,7 +584,7 @@
16015 c->cputype = CPU_UNKNOWN;
16016
16017 c->processor_id = read_c0_prid();
16018 - switch (c->processor_id & 0xff0000) {
16019 + switch (c->processor_id & PRID_COMP_MASK) {
16020
16021 case PRID_COMP_LEGACY:
16022 cpu_probe_legacy(c);
16023 @@ -571,6 +595,9 @@
16024 case PRID_COMP_ALCHEMY:
16025 cpu_probe_alchemy(c);
16026 break;
16027 + case PRID_COMP_BROADCOM:
16028 + cpu_probe_broadcom(c);
16029 + break;
16030 case PRID_COMP_SIBYTE:
16031 cpu_probe_sibyte(c);
16032 break;
16033 diff -urN linux.old/arch/mips/kernel/head.S linux.dev/arch/mips/kernel/head.S
16034 --- linux.old/arch/mips/kernel/head.S 2006-10-02 21:23:10.000000000 +0200
16035 +++ linux.dev/arch/mips/kernel/head.S 2006-10-02 21:19:59.000000000 +0200
16036 @@ -28,12 +28,20 @@
16037 #include <asm/mipsregs.h>
16038 #include <asm/stackframe.h>
16039
16040 +#ifdef CONFIG_BCM4710
16041 +#undef eret
16042 +#define eret nop; nop; eret
16043 +#endif
16044 +
16045 .text
16046 + j kernel_entry
16047 + nop
16048 +
16049 /*
16050 * Reserved space for exception handlers.
16051 * Necessary for machines which link their kernels at KSEG0.
16052 */
16053 - .fill 0x400
16054 + .fill 0x3f4
16055
16056 /* The following two symbols are used for kernel profiling. */
16057 EXPORT(stext)
16058 diff -urN linux.old/arch/mips/kernel/proc.c linux.dev/arch/mips/kernel/proc.c
16059 --- linux.old/arch/mips/kernel/proc.c 2006-10-02 21:23:10.000000000 +0200
16060 +++ linux.dev/arch/mips/kernel/proc.c 2006-10-02 21:19:59.000000000 +0200
16061 @@ -78,9 +78,10 @@
16062 [CPU_AU1550] "Au1550",
16063 [CPU_24K] "MIPS 24K",
16064 [CPU_AU1200] "Au1200",
16065 + [CPU_BCM4710] "BCM4710",
16066 + [CPU_BCM3302] "BCM3302",
16067 };
16068
16069 -
16070 static int show_cpuinfo(struct seq_file *m, void *v)
16071 {
16072 unsigned int version = current_cpu_data.processor_id;
16073 diff -urN linux.old/arch/mips/kernel/setup.c linux.dev/arch/mips/kernel/setup.c
16074 --- linux.old/arch/mips/kernel/setup.c 2006-10-02 21:23:10.000000000 +0200
16075 +++ linux.dev/arch/mips/kernel/setup.c 2006-10-02 21:19:59.000000000 +0200
16076 @@ -493,6 +493,7 @@
16077 void swarm_setup(void);
16078 void hp_setup(void);
16079 void au1x00_setup(void);
16080 + void brcm_setup(void);
16081 void frame_info_init(void);
16082
16083 frame_info_init();
16084 @@ -691,6 +692,11 @@
16085 pmc_yosemite_setup();
16086 break;
16087 #endif
16088 +#if defined(CONFIG_BCM4710) || defined(CONFIG_BCM4310)
16089 + case MACH_GROUP_BRCM:
16090 + brcm_setup();
16091 + break;
16092 +#endif
16093 default:
16094 panic("Unsupported architecture");
16095 }
16096 diff -urN linux.old/arch/mips/kernel/traps.c linux.dev/arch/mips/kernel/traps.c
16097 --- linux.old/arch/mips/kernel/traps.c 2006-10-02 21:23:10.000000000 +0200
16098 +++ linux.dev/arch/mips/kernel/traps.c 2006-10-02 21:19:59.000000000 +0200
16099 @@ -920,6 +920,7 @@
16100 void __init trap_init(void)
16101 {
16102 extern char except_vec1_generic;
16103 + extern char except_vec2_generic;
16104 extern char except_vec3_generic, except_vec3_r4000;
16105 extern char except_vec_ejtag_debug;
16106 extern char except_vec4;
16107 @@ -927,6 +928,7 @@
16108
16109 /* Copy the generic exception handler code to it's final destination. */
16110 memcpy((void *)(KSEG0 + 0x80), &except_vec1_generic, 0x80);
16111 + memcpy((void *)(KSEG0 + 0x100), &except_vec2_generic, 0x80);
16112
16113 /*
16114 * Setup default vectors
16115 @@ -985,6 +987,12 @@
16116 set_except_vector(13, handle_tr);
16117 set_except_vector(22, handle_mdmx);
16118
16119 + if (current_cpu_data.cputype == CPU_SB1) {
16120 + /* Enable timer interrupt and scd mapped interrupt */
16121 + clear_c0_status(0xf000);
16122 + set_c0_status(0xc00);
16123 + }
16124 +
16125 if (cpu_has_fpu && !cpu_has_nofpuex)
16126 set_except_vector(15, handle_fpe);
16127
16128 diff -urN linux.old/arch/mips/Makefile linux.dev/arch/mips/Makefile
16129 --- linux.old/arch/mips/Makefile 2006-10-02 21:23:10.000000000 +0200
16130 +++ linux.dev/arch/mips/Makefile 2006-10-02 21:19:59.000000000 +0200
16131 @@ -726,6 +726,19 @@
16132 endif
16133
16134 #
16135 +# Broadcom BCM947XX variants
16136 +#
16137 +ifdef CONFIG_BCM947XX
16138 +LIBS += arch/mips/bcm947xx/generic/brcm.o arch/mips/bcm947xx/bcm947xx.o
16139 +SUBDIRS += arch/mips/bcm947xx/generic arch/mips/bcm947xx
16140 +LOADADDR := 0x80001000
16141 +
16142 +zImage: vmlinux
16143 + $(MAKE) -C arch/$(ARCH)/bcm947xx/compressed
16144 +export LOADADDR
16145 +endif
16146 +
16147 +#
16148 # Choosing incompatible machines durings configuration will result in
16149 # error messages during linking. Select a default linkscript if
16150 # none has been choosen above.
16151 @@ -778,6 +791,7 @@
16152 $(MAKE) -C arch/$(ARCH)/tools clean
16153 $(MAKE) -C arch/mips/baget clean
16154 $(MAKE) -C arch/mips/lasat clean
16155 + $(MAKE) -C arch/mips/bcm947xx/compressed clean
16156
16157 archmrproper:
16158 @$(MAKEBOOT) mrproper
16159 diff -urN linux.old/arch/mips/mm/c-r4k.c linux.dev/arch/mips/mm/c-r4k.c
16160 --- linux.old/arch/mips/mm/c-r4k.c 2006-10-02 21:23:10.000000000 +0200
16161 +++ linux.dev/arch/mips/mm/c-r4k.c 2006-10-02 21:19:59.000000000 +0200
16162 @@ -1166,3 +1166,47 @@
16163 build_clear_page();
16164 build_copy_page();
16165 }
16166 +
16167 +#ifdef CONFIG_BCM4704
16168 +static void __init mips32_icache_fill(unsigned long addr, uint nbytes)
16169 +{
16170 + unsigned long ic_lsize = current_cpu_data.icache.linesz;
16171 + int i;
16172 + for (i = 0; i < nbytes; i += ic_lsize)
16173 + fill_icache_line((addr + i));
16174 +}
16175 +
16176 +/*
16177 + * This must be run from the cache on 4704A0
16178 + * so there are no mips core BIU ops in progress
16179 + * when the PFC is enabled.
16180 + */
16181 +#define PFC_CR0 0xff400000 /* control reg 0 */
16182 +#define PFC_CR1 0xff400004 /* control reg 1 */
16183 +static void __init enable_pfc(u32 mode)
16184 +{
16185 + /* write range */
16186 + *(volatile u32 *)PFC_CR1 = 0xffff0000;
16187 +
16188 + /* enable */
16189 + *(volatile u32 *)PFC_CR0 = mode;
16190 +}
16191 +#endif
16192 +
16193 +
16194 +void check_enable_mips_pfc(int val)
16195 +{
16196 +
16197 +#ifdef CONFIG_BCM4704
16198 + struct cpuinfo_mips *c = &current_cpu_data;
16199 +
16200 + /* enable prefetch cache */
16201 + if (((c->processor_id & (PRID_COMP_MASK | PRID_IMP_MASK)) == PRID_IMP_BCM3302)
16202 + && (read_c0_diag() & (1 << 29))) {
16203 + mips32_icache_fill((unsigned long) &enable_pfc, 64);
16204 + enable_pfc(val);
16205 + }
16206 +#endif
16207 +}
16208 +
16209 +
16210 diff -urN linux.old/arch/mips/pci/Makefile linux.dev/arch/mips/pci/Makefile
16211 --- linux.old/arch/mips/pci/Makefile 2006-10-02 21:23:10.000000000 +0200
16212 +++ linux.dev/arch/mips/pci/Makefile 2006-10-02 21:19:59.000000000 +0200
16213 @@ -13,7 +13,9 @@
16214 obj-$(CONFIG_MIPS_MSC) += ops-msc.o
16215 obj-$(CONFIG_MIPS_NILE4) += ops-nile4.o
16216 obj-$(CONFIG_SNI_RM200_PCI) += ops-sni.o
16217 +ifndef CONFIG_BCM947XX
16218 obj-y += pci.o
16219 +endif
16220 obj-$(CONFIG_PCI_AUTO) += pci_auto.o
16221
16222 include $(TOPDIR)/Rules.make
16223 diff -urN linux.old/drivers/char/serial.c linux.dev/drivers/char/serial.c
16224 --- linux.old/drivers/char/serial.c 2006-10-02 21:23:10.000000000 +0200
16225 +++ linux.dev/drivers/char/serial.c 2006-10-02 21:19:59.000000000 +0200
16226 @@ -444,6 +444,10 @@
16227 return inb(info->port+1);
16228 #endif
16229 case SERIAL_IO_MEM:
16230 +#ifdef CONFIG_BCM4310
16231 + readb((unsigned long) info->iomem_base +
16232 + (UART_SCR<<info->iomem_reg_shift));
16233 +#endif
16234 return readb((unsigned long) info->iomem_base +
16235 (offset<<info->iomem_reg_shift));
16236 default:
16237 @@ -464,6 +468,9 @@
16238 case SERIAL_IO_MEM:
16239 writeb(value, (unsigned long) info->iomem_base +
16240 (offset<<info->iomem_reg_shift));
16241 +#ifdef CONFIG_BCM4704
16242 + *((volatile unsigned int *) KSEG1ADDR(0x18000000));
16243 +#endif
16244 break;
16245 default:
16246 outb(value, info->port+offset);
16247 @@ -1728,7 +1735,7 @@
16248 /* Special case since 134 is really 134.5 */
16249 quot = (2*baud_base / 269);
16250 else if (baud)
16251 - quot = baud_base / baud;
16252 + quot = (baud_base + (baud / 2)) / baud;
16253 }
16254 /* If the quotient is zero refuse the change */
16255 if (!quot && old_termios) {
16256 @@ -1745,12 +1752,12 @@
16257 /* Special case since 134 is really 134.5 */
16258 quot = (2*baud_base / 269);
16259 else if (baud)
16260 - quot = baud_base / baud;
16261 + quot = (baud_base + (baud / 2)) / baud;
16262 }
16263 }
16264 /* As a last resort, if the quotient is zero, default to 9600 bps */
16265 if (!quot)
16266 - quot = baud_base / 9600;
16267 + quot = (baud_base + 4800) / 9600;
16268 /*
16269 * Work around a bug in the Oxford Semiconductor 952 rev B
16270 * chip which causes it to seriously miscalculate baud rates
16271 @@ -5994,6 +6001,13 @@
16272 * Divisor, bytesize and parity
16273 */
16274 state = rs_table + co->index;
16275 + /*
16276 + * Safe guard: state structure must have been initialized
16277 + */
16278 + if (state->iomem_base == NULL) {
16279 + printk("!unable to setup serial console!\n");
16280 + return -1;
16281 + }
16282 if (doflow)
16283 state->flags |= ASYNC_CONS_FLOW;
16284 info = &async_sercons;
16285 @@ -6007,7 +6021,7 @@
16286 info->io_type = state->io_type;
16287 info->iomem_base = state->iomem_base;
16288 info->iomem_reg_shift = state->iomem_reg_shift;
16289 - quot = state->baud_base / baud;
16290 + quot = (state->baud_base + (baud / 2)) / baud;
16291 cval = cflag & (CSIZE | CSTOPB);
16292 #if defined(__powerpc__) || defined(__alpha__)
16293 cval >>= 8;
16294 diff -urN linux.old/drivers/net/Makefile linux.dev/drivers/net/Makefile
16295 --- linux.old/drivers/net/Makefile 2006-10-02 21:23:10.000000000 +0200
16296 +++ linux.dev/drivers/net/Makefile 2006-10-02 21:19:59.000000000 +0200
16297 @@ -3,6 +3,8 @@
16298 # Makefile for the Linux network (ethercard) device drivers.
16299 #
16300
16301 +EXTRA_CFLAGS := -I$(TOPDIR)/arch/mips/bcm947xx/include
16302 +
16303 obj-y :=
16304 obj-m :=
16305 obj-n :=
16306 diff -urN linux.old/drivers/parport/Config.in linux.dev/drivers/parport/Config.in
16307 --- linux.old/drivers/parport/Config.in 2006-10-02 21:23:10.000000000 +0200
16308 +++ linux.dev/drivers/parport/Config.in 2006-10-02 21:19:59.000000000 +0200
16309 @@ -11,6 +11,7 @@
16310 tristate 'Parallel port support' CONFIG_PARPORT
16311 if [ "$CONFIG_PARPORT" != "n" ]; then
16312 dep_tristate ' PC-style hardware' CONFIG_PARPORT_PC $CONFIG_PARPORT
16313 + dep_tristate ' Asus WL500g parallel port' CONFIG_PARPORT_SPLINK $CONFIG_PARPORT
16314 if [ "$CONFIG_PARPORT_PC" != "n" -a "$CONFIG_SERIAL" != "n" ]; then
16315 if [ "$CONFIG_SERIAL" = "m" ]; then
16316 define_tristate CONFIG_PARPORT_PC_CML1 m
16317 diff -urN linux.old/drivers/parport/Makefile linux.dev/drivers/parport/Makefile
16318 --- linux.old/drivers/parport/Makefile 2006-10-02 21:23:10.000000000 +0200
16319 +++ linux.dev/drivers/parport/Makefile 2006-10-02 21:19:59.000000000 +0200
16320 @@ -22,6 +22,7 @@
16321
16322 obj-$(CONFIG_PARPORT) += parport.o
16323 obj-$(CONFIG_PARPORT_PC) += parport_pc.o
16324 +obj-$(CONFIG_PARPORT_SPLINK) += parport_splink.o
16325 obj-$(CONFIG_PARPORT_PC_PCMCIA) += parport_cs.o
16326 obj-$(CONFIG_PARPORT_AMIGA) += parport_amiga.o
16327 obj-$(CONFIG_PARPORT_MFC3) += parport_mfc3.o
16328 diff -urN linux.old/drivers/parport/parport_splink.c linux.dev/drivers/parport/parport_splink.c
16329 --- linux.old/drivers/parport/parport_splink.c 1970-01-01 01:00:00.000000000 +0100
16330 +++ linux.dev/drivers/parport/parport_splink.c 2006-10-02 21:19:59.000000000 +0200
16331 @@ -0,0 +1,345 @@
16332 +/* Low-level parallel port routines for the ASUS WL-500g built-in port
16333 + *
16334 + * Author: Nuno Grilo <nuno.grilo@netcabo.pt>
16335 + * Based on parport_pc source
16336 + */
16337 +
16338 +#include <linux/config.h>
16339 +#include <linux/module.h>
16340 +#include <linux/init.h>
16341 +#include <linux/ioport.h>
16342 +#include <linux/kernel.h>
16343 +#include <linux/slab.h>
16344 +#include <linux/parport.h>
16345 +#include <linux/parport_pc.h>
16346 +
16347 +#define SPLINK_ADDRESS 0xBF800010
16348 +
16349 +#undef DEBUG
16350 +
16351 +#ifdef DEBUG
16352 +#define DPRINTK printk
16353 +#else
16354 +#define DPRINTK(stuff...)
16355 +#endif
16356 +
16357 +
16358 +/* __parport_splink_frob_control differs from parport_splink_frob_control in that
16359 + * it doesn't do any extra masking. */
16360 +static __inline__ unsigned char __parport_splink_frob_control (struct parport *p,
16361 + unsigned char mask,
16362 + unsigned char val)
16363 +{
16364 + struct parport_pc_private *priv = p->physport->private_data;
16365 + unsigned char *io = (unsigned char *) p->base;
16366 + unsigned char ctr = priv->ctr;
16367 +#ifdef DEBUG_PARPORT
16368 + printk (KERN_DEBUG
16369 + "__parport_splink_frob_control(%02x,%02x): %02x -> %02x\n",
16370 + mask, val, ctr, ((ctr & ~mask) ^ val) & priv->ctr_writable);
16371 +#endif
16372 + ctr = (ctr & ~mask) ^ val;
16373 + ctr &= priv->ctr_writable; /* only write writable bits. */
16374 + *(io+2) = ctr;
16375 + priv->ctr = ctr; /* Update soft copy */
16376 + return ctr;
16377 +}
16378 +
16379 +
16380 +
16381 +static void parport_splink_data_forward (struct parport *p)
16382 +{
16383 + DPRINTK(KERN_DEBUG "parport_splink: parport_data_forward called\n");
16384 + __parport_splink_frob_control (p, 0x20, 0);
16385 +}
16386 +
16387 +static void parport_splink_data_reverse (struct parport *p)
16388 +{
16389 + DPRINTK(KERN_DEBUG "parport_splink: parport_data_forward called\n");
16390 + __parport_splink_frob_control (p, 0x20, 0x20);
16391 +}
16392 +
16393 +/*
16394 +static void parport_splink_interrupt(int irq, void *dev_id, struct pt_regs *regs)
16395 +{
16396 + DPRINTK(KERN_DEBUG "parport_splink: IRQ handler called\n");
16397 + parport_generic_irq(irq, (struct parport *) dev_id, regs);
16398 +}
16399 +*/
16400 +
16401 +static void parport_splink_enable_irq(struct parport *p)
16402 +{
16403 + DPRINTK(KERN_DEBUG "parport_splink: parport_splink_enable_irq called\n");
16404 + __parport_splink_frob_control (p, 0x10, 0x10);
16405 +}
16406 +
16407 +static void parport_splink_disable_irq(struct parport *p)
16408 +{
16409 + DPRINTK(KERN_DEBUG "parport_splink: parport_splink_disable_irq called\n");
16410 + __parport_splink_frob_control (p, 0x10, 0);
16411 +}
16412 +
16413 +static void parport_splink_init_state(struct pardevice *dev, struct parport_state *s)
16414 +{
16415 + DPRINTK(KERN_DEBUG "parport_splink: parport_splink_init_state called\n");
16416 + s->u.pc.ctr = 0xc | (dev->irq_func ? 0x10 : 0x0);
16417 + if (dev->irq_func &&
16418 + dev->port->irq != PARPORT_IRQ_NONE)
16419 + /* Set ackIntEn */
16420 + s->u.pc.ctr |= 0x10;
16421 +}
16422 +
16423 +static void parport_splink_save_state(struct parport *p, struct parport_state *s)
16424 +{
16425 + const struct parport_pc_private *priv = p->physport->private_data;
16426 + DPRINTK(KERN_DEBUG "parport_splink: parport_splink_save_state called\n");
16427 + s->u.pc.ctr = priv->ctr;
16428 +}
16429 +
16430 +static void parport_splink_restore_state(struct parport *p, struct parport_state *s)
16431 +{
16432 + struct parport_pc_private *priv = p->physport->private_data;
16433 + unsigned char *io = (unsigned char *) p->base;
16434 + unsigned char ctr = s->u.pc.ctr;
16435 +
16436 + DPRINTK(KERN_DEBUG "parport_splink: parport_splink_restore_state called\n");
16437 + *(io+2) = ctr;
16438 + priv->ctr = ctr;
16439 +}
16440 +
16441 +static void parport_splink_setup_interrupt(void) {
16442 + return;
16443 +}
16444 +
16445 +static void parport_splink_write_data(struct parport *p, unsigned char d) {
16446 + DPRINTK(KERN_DEBUG "parport_splink: write data called\n");
16447 + unsigned char *io = (unsigned char *) p->base;
16448 + *io = d;
16449 +}
16450 +
16451 +static unsigned char parport_splink_read_data(struct parport *p) {
16452 + DPRINTK(KERN_DEBUG "parport_splink: read data called\n");
16453 + unsigned char *io = (unsigned char *) p->base;
16454 + return *io;
16455 +}
16456 +
16457 +static void parport_splink_write_control(struct parport *p, unsigned char d)
16458 +{
16459 + const unsigned char wm = (PARPORT_CONTROL_STROBE |
16460 + PARPORT_CONTROL_AUTOFD |
16461 + PARPORT_CONTROL_INIT |
16462 + PARPORT_CONTROL_SELECT);
16463 +
16464 + DPRINTK(KERN_DEBUG "parport_splink: write control called\n");
16465 + /* Take this out when drivers have adapted to the newer interface. */
16466 + if (d & 0x20) {
16467 + printk (KERN_DEBUG "%s (%s): use data_reverse for this!\n",
16468 + p->name, p->cad->name);
16469 + parport_splink_data_reverse (p);
16470 + }
16471 +
16472 + __parport_splink_frob_control (p, wm, d & wm);
16473 +}
16474 +
16475 +static unsigned char parport_splink_read_control(struct parport *p)
16476 +{
16477 + const unsigned char wm = (PARPORT_CONTROL_STROBE |
16478 + PARPORT_CONTROL_AUTOFD |
16479 + PARPORT_CONTROL_INIT |
16480 + PARPORT_CONTROL_SELECT);
16481 + DPRINTK(KERN_DEBUG "parport_splink: read control called\n");
16482 + const struct parport_pc_private *priv = p->physport->private_data;
16483 + return priv->ctr & wm; /* Use soft copy */
16484 +}
16485 +
16486 +static unsigned char parport_splink_frob_control (struct parport *p, unsigned char mask,
16487 + unsigned char val)
16488 +{
16489 + const unsigned char wm = (PARPORT_CONTROL_STROBE |
16490 + PARPORT_CONTROL_AUTOFD |
16491 + PARPORT_CONTROL_INIT |
16492 + PARPORT_CONTROL_SELECT);
16493 +
16494 + DPRINTK(KERN_DEBUG "parport_splink: frob control called\n");
16495 + /* Take this out when drivers have adapted to the newer interface. */
16496 + if (mask & 0x20) {
16497 + printk (KERN_DEBUG "%s (%s): use data_%s for this!\n",
16498 + p->name, p->cad->name,
16499 + (val & 0x20) ? "reverse" : "forward");
16500 + if (val & 0x20)
16501 + parport_splink_data_reverse (p);
16502 + else
16503 + parport_splink_data_forward (p);
16504 + }
16505 +
16506 + /* Restrict mask and val to control lines. */
16507 + mask &= wm;
16508 + val &= wm;
16509 +
16510 + return __parport_splink_frob_control (p, mask, val);
16511 +}
16512 +
16513 +static unsigned char parport_splink_read_status(struct parport *p)
16514 +{
16515 + DPRINTK(KERN_DEBUG "parport_splink: read status called\n");
16516 + unsigned char *io = (unsigned char *) p->base;
16517 + return *(io+1);
16518 +}
16519 +
16520 +static void parport_splink_inc_use_count(void)
16521 +{
16522 +#ifdef MODULE
16523 + MOD_INC_USE_COUNT;
16524 +#endif
16525 +}
16526 +
16527 +static void parport_splink_dec_use_count(void)
16528 +{
16529 +#ifdef MODULE
16530 + MOD_DEC_USE_COUNT;
16531 +#endif
16532 +}
16533 +
16534 +static struct parport_operations parport_splink_ops =
16535 +{
16536 + parport_splink_write_data,
16537 + parport_splink_read_data,
16538 +
16539 + parport_splink_write_control,
16540 + parport_splink_read_control,
16541 + parport_splink_frob_control,
16542 +
16543 + parport_splink_read_status,
16544 +
16545 + parport_splink_enable_irq,
16546 + parport_splink_disable_irq,
16547 +
16548 + parport_splink_data_forward,
16549 + parport_splink_data_reverse,
16550 +
16551 + parport_splink_init_state,
16552 + parport_splink_save_state,
16553 + parport_splink_restore_state,
16554 +
16555 + parport_splink_inc_use_count,
16556 + parport_splink_dec_use_count,
16557 +
16558 + parport_ieee1284_epp_write_data,
16559 + parport_ieee1284_epp_read_data,
16560 + parport_ieee1284_epp_write_addr,
16561 + parport_ieee1284_epp_read_addr,
16562 +
16563 + parport_ieee1284_ecp_write_data,
16564 + parport_ieee1284_ecp_read_data,
16565 + parport_ieee1284_ecp_write_addr,
16566 +
16567 + parport_ieee1284_write_compat,
16568 + parport_ieee1284_read_nibble,
16569 + parport_ieee1284_read_byte,
16570 +};
16571 +
16572 +/* --- Initialisation code -------------------------------- */
16573 +
16574 +static struct parport *parport_splink_probe_port (unsigned long int base)
16575 +{
16576 + struct parport_pc_private *priv;
16577 + struct parport_operations *ops;
16578 + struct parport *p;
16579 +
16580 + if (check_mem_region(base, 3)) {
16581 + printk (KERN_DEBUG "parport (0x%lx): iomem region not available\n", base);
16582 + return NULL;
16583 + }
16584 + priv = kmalloc (sizeof (struct parport_pc_private), GFP_KERNEL);
16585 + if (!priv) {
16586 + printk (KERN_DEBUG "parport (0x%lx): no memory!\n", base);
16587 + return NULL;
16588 + }
16589 + ops = kmalloc (sizeof (struct parport_operations), GFP_KERNEL);
16590 + if (!ops) {
16591 + printk (KERN_DEBUG "parport (0x%lx): no memory for ops!\n",
16592 + base);
16593 + kfree (priv);
16594 + return NULL;
16595 + }
16596 + memcpy (ops, &parport_splink_ops, sizeof (struct parport_operations));
16597 + priv->ctr = 0xc;
16598 + priv->ctr_writable = 0xff;
16599 +
16600 + if (!(p = parport_register_port(base, PARPORT_IRQ_NONE,
16601 + PARPORT_DMA_NONE, ops))) {
16602 + printk (KERN_DEBUG "parport (0x%lx): registration failed!\n",
16603 + base);
16604 + kfree (priv);
16605 + kfree (ops);
16606 + return NULL;
16607 + }
16608 +
16609 + p->modes = PARPORT_MODE_PCSPP | PARPORT_MODE_SAFEININT;
16610 + p->size = (p->modes & PARPORT_MODE_EPP)?8:3;
16611 + p->private_data = priv;
16612 +
16613 + parport_proc_register(p);
16614 + request_mem_region (p->base, 3, p->name);
16615 +
16616 + /* Done probing. Now put the port into a sensible start-up state. */
16617 + parport_splink_write_data(p, 0);
16618 + parport_splink_data_forward (p);
16619 +
16620 + /* Now that we've told the sharing engine about the port, and
16621 + found out its characteristics, let the high-level drivers
16622 + know about it. */
16623 + parport_announce_port (p);
16624 +
16625 + DPRINTK(KERN_DEBUG "parport (0x%lx): init ok!\n",
16626 + base);
16627 + return p;
16628 +}
16629 +
16630 +static void parport_splink_unregister_port(struct parport *p) {
16631 + struct parport_pc_private *priv = p->private_data;
16632 + struct parport_operations *ops = p->ops;
16633 +
16634 + if (p->irq != PARPORT_IRQ_NONE)
16635 + free_irq(p->irq, p);
16636 + release_mem_region(p->base, 3);
16637 + parport_proc_unregister(p);
16638 + kfree (priv);
16639 + parport_unregister_port(p);
16640 + kfree (ops);
16641 +}
16642 +
16643 +
16644 +int parport_splink_init(void)
16645 +{
16646 + int ret;
16647 +
16648 + DPRINTK(KERN_DEBUG "parport_splink init called\n");
16649 + parport_splink_setup_interrupt();
16650 + ret = !parport_splink_probe_port(SPLINK_ADDRESS);
16651 +
16652 + return ret;
16653 +}
16654 +
16655 +void parport_splink_cleanup(void) {
16656 + struct parport *p = parport_enumerate(), *tmp;
16657 + DPRINTK(KERN_DEBUG "parport_splink cleanup called\n");
16658 + if (p->size) {
16659 + if (p->modes & PARPORT_MODE_PCSPP) {
16660 + while(p) {
16661 + tmp = p->next;
16662 + parport_splink_unregister_port(p);
16663 + p = tmp;
16664 + }
16665 + }
16666 + }
16667 +}
16668 +
16669 +MODULE_AUTHOR("Nuno Grilo <nuno.grilo@netcabo.pt>");
16670 +MODULE_DESCRIPTION("Parport Driver for ASUS WL-500g router builtin Port");
16671 +MODULE_SUPPORTED_DEVICE("ASUS WL-500g builtin Parallel Port");
16672 +MODULE_LICENSE("GPL");
16673 +
16674 +module_init(parport_splink_init)
16675 +module_exit(parport_splink_cleanup)
16676 +
16677 diff -urN linux.old/include/asm-mips/bootinfo.h linux.dev/include/asm-mips/bootinfo.h
16678 --- linux.old/include/asm-mips/bootinfo.h 2006-10-02 21:23:10.000000000 +0200
16679 +++ linux.dev/include/asm-mips/bootinfo.h 2006-10-02 21:19:59.000000000 +0200
16680 @@ -37,6 +37,7 @@
16681 #define MACH_GROUP_HP_LJ 20 /* Hewlett Packard LaserJet */
16682 #define MACH_GROUP_LASAT 21
16683 #define MACH_GROUP_TITAN 22 /* PMC-Sierra Titan */
16684 +#define MACH_GROUP_BRCM 23 /* Broadcom */
16685
16686 /*
16687 * Valid machtype values for group unknown (low order halfword of mips_machtype)
16688 @@ -197,6 +198,15 @@
16689 #define MACH_TANBAC_TB0229 7 /* TANBAC TB0229 (VR4131DIMM) */
16690
16691 /*
16692 + * Valid machtypes for group Broadcom
16693 + */
16694 +#define MACH_BCM93725 0
16695 +#define MACH_BCM93725_VJ 1
16696 +#define MACH_BCM93730 2
16697 +#define MACH_BCM947XX 3
16698 +#define MACH_BCM933XX 4
16699 +
16700 +/*
16701 * Valid machtype for group TITAN
16702 */
16703 #define MACH_TITAN_YOSEMITE 1 /* PMC-Sierra Yosemite */
16704 diff -urN linux.old/include/asm-mips/cpu.h linux.dev/include/asm-mips/cpu.h
16705 --- linux.old/include/asm-mips/cpu.h 2006-10-02 21:23:10.000000000 +0200
16706 +++ linux.dev/include/asm-mips/cpu.h 2006-10-02 21:19:59.000000000 +0200
16707 @@ -22,6 +22,11 @@
16708 spec.
16709 */
16710
16711 +#define PRID_COPT_MASK 0xff000000
16712 +#define PRID_COMP_MASK 0x00ff0000
16713 +#define PRID_IMP_MASK 0x0000ff00
16714 +#define PRID_REV_MASK 0x000000ff
16715 +
16716 #define PRID_COMP_LEGACY 0x000000
16717 #define PRID_COMP_MIPS 0x010000
16718 #define PRID_COMP_BROADCOM 0x020000
16719 @@ -58,6 +63,7 @@
16720 #define PRID_IMP_RM7000 0x2700
16721 #define PRID_IMP_NEVADA 0x2800 /* RM5260 ??? */
16722 #define PRID_IMP_RM9000 0x3400
16723 +#define PRID_IMP_BCM4710 0x4000
16724 #define PRID_IMP_R5432 0x5400
16725 #define PRID_IMP_R5500 0x5500
16726 #define PRID_IMP_4KC 0x8000
16727 @@ -66,10 +72,16 @@
16728 #define PRID_IMP_4KEC 0x8400
16729 #define PRID_IMP_4KSC 0x8600
16730 #define PRID_IMP_25KF 0x8800
16731 +#define PRID_IMP_BCM3302 0x9000
16732 +#define PRID_IMP_BCM3303 0x9100
16733 #define PRID_IMP_24K 0x9300
16734
16735 #define PRID_IMP_UNKNOWN 0xff00
16736
16737 +#define BCM330X(id) \
16738 + (((id & (PRID_COMP_MASK | PRID_IMP_MASK)) == (PRID_COMP_BROADCOM | PRID_IMP_BCM3302)) \
16739 + || ((id & (PRID_COMP_MASK | PRID_IMP_MASK)) == (PRID_COMP_BROADCOM | PRID_IMP_BCM3303)))
16740 +
16741 /*
16742 * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE
16743 */
16744 @@ -174,7 +186,9 @@
16745 #define CPU_AU1550 57
16746 #define CPU_24K 58
16747 #define CPU_AU1200 59
16748 -#define CPU_LAST 59
16749 +#define CPU_BCM4710 60
16750 +#define CPU_BCM3302 61
16751 +#define CPU_LAST 61
16752
16753 /*
16754 * ISA Level encodings
16755 diff -urN linux.old/include/asm-mips/r4kcache.h linux.dev/include/asm-mips/r4kcache.h
16756 --- linux.old/include/asm-mips/r4kcache.h 2006-10-02 21:23:10.000000000 +0200
16757 +++ linux.dev/include/asm-mips/r4kcache.h 2006-10-02 21:19:59.000000000 +0200
16758 @@ -658,4 +658,17 @@
16759 cache128_unroll32(addr|ws,Index_Writeback_Inv_SD);
16760 }
16761
16762 +extern inline void fill_icache_line(unsigned long addr)
16763 +{
16764 + __asm__ __volatile__(
16765 + ".set noreorder\n\t"
16766 + ".set mips3\n\t"
16767 + "cache %1, (%0)\n\t"
16768 + ".set mips0\n\t"
16769 + ".set reorder"
16770 + :
16771 + : "r" (addr),
16772 + "i" (Fill));
16773 +}
16774 +
16775 #endif /* __ASM_R4KCACHE_H */
16776 diff -urN linux.old/include/asm-mips/serial.h linux.dev/include/asm-mips/serial.h
16777 --- linux.old/include/asm-mips/serial.h 2006-10-02 21:23:10.000000000 +0200
16778 +++ linux.dev/include/asm-mips/serial.h 2006-10-02 21:19:59.000000000 +0200
16779 @@ -223,6 +223,13 @@
16780 #define TXX927_SERIAL_PORT_DEFNS
16781 #endif
16782
16783 +#ifdef CONFIG_BCM947XX
16784 +/* reserve 4 ports to be configured at runtime */
16785 +#define BCM947XX_SERIAL_PORT_DEFNS { 0, }, { 0, }, { 0, }, { 0, },
16786 +#else
16787 +#define BCM947XX_SERIAL_PORT_DEFNS
16788 +#endif
16789 +
16790 #ifdef CONFIG_HAVE_STD_PC_SERIAL_PORT
16791 #define STD_SERIAL_PORT_DEFNS \
16792 /* UART CLK PORT IRQ FLAGS */ \
16793 @@ -470,6 +477,7 @@
16794 #define SERIAL_PORT_DFNS \
16795 ATLAS_SERIAL_PORT_DEFNS \
16796 AU1000_SERIAL_PORT_DEFNS \
16797 + BCM947XX_SERIAL_PORT_DEFNS \
16798 COBALT_SERIAL_PORT_DEFNS \
16799 DDB5477_SERIAL_PORT_DEFNS \
16800 EV96100_SERIAL_PORT_DEFNS \
16801 diff -urN linux.old/init/do_mounts.c linux.dev/init/do_mounts.c
16802 --- linux.old/init/do_mounts.c 2006-10-02 21:23:10.000000000 +0200
16803 +++ linux.dev/init/do_mounts.c 2006-10-02 21:19:59.000000000 +0200
16804 @@ -254,7 +254,13 @@
16805 { "ftlb", 0x2c08 },
16806 { "ftlc", 0x2c10 },
16807 { "ftld", 0x2c18 },
16808 +#if defined(CONFIG_MTD_BLOCK) || defined(CONFIG_MTD_BLOCK_RO)
16809 { "mtdblock", 0x1f00 },
16810 + { "mtdblock0",0x1f00 },
16811 + { "mtdblock1",0x1f01 },
16812 + { "mtdblock2",0x1f02 },
16813 + { "mtdblock3",0x1f03 },
16814 +#endif
16815 { "nb", 0x2b00 },
16816 { NULL, 0 }
16817 };
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