brcm2708: update against latest rpi-3.10.y branch
[openwrt/svn-archive/archive.git] / target / linux / brcm2708 / patches-3.10 / 0001-Main-bcm2708-linux-port.patch
1 From 47ecfc09ad3289994f80bd3dcaec876ac536d884 Mon Sep 17 00:00:00 2001
2 From: popcornmix <popcornmix@gmail.com>
3 Date: Sun, 12 May 2013 12:24:19 +0100
4 Subject: [PATCH 001/174] Main bcm2708 linux port
5
6 Signed-off-by: popcornmix <popcornmix@gmail.com>
7 ---
8 arch/arm/Kconfig | 16 +
9 arch/arm/Kconfig.debug | 8 +
10 arch/arm/Makefile | 1 +
11 arch/arm/configs/bcmrpi_cutdown_defconfig | 474 +++++++
12 arch/arm/configs/bcmrpi_defconfig | 510 ++++++++
13 arch/arm/configs/bcmrpi_emergency_defconfig | 532 ++++++++
14 arch/arm/kernel/process.c | 2 +-
15 arch/arm/mach-bcm2708/Kconfig | 34 +
16 arch/arm/mach-bcm2708/Makefile | 8 +
17 arch/arm/mach-bcm2708/Makefile.boot | 3 +
18 arch/arm/mach-bcm2708/armctrl.c | 208 ++++
19 arch/arm/mach-bcm2708/armctrl.h | 27 +
20 arch/arm/mach-bcm2708/bcm2708.c | 695 +++++++++++
21 arch/arm/mach-bcm2708/bcm2708.h | 51 +
22 arch/arm/mach-bcm2708/bcm2708_gpio.c | 339 +++++
23 arch/arm/mach-bcm2708/clock.c | 61 +
24 arch/arm/mach-bcm2708/clock.h | 24 +
25 arch/arm/mach-bcm2708/dma.c | 399 ++++++
26 arch/arm/mach-bcm2708/include/mach/arm_control.h | 419 +++++++
27 arch/arm/mach-bcm2708/include/mach/arm_power.h | 60 +
28 arch/arm/mach-bcm2708/include/mach/clkdev.h | 7 +
29 arch/arm/mach-bcm2708/include/mach/debug-macro.S | 22 +
30 arch/arm/mach-bcm2708/include/mach/dma.h | 86 ++
31 arch/arm/mach-bcm2708/include/mach/entry-macro.S | 69 ++
32 arch/arm/mach-bcm2708/include/mach/frc.h | 38 +
33 arch/arm/mach-bcm2708/include/mach/gpio.h | 18 +
34 arch/arm/mach-bcm2708/include/mach/hardware.h | 28 +
35 arch/arm/mach-bcm2708/include/mach/io.h | 27 +
36 arch/arm/mach-bcm2708/include/mach/irqs.h | 196 +++
37 arch/arm/mach-bcm2708/include/mach/memory.h | 57 +
38 arch/arm/mach-bcm2708/include/mach/platform.h | 220 ++++
39 arch/arm/mach-bcm2708/include/mach/power.h | 26 +
40 arch/arm/mach-bcm2708/include/mach/system.h | 38 +
41 arch/arm/mach-bcm2708/include/mach/timex.h | 23 +
42 arch/arm/mach-bcm2708/include/mach/uncompress.h | 85 ++
43 arch/arm/mach-bcm2708/include/mach/vc_mem.h | 36 +
44 arch/arm/mach-bcm2708/include/mach/vcio.h | 141 +++
45 arch/arm/mach-bcm2708/include/mach/vmalloc.h | 20 +
46 arch/arm/mach-bcm2708/power.c | 194 +++
47 arch/arm/mach-bcm2708/vc_mem.c | 462 +++++++
48 arch/arm/mach-bcm2708/vcio.c | 474 +++++++
49 arch/arm/mm/Kconfig | 2 +-
50 arch/arm/mm/proc-v6.S | 15 +-
51 arch/arm/tools/mach-types | 1 +
52 drivers/mmc/host/Kconfig | 21 +
53 drivers/mmc/host/Makefile | 1 +
54 drivers/mmc/host/sdhci-bcm2708.c | 1425 ++++++++++++++++++++++
55 drivers/mmc/host/sdhci.c | 209 +++-
56 drivers/mmc/host/sdhci.h | 37 +
57 include/linux/mmc/sdhci.h | 2 +
58 50 files changed, 7779 insertions(+), 72 deletions(-)
59 create mode 100644 arch/arm/configs/bcmrpi_cutdown_defconfig
60 create mode 100644 arch/arm/configs/bcmrpi_defconfig
61 create mode 100644 arch/arm/configs/bcmrpi_emergency_defconfig
62 create mode 100644 arch/arm/mach-bcm2708/Kconfig
63 create mode 100644 arch/arm/mach-bcm2708/Makefile
64 create mode 100644 arch/arm/mach-bcm2708/Makefile.boot
65 create mode 100644 arch/arm/mach-bcm2708/armctrl.c
66 create mode 100644 arch/arm/mach-bcm2708/armctrl.h
67 create mode 100644 arch/arm/mach-bcm2708/bcm2708.c
68 create mode 100644 arch/arm/mach-bcm2708/bcm2708.h
69 create mode 100644 arch/arm/mach-bcm2708/bcm2708_gpio.c
70 create mode 100644 arch/arm/mach-bcm2708/clock.c
71 create mode 100644 arch/arm/mach-bcm2708/clock.h
72 create mode 100644 arch/arm/mach-bcm2708/dma.c
73 create mode 100644 arch/arm/mach-bcm2708/include/mach/arm_control.h
74 create mode 100644 arch/arm/mach-bcm2708/include/mach/arm_power.h
75 create mode 100644 arch/arm/mach-bcm2708/include/mach/clkdev.h
76 create mode 100644 arch/arm/mach-bcm2708/include/mach/debug-macro.S
77 create mode 100644 arch/arm/mach-bcm2708/include/mach/dma.h
78 create mode 100644 arch/arm/mach-bcm2708/include/mach/entry-macro.S
79 create mode 100644 arch/arm/mach-bcm2708/include/mach/frc.h
80 create mode 100644 arch/arm/mach-bcm2708/include/mach/gpio.h
81 create mode 100644 arch/arm/mach-bcm2708/include/mach/hardware.h
82 create mode 100644 arch/arm/mach-bcm2708/include/mach/io.h
83 create mode 100644 arch/arm/mach-bcm2708/include/mach/irqs.h
84 create mode 100644 arch/arm/mach-bcm2708/include/mach/memory.h
85 create mode 100644 arch/arm/mach-bcm2708/include/mach/platform.h
86 create mode 100644 arch/arm/mach-bcm2708/include/mach/power.h
87 create mode 100644 arch/arm/mach-bcm2708/include/mach/system.h
88 create mode 100644 arch/arm/mach-bcm2708/include/mach/timex.h
89 create mode 100644 arch/arm/mach-bcm2708/include/mach/uncompress.h
90 create mode 100644 arch/arm/mach-bcm2708/include/mach/vc_mem.h
91 create mode 100644 arch/arm/mach-bcm2708/include/mach/vcio.h
92 create mode 100644 arch/arm/mach-bcm2708/include/mach/vmalloc.h
93 create mode 100644 arch/arm/mach-bcm2708/power.c
94 create mode 100644 arch/arm/mach-bcm2708/vc_mem.c
95 create mode 100644 arch/arm/mach-bcm2708/vcio.c
96 create mode 100644 drivers/mmc/host/sdhci-bcm2708.c
97
98 --- a/arch/arm/Kconfig
99 +++ b/arch/arm/Kconfig
100 @@ -361,6 +361,21 @@ config ARCH_AT91
101 This enables support for systems based on Atmel
102 AT91RM9200 and AT91SAM9* processors.
103
104 +config ARCH_BCM2708
105 + bool "Broadcom BCM2708 family"
106 + select CPU_V6
107 + select ARM_AMBA
108 + select HAVE_CLK
109 + select HAVE_SCHED_CLOCK
110 + select NEED_MACH_MEMORY_H
111 + select CLKDEV_LOOKUP
112 + select GENERIC_CLOCKEVENTS
113 + select ARM_ERRATA_411920
114 + select MACH_BCM2708
115 + select VC4
116 + help
117 + This enables support for Broadcom BCM2708 boards.
118 +
119 config ARCH_CLPS711X
120 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
121 select ARCH_REQUIRE_GPIOLIB
122 @@ -1025,6 +1040,7 @@ source "arch/arm/mach-virt/Kconfig"
123 source "arch/arm/mach-vt8500/Kconfig"
124
125 source "arch/arm/mach-w90x900/Kconfig"
126 +source "arch/arm/mach-bcm2708/Kconfig"
127
128 source "arch/arm/mach-zynq/Kconfig"
129
130 --- a/arch/arm/Kconfig.debug
131 +++ b/arch/arm/Kconfig.debug
132 @@ -519,6 +519,14 @@ choice
133 For more details about semihosting, please see
134 chapter 8 of DUI0203I_rvct_developer_guide.pdf from ARM Ltd.
135
136 + config DEBUG_BCM2708_UART0
137 + bool "Broadcom BCM2708 UART0 (PL011)"
138 + depends on MACH_BCM2708
139 + help
140 + Say Y here if you want the debug print routines to direct
141 + their output to UART 0. The port must have been initialised
142 + by the boot-loader before use.
143 +
144 endchoice
145
146 config DEBUG_EXYNOS_UART
147 --- a/arch/arm/Makefile
148 +++ b/arch/arm/Makefile
149 @@ -144,6 +144,7 @@ textofs-$(CONFIG_ARCH_MSM8960) := 0x0020
150 # by CONFIG_* macro name.
151 machine-$(CONFIG_ARCH_AT91) += at91
152 machine-$(CONFIG_ARCH_BCM) += bcm
153 +machine-$(CONFIG_ARCH_BCM2708) += bcm2708
154 machine-$(CONFIG_ARCH_BCM2835) += bcm2835
155 machine-$(CONFIG_ARCH_CLPS711X) += clps711x
156 machine-$(CONFIG_ARCH_CNS3XXX) += cns3xxx
157 --- /dev/null
158 +++ b/arch/arm/configs/bcmrpi_cutdown_defconfig
159 @@ -0,0 +1,474 @@
160 +CONFIG_EXPERIMENTAL=y
161 +# CONFIG_LOCALVERSION_AUTO is not set
162 +CONFIG_SYSVIPC=y
163 +CONFIG_POSIX_MQUEUE=y
164 +CONFIG_IKCONFIG=y
165 +CONFIG_IKCONFIG_PROC=y
166 +# CONFIG_UID16 is not set
167 +# CONFIG_KALLSYMS is not set
168 +CONFIG_EMBEDDED=y
169 +# CONFIG_VM_EVENT_COUNTERS is not set
170 +# CONFIG_COMPAT_BRK is not set
171 +CONFIG_SLAB=y
172 +CONFIG_MODULES=y
173 +CONFIG_MODULE_UNLOAD=y
174 +CONFIG_MODVERSIONS=y
175 +CONFIG_MODULE_SRCVERSION_ALL=y
176 +# CONFIG_BLK_DEV_BSG is not set
177 +CONFIG_ARCH_BCM2708=y
178 +CONFIG_NO_HZ=y
179 +CONFIG_HIGH_RES_TIMERS=y
180 +CONFIG_AEABI=y
181 +CONFIG_ZBOOT_ROM_TEXT=0x0
182 +CONFIG_ZBOOT_ROM_BSS=0x0
183 +CONFIG_CMDLINE="dwc_otg.lpm_enable=0 console=ttyAMA0,115200 kgdboc=ttyAMA0,115200 root=/dev/mmcblk0p2 rootfstype=ext3 rootwait"
184 +CONFIG_CPU_IDLE=y
185 +CONFIG_VFP=y
186 +CONFIG_BINFMT_MISC=m
187 +CONFIG_NET=y
188 +CONFIG_PACKET=y
189 +CONFIG_UNIX=y
190 +CONFIG_XFRM_USER=y
191 +CONFIG_NET_KEY=m
192 +CONFIG_INET=y
193 +CONFIG_IP_MULTICAST=y
194 +CONFIG_IP_PNP=y
195 +CONFIG_IP_PNP_DHCP=y
196 +CONFIG_IP_PNP_RARP=y
197 +CONFIG_SYN_COOKIES=y
198 +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
199 +# CONFIG_INET_XFRM_MODE_TUNNEL is not set
200 +# CONFIG_INET_XFRM_MODE_BEET is not set
201 +# CONFIG_INET_LRO is not set
202 +# CONFIG_INET_DIAG is not set
203 +# CONFIG_IPV6 is not set
204 +CONFIG_NET_PKTGEN=m
205 +CONFIG_IRDA=m
206 +CONFIG_IRLAN=m
207 +CONFIG_IRCOMM=m
208 +CONFIG_IRDA_ULTRA=y
209 +CONFIG_IRDA_CACHE_LAST_LSAP=y
210 +CONFIG_IRDA_FAST_RR=y
211 +CONFIG_IRTTY_SIR=m
212 +CONFIG_KINGSUN_DONGLE=m
213 +CONFIG_KSDAZZLE_DONGLE=m
214 +CONFIG_KS959_DONGLE=m
215 +CONFIG_USB_IRDA=m
216 +CONFIG_SIGMATEL_FIR=m
217 +CONFIG_MCS_FIR=m
218 +CONFIG_BT=m
219 +CONFIG_BT_L2CAP=y
220 +CONFIG_BT_SCO=y
221 +CONFIG_BT_RFCOMM=m
222 +CONFIG_BT_RFCOMM_TTY=y
223 +CONFIG_BT_BNEP=m
224 +CONFIG_BT_BNEP_MC_FILTER=y
225 +CONFIG_BT_BNEP_PROTO_FILTER=y
226 +CONFIG_BT_HIDP=m
227 +CONFIG_BT_HCIBTUSB=m
228 +CONFIG_BT_HCIBCM203X=m
229 +CONFIG_BT_HCIBPA10X=m
230 +CONFIG_BT_HCIBFUSB=m
231 +CONFIG_BT_HCIVHCI=m
232 +CONFIG_BT_MRVL=m
233 +CONFIG_BT_MRVL_SDIO=m
234 +CONFIG_BT_ATH3K=m
235 +CONFIG_CFG80211=m
236 +CONFIG_MAC80211=m
237 +CONFIG_MAC80211_RC_PID=y
238 +CONFIG_MAC80211_MESH=y
239 +CONFIG_WIMAX=m
240 +CONFIG_NET_9P=m
241 +CONFIG_NFC=m
242 +CONFIG_NFC_PN533=m
243 +CONFIG_DEVTMPFS=y
244 +CONFIG_BLK_DEV_LOOP=y
245 +CONFIG_BLK_DEV_CRYPTOLOOP=m
246 +CONFIG_BLK_DEV_NBD=m
247 +CONFIG_BLK_DEV_RAM=y
248 +CONFIG_CDROM_PKTCDVD=m
249 +CONFIG_MISC_DEVICES=y
250 +CONFIG_SCSI=y
251 +# CONFIG_SCSI_PROC_FS is not set
252 +CONFIG_BLK_DEV_SD=m
253 +CONFIG_BLK_DEV_SR=m
254 +CONFIG_SCSI_MULTI_LUN=y
255 +# CONFIG_SCSI_LOWLEVEL is not set
256 +CONFIG_NETDEVICES=y
257 +CONFIG_TUN=m
258 +CONFIG_PHYLIB=m
259 +CONFIG_MDIO_BITBANG=m
260 +CONFIG_NET_ETHERNET=y
261 +# CONFIG_NETDEV_1000 is not set
262 +# CONFIG_NETDEV_10000 is not set
263 +CONFIG_LIBERTAS_THINFIRM=m
264 +CONFIG_LIBERTAS_THINFIRM_USB=m
265 +CONFIG_AT76C50X_USB=m
266 +CONFIG_USB_ZD1201=m
267 +CONFIG_USB_NET_RNDIS_WLAN=m
268 +CONFIG_RTL8187=m
269 +CONFIG_MAC80211_HWSIM=m
270 +CONFIG_ATH_COMMON=m
271 +CONFIG_ATH9K=m
272 +CONFIG_ATH9K_HTC=m
273 +CONFIG_CARL9170=m
274 +CONFIG_B43=m
275 +CONFIG_B43LEGACY=m
276 +CONFIG_HOSTAP=m
277 +CONFIG_IWM=m
278 +CONFIG_LIBERTAS=m
279 +CONFIG_LIBERTAS_USB=m
280 +CONFIG_LIBERTAS_SDIO=m
281 +CONFIG_P54_COMMON=m
282 +CONFIG_P54_USB=m
283 +CONFIG_RT2X00=m
284 +CONFIG_RT2500USB=m
285 +CONFIG_RT73USB=m
286 +CONFIG_RT2800USB=m
287 +CONFIG_RT2800USB_RT53XX=y
288 +CONFIG_RTL8192CU=m
289 +CONFIG_WL1251=m
290 +CONFIG_WL12XX_MENU=m
291 +CONFIG_ZD1211RW=m
292 +CONFIG_MWIFIEX=m
293 +CONFIG_MWIFIEX_SDIO=m
294 +CONFIG_WIMAX_I2400M_USB=m
295 +CONFIG_USB_CATC=m
296 +CONFIG_USB_KAWETH=m
297 +CONFIG_USB_PEGASUS=m
298 +CONFIG_USB_RTL8150=m
299 +CONFIG_USB_USBNET=y
300 +CONFIG_USB_NET_AX8817X=m
301 +CONFIG_USB_NET_CDCETHER=m
302 +CONFIG_USB_NET_CDC_EEM=m
303 +CONFIG_USB_NET_DM9601=m
304 +CONFIG_USB_NET_SMSC75XX=m
305 +CONFIG_USB_NET_SMSC95XX=y
306 +CONFIG_USB_NET_GL620A=m
307 +CONFIG_USB_NET_NET1080=m
308 +CONFIG_USB_NET_PLUSB=m
309 +CONFIG_USB_NET_MCS7830=m
310 +CONFIG_USB_NET_CDC_SUBSET=m
311 +CONFIG_USB_ALI_M5632=y
312 +CONFIG_USB_AN2720=y
313 +CONFIG_USB_KC2190=y
314 +# CONFIG_USB_NET_ZAURUS is not set
315 +CONFIG_USB_NET_CX82310_ETH=m
316 +CONFIG_USB_NET_KALMIA=m
317 +CONFIG_USB_NET_INT51X1=m
318 +CONFIG_USB_IPHETH=m
319 +CONFIG_USB_SIERRA_NET=m
320 +CONFIG_USB_VL600=m
321 +CONFIG_PPP=m
322 +CONFIG_PPP_ASYNC=m
323 +CONFIG_PPP_SYNC_TTY=m
324 +CONFIG_PPP_DEFLATE=m
325 +CONFIG_PPP_BSDCOMP=m
326 +CONFIG_SLIP=m
327 +CONFIG_SLIP_COMPRESSED=y
328 +CONFIG_NETCONSOLE=m
329 +CONFIG_INPUT_POLLDEV=m
330 +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
331 +CONFIG_INPUT_JOYDEV=m
332 +CONFIG_INPUT_EVDEV=m
333 +# CONFIG_INPUT_KEYBOARD is not set
334 +# CONFIG_INPUT_MOUSE is not set
335 +CONFIG_INPUT_MISC=y
336 +CONFIG_INPUT_AD714X=m
337 +CONFIG_INPUT_ATI_REMOTE=m
338 +CONFIG_INPUT_ATI_REMOTE2=m
339 +CONFIG_INPUT_KEYSPAN_REMOTE=m
340 +CONFIG_INPUT_POWERMATE=m
341 +CONFIG_INPUT_YEALINK=m
342 +CONFIG_INPUT_CM109=m
343 +CONFIG_INPUT_UINPUT=m
344 +CONFIG_INPUT_GPIO_ROTARY_ENCODER=m
345 +CONFIG_INPUT_ADXL34X=m
346 +CONFIG_INPUT_CMA3000=m
347 +CONFIG_SERIO=m
348 +CONFIG_SERIO_RAW=m
349 +CONFIG_GAMEPORT=m
350 +CONFIG_GAMEPORT_NS558=m
351 +CONFIG_GAMEPORT_L4=m
352 +CONFIG_VT_HW_CONSOLE_BINDING=y
353 +# CONFIG_LEGACY_PTYS is not set
354 +# CONFIG_DEVKMEM is not set
355 +CONFIG_SERIAL_AMBA_PL011=y
356 +CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
357 +# CONFIG_HW_RANDOM is not set
358 +CONFIG_RAW_DRIVER=y
359 +CONFIG_GPIO_SYSFS=y
360 +# CONFIG_HWMON is not set
361 +CONFIG_WATCHDOG=y
362 +CONFIG_BCM2708_WDT=m
363 +# CONFIG_MFD_SUPPORT is not set
364 +CONFIG_FB=y
365 +CONFIG_FB_BCM2708=y
366 +CONFIG_FRAMEBUFFER_CONSOLE=y
367 +CONFIG_LOGO=y
368 +# CONFIG_LOGO_LINUX_MONO is not set
369 +# CONFIG_LOGO_LINUX_VGA16 is not set
370 +CONFIG_HID_PID=y
371 +CONFIG_USB_HIDDEV=y
372 +CONFIG_HID_A4TECH=m
373 +CONFIG_HID_ACRUX=m
374 +CONFIG_HID_APPLE=m
375 +CONFIG_HID_BELKIN=m
376 +CONFIG_HID_CHERRY=m
377 +CONFIG_HID_CHICONY=m
378 +CONFIG_HID_CYPRESS=m
379 +CONFIG_HID_DRAGONRISE=m
380 +CONFIG_HID_EMS_FF=m
381 +CONFIG_HID_ELECOM=m
382 +CONFIG_HID_EZKEY=m
383 +CONFIG_HID_HOLTEK=m
384 +CONFIG_HID_KEYTOUCH=m
385 +CONFIG_HID_KYE=m
386 +CONFIG_HID_UCLOGIC=m
387 +CONFIG_HID_WALTOP=m
388 +CONFIG_HID_GYRATION=m
389 +CONFIG_HID_TWINHAN=m
390 +CONFIG_HID_KENSINGTON=m
391 +CONFIG_HID_LCPOWER=m
392 +CONFIG_HID_LOGITECH=m
393 +CONFIG_HID_MAGICMOUSE=m
394 +CONFIG_HID_MICROSOFT=m
395 +CONFIG_HID_MONTEREY=m
396 +CONFIG_HID_MULTITOUCH=m
397 +CONFIG_HID_NTRIG=m
398 +CONFIG_HID_ORTEK=m
399 +CONFIG_HID_PANTHERLORD=m
400 +CONFIG_HID_PETALYNX=m
401 +CONFIG_HID_PICOLCD=m
402 +CONFIG_HID_QUANTA=m
403 +CONFIG_HID_ROCCAT=m
404 +CONFIG_HID_SAMSUNG=m
405 +CONFIG_HID_SONY=m
406 +CONFIG_HID_SPEEDLINK=m
407 +CONFIG_HID_SUNPLUS=m
408 +CONFIG_HID_GREENASIA=m
409 +CONFIG_HID_SMARTJOYPLUS=m
410 +CONFIG_HID_TOPSEED=m
411 +CONFIG_HID_THRUSTMASTER=m
412 +CONFIG_HID_WACOM=m
413 +CONFIG_HID_WIIMOTE=m
414 +CONFIG_HID_ZEROPLUS=m
415 +CONFIG_HID_ZYDACRON=m
416 +CONFIG_USB=y
417 +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
418 +CONFIG_USB_MON=m
419 +CONFIG_USB_DWCOTG=y
420 +CONFIG_USB_STORAGE=y
421 +CONFIG_USB_STORAGE_REALTEK=m
422 +CONFIG_USB_STORAGE_DATAFAB=m
423 +CONFIG_USB_STORAGE_FREECOM=m
424 +CONFIG_USB_STORAGE_ISD200=m
425 +CONFIG_USB_STORAGE_USBAT=m
426 +CONFIG_USB_STORAGE_SDDR09=m
427 +CONFIG_USB_STORAGE_SDDR55=m
428 +CONFIG_USB_STORAGE_JUMPSHOT=m
429 +CONFIG_USB_STORAGE_ALAUDA=m
430 +CONFIG_USB_STORAGE_ONETOUCH=m
431 +CONFIG_USB_STORAGE_KARMA=m
432 +CONFIG_USB_STORAGE_CYPRESS_ATACB=m
433 +CONFIG_USB_STORAGE_ENE_UB6250=m
434 +CONFIG_USB_UAS=m
435 +CONFIG_USB_LIBUSUAL=y
436 +CONFIG_USB_MDC800=m
437 +CONFIG_USB_MICROTEK=m
438 +CONFIG_USB_SERIAL=m
439 +CONFIG_USB_SERIAL_GENERIC=y
440 +CONFIG_USB_SERIAL_AIRCABLE=m
441 +CONFIG_USB_SERIAL_ARK3116=m
442 +CONFIG_USB_SERIAL_BELKIN=m
443 +CONFIG_USB_SERIAL_CH341=m
444 +CONFIG_USB_SERIAL_WHITEHEAT=m
445 +CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
446 +CONFIG_USB_SERIAL_CP210X=m
447 +CONFIG_USB_SERIAL_CYPRESS_M8=m
448 +CONFIG_USB_SERIAL_EMPEG=m
449 +CONFIG_USB_SERIAL_FTDI_SIO=m
450 +CONFIG_USB_SERIAL_FUNSOFT=m
451 +CONFIG_USB_SERIAL_VISOR=m
452 +CONFIG_USB_SERIAL_IPAQ=m
453 +CONFIG_USB_SERIAL_IR=m
454 +CONFIG_USB_SERIAL_EDGEPORT=m
455 +CONFIG_USB_SERIAL_EDGEPORT_TI=m
456 +CONFIG_USB_SERIAL_GARMIN=m
457 +CONFIG_USB_SERIAL_IPW=m
458 +CONFIG_USB_SERIAL_IUU=m
459 +CONFIG_USB_SERIAL_KEYSPAN_PDA=m
460 +CONFIG_USB_SERIAL_KEYSPAN=m
461 +CONFIG_USB_SERIAL_KLSI=m
462 +CONFIG_USB_SERIAL_KOBIL_SCT=m
463 +CONFIG_USB_SERIAL_MCT_U232=m
464 +CONFIG_USB_SERIAL_MOS7720=m
465 +CONFIG_USB_SERIAL_MOS7840=m
466 +CONFIG_USB_SERIAL_MOTOROLA=m
467 +CONFIG_USB_SERIAL_NAVMAN=m
468 +CONFIG_USB_SERIAL_PL2303=m
469 +CONFIG_USB_SERIAL_OTI6858=m
470 +CONFIG_USB_SERIAL_QCAUX=m
471 +CONFIG_USB_SERIAL_QUALCOMM=m
472 +CONFIG_USB_SERIAL_SPCP8X5=m
473 +CONFIG_USB_SERIAL_HP4X=m
474 +CONFIG_USB_SERIAL_SAFE=m
475 +CONFIG_USB_SERIAL_SIEMENS_MPI=m
476 +CONFIG_USB_SERIAL_SIERRAWIRELESS=m
477 +CONFIG_USB_SERIAL_SYMBOL=m
478 +CONFIG_USB_SERIAL_TI=m
479 +CONFIG_USB_SERIAL_CYBERJACK=m
480 +CONFIG_USB_SERIAL_XIRCOM=m
481 +CONFIG_USB_SERIAL_OPTION=m
482 +CONFIG_USB_SERIAL_OMNINET=m
483 +CONFIG_USB_SERIAL_OPTICON=m
484 +CONFIG_USB_SERIAL_VIVOPAY_SERIAL=m
485 +CONFIG_USB_SERIAL_ZIO=m
486 +CONFIG_USB_SERIAL_SSU100=m
487 +CONFIG_USB_SERIAL_DEBUG=m
488 +CONFIG_USB_EMI62=m
489 +CONFIG_USB_EMI26=m
490 +CONFIG_USB_ADUTUX=m
491 +CONFIG_USB_SEVSEG=m
492 +CONFIG_USB_RIO500=m
493 +CONFIG_USB_LEGOTOWER=m
494 +CONFIG_USB_LCD=m
495 +CONFIG_USB_LED=m
496 +CONFIG_USB_CYPRESS_CY7C63=m
497 +CONFIG_USB_CYTHERM=m
498 +CONFIG_USB_IDMOUSE=m
499 +CONFIG_USB_FTDI_ELAN=m
500 +CONFIG_USB_APPLEDISPLAY=m
501 +CONFIG_USB_LD=m
502 +CONFIG_USB_TRANCEVIBRATOR=m
503 +CONFIG_USB_IOWARRIOR=m
504 +CONFIG_USB_TEST=m
505 +CONFIG_USB_ISIGHTFW=m
506 +CONFIG_USB_YUREX=m
507 +CONFIG_MMC=y
508 +CONFIG_MMC_SDHCI=y
509 +CONFIG_MMC_SDHCI_PLTFM=y
510 +CONFIG_MMC_SDHCI_BCM2708=y
511 +CONFIG_MMC_SDHCI_BCM2708_DMA=y
512 +CONFIG_LEDS_GPIO=y
513 +CONFIG_LEDS_TRIGGER_TIMER=m
514 +CONFIG_LEDS_TRIGGER_HEARTBEAT=m
515 +CONFIG_LEDS_TRIGGER_DEFAULT_ON=m
516 +CONFIG_UIO=m
517 +CONFIG_UIO_PDRV=m
518 +CONFIG_UIO_PDRV_GENIRQ=m
519 +# CONFIG_IOMMU_SUPPORT is not set
520 +CONFIG_EXT4_FS=y
521 +CONFIG_EXT4_FS_POSIX_ACL=y
522 +CONFIG_EXT4_FS_SECURITY=y
523 +CONFIG_REISERFS_FS=m
524 +CONFIG_REISERFS_FS_XATTR=y
525 +CONFIG_REISERFS_FS_POSIX_ACL=y
526 +CONFIG_REISERFS_FS_SECURITY=y
527 +CONFIG_JFS_FS=m
528 +CONFIG_JFS_POSIX_ACL=y
529 +CONFIG_JFS_SECURITY=y
530 +CONFIG_XFS_FS=m
531 +CONFIG_XFS_QUOTA=y
532 +CONFIG_XFS_POSIX_ACL=y
533 +CONFIG_XFS_RT=y
534 +CONFIG_GFS2_FS=m
535 +CONFIG_OCFS2_FS=m
536 +CONFIG_BTRFS_FS=m
537 +CONFIG_BTRFS_FS_POSIX_ACL=y
538 +CONFIG_NILFS2_FS=m
539 +CONFIG_AUTOFS4_FS=y
540 +CONFIG_FUSE_FS=m
541 +CONFIG_CUSE=m
542 +CONFIG_FSCACHE=y
543 +CONFIG_CACHEFILES=y
544 +CONFIG_ISO9660_FS=m
545 +CONFIG_JOLIET=y
546 +CONFIG_ZISOFS=y
547 +CONFIG_UDF_FS=m
548 +CONFIG_MSDOS_FS=y
549 +CONFIG_VFAT_FS=y
550 +CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
551 +CONFIG_NTFS_FS=m
552 +CONFIG_TMPFS=y
553 +CONFIG_TMPFS_POSIX_ACL=y
554 +CONFIG_CONFIGFS_FS=y
555 +CONFIG_SQUASHFS=m
556 +CONFIG_SQUASHFS_XATTR=y
557 +CONFIG_SQUASHFS_LZO=y
558 +CONFIG_SQUASHFS_XZ=y
559 +CONFIG_NFS_FS=y
560 +CONFIG_NFS_V3=y
561 +CONFIG_NFS_V3_ACL=y
562 +CONFIG_NFS_V4=y
563 +CONFIG_ROOT_NFS=y
564 +CONFIG_NFS_FSCACHE=y
565 +CONFIG_CIFS=m
566 +CONFIG_CIFS_WEAK_PW_HASH=y
567 +CONFIG_CIFS_XATTR=y
568 +CONFIG_CIFS_POSIX=y
569 +CONFIG_9P_FS=m
570 +CONFIG_PARTITION_ADVANCED=y
571 +CONFIG_MAC_PARTITION=y
572 +CONFIG_EFI_PARTITION=y
573 +CONFIG_NLS_DEFAULT="utf8"
574 +CONFIG_NLS_CODEPAGE_437=y
575 +CONFIG_NLS_CODEPAGE_737=m
576 +CONFIG_NLS_CODEPAGE_775=m
577 +CONFIG_NLS_CODEPAGE_850=m
578 +CONFIG_NLS_CODEPAGE_852=m
579 +CONFIG_NLS_CODEPAGE_855=m
580 +CONFIG_NLS_CODEPAGE_857=m
581 +CONFIG_NLS_CODEPAGE_860=m
582 +CONFIG_NLS_CODEPAGE_861=m
583 +CONFIG_NLS_CODEPAGE_862=m
584 +CONFIG_NLS_CODEPAGE_863=m
585 +CONFIG_NLS_CODEPAGE_864=m
586 +CONFIG_NLS_CODEPAGE_865=m
587 +CONFIG_NLS_CODEPAGE_866=m
588 +CONFIG_NLS_CODEPAGE_869=m
589 +CONFIG_NLS_CODEPAGE_936=m
590 +CONFIG_NLS_CODEPAGE_950=m
591 +CONFIG_NLS_CODEPAGE_932=m
592 +CONFIG_NLS_CODEPAGE_949=m
593 +CONFIG_NLS_CODEPAGE_874=m
594 +CONFIG_NLS_ISO8859_8=m
595 +CONFIG_NLS_CODEPAGE_1250=m
596 +CONFIG_NLS_CODEPAGE_1251=m
597 +CONFIG_NLS_ASCII=y
598 +CONFIG_NLS_ISO8859_1=m
599 +CONFIG_NLS_ISO8859_2=m
600 +CONFIG_NLS_ISO8859_3=m
601 +CONFIG_NLS_ISO8859_4=m
602 +CONFIG_NLS_ISO8859_5=m
603 +CONFIG_NLS_ISO8859_6=m
604 +CONFIG_NLS_ISO8859_7=m
605 +CONFIG_NLS_ISO8859_9=m
606 +CONFIG_NLS_ISO8859_13=m
607 +CONFIG_NLS_ISO8859_14=m
608 +CONFIG_NLS_ISO8859_15=m
609 +CONFIG_NLS_KOI8_R=m
610 +CONFIG_NLS_KOI8_U=m
611 +CONFIG_NLS_UTF8=m
612 +# CONFIG_SCHED_DEBUG is not set
613 +# CONFIG_DEBUG_BUGVERBOSE is not set
614 +# CONFIG_FTRACE is not set
615 +# CONFIG_ARM_UNWIND is not set
616 +CONFIG_CRYPTO_AUTHENC=m
617 +CONFIG_CRYPTO_SEQIV=m
618 +CONFIG_CRYPTO_CBC=y
619 +CONFIG_CRYPTO_HMAC=y
620 +CONFIG_CRYPTO_XCBC=m
621 +CONFIG_CRYPTO_MD5=y
622 +CONFIG_CRYPTO_SHA1=y
623 +CONFIG_CRYPTO_SHA256=m
624 +CONFIG_CRYPTO_SHA512=m
625 +CONFIG_CRYPTO_TGR192=m
626 +CONFIG_CRYPTO_WP512=m
627 +CONFIG_CRYPTO_CAST5=m
628 +CONFIG_CRYPTO_DES=y
629 +CONFIG_CRYPTO_DEFLATE=m
630 +# CONFIG_CRYPTO_ANSI_CPRNG is not set
631 +# CONFIG_CRYPTO_HW is not set
632 +CONFIG_CRC_ITU_T=y
633 +CONFIG_LIBCRC32C=y
634 --- /dev/null
635 +++ b/arch/arm/configs/bcmrpi_defconfig
636 @@ -0,0 +1,510 @@
637 +CONFIG_EXPERIMENTAL=y
638 +# CONFIG_LOCALVERSION_AUTO is not set
639 +CONFIG_SYSVIPC=y
640 +CONFIG_POSIX_MQUEUE=y
641 +CONFIG_BSD_PROCESS_ACCT=y
642 +CONFIG_BSD_PROCESS_ACCT_V3=y
643 +CONFIG_FHANDLE=y
644 +CONFIG_AUDIT=y
645 +CONFIG_IKCONFIG=y
646 +CONFIG_IKCONFIG_PROC=y
647 +CONFIG_CGROUP_FREEZER=y
648 +CONFIG_CGROUP_DEVICE=y
649 +CONFIG_CGROUP_CPUACCT=y
650 +CONFIG_RESOURCE_COUNTERS=y
651 +CONFIG_BLK_CGROUP=y
652 +CONFIG_NAMESPACES=y
653 +CONFIG_SCHED_AUTOGROUP=y
654 +CONFIG_EMBEDDED=y
655 +# CONFIG_COMPAT_BRK is not set
656 +CONFIG_SLAB=y
657 +CONFIG_PROFILING=y
658 +CONFIG_OPROFILE=m
659 +CONFIG_KPROBES=y
660 +CONFIG_MODULES=y
661 +CONFIG_MODULE_UNLOAD=y
662 +CONFIG_MODVERSIONS=y
663 +CONFIG_MODULE_SRCVERSION_ALL=y
664 +# CONFIG_BLK_DEV_BSG is not set
665 +CONFIG_BLK_DEV_THROTTLING=y
666 +CONFIG_CFQ_GROUP_IOSCHED=y
667 +CONFIG_ARCH_BCM2708=y
668 +CONFIG_NO_HZ=y
669 +CONFIG_HIGH_RES_TIMERS=y
670 +CONFIG_AEABI=y
671 +CONFIG_SECCOMP=y
672 +CONFIG_CC_STACKPROTECTOR=y
673 +CONFIG_ZBOOT_ROM_TEXT=0x0
674 +CONFIG_ZBOOT_ROM_BSS=0x0
675 +CONFIG_CMDLINE="dwc_otg.lpm_enable=0 console=ttyAMA0,115200 kgdboc=ttyAMA0,115200 root=/dev/mmcblk0p2 rootfstype=ext3 rootwait"
676 +CONFIG_KEXEC=y
677 +CONFIG_CPU_IDLE=y
678 +CONFIG_VFP=y
679 +CONFIG_BINFMT_MISC=m
680 +CONFIG_NET=y
681 +CONFIG_PACKET=y
682 +CONFIG_UNIX=y
683 +CONFIG_XFRM_USER=y
684 +CONFIG_NET_KEY=m
685 +CONFIG_INET=y
686 +CONFIG_IP_MULTICAST=y
687 +CONFIG_IP_PNP=y
688 +CONFIG_IP_PNP_DHCP=y
689 +CONFIG_IP_PNP_RARP=y
690 +CONFIG_SYN_COOKIES=y
691 +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
692 +# CONFIG_INET_XFRM_MODE_TUNNEL is not set
693 +# CONFIG_INET_XFRM_MODE_BEET is not set
694 +# CONFIG_INET_LRO is not set
695 +# CONFIG_INET_DIAG is not set
696 +# CONFIG_IPV6 is not set
697 +CONFIG_NET_PKTGEN=m
698 +CONFIG_IRDA=m
699 +CONFIG_IRLAN=m
700 +CONFIG_IRCOMM=m
701 +CONFIG_IRDA_ULTRA=y
702 +CONFIG_IRDA_CACHE_LAST_LSAP=y
703 +CONFIG_IRDA_FAST_RR=y
704 +CONFIG_IRTTY_SIR=m
705 +CONFIG_KINGSUN_DONGLE=m
706 +CONFIG_KSDAZZLE_DONGLE=m
707 +CONFIG_KS959_DONGLE=m
708 +CONFIG_USB_IRDA=m
709 +CONFIG_SIGMATEL_FIR=m
710 +CONFIG_MCS_FIR=m
711 +CONFIG_BT=m
712 +CONFIG_BT_L2CAP=y
713 +CONFIG_BT_SCO=y
714 +CONFIG_BT_RFCOMM=m
715 +CONFIG_BT_RFCOMM_TTY=y
716 +CONFIG_BT_BNEP=m
717 +CONFIG_BT_BNEP_MC_FILTER=y
718 +CONFIG_BT_BNEP_PROTO_FILTER=y
719 +CONFIG_BT_HIDP=m
720 +CONFIG_BT_HCIBTUSB=m
721 +CONFIG_BT_HCIBCM203X=m
722 +CONFIG_BT_HCIBPA10X=m
723 +CONFIG_BT_HCIBFUSB=m
724 +CONFIG_BT_HCIVHCI=m
725 +CONFIG_BT_MRVL=m
726 +CONFIG_BT_MRVL_SDIO=m
727 +CONFIG_BT_ATH3K=m
728 +CONFIG_CFG80211=m
729 +CONFIG_MAC80211=m
730 +CONFIG_MAC80211_RC_PID=y
731 +CONFIG_MAC80211_MESH=y
732 +CONFIG_WIMAX=m
733 +CONFIG_NET_9P=m
734 +CONFIG_NFC=m
735 +CONFIG_NFC_PN533=m
736 +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
737 +CONFIG_BLK_DEV_LOOP=y
738 +CONFIG_BLK_DEV_CRYPTOLOOP=m
739 +CONFIG_BLK_DEV_NBD=m
740 +CONFIG_BLK_DEV_RAM=y
741 +CONFIG_CDROM_PKTCDVD=m
742 +CONFIG_MISC_DEVICES=y
743 +CONFIG_SCSI=y
744 +# CONFIG_SCSI_PROC_FS is not set
745 +CONFIG_BLK_DEV_SD=m
746 +CONFIG_BLK_DEV_SR=m
747 +CONFIG_SCSI_MULTI_LUN=y
748 +# CONFIG_SCSI_LOWLEVEL is not set
749 +CONFIG_MD=y
750 +CONFIG_NETDEVICES=y
751 +CONFIG_TUN=m
752 +CONFIG_PHYLIB=m
753 +CONFIG_MDIO_BITBANG=m
754 +CONFIG_NET_ETHERNET=y
755 +# CONFIG_NETDEV_1000 is not set
756 +# CONFIG_NETDEV_10000 is not set
757 +CONFIG_LIBERTAS_THINFIRM=m
758 +CONFIG_LIBERTAS_THINFIRM_USB=m
759 +CONFIG_AT76C50X_USB=m
760 +CONFIG_USB_ZD1201=m
761 +CONFIG_USB_NET_RNDIS_WLAN=m
762 +CONFIG_RTL8187=m
763 +CONFIG_MAC80211_HWSIM=m
764 +CONFIG_ATH_COMMON=m
765 +CONFIG_ATH9K=m
766 +CONFIG_ATH9K_HTC=m
767 +CONFIG_CARL9170=m
768 +CONFIG_B43=m
769 +CONFIG_B43LEGACY=m
770 +CONFIG_HOSTAP=m
771 +CONFIG_IWM=m
772 +CONFIG_LIBERTAS=m
773 +CONFIG_LIBERTAS_USB=m
774 +CONFIG_LIBERTAS_SDIO=m
775 +CONFIG_P54_COMMON=m
776 +CONFIG_P54_USB=m
777 +CONFIG_RT2X00=m
778 +CONFIG_RT2500USB=m
779 +CONFIG_RT73USB=m
780 +CONFIG_RT2800USB=m
781 +CONFIG_RT2800USB_RT53XX=y
782 +CONFIG_RTL8192CU=m
783 +CONFIG_WL1251=m
784 +CONFIG_WL12XX_MENU=m
785 +CONFIG_ZD1211RW=m
786 +CONFIG_MWIFIEX=m
787 +CONFIG_MWIFIEX_SDIO=m
788 +CONFIG_WIMAX_I2400M_USB=m
789 +CONFIG_USB_CATC=m
790 +CONFIG_USB_KAWETH=m
791 +CONFIG_USB_PEGASUS=m
792 +CONFIG_USB_RTL8150=m
793 +CONFIG_USB_USBNET=y
794 +CONFIG_USB_NET_AX8817X=m
795 +CONFIG_USB_NET_CDCETHER=m
796 +CONFIG_USB_NET_CDC_EEM=m
797 +CONFIG_USB_NET_DM9601=m
798 +CONFIG_USB_NET_SMSC75XX=m
799 +CONFIG_USB_NET_SMSC95XX=y
800 +CONFIG_USB_NET_GL620A=m
801 +CONFIG_USB_NET_NET1080=m
802 +CONFIG_USB_NET_PLUSB=m
803 +CONFIG_USB_NET_MCS7830=m
804 +CONFIG_USB_NET_CDC_SUBSET=m
805 +CONFIG_USB_ALI_M5632=y
806 +CONFIG_USB_AN2720=y
807 +CONFIG_USB_KC2190=y
808 +# CONFIG_USB_NET_ZAURUS is not set
809 +CONFIG_USB_NET_CX82310_ETH=m
810 +CONFIG_USB_NET_KALMIA=m
811 +CONFIG_USB_NET_INT51X1=m
812 +CONFIG_USB_IPHETH=m
813 +CONFIG_USB_SIERRA_NET=m
814 +CONFIG_USB_VL600=m
815 +CONFIG_PPP=m
816 +CONFIG_PPP_ASYNC=m
817 +CONFIG_PPP_SYNC_TTY=m
818 +CONFIG_PPP_DEFLATE=m
819 +CONFIG_PPP_BSDCOMP=m
820 +CONFIG_SLIP=m
821 +CONFIG_SLIP_COMPRESSED=y
822 +CONFIG_NETCONSOLE=m
823 +CONFIG_INPUT_POLLDEV=m
824 +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
825 +CONFIG_INPUT_JOYDEV=m
826 +CONFIG_INPUT_EVDEV=m
827 +# CONFIG_INPUT_KEYBOARD is not set
828 +# CONFIG_INPUT_MOUSE is not set
829 +CONFIG_INPUT_MISC=y
830 +CONFIG_INPUT_AD714X=m
831 +CONFIG_INPUT_ATI_REMOTE=m
832 +CONFIG_INPUT_ATI_REMOTE2=m
833 +CONFIG_INPUT_KEYSPAN_REMOTE=m
834 +CONFIG_INPUT_POWERMATE=m
835 +CONFIG_INPUT_YEALINK=m
836 +CONFIG_INPUT_CM109=m
837 +CONFIG_INPUT_UINPUT=m
838 +CONFIG_INPUT_GPIO_ROTARY_ENCODER=m
839 +CONFIG_INPUT_ADXL34X=m
840 +CONFIG_INPUT_CMA3000=m
841 +CONFIG_SERIO=m
842 +CONFIG_SERIO_RAW=m
843 +CONFIG_GAMEPORT=m
844 +CONFIG_GAMEPORT_NS558=m
845 +CONFIG_GAMEPORT_L4=m
846 +CONFIG_VT_HW_CONSOLE_BINDING=y
847 +# CONFIG_LEGACY_PTYS is not set
848 +# CONFIG_DEVKMEM is not set
849 +CONFIG_SERIAL_AMBA_PL011=y
850 +CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
851 +# CONFIG_HW_RANDOM is not set
852 +CONFIG_RAW_DRIVER=y
853 +CONFIG_GPIO_SYSFS=y
854 +# CONFIG_HWMON is not set
855 +CONFIG_WATCHDOG=y
856 +CONFIG_BCM2708_WDT=m
857 +# CONFIG_MFD_SUPPORT is not set
858 +CONFIG_FB=y
859 +CONFIG_FB_BCM2708=y
860 +CONFIG_FRAMEBUFFER_CONSOLE=y
861 +CONFIG_LOGO=y
862 +# CONFIG_LOGO_LINUX_MONO is not set
863 +# CONFIG_LOGO_LINUX_VGA16 is not set
864 +CONFIG_HID_PID=y
865 +CONFIG_USB_HIDDEV=y
866 +CONFIG_HID_A4TECH=m
867 +CONFIG_HID_ACRUX=m
868 +CONFIG_HID_APPLE=m
869 +CONFIG_HID_BELKIN=m
870 +CONFIG_HID_CHERRY=m
871 +CONFIG_HID_CHICONY=m
872 +CONFIG_HID_CYPRESS=m
873 +CONFIG_HID_DRAGONRISE=m
874 +CONFIG_HID_EMS_FF=m
875 +CONFIG_HID_ELECOM=m
876 +CONFIG_HID_EZKEY=m
877 +CONFIG_HID_HOLTEK=m
878 +CONFIG_HID_KEYTOUCH=m
879 +CONFIG_HID_KYE=m
880 +CONFIG_HID_UCLOGIC=m
881 +CONFIG_HID_WALTOP=m
882 +CONFIG_HID_GYRATION=m
883 +CONFIG_HID_TWINHAN=m
884 +CONFIG_HID_KENSINGTON=m
885 +CONFIG_HID_LCPOWER=m
886 +CONFIG_HID_LOGITECH=m
887 +CONFIG_HID_MAGICMOUSE=m
888 +CONFIG_HID_MICROSOFT=m
889 +CONFIG_HID_MONTEREY=m
890 +CONFIG_HID_MULTITOUCH=m
891 +CONFIG_HID_NTRIG=m
892 +CONFIG_HID_ORTEK=m
893 +CONFIG_HID_PANTHERLORD=m
894 +CONFIG_HID_PETALYNX=m
895 +CONFIG_HID_PICOLCD=m
896 +CONFIG_HID_QUANTA=m
897 +CONFIG_HID_ROCCAT=m
898 +CONFIG_HID_SAMSUNG=m
899 +CONFIG_HID_SONY=m
900 +CONFIG_HID_SPEEDLINK=m
901 +CONFIG_HID_SUNPLUS=m
902 +CONFIG_HID_GREENASIA=m
903 +CONFIG_HID_SMARTJOYPLUS=m
904 +CONFIG_HID_TOPSEED=m
905 +CONFIG_HID_THRUSTMASTER=m
906 +CONFIG_HID_WACOM=m
907 +CONFIG_HID_WIIMOTE=m
908 +CONFIG_HID_ZEROPLUS=m
909 +CONFIG_HID_ZYDACRON=m
910 +CONFIG_USB=y
911 +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
912 +CONFIG_USB_MON=m
913 +CONFIG_USB_DWCOTG=y
914 +CONFIG_USB_STORAGE=y
915 +CONFIG_USB_STORAGE_REALTEK=m
916 +CONFIG_USB_STORAGE_DATAFAB=m
917 +CONFIG_USB_STORAGE_FREECOM=m
918 +CONFIG_USB_STORAGE_ISD200=m
919 +CONFIG_USB_STORAGE_USBAT=m
920 +CONFIG_USB_STORAGE_SDDR09=m
921 +CONFIG_USB_STORAGE_SDDR55=m
922 +CONFIG_USB_STORAGE_JUMPSHOT=m
923 +CONFIG_USB_STORAGE_ALAUDA=m
924 +CONFIG_USB_STORAGE_ONETOUCH=m
925 +CONFIG_USB_STORAGE_KARMA=m
926 +CONFIG_USB_STORAGE_CYPRESS_ATACB=m
927 +CONFIG_USB_STORAGE_ENE_UB6250=m
928 +CONFIG_USB_UAS=m
929 +CONFIG_USB_LIBUSUAL=y
930 +CONFIG_USB_MDC800=m
931 +CONFIG_USB_MICROTEK=m
932 +CONFIG_USB_SERIAL=m
933 +CONFIG_USB_SERIAL_GENERIC=y
934 +CONFIG_USB_SERIAL_AIRCABLE=m
935 +CONFIG_USB_SERIAL_ARK3116=m
936 +CONFIG_USB_SERIAL_BELKIN=m
937 +CONFIG_USB_SERIAL_CH341=m
938 +CONFIG_USB_SERIAL_WHITEHEAT=m
939 +CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
940 +CONFIG_USB_SERIAL_CP210X=m
941 +CONFIG_USB_SERIAL_CYPRESS_M8=m
942 +CONFIG_USB_SERIAL_EMPEG=m
943 +CONFIG_USB_SERIAL_FTDI_SIO=m
944 +CONFIG_USB_SERIAL_FUNSOFT=m
945 +CONFIG_USB_SERIAL_VISOR=m
946 +CONFIG_USB_SERIAL_IPAQ=m
947 +CONFIG_USB_SERIAL_IR=m
948 +CONFIG_USB_SERIAL_EDGEPORT=m
949 +CONFIG_USB_SERIAL_EDGEPORT_TI=m
950 +CONFIG_USB_SERIAL_GARMIN=m
951 +CONFIG_USB_SERIAL_IPW=m
952 +CONFIG_USB_SERIAL_IUU=m
953 +CONFIG_USB_SERIAL_KEYSPAN_PDA=m
954 +CONFIG_USB_SERIAL_KEYSPAN=m
955 +CONFIG_USB_SERIAL_KLSI=m
956 +CONFIG_USB_SERIAL_KOBIL_SCT=m
957 +CONFIG_USB_SERIAL_MCT_U232=m
958 +CONFIG_USB_SERIAL_MOS7720=m
959 +CONFIG_USB_SERIAL_MOS7840=m
960 +CONFIG_USB_SERIAL_MOTOROLA=m
961 +CONFIG_USB_SERIAL_NAVMAN=m
962 +CONFIG_USB_SERIAL_PL2303=m
963 +CONFIG_USB_SERIAL_OTI6858=m
964 +CONFIG_USB_SERIAL_QCAUX=m
965 +CONFIG_USB_SERIAL_QUALCOMM=m
966 +CONFIG_USB_SERIAL_SPCP8X5=m
967 +CONFIG_USB_SERIAL_HP4X=m
968 +CONFIG_USB_SERIAL_SAFE=m
969 +CONFIG_USB_SERIAL_SIEMENS_MPI=m
970 +CONFIG_USB_SERIAL_SIERRAWIRELESS=m
971 +CONFIG_USB_SERIAL_SYMBOL=m
972 +CONFIG_USB_SERIAL_TI=m
973 +CONFIG_USB_SERIAL_CYBERJACK=m
974 +CONFIG_USB_SERIAL_XIRCOM=m
975 +CONFIG_USB_SERIAL_OPTION=m
976 +CONFIG_USB_SERIAL_OMNINET=m
977 +CONFIG_USB_SERIAL_OPTICON=m
978 +CONFIG_USB_SERIAL_VIVOPAY_SERIAL=m
979 +CONFIG_USB_SERIAL_ZIO=m
980 +CONFIG_USB_SERIAL_SSU100=m
981 +CONFIG_USB_SERIAL_DEBUG=m
982 +CONFIG_USB_EMI62=m
983 +CONFIG_USB_EMI26=m
984 +CONFIG_USB_ADUTUX=m
985 +CONFIG_USB_SEVSEG=m
986 +CONFIG_USB_RIO500=m
987 +CONFIG_USB_LEGOTOWER=m
988 +CONFIG_USB_LCD=m
989 +CONFIG_USB_LED=m
990 +CONFIG_USB_CYPRESS_CY7C63=m
991 +CONFIG_USB_CYTHERM=m
992 +CONFIG_USB_IDMOUSE=m
993 +CONFIG_USB_FTDI_ELAN=m
994 +CONFIG_USB_APPLEDISPLAY=m
995 +CONFIG_USB_LD=m
996 +CONFIG_USB_TRANCEVIBRATOR=m
997 +CONFIG_USB_IOWARRIOR=m
998 +CONFIG_USB_TEST=m
999 +CONFIG_USB_ISIGHTFW=m
1000 +CONFIG_USB_YUREX=m
1001 +CONFIG_MMC=y
1002 +CONFIG_MMC_SDHCI=y
1003 +CONFIG_MMC_SDHCI_PLTFM=y
1004 +CONFIG_MMC_SDHCI_BCM2708=y
1005 +CONFIG_MMC_SDHCI_BCM2708_DMA=y
1006 +CONFIG_LEDS_GPIO=y
1007 +CONFIG_LEDS_TRIGGER_TIMER=m
1008 +CONFIG_LEDS_TRIGGER_HEARTBEAT=m
1009 +CONFIG_LEDS_TRIGGER_DEFAULT_ON=m
1010 +CONFIG_UIO=m
1011 +CONFIG_UIO_PDRV=m
1012 +CONFIG_UIO_PDRV_GENIRQ=m
1013 +# CONFIG_IOMMU_SUPPORT is not set
1014 +CONFIG_EXT4_FS=y
1015 +CONFIG_EXT4_FS_POSIX_ACL=y
1016 +CONFIG_EXT4_FS_SECURITY=y
1017 +CONFIG_REISERFS_FS=m
1018 +CONFIG_REISERFS_FS_XATTR=y
1019 +CONFIG_REISERFS_FS_POSIX_ACL=y
1020 +CONFIG_REISERFS_FS_SECURITY=y
1021 +CONFIG_JFS_FS=m
1022 +CONFIG_JFS_POSIX_ACL=y
1023 +CONFIG_JFS_SECURITY=y
1024 +CONFIG_JFS_STATISTICS=y
1025 +CONFIG_XFS_FS=m
1026 +CONFIG_XFS_QUOTA=y
1027 +CONFIG_XFS_POSIX_ACL=y
1028 +CONFIG_XFS_RT=y
1029 +CONFIG_GFS2_FS=m
1030 +CONFIG_OCFS2_FS=m
1031 +CONFIG_BTRFS_FS=m
1032 +CONFIG_BTRFS_FS_POSIX_ACL=y
1033 +CONFIG_NILFS2_FS=m
1034 +CONFIG_FANOTIFY=y
1035 +CONFIG_AUTOFS4_FS=y
1036 +CONFIG_FUSE_FS=m
1037 +CONFIG_CUSE=m
1038 +CONFIG_FSCACHE=y
1039 +CONFIG_FSCACHE_STATS=y
1040 +CONFIG_FSCACHE_HISTOGRAM=y
1041 +CONFIG_CACHEFILES=y
1042 +CONFIG_ISO9660_FS=m
1043 +CONFIG_JOLIET=y
1044 +CONFIG_ZISOFS=y
1045 +CONFIG_UDF_FS=m
1046 +CONFIG_MSDOS_FS=y
1047 +CONFIG_VFAT_FS=y
1048 +CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
1049 +CONFIG_NTFS_FS=m
1050 +CONFIG_TMPFS=y
1051 +CONFIG_TMPFS_POSIX_ACL=y
1052 +CONFIG_CONFIGFS_FS=y
1053 +CONFIG_SQUASHFS=m
1054 +CONFIG_SQUASHFS_XATTR=y
1055 +CONFIG_SQUASHFS_LZO=y
1056 +CONFIG_SQUASHFS_XZ=y
1057 +CONFIG_NFS_FS=y
1058 +CONFIG_NFS_V3=y
1059 +CONFIG_NFS_V3_ACL=y
1060 +CONFIG_NFS_V4=y
1061 +CONFIG_ROOT_NFS=y
1062 +CONFIG_NFS_FSCACHE=y
1063 +CONFIG_CIFS=m
1064 +CONFIG_CIFS_WEAK_PW_HASH=y
1065 +CONFIG_CIFS_XATTR=y
1066 +CONFIG_CIFS_POSIX=y
1067 +CONFIG_9P_FS=m
1068 +CONFIG_9P_FS_POSIX_ACL=y
1069 +CONFIG_PARTITION_ADVANCED=y
1070 +CONFIG_MAC_PARTITION=y
1071 +CONFIG_EFI_PARTITION=y
1072 +CONFIG_NLS_DEFAULT="utf8"
1073 +CONFIG_NLS_CODEPAGE_437=y
1074 +CONFIG_NLS_CODEPAGE_737=m
1075 +CONFIG_NLS_CODEPAGE_775=m
1076 +CONFIG_NLS_CODEPAGE_850=m
1077 +CONFIG_NLS_CODEPAGE_852=m
1078 +CONFIG_NLS_CODEPAGE_855=m
1079 +CONFIG_NLS_CODEPAGE_857=m
1080 +CONFIG_NLS_CODEPAGE_860=m
1081 +CONFIG_NLS_CODEPAGE_861=m
1082 +CONFIG_NLS_CODEPAGE_862=m
1083 +CONFIG_NLS_CODEPAGE_863=m
1084 +CONFIG_NLS_CODEPAGE_864=m
1085 +CONFIG_NLS_CODEPAGE_865=m
1086 +CONFIG_NLS_CODEPAGE_866=m
1087 +CONFIG_NLS_CODEPAGE_869=m
1088 +CONFIG_NLS_CODEPAGE_936=m
1089 +CONFIG_NLS_CODEPAGE_950=m
1090 +CONFIG_NLS_CODEPAGE_932=m
1091 +CONFIG_NLS_CODEPAGE_949=m
1092 +CONFIG_NLS_CODEPAGE_874=m
1093 +CONFIG_NLS_ISO8859_8=m
1094 +CONFIG_NLS_CODEPAGE_1250=m
1095 +CONFIG_NLS_CODEPAGE_1251=m
1096 +CONFIG_NLS_ASCII=y
1097 +CONFIG_NLS_ISO8859_1=m
1098 +CONFIG_NLS_ISO8859_2=m
1099 +CONFIG_NLS_ISO8859_3=m
1100 +CONFIG_NLS_ISO8859_4=m
1101 +CONFIG_NLS_ISO8859_5=m
1102 +CONFIG_NLS_ISO8859_6=m
1103 +CONFIG_NLS_ISO8859_7=m
1104 +CONFIG_NLS_ISO8859_9=m
1105 +CONFIG_NLS_ISO8859_13=m
1106 +CONFIG_NLS_ISO8859_14=m
1107 +CONFIG_NLS_ISO8859_15=m
1108 +CONFIG_NLS_KOI8_R=m
1109 +CONFIG_NLS_KOI8_U=m
1110 +CONFIG_NLS_UTF8=m
1111 +CONFIG_PRINTK_TIME=y
1112 +CONFIG_DETECT_HUNG_TASK=y
1113 +CONFIG_TIMER_STATS=y
1114 +CONFIG_DEBUG_STACK_USAGE=y
1115 +CONFIG_DEBUG_INFO=y
1116 +CONFIG_DEBUG_MEMORY_INIT=y
1117 +CONFIG_BOOT_PRINTK_DELAY=y
1118 +CONFIG_LATENCYTOP=y
1119 +CONFIG_SYSCTL_SYSCALL_CHECK=y
1120 +CONFIG_IRQSOFF_TRACER=y
1121 +CONFIG_SCHED_TRACER=y
1122 +CONFIG_STACK_TRACER=y
1123 +CONFIG_BLK_DEV_IO_TRACE=y
1124 +CONFIG_FUNCTION_PROFILER=y
1125 +CONFIG_KGDB=y
1126 +CONFIG_KGDB_KDB=y
1127 +CONFIG_KDB_KEYBOARD=y
1128 +CONFIG_STRICT_DEVMEM=y
1129 +CONFIG_CRYPTO_AUTHENC=m
1130 +CONFIG_CRYPTO_SEQIV=m
1131 +CONFIG_CRYPTO_CBC=y
1132 +CONFIG_CRYPTO_HMAC=y
1133 +CONFIG_CRYPTO_XCBC=m
1134 +CONFIG_CRYPTO_MD5=y
1135 +CONFIG_CRYPTO_SHA1=y
1136 +CONFIG_CRYPTO_SHA256=m
1137 +CONFIG_CRYPTO_SHA512=m
1138 +CONFIG_CRYPTO_TGR192=m
1139 +CONFIG_CRYPTO_WP512=m
1140 +CONFIG_CRYPTO_CAST5=m
1141 +CONFIG_CRYPTO_DES=y
1142 +CONFIG_CRYPTO_DEFLATE=m
1143 +# CONFIG_CRYPTO_ANSI_CPRNG is not set
1144 +# CONFIG_CRYPTO_HW is not set
1145 +CONFIG_CRC_ITU_T=y
1146 +CONFIG_LIBCRC32C=y
1147 --- /dev/null
1148 +++ b/arch/arm/configs/bcmrpi_emergency_defconfig
1149 @@ -0,0 +1,532 @@
1150 +CONFIG_EXPERIMENTAL=y
1151 +# CONFIG_LOCALVERSION_AUTO is not set
1152 +CONFIG_SYSVIPC=y
1153 +CONFIG_POSIX_MQUEUE=y
1154 +CONFIG_BSD_PROCESS_ACCT=y
1155 +CONFIG_BSD_PROCESS_ACCT_V3=y
1156 +CONFIG_FHANDLE=y
1157 +CONFIG_AUDIT=y
1158 +CONFIG_IKCONFIG=y
1159 +CONFIG_IKCONFIG_PROC=y
1160 +CONFIG_BLK_DEV_INITRD=y
1161 +CONFIG_INITRAMFS_SOURCE="../target_fs"
1162 +CONFIG_CGROUP_FREEZER=y
1163 +CONFIG_CGROUP_DEVICE=y
1164 +CONFIG_CGROUP_CPUACCT=y
1165 +CONFIG_RESOURCE_COUNTERS=y
1166 +CONFIG_BLK_CGROUP=y
1167 +CONFIG_NAMESPACES=y
1168 +CONFIG_SCHED_AUTOGROUP=y
1169 +CONFIG_EMBEDDED=y
1170 +# CONFIG_COMPAT_BRK is not set
1171 +CONFIG_SLAB=y
1172 +CONFIG_PROFILING=y
1173 +CONFIG_OPROFILE=m
1174 +CONFIG_KPROBES=y
1175 +CONFIG_MODULES=y
1176 +CONFIG_MODULE_UNLOAD=y
1177 +CONFIG_MODVERSIONS=y
1178 +CONFIG_MODULE_SRCVERSION_ALL=y
1179 +# CONFIG_BLK_DEV_BSG is not set
1180 +CONFIG_BLK_DEV_THROTTLING=y
1181 +CONFIG_CFQ_GROUP_IOSCHED=y
1182 +CONFIG_ARCH_BCM2708=y
1183 +CONFIG_NO_HZ=y
1184 +CONFIG_HIGH_RES_TIMERS=y
1185 +CONFIG_AEABI=y
1186 +CONFIG_SECCOMP=y
1187 +CONFIG_CC_STACKPROTECTOR=y
1188 +CONFIG_ZBOOT_ROM_TEXT=0x0
1189 +CONFIG_ZBOOT_ROM_BSS=0x0
1190 +CONFIG_CMDLINE="dwc_otg.lpm_enable=0 console=ttyAMA0,115200 kgdboc=ttyAMA0,115200 root=/dev/mmcblk0p2 rootfstype=ext3 rootwait"
1191 +CONFIG_KEXEC=y
1192 +CONFIG_CPU_IDLE=y
1193 +CONFIG_VFP=y
1194 +CONFIG_BINFMT_MISC=m
1195 +CONFIG_NET=y
1196 +CONFIG_PACKET=y
1197 +CONFIG_UNIX=y
1198 +CONFIG_XFRM_USER=y
1199 +CONFIG_NET_KEY=m
1200 +CONFIG_INET=y
1201 +CONFIG_IP_MULTICAST=y
1202 +CONFIG_IP_PNP=y
1203 +CONFIG_IP_PNP_DHCP=y
1204 +CONFIG_IP_PNP_RARP=y
1205 +CONFIG_SYN_COOKIES=y
1206 +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
1207 +# CONFIG_INET_XFRM_MODE_TUNNEL is not set
1208 +# CONFIG_INET_XFRM_MODE_BEET is not set
1209 +# CONFIG_INET_LRO is not set
1210 +# CONFIG_INET_DIAG is not set
1211 +# CONFIG_IPV6 is not set
1212 +CONFIG_NET_PKTGEN=m
1213 +CONFIG_IRDA=m
1214 +CONFIG_IRLAN=m
1215 +CONFIG_IRCOMM=m
1216 +CONFIG_IRDA_ULTRA=y
1217 +CONFIG_IRDA_CACHE_LAST_LSAP=y
1218 +CONFIG_IRDA_FAST_RR=y
1219 +CONFIG_IRTTY_SIR=m
1220 +CONFIG_KINGSUN_DONGLE=m
1221 +CONFIG_KSDAZZLE_DONGLE=m
1222 +CONFIG_KS959_DONGLE=m
1223 +CONFIG_USB_IRDA=m
1224 +CONFIG_SIGMATEL_FIR=m
1225 +CONFIG_MCS_FIR=m
1226 +CONFIG_BT=m
1227 +CONFIG_BT_L2CAP=y
1228 +CONFIG_BT_SCO=y
1229 +CONFIG_BT_RFCOMM=m
1230 +CONFIG_BT_RFCOMM_TTY=y
1231 +CONFIG_BT_BNEP=m
1232 +CONFIG_BT_BNEP_MC_FILTER=y
1233 +CONFIG_BT_BNEP_PROTO_FILTER=y
1234 +CONFIG_BT_HIDP=m
1235 +CONFIG_BT_HCIBTUSB=m
1236 +CONFIG_BT_HCIBCM203X=m
1237 +CONFIG_BT_HCIBPA10X=m
1238 +CONFIG_BT_HCIBFUSB=m
1239 +CONFIG_BT_HCIVHCI=m
1240 +CONFIG_BT_MRVL=m
1241 +CONFIG_BT_MRVL_SDIO=m
1242 +CONFIG_BT_ATH3K=m
1243 +CONFIG_CFG80211=m
1244 +CONFIG_MAC80211=m
1245 +CONFIG_MAC80211_RC_PID=y
1246 +CONFIG_MAC80211_MESH=y
1247 +CONFIG_WIMAX=m
1248 +CONFIG_NET_9P=m
1249 +CONFIG_NFC=m
1250 +CONFIG_NFC_PN533=m
1251 +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
1252 +CONFIG_BLK_DEV_LOOP=y
1253 +CONFIG_BLK_DEV_CRYPTOLOOP=m
1254 +CONFIG_BLK_DEV_NBD=m
1255 +CONFIG_BLK_DEV_RAM=y
1256 +CONFIG_CDROM_PKTCDVD=m
1257 +CONFIG_MISC_DEVICES=y
1258 +CONFIG_SCSI=y
1259 +# CONFIG_SCSI_PROC_FS is not set
1260 +CONFIG_BLK_DEV_SD=y
1261 +CONFIG_BLK_DEV_SR=m
1262 +CONFIG_SCSI_MULTI_LUN=y
1263 +# CONFIG_SCSI_LOWLEVEL is not set
1264 +CONFIG_MD=y
1265 +CONFIG_NETDEVICES=y
1266 +CONFIG_TUN=m
1267 +CONFIG_PHYLIB=m
1268 +CONFIG_MDIO_BITBANG=m
1269 +CONFIG_NET_ETHERNET=y
1270 +# CONFIG_NETDEV_1000 is not set
1271 +# CONFIG_NETDEV_10000 is not set
1272 +CONFIG_LIBERTAS_THINFIRM=m
1273 +CONFIG_LIBERTAS_THINFIRM_USB=m
1274 +CONFIG_AT76C50X_USB=m
1275 +CONFIG_USB_ZD1201=m
1276 +CONFIG_USB_NET_RNDIS_WLAN=m
1277 +CONFIG_RTL8187=m
1278 +CONFIG_MAC80211_HWSIM=m
1279 +CONFIG_ATH_COMMON=m
1280 +CONFIG_ATH9K=m
1281 +CONFIG_ATH9K_HTC=m
1282 +CONFIG_CARL9170=m
1283 +CONFIG_B43=m
1284 +CONFIG_B43LEGACY=m
1285 +CONFIG_HOSTAP=m
1286 +CONFIG_IWM=m
1287 +CONFIG_LIBERTAS=m
1288 +CONFIG_LIBERTAS_USB=m
1289 +CONFIG_LIBERTAS_SDIO=m
1290 +CONFIG_P54_COMMON=m
1291 +CONFIG_P54_USB=m
1292 +CONFIG_RT2X00=m
1293 +CONFIG_RT2500USB=m
1294 +CONFIG_RT73USB=m
1295 +CONFIG_RT2800USB=m
1296 +CONFIG_RT2800USB_RT53XX=y
1297 +CONFIG_RTL8192CU=m
1298 +CONFIG_WL1251=m
1299 +CONFIG_WL12XX_MENU=m
1300 +CONFIG_ZD1211RW=m
1301 +CONFIG_MWIFIEX=m
1302 +CONFIG_MWIFIEX_SDIO=m
1303 +CONFIG_WIMAX_I2400M_USB=m
1304 +CONFIG_USB_CATC=m
1305 +CONFIG_USB_KAWETH=m
1306 +CONFIG_USB_PEGASUS=m
1307 +CONFIG_USB_RTL8150=m
1308 +CONFIG_USB_USBNET=y
1309 +CONFIG_USB_NET_AX8817X=m
1310 +CONFIG_USB_NET_CDCETHER=m
1311 +CONFIG_USB_NET_CDC_EEM=m
1312 +CONFIG_USB_NET_DM9601=m
1313 +CONFIG_USB_NET_SMSC75XX=m
1314 +CONFIG_USB_NET_SMSC95XX=y
1315 +CONFIG_USB_NET_GL620A=m
1316 +CONFIG_USB_NET_NET1080=m
1317 +CONFIG_USB_NET_PLUSB=m
1318 +CONFIG_USB_NET_MCS7830=m
1319 +CONFIG_USB_NET_CDC_SUBSET=m
1320 +CONFIG_USB_ALI_M5632=y
1321 +CONFIG_USB_AN2720=y
1322 +CONFIG_USB_KC2190=y
1323 +# CONFIG_USB_NET_ZAURUS is not set
1324 +CONFIG_USB_NET_CX82310_ETH=m
1325 +CONFIG_USB_NET_KALMIA=m
1326 +CONFIG_USB_NET_INT51X1=m
1327 +CONFIG_USB_IPHETH=m
1328 +CONFIG_USB_SIERRA_NET=m
1329 +CONFIG_USB_VL600=m
1330 +CONFIG_PPP=m
1331 +CONFIG_PPP_ASYNC=m
1332 +CONFIG_PPP_SYNC_TTY=m
1333 +CONFIG_PPP_DEFLATE=m
1334 +CONFIG_PPP_BSDCOMP=m
1335 +CONFIG_SLIP=m
1336 +CONFIG_SLIP_COMPRESSED=y
1337 +CONFIG_NETCONSOLE=m
1338 +CONFIG_INPUT_POLLDEV=m
1339 +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
1340 +CONFIG_INPUT_JOYDEV=m
1341 +CONFIG_INPUT_EVDEV=m
1342 +# CONFIG_INPUT_KEYBOARD is not set
1343 +# CONFIG_INPUT_MOUSE is not set
1344 +CONFIG_INPUT_MISC=y
1345 +CONFIG_INPUT_AD714X=m
1346 +CONFIG_INPUT_ATI_REMOTE=m
1347 +CONFIG_INPUT_ATI_REMOTE2=m
1348 +CONFIG_INPUT_KEYSPAN_REMOTE=m
1349 +CONFIG_INPUT_POWERMATE=m
1350 +CONFIG_INPUT_YEALINK=m
1351 +CONFIG_INPUT_CM109=m
1352 +CONFIG_INPUT_UINPUT=m
1353 +CONFIG_INPUT_GPIO_ROTARY_ENCODER=m
1354 +CONFIG_INPUT_ADXL34X=m
1355 +CONFIG_INPUT_CMA3000=m
1356 +CONFIG_SERIO=m
1357 +CONFIG_SERIO_RAW=m
1358 +CONFIG_GAMEPORT=m
1359 +CONFIG_GAMEPORT_NS558=m
1360 +CONFIG_GAMEPORT_L4=m
1361 +CONFIG_VT_HW_CONSOLE_BINDING=y
1362 +# CONFIG_LEGACY_PTYS is not set
1363 +# CONFIG_DEVKMEM is not set
1364 +CONFIG_SERIAL_AMBA_PL011=y
1365 +CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
1366 +# CONFIG_HW_RANDOM is not set
1367 +CONFIG_RAW_DRIVER=y
1368 +CONFIG_GPIO_SYSFS=y
1369 +# CONFIG_HWMON is not set
1370 +CONFIG_WATCHDOG=y
1371 +CONFIG_BCM2708_WDT=m
1372 +# CONFIG_MFD_SUPPORT is not set
1373 +CONFIG_FB=y
1374 +CONFIG_FB_BCM2708=y
1375 +CONFIG_FRAMEBUFFER_CONSOLE=y
1376 +CONFIG_LOGO=y
1377 +# CONFIG_LOGO_LINUX_MONO is not set
1378 +# CONFIG_LOGO_LINUX_VGA16 is not set
1379 +CONFIG_SOUND=y
1380 +CONFIG_SND=m
1381 +CONFIG_SND_SEQUENCER=m
1382 +CONFIG_SND_SEQ_DUMMY=m
1383 +CONFIG_SND_MIXER_OSS=m
1384 +CONFIG_SND_PCM_OSS=m
1385 +CONFIG_SND_SEQUENCER_OSS=y
1386 +CONFIG_SND_HRTIMER=m
1387 +CONFIG_SND_DUMMY=m
1388 +CONFIG_SND_ALOOP=m
1389 +CONFIG_SND_VIRMIDI=m
1390 +CONFIG_SND_MTPAV=m
1391 +CONFIG_SND_SERIAL_U16550=m
1392 +CONFIG_SND_MPU401=m
1393 +CONFIG_SND_BCM2835=m
1394 +CONFIG_SND_USB_AUDIO=m
1395 +CONFIG_SND_USB_UA101=m
1396 +CONFIG_SND_USB_CAIAQ=m
1397 +CONFIG_SND_USB_6FIRE=m
1398 +CONFIG_SOUND_PRIME=m
1399 +CONFIG_HID_PID=y
1400 +CONFIG_USB_HIDDEV=y
1401 +CONFIG_HID_A4TECH=m
1402 +CONFIG_HID_ACRUX=m
1403 +CONFIG_HID_APPLE=m
1404 +CONFIG_HID_BELKIN=m
1405 +CONFIG_HID_CHERRY=m
1406 +CONFIG_HID_CHICONY=m
1407 +CONFIG_HID_CYPRESS=m
1408 +CONFIG_HID_DRAGONRISE=m
1409 +CONFIG_HID_EMS_FF=m
1410 +CONFIG_HID_ELECOM=m
1411 +CONFIG_HID_EZKEY=m
1412 +CONFIG_HID_HOLTEK=m
1413 +CONFIG_HID_KEYTOUCH=m
1414 +CONFIG_HID_KYE=m
1415 +CONFIG_HID_UCLOGIC=m
1416 +CONFIG_HID_WALTOP=m
1417 +CONFIG_HID_GYRATION=m
1418 +CONFIG_HID_TWINHAN=m
1419 +CONFIG_HID_KENSINGTON=m
1420 +CONFIG_HID_LCPOWER=m
1421 +CONFIG_HID_LOGITECH=m
1422 +CONFIG_HID_MAGICMOUSE=m
1423 +CONFIG_HID_MICROSOFT=m
1424 +CONFIG_HID_MONTEREY=m
1425 +CONFIG_HID_MULTITOUCH=m
1426 +CONFIG_HID_NTRIG=m
1427 +CONFIG_HID_ORTEK=m
1428 +CONFIG_HID_PANTHERLORD=m
1429 +CONFIG_HID_PETALYNX=m
1430 +CONFIG_HID_PICOLCD=m
1431 +CONFIG_HID_QUANTA=m
1432 +CONFIG_HID_ROCCAT=m
1433 +CONFIG_HID_SAMSUNG=m
1434 +CONFIG_HID_SONY=m
1435 +CONFIG_HID_SPEEDLINK=m
1436 +CONFIG_HID_SUNPLUS=m
1437 +CONFIG_HID_GREENASIA=m
1438 +CONFIG_HID_SMARTJOYPLUS=m
1439 +CONFIG_HID_TOPSEED=m
1440 +CONFIG_HID_THRUSTMASTER=m
1441 +CONFIG_HID_WACOM=m
1442 +CONFIG_HID_WIIMOTE=m
1443 +CONFIG_HID_ZEROPLUS=m
1444 +CONFIG_HID_ZYDACRON=m
1445 +CONFIG_USB=y
1446 +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
1447 +CONFIG_USB_MON=m
1448 +CONFIG_USB_DWCOTG=y
1449 +CONFIG_USB_STORAGE=y
1450 +CONFIG_USB_STORAGE_REALTEK=m
1451 +CONFIG_USB_STORAGE_DATAFAB=m
1452 +CONFIG_USB_STORAGE_FREECOM=m
1453 +CONFIG_USB_STORAGE_ISD200=m
1454 +CONFIG_USB_STORAGE_USBAT=m
1455 +CONFIG_USB_STORAGE_SDDR09=m
1456 +CONFIG_USB_STORAGE_SDDR55=m
1457 +CONFIG_USB_STORAGE_JUMPSHOT=m
1458 +CONFIG_USB_STORAGE_ALAUDA=m
1459 +CONFIG_USB_STORAGE_ONETOUCH=m
1460 +CONFIG_USB_STORAGE_KARMA=m
1461 +CONFIG_USB_STORAGE_CYPRESS_ATACB=m
1462 +CONFIG_USB_STORAGE_ENE_UB6250=m
1463 +CONFIG_USB_UAS=y
1464 +CONFIG_USB_LIBUSUAL=y
1465 +CONFIG_USB_MDC800=m
1466 +CONFIG_USB_MICROTEK=m
1467 +CONFIG_USB_SERIAL=m
1468 +CONFIG_USB_SERIAL_GENERIC=y
1469 +CONFIG_USB_SERIAL_AIRCABLE=m
1470 +CONFIG_USB_SERIAL_ARK3116=m
1471 +CONFIG_USB_SERIAL_BELKIN=m
1472 +CONFIG_USB_SERIAL_CH341=m
1473 +CONFIG_USB_SERIAL_WHITEHEAT=m
1474 +CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
1475 +CONFIG_USB_SERIAL_CP210X=m
1476 +CONFIG_USB_SERIAL_CYPRESS_M8=m
1477 +CONFIG_USB_SERIAL_EMPEG=m
1478 +CONFIG_USB_SERIAL_FTDI_SIO=m
1479 +CONFIG_USB_SERIAL_FUNSOFT=m
1480 +CONFIG_USB_SERIAL_VISOR=m
1481 +CONFIG_USB_SERIAL_IPAQ=m
1482 +CONFIG_USB_SERIAL_IR=m
1483 +CONFIG_USB_SERIAL_EDGEPORT=m
1484 +CONFIG_USB_SERIAL_EDGEPORT_TI=m
1485 +CONFIG_USB_SERIAL_GARMIN=m
1486 +CONFIG_USB_SERIAL_IPW=m
1487 +CONFIG_USB_SERIAL_IUU=m
1488 +CONFIG_USB_SERIAL_KEYSPAN_PDA=m
1489 +CONFIG_USB_SERIAL_KEYSPAN=m
1490 +CONFIG_USB_SERIAL_KLSI=m
1491 +CONFIG_USB_SERIAL_KOBIL_SCT=m
1492 +CONFIG_USB_SERIAL_MCT_U232=m
1493 +CONFIG_USB_SERIAL_MOS7720=m
1494 +CONFIG_USB_SERIAL_MOS7840=m
1495 +CONFIG_USB_SERIAL_MOTOROLA=m
1496 +CONFIG_USB_SERIAL_NAVMAN=m
1497 +CONFIG_USB_SERIAL_PL2303=m
1498 +CONFIG_USB_SERIAL_OTI6858=m
1499 +CONFIG_USB_SERIAL_QCAUX=m
1500 +CONFIG_USB_SERIAL_QUALCOMM=m
1501 +CONFIG_USB_SERIAL_SPCP8X5=m
1502 +CONFIG_USB_SERIAL_HP4X=m
1503 +CONFIG_USB_SERIAL_SAFE=m
1504 +CONFIG_USB_SERIAL_SIEMENS_MPI=m
1505 +CONFIG_USB_SERIAL_SIERRAWIRELESS=m
1506 +CONFIG_USB_SERIAL_SYMBOL=m
1507 +CONFIG_USB_SERIAL_TI=m
1508 +CONFIG_USB_SERIAL_CYBERJACK=m
1509 +CONFIG_USB_SERIAL_XIRCOM=m
1510 +CONFIG_USB_SERIAL_OPTION=m
1511 +CONFIG_USB_SERIAL_OMNINET=m
1512 +CONFIG_USB_SERIAL_OPTICON=m
1513 +CONFIG_USB_SERIAL_VIVOPAY_SERIAL=m
1514 +CONFIG_USB_SERIAL_ZIO=m
1515 +CONFIG_USB_SERIAL_SSU100=m
1516 +CONFIG_USB_SERIAL_DEBUG=m
1517 +CONFIG_USB_EMI62=m
1518 +CONFIG_USB_EMI26=m
1519 +CONFIG_USB_ADUTUX=m
1520 +CONFIG_USB_SEVSEG=m
1521 +CONFIG_USB_RIO500=m
1522 +CONFIG_USB_LEGOTOWER=m
1523 +CONFIG_USB_LCD=m
1524 +CONFIG_USB_LED=m
1525 +CONFIG_USB_CYPRESS_CY7C63=m
1526 +CONFIG_USB_CYTHERM=m
1527 +CONFIG_USB_IDMOUSE=m
1528 +CONFIG_USB_FTDI_ELAN=m
1529 +CONFIG_USB_APPLEDISPLAY=m
1530 +CONFIG_USB_LD=m
1531 +CONFIG_USB_TRANCEVIBRATOR=m
1532 +CONFIG_USB_IOWARRIOR=m
1533 +CONFIG_USB_TEST=m
1534 +CONFIG_USB_ISIGHTFW=m
1535 +CONFIG_USB_YUREX=m
1536 +CONFIG_MMC=y
1537 +CONFIG_MMC_SDHCI=y
1538 +CONFIG_MMC_SDHCI_PLTFM=y
1539 +CONFIG_MMC_SDHCI_BCM2708=y
1540 +CONFIG_MMC_SDHCI_BCM2708_DMA=y
1541 +CONFIG_LEDS_GPIO=y
1542 +CONFIG_LEDS_TRIGGER_TIMER=m
1543 +CONFIG_LEDS_TRIGGER_HEARTBEAT=m
1544 +CONFIG_LEDS_TRIGGER_DEFAULT_ON=m
1545 +CONFIG_UIO=m
1546 +CONFIG_UIO_PDRV=m
1547 +CONFIG_UIO_PDRV_GENIRQ=m
1548 +# CONFIG_IOMMU_SUPPORT is not set
1549 +CONFIG_EXT4_FS=y
1550 +CONFIG_EXT4_FS_POSIX_ACL=y
1551 +CONFIG_EXT4_FS_SECURITY=y
1552 +CONFIG_REISERFS_FS=m
1553 +CONFIG_REISERFS_FS_XATTR=y
1554 +CONFIG_REISERFS_FS_POSIX_ACL=y
1555 +CONFIG_REISERFS_FS_SECURITY=y
1556 +CONFIG_JFS_FS=m
1557 +CONFIG_JFS_POSIX_ACL=y
1558 +CONFIG_JFS_SECURITY=y
1559 +CONFIG_JFS_STATISTICS=y
1560 +CONFIG_XFS_FS=m
1561 +CONFIG_XFS_QUOTA=y
1562 +CONFIG_XFS_POSIX_ACL=y
1563 +CONFIG_XFS_RT=y
1564 +CONFIG_GFS2_FS=m
1565 +CONFIG_OCFS2_FS=m
1566 +CONFIG_BTRFS_FS=m
1567 +CONFIG_BTRFS_FS_POSIX_ACL=y
1568 +CONFIG_NILFS2_FS=m
1569 +CONFIG_FANOTIFY=y
1570 +CONFIG_AUTOFS4_FS=y
1571 +CONFIG_FUSE_FS=m
1572 +CONFIG_CUSE=m
1573 +CONFIG_FSCACHE=y
1574 +CONFIG_FSCACHE_STATS=y
1575 +CONFIG_FSCACHE_HISTOGRAM=y
1576 +CONFIG_CACHEFILES=y
1577 +CONFIG_ISO9660_FS=m
1578 +CONFIG_JOLIET=y
1579 +CONFIG_ZISOFS=y
1580 +CONFIG_UDF_FS=m
1581 +CONFIG_MSDOS_FS=y
1582 +CONFIG_VFAT_FS=y
1583 +CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
1584 +CONFIG_NTFS_FS=m
1585 +CONFIG_TMPFS=y
1586 +CONFIG_TMPFS_POSIX_ACL=y
1587 +CONFIG_CONFIGFS_FS=y
1588 +CONFIG_SQUASHFS=m
1589 +CONFIG_SQUASHFS_XATTR=y
1590 +CONFIG_SQUASHFS_LZO=y
1591 +CONFIG_SQUASHFS_XZ=y
1592 +CONFIG_NFS_FS=y
1593 +CONFIG_NFS_V3=y
1594 +CONFIG_NFS_V3_ACL=y
1595 +CONFIG_NFS_V4=y
1596 +CONFIG_ROOT_NFS=y
1597 +CONFIG_NFS_FSCACHE=y
1598 +CONFIG_CIFS=m
1599 +CONFIG_CIFS_WEAK_PW_HASH=y
1600 +CONFIG_CIFS_XATTR=y
1601 +CONFIG_CIFS_POSIX=y
1602 +CONFIG_9P_FS=m
1603 +CONFIG_9P_FS_POSIX_ACL=y
1604 +CONFIG_PARTITION_ADVANCED=y
1605 +CONFIG_MAC_PARTITION=y
1606 +CONFIG_EFI_PARTITION=y
1607 +CONFIG_NLS_DEFAULT="utf8"
1608 +CONFIG_NLS_CODEPAGE_437=y
1609 +CONFIG_NLS_CODEPAGE_737=m
1610 +CONFIG_NLS_CODEPAGE_775=m
1611 +CONFIG_NLS_CODEPAGE_850=m
1612 +CONFIG_NLS_CODEPAGE_852=m
1613 +CONFIG_NLS_CODEPAGE_855=m
1614 +CONFIG_NLS_CODEPAGE_857=m
1615 +CONFIG_NLS_CODEPAGE_860=m
1616 +CONFIG_NLS_CODEPAGE_861=m
1617 +CONFIG_NLS_CODEPAGE_862=m
1618 +CONFIG_NLS_CODEPAGE_863=m
1619 +CONFIG_NLS_CODEPAGE_864=m
1620 +CONFIG_NLS_CODEPAGE_865=m
1621 +CONFIG_NLS_CODEPAGE_866=m
1622 +CONFIG_NLS_CODEPAGE_869=m
1623 +CONFIG_NLS_CODEPAGE_936=m
1624 +CONFIG_NLS_CODEPAGE_950=m
1625 +CONFIG_NLS_CODEPAGE_932=m
1626 +CONFIG_NLS_CODEPAGE_949=m
1627 +CONFIG_NLS_CODEPAGE_874=m
1628 +CONFIG_NLS_ISO8859_8=m
1629 +CONFIG_NLS_CODEPAGE_1250=m
1630 +CONFIG_NLS_CODEPAGE_1251=m
1631 +CONFIG_NLS_ASCII=y
1632 +CONFIG_NLS_ISO8859_1=m
1633 +CONFIG_NLS_ISO8859_2=m
1634 +CONFIG_NLS_ISO8859_3=m
1635 +CONFIG_NLS_ISO8859_4=m
1636 +CONFIG_NLS_ISO8859_5=m
1637 +CONFIG_NLS_ISO8859_6=m
1638 +CONFIG_NLS_ISO8859_7=m
1639 +CONFIG_NLS_ISO8859_9=m
1640 +CONFIG_NLS_ISO8859_13=m
1641 +CONFIG_NLS_ISO8859_14=m
1642 +CONFIG_NLS_ISO8859_15=m
1643 +CONFIG_NLS_KOI8_R=m
1644 +CONFIG_NLS_KOI8_U=m
1645 +CONFIG_NLS_UTF8=m
1646 +CONFIG_PRINTK_TIME=y
1647 +CONFIG_DETECT_HUNG_TASK=y
1648 +CONFIG_TIMER_STATS=y
1649 +CONFIG_DEBUG_STACK_USAGE=y
1650 +CONFIG_DEBUG_INFO=y
1651 +CONFIG_DEBUG_MEMORY_INIT=y
1652 +CONFIG_BOOT_PRINTK_DELAY=y
1653 +CONFIG_LATENCYTOP=y
1654 +CONFIG_SYSCTL_SYSCALL_CHECK=y
1655 +CONFIG_IRQSOFF_TRACER=y
1656 +CONFIG_SCHED_TRACER=y
1657 +CONFIG_STACK_TRACER=y
1658 +CONFIG_BLK_DEV_IO_TRACE=y
1659 +CONFIG_FUNCTION_PROFILER=y
1660 +CONFIG_KGDB=y
1661 +CONFIG_KGDB_KDB=y
1662 +CONFIG_KDB_KEYBOARD=y
1663 +CONFIG_STRICT_DEVMEM=y
1664 +CONFIG_CRYPTO_AUTHENC=m
1665 +CONFIG_CRYPTO_SEQIV=m
1666 +CONFIG_CRYPTO_CBC=y
1667 +CONFIG_CRYPTO_HMAC=y
1668 +CONFIG_CRYPTO_XCBC=m
1669 +CONFIG_CRYPTO_MD5=y
1670 +CONFIG_CRYPTO_SHA1=y
1671 +CONFIG_CRYPTO_SHA256=m
1672 +CONFIG_CRYPTO_SHA512=m
1673 +CONFIG_CRYPTO_TGR192=m
1674 +CONFIG_CRYPTO_WP512=m
1675 +CONFIG_CRYPTO_CAST5=m
1676 +CONFIG_CRYPTO_DES=y
1677 +CONFIG_CRYPTO_DEFLATE=m
1678 +# CONFIG_CRYPTO_ANSI_CPRNG is not set
1679 +# CONFIG_CRYPTO_HW is not set
1680 +CONFIG_CRC_ITU_T=y
1681 +CONFIG_LIBCRC32C=y
1682 --- a/arch/arm/kernel/process.c
1683 +++ b/arch/arm/kernel/process.c
1684 @@ -174,7 +174,7 @@ void arch_cpu_idle(void)
1685 default_idle();
1686 }
1687
1688 -static char reboot_mode = 'h';
1689 +char reboot_mode = 'h';
1690
1691 int __init reboot_setup(char *str)
1692 {
1693 --- /dev/null
1694 +++ b/arch/arm/mach-bcm2708/Kconfig
1695 @@ -0,0 +1,34 @@
1696 +menu "Broadcom BCM2708 Implementations"
1697 + depends on ARCH_BCM2708
1698 +
1699 +config MACH_BCM2708
1700 + bool "Broadcom BCM2708 Development Platform"
1701 + select NEED_MACH_MEMORY_H
1702 + select NEED_MACH_IO_H
1703 + select CPU_V6
1704 + help
1705 + Include support for the Broadcom(R) BCM2708 platform.
1706 +
1707 +config BCM2708_GPIO
1708 + bool "BCM2708 gpio support"
1709 + depends on MACH_BCM2708
1710 + select ARCH_REQUIRE_GPIOLIB
1711 + default y
1712 + help
1713 + Include support for the Broadcom(R) BCM2708 gpio.
1714 +
1715 +config BCM2708_VCMEM
1716 + bool "Videocore Memory"
1717 + depends on MACH_BCM2708
1718 + default y
1719 + help
1720 + Helper for videocore memory access and total size allocation.
1721 +
1722 +config BCM2708_NOL2CACHE
1723 + bool "Videocore L2 cache disable"
1724 + depends on MACH_BCM2708
1725 + default n
1726 + help
1727 + Do not allow ARM to use GPU's L2 cache. Requires disable_l2cache in config.txt.
1728 +
1729 +endmenu
1730 --- /dev/null
1731 +++ b/arch/arm/mach-bcm2708/Makefile
1732 @@ -0,0 +1,8 @@
1733 +#
1734 +# Makefile for the linux kernel.
1735 +#
1736 +
1737 +obj-$(CONFIG_MACH_BCM2708) += clock.o bcm2708.o armctrl.o vcio.o power.o dma.o
1738 +obj-$(CONFIG_BCM2708_GPIO) += bcm2708_gpio.o
1739 +obj-$(CONFIG_BCM2708_VCMEM) += vc_mem.o
1740 +
1741 --- /dev/null
1742 +++ b/arch/arm/mach-bcm2708/Makefile.boot
1743 @@ -0,0 +1,3 @@
1744 + zreladdr-y := 0x00008000
1745 +params_phys-y := 0x00000100
1746 +initrd_phys-y := 0x00800000
1747 --- /dev/null
1748 +++ b/arch/arm/mach-bcm2708/armctrl.c
1749 @@ -0,0 +1,208 @@
1750 +/*
1751 + * linux/arch/arm/mach-bcm2708/armctrl.c
1752 + *
1753 + * Copyright (C) 2010 Broadcom
1754 + *
1755 + * This program is free software; you can redistribute it and/or modify
1756 + * it under the terms of the GNU General Public License as published by
1757 + * the Free Software Foundation; either version 2 of the License, or
1758 + * (at your option) any later version.
1759 + *
1760 + * This program is distributed in the hope that it will be useful,
1761 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1762 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1763 + * GNU General Public License for more details.
1764 + *
1765 + * You should have received a copy of the GNU General Public License
1766 + * along with this program; if not, write to the Free Software
1767 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
1768 + */
1769 +#include <linux/init.h>
1770 +#include <linux/list.h>
1771 +#include <linux/io.h>
1772 +#include <linux/version.h>
1773 +#include <linux/syscore_ops.h>
1774 +#include <linux/interrupt.h>
1775 +
1776 +#include <asm/mach/irq.h>
1777 +#include <mach/hardware.h>
1778 +#include "armctrl.h"
1779 +
1780 +/* For support of kernels >= 3.0 assume only one VIC for now*/
1781 +static unsigned int remap_irqs[(INTERRUPT_ARASANSDIO + 1) - INTERRUPT_JPEG] = {
1782 + INTERRUPT_VC_JPEG,
1783 + INTERRUPT_VC_USB,
1784 + INTERRUPT_VC_3D,
1785 + INTERRUPT_VC_DMA2,
1786 + INTERRUPT_VC_DMA3,
1787 + INTERRUPT_VC_I2C,
1788 + INTERRUPT_VC_SPI,
1789 + INTERRUPT_VC_I2SPCM,
1790 + INTERRUPT_VC_SDIO,
1791 + INTERRUPT_VC_UART,
1792 + INTERRUPT_VC_ARASANSDIO
1793 +};
1794 +
1795 +static void armctrl_mask_irq(struct irq_data *d)
1796 +{
1797 + static const unsigned int disables[4] = {
1798 + ARM_IRQ_DIBL1,
1799 + ARM_IRQ_DIBL2,
1800 + ARM_IRQ_DIBL3,
1801 + 0
1802 + };
1803 +
1804 + unsigned int data = (unsigned int)irq_get_chip_data(d->irq);
1805 + writel(1 << (data & 0x1f), __io_address(disables[(data >> 5) & 0x3]));
1806 +}
1807 +
1808 +static void armctrl_unmask_irq(struct irq_data *d)
1809 +{
1810 + static const unsigned int enables[4] = {
1811 + ARM_IRQ_ENBL1,
1812 + ARM_IRQ_ENBL2,
1813 + ARM_IRQ_ENBL3,
1814 + 0
1815 + };
1816 +
1817 + unsigned int data = (unsigned int)irq_get_chip_data(d->irq);
1818 + writel(1 << (data & 0x1f), __io_address(enables[(data >> 5) & 0x3]));
1819 +}
1820 +
1821 +#if defined(CONFIG_PM)
1822 +
1823 +/* for kernels 3.xx use the new syscore_ops apis but for older kernels use the sys dev class */
1824 +
1825 +/* Static defines
1826 + * struct armctrl_device - VIC PM device (< 3.xx)
1827 + * @sysdev: The system device which is registered. (< 3.xx)
1828 + * @irq: The IRQ number for the base of the VIC.
1829 + * @base: The register base for the VIC.
1830 + * @resume_sources: A bitmask of interrupts for resume.
1831 + * @resume_irqs: The IRQs enabled for resume.
1832 + * @int_select: Save for VIC_INT_SELECT.
1833 + * @int_enable: Save for VIC_INT_ENABLE.
1834 + * @soft_int: Save for VIC_INT_SOFT.
1835 + * @protect: Save for VIC_PROTECT.
1836 + */
1837 +struct armctrl_info {
1838 + void __iomem *base;
1839 + int irq;
1840 + u32 resume_sources;
1841 + u32 resume_irqs;
1842 + u32 int_select;
1843 + u32 int_enable;
1844 + u32 soft_int;
1845 + u32 protect;
1846 +} armctrl;
1847 +
1848 +static int armctrl_suspend(void)
1849 +{
1850 + return 0;
1851 +}
1852 +
1853 +static void armctrl_resume(void)
1854 +{
1855 + return;
1856 +}
1857 +
1858 +/**
1859 + * armctrl_pm_register - Register a VIC for later power management control
1860 + * @base: The base address of the VIC.
1861 + * @irq: The base IRQ for the VIC.
1862 + * @resume_sources: bitmask of interrupts allowed for resume sources.
1863 + *
1864 + * For older kernels (< 3.xx) do -
1865 + * Register the VIC with the system device tree so that it can be notified
1866 + * of suspend and resume requests and ensure that the correct actions are
1867 + * taken to re-instate the settings on resume.
1868 + */
1869 +static void __init armctrl_pm_register(void __iomem * base, unsigned int irq,
1870 + u32 resume_sources)
1871 +{
1872 + armctrl.base = base;
1873 + armctrl.resume_sources = resume_sources;
1874 + armctrl.irq = irq;
1875 +}
1876 +
1877 +static int armctrl_set_wake(struct irq_data *d, unsigned int on)
1878 +{
1879 + unsigned int off = d->irq & 31;
1880 + u32 bit = 1 << off;
1881 +
1882 + if (!(bit & armctrl.resume_sources))
1883 + return -EINVAL;
1884 +
1885 + if (on)
1886 + armctrl.resume_irqs |= bit;
1887 + else
1888 + armctrl.resume_irqs &= ~bit;
1889 +
1890 + return 0;
1891 +}
1892 +
1893 +#else
1894 +static inline void armctrl_pm_register(void __iomem * base, unsigned int irq,
1895 + u32 arg1)
1896 +{
1897 +}
1898 +
1899 +#define armctrl_suspend NULL
1900 +#define armctrl_resume NULL
1901 +#define armctrl_set_wake NULL
1902 +#endif /* CONFIG_PM */
1903 +
1904 +static struct syscore_ops armctrl_syscore_ops = {
1905 + .suspend = armctrl_suspend,
1906 + .resume = armctrl_resume,
1907 +};
1908 +
1909 +/**
1910 + * armctrl_syscore_init - initicall to register VIC pm functions
1911 + *
1912 + * This is called via late_initcall() to register
1913 + * the resources for the VICs due to the early
1914 + * nature of the VIC's registration.
1915 +*/
1916 +static int __init armctrl_syscore_init(void)
1917 +{
1918 + register_syscore_ops(&armctrl_syscore_ops);
1919 + return 0;
1920 +}
1921 +
1922 +late_initcall(armctrl_syscore_init);
1923 +
1924 +static struct irq_chip armctrl_chip = {
1925 + .name = "ARMCTRL",
1926 + .irq_ack = armctrl_mask_irq,
1927 + .irq_mask = armctrl_mask_irq,
1928 + .irq_unmask = armctrl_unmask_irq,
1929 + .irq_set_wake = armctrl_set_wake,
1930 +};
1931 +
1932 +/**
1933 + * armctrl_init - initialise a vectored interrupt controller
1934 + * @base: iomem base address
1935 + * @irq_start: starting interrupt number, must be muliple of 32
1936 + * @armctrl_sources: bitmask of interrupt sources to allow
1937 + * @resume_sources: bitmask of interrupt sources to allow for resume
1938 + */
1939 +int __init armctrl_init(void __iomem * base, unsigned int irq_start,
1940 + u32 armctrl_sources, u32 resume_sources)
1941 +{
1942 + unsigned int irq;
1943 +
1944 + for (irq = 0; irq < NR_IRQS; irq++) {
1945 + unsigned int data = irq;
1946 + if (irq >= INTERRUPT_JPEG && irq <= INTERRUPT_ARASANSDIO)
1947 + data = remap_irqs[irq - INTERRUPT_JPEG];
1948 +
1949 + irq_set_chip(irq, &armctrl_chip);
1950 + irq_set_chip_data(irq, (void *)data);
1951 + irq_set_handler(irq, handle_level_irq);
1952 + set_irq_flags(irq, IRQF_VALID | IRQF_PROBE | IRQF_DISABLED);
1953 + }
1954 +
1955 + armctrl_pm_register(base, irq_start, resume_sources);
1956 + return 0;
1957 +}
1958 --- /dev/null
1959 +++ b/arch/arm/mach-bcm2708/armctrl.h
1960 @@ -0,0 +1,27 @@
1961 +/*
1962 + * linux/arch/arm/mach-bcm2708/armctrl.h
1963 + *
1964 + * Copyright (C) 2010 Broadcom
1965 + *
1966 + * This program is free software; you can redistribute it and/or modify
1967 + * it under the terms of the GNU General Public License as published by
1968 + * the Free Software Foundation; either version 2 of the License, or
1969 + * (at your option) any later version.
1970 + *
1971 + * This program is distributed in the hope that it will be useful,
1972 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1973 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1974 + * GNU General Public License for more details.
1975 + *
1976 + * You should have received a copy of the GNU General Public License
1977 + * along with this program; if not, write to the Free Software
1978 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
1979 + */
1980 +
1981 +#ifndef __BCM2708_ARMCTRL_H
1982 +#define __BCM2708_ARMCTRL_H
1983 +
1984 +extern int __init armctrl_init(void __iomem * base, unsigned int irq_start,
1985 + u32 armctrl_sources, u32 resume_sources);
1986 +
1987 +#endif
1988 --- /dev/null
1989 +++ b/arch/arm/mach-bcm2708/bcm2708.c
1990 @@ -0,0 +1,695 @@
1991 +/*
1992 + * linux/arch/arm/mach-bcm2708/bcm2708.c
1993 + *
1994 + * Copyright (C) 2010 Broadcom
1995 + *
1996 + * This program is free software; you can redistribute it and/or modify
1997 + * it under the terms of the GNU General Public License as published by
1998 + * the Free Software Foundation; either version 2 of the License, or
1999 + * (at your option) any later version.
2000 + *
2001 + * This program is distributed in the hope that it will be useful,
2002 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2003 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2004 + * GNU General Public License for more details.
2005 + *
2006 + * You should have received a copy of the GNU General Public License
2007 + * along with this program; if not, write to the Free Software
2008 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
2009 + */
2010 +
2011 +#include <linux/init.h>
2012 +#include <linux/device.h>
2013 +#include <linux/dma-mapping.h>
2014 +#include <linux/serial_8250.h>
2015 +#include <linux/platform_device.h>
2016 +#include <linux/syscore_ops.h>
2017 +#include <linux/interrupt.h>
2018 +#include <linux/amba/bus.h>
2019 +#include <linux/amba/clcd.h>
2020 +#include <linux/clockchips.h>
2021 +#include <linux/cnt32_to_63.h>
2022 +#include <linux/io.h>
2023 +#include <linux/module.h>
2024 +
2025 +#include <linux/version.h>
2026 +#include <linux/clkdev.h>
2027 +#include <asm/system.h>
2028 +#include <mach/hardware.h>
2029 +#include <asm/irq.h>
2030 +#include <linux/leds.h>
2031 +#include <asm/mach-types.h>
2032 +#include <asm/sched_clock.h>
2033 +
2034 +#include <asm/mach/arch.h>
2035 +#include <asm/mach/flash.h>
2036 +#include <asm/mach/irq.h>
2037 +#include <asm/mach/time.h>
2038 +#include <asm/mach/map.h>
2039 +
2040 +#include <mach/timex.h>
2041 +#include <mach/dma.h>
2042 +#include <mach/vcio.h>
2043 +#include <mach/system.h>
2044 +
2045 +#include <linux/delay.h>
2046 +
2047 +#include "bcm2708.h"
2048 +#include "armctrl.h"
2049 +#include "clock.h"
2050 +
2051 +/* Effectively we have an IOMMU (ARM<->VideoCore map) that is set up to
2052 + * give us IO access only to 64Mbytes of physical memory (26 bits). We could
2053 + * represent this window by setting our dmamasks to 26 bits but, in fact
2054 + * we're not going to use addresses outside this range (they're not in real
2055 + * memory) so we don't bother.
2056 + *
2057 + * In the future we might include code to use this IOMMU to remap other
2058 + * physical addresses onto VideoCore memory then the use of 32-bits would be
2059 + * more legitimate.
2060 + */
2061 +#define DMA_MASK_BITS_COMMON 32
2062 +
2063 +/* command line parameters */
2064 +static unsigned boardrev, serial;
2065 +static unsigned uart_clock;
2066 +static unsigned reboot_part = 0;
2067 +
2068 +static void __init bcm2708_init_led(void);
2069 +
2070 +void __init bcm2708_init_irq(void)
2071 +{
2072 + armctrl_init(__io_address(ARMCTRL_IC_BASE), 0, 0, 0);
2073 +}
2074 +
2075 +static struct map_desc bcm2708_io_desc[] __initdata = {
2076 + {
2077 + .virtual = IO_ADDRESS(ARMCTRL_BASE),
2078 + .pfn = __phys_to_pfn(ARMCTRL_BASE),
2079 + .length = SZ_4K,
2080 + .type = MT_DEVICE},
2081 + {
2082 + .virtual = IO_ADDRESS(UART0_BASE),
2083 + .pfn = __phys_to_pfn(UART0_BASE),
2084 + .length = SZ_4K,
2085 + .type = MT_DEVICE},
2086 + {
2087 + .virtual = IO_ADDRESS(UART1_BASE),
2088 + .pfn = __phys_to_pfn(UART1_BASE),
2089 + .length = SZ_4K,
2090 + .type = MT_DEVICE},
2091 + {
2092 + .virtual = IO_ADDRESS(DMA_BASE),
2093 + .pfn = __phys_to_pfn(DMA_BASE),
2094 + .length = SZ_4K,
2095 + .type = MT_DEVICE},
2096 + {
2097 + .virtual = IO_ADDRESS(MCORE_BASE),
2098 + .pfn = __phys_to_pfn(MCORE_BASE),
2099 + .length = SZ_4K,
2100 + .type = MT_DEVICE},
2101 + {
2102 + .virtual = IO_ADDRESS(ST_BASE),
2103 + .pfn = __phys_to_pfn(ST_BASE),
2104 + .length = SZ_4K,
2105 + .type = MT_DEVICE},
2106 + {
2107 + .virtual = IO_ADDRESS(USB_BASE),
2108 + .pfn = __phys_to_pfn(USB_BASE),
2109 + .length = SZ_128K,
2110 + .type = MT_DEVICE},
2111 + {
2112 + .virtual = IO_ADDRESS(PM_BASE),
2113 + .pfn = __phys_to_pfn(PM_BASE),
2114 + .length = SZ_4K,
2115 + .type = MT_DEVICE},
2116 + {
2117 + .virtual = IO_ADDRESS(GPIO_BASE),
2118 + .pfn = __phys_to_pfn(GPIO_BASE),
2119 + .length = SZ_4K,
2120 + .type = MT_DEVICE}
2121 +};
2122 +
2123 +void __init bcm2708_map_io(void)
2124 +{
2125 + iotable_init(bcm2708_io_desc, ARRAY_SIZE(bcm2708_io_desc));
2126 +}
2127 +
2128 +/* The STC is a free running counter that increments at the rate of 1MHz */
2129 +#define STC_FREQ_HZ 1000000
2130 +
2131 +static inline uint32_t timer_read(void)
2132 +{
2133 + /* STC: a free running counter that increments at the rate of 1MHz */
2134 + return readl(__io_address(ST_BASE + 0x04));
2135 +}
2136 +
2137 +static unsigned long bcm2708_read_current_timer(void)
2138 +{
2139 + return timer_read();
2140 +}
2141 +
2142 +static u32 notrace bcm2708_read_sched_clock(void)
2143 +{
2144 + return timer_read();
2145 +}
2146 +
2147 +static cycle_t clksrc_read(struct clocksource *cs)
2148 +{
2149 + return timer_read();
2150 +}
2151 +
2152 +static struct clocksource clocksource_stc = {
2153 + .name = "stc",
2154 + .rating = 300,
2155 + .read = clksrc_read,
2156 + .mask = CLOCKSOURCE_MASK(32),
2157 + .flags = CLOCK_SOURCE_IS_CONTINUOUS,
2158 +};
2159 +
2160 +unsigned long frc_clock_ticks32(void)
2161 +{
2162 + return timer_read();
2163 +}
2164 +
2165 +static void __init bcm2708_clocksource_init(void)
2166 +{
2167 + if (clocksource_register_hz(&clocksource_stc, STC_FREQ_HZ)) {
2168 + printk(KERN_ERR "timer: failed to initialize clock "
2169 + "source %s\n", clocksource_stc.name);
2170 + }
2171 +}
2172 +
2173 +
2174 +/*
2175 + * These are fixed clocks.
2176 + */
2177 +static struct clk ref24_clk = {
2178 + .rate = UART0_CLOCK, /* The UART is clocked at 3MHz via APB_CLK */
2179 +};
2180 +
2181 +static struct clk osc_clk = {
2182 +#ifdef CONFIG_ARCH_BCM2708_CHIPIT
2183 + .rate = 27000000,
2184 +#else
2185 + .rate = 500000000, /* ARM clock is set from the VideoCore booter */
2186 +#endif
2187 +};
2188 +
2189 +/* warning - the USB needs a clock > 34MHz */
2190 +
2191 +#ifdef CONFIG_MMC_BCM2708
2192 +static struct clk sdhost_clk = {
2193 +#ifdef CONFIG_ARCH_BCM2708_CHIPIT
2194 + .rate = 4000000, /* 4MHz */
2195 +#else
2196 + .rate = 250000000, /* 250MHz */
2197 +#endif
2198 +};
2199 +#endif
2200 +
2201 +static struct clk_lookup lookups[] = {
2202 + { /* UART0 */
2203 + .dev_id = "dev:f1",
2204 + .clk = &ref24_clk,
2205 + },
2206 + { /* USB */
2207 + .dev_id = "bcm2708_usb",
2208 + .clk = &osc_clk,
2209 + }
2210 +};
2211 +
2212 +#define UART0_IRQ { IRQ_UART, 0 /*NO_IRQ*/ }
2213 +#define UART0_DMA { 15, 14 }
2214 +
2215 +AMBA_DEVICE(uart0, "dev:f1", UART0, NULL);
2216 +
2217 +static struct amba_device *amba_devs[] __initdata = {
2218 + &uart0_device,
2219 +};
2220 +
2221 +static struct resource bcm2708_dmaman_resources[] = {
2222 + {
2223 + .start = DMA_BASE,
2224 + .end = DMA_BASE + SZ_4K - 1,
2225 + .flags = IORESOURCE_MEM,
2226 + }
2227 +};
2228 +
2229 +static struct platform_device bcm2708_dmaman_device = {
2230 + .name = BCM_DMAMAN_DRIVER_NAME,
2231 + .id = 0, /* first bcm2708_dma */
2232 + .resource = bcm2708_dmaman_resources,
2233 + .num_resources = ARRAY_SIZE(bcm2708_dmaman_resources),
2234 +};
2235 +
2236 +static u64 fb_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON);
2237 +
2238 +static struct platform_device bcm2708_fb_device = {
2239 + .name = "bcm2708_fb",
2240 + .id = -1, /* only one bcm2708_fb */
2241 + .resource = NULL,
2242 + .num_resources = 0,
2243 + .dev = {
2244 + .dma_mask = &fb_dmamask,
2245 + .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON),
2246 + },
2247 +};
2248 +
2249 +static struct plat_serial8250_port bcm2708_uart1_platform_data[] = {
2250 + {
2251 + .mapbase = UART1_BASE + 0x40,
2252 + .irq = IRQ_AUX,
2253 + .uartclk = 125000000,
2254 + .regshift = 2,
2255 + .iotype = UPIO_MEM,
2256 + .flags = UPF_FIXED_TYPE | UPF_IOREMAP | UPF_SKIP_TEST,
2257 + .type = PORT_8250,
2258 + },
2259 + {},
2260 +};
2261 +
2262 +static struct platform_device bcm2708_uart1_device = {
2263 + .name = "serial8250",
2264 + .id = PLAT8250_DEV_PLATFORM,
2265 + .dev = {
2266 + .platform_data = bcm2708_uart1_platform_data,
2267 + },
2268 +};
2269 +
2270 +static struct resource bcm2708_usb_resources[] = {
2271 + [0] = {
2272 + .start = USB_BASE,
2273 + .end = USB_BASE + SZ_128K - 1,
2274 + .flags = IORESOURCE_MEM,
2275 + },
2276 + [1] = {
2277 + .start = IRQ_USB,
2278 + .end = IRQ_USB,
2279 + .flags = IORESOURCE_IRQ,
2280 + },
2281 +};
2282 +
2283 +static u64 usb_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON);
2284 +
2285 +static struct platform_device bcm2708_usb_device = {
2286 + .name = "bcm2708_usb",
2287 + .id = -1, /* only one bcm2708_usb */
2288 + .resource = bcm2708_usb_resources,
2289 + .num_resources = ARRAY_SIZE(bcm2708_usb_resources),
2290 + .dev = {
2291 + .dma_mask = &usb_dmamask,
2292 + .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON),
2293 + },
2294 +};
2295 +
2296 +static struct resource bcm2708_vcio_resources[] = {
2297 + [0] = { /* mailbox/semaphore/doorbell access */
2298 + .start = MCORE_BASE,
2299 + .end = MCORE_BASE + SZ_4K - 1,
2300 + .flags = IORESOURCE_MEM,
2301 + },
2302 +};
2303 +
2304 +static u64 vcio_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON);
2305 +
2306 +static struct platform_device bcm2708_vcio_device = {
2307 + .name = BCM_VCIO_DRIVER_NAME,
2308 + .id = -1, /* only one VideoCore I/O area */
2309 + .resource = bcm2708_vcio_resources,
2310 + .num_resources = ARRAY_SIZE(bcm2708_vcio_resources),
2311 + .dev = {
2312 + .dma_mask = &vcio_dmamask,
2313 + .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON),
2314 + },
2315 +};
2316 +
2317 +#ifdef CONFIG_BCM2708_GPIO
2318 +#define BCM_GPIO_DRIVER_NAME "bcm2708_gpio"
2319 +
2320 +static struct resource bcm2708_gpio_resources[] = {
2321 + [0] = { /* general purpose I/O */
2322 + .start = GPIO_BASE,
2323 + .end = GPIO_BASE + SZ_4K - 1,
2324 + .flags = IORESOURCE_MEM,
2325 + },
2326 +};
2327 +
2328 +static u64 gpio_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON);
2329 +
2330 +static struct platform_device bcm2708_gpio_device = {
2331 + .name = BCM_GPIO_DRIVER_NAME,
2332 + .id = -1, /* only one VideoCore I/O area */
2333 + .resource = bcm2708_gpio_resources,
2334 + .num_resources = ARRAY_SIZE(bcm2708_gpio_resources),
2335 + .dev = {
2336 + .dma_mask = &gpio_dmamask,
2337 + .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON),
2338 + },
2339 +};
2340 +#endif
2341 +
2342 +static struct resource bcm2708_systemtimer_resources[] = {
2343 + [0] = { /* system timer access */
2344 + .start = ST_BASE,
2345 + .end = ST_BASE + SZ_4K - 1,
2346 + .flags = IORESOURCE_MEM,
2347 + },
2348 + {
2349 + .start = IRQ_TIMER3,
2350 + .end = IRQ_TIMER3,
2351 + .flags = IORESOURCE_IRQ,
2352 + }
2353 +
2354 +};
2355 +
2356 +static u64 systemtimer_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON);
2357 +
2358 +static struct platform_device bcm2708_systemtimer_device = {
2359 + .name = "bcm2708_systemtimer",
2360 + .id = -1, /* only one VideoCore I/O area */
2361 + .resource = bcm2708_systemtimer_resources,
2362 + .num_resources = ARRAY_SIZE(bcm2708_systemtimer_resources),
2363 + .dev = {
2364 + .dma_mask = &systemtimer_dmamask,
2365 + .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON),
2366 + },
2367 +};
2368 +
2369 +#ifdef CONFIG_MMC_SDHCI_BCM2708 /* Arasan emmc SD */
2370 +static struct resource bcm2708_emmc_resources[] = {
2371 + [0] = {
2372 + .start = EMMC_BASE,
2373 + .end = EMMC_BASE + SZ_256 - 1, /* we only need this area */
2374 + /* the memory map actually makes SZ_4K available */
2375 + .flags = IORESOURCE_MEM,
2376 + },
2377 + [1] = {
2378 + .start = IRQ_ARASANSDIO,
2379 + .end = IRQ_ARASANSDIO,
2380 + .flags = IORESOURCE_IRQ,
2381 + },
2382 +};
2383 +
2384 +static u64 bcm2708_emmc_dmamask = 0xffffffffUL;
2385 +
2386 +struct platform_device bcm2708_emmc_device = {
2387 + .name = "bcm2708_sdhci",
2388 + .id = 0,
2389 + .num_resources = ARRAY_SIZE(bcm2708_emmc_resources),
2390 + .resource = bcm2708_emmc_resources,
2391 + .dev = {
2392 + .dma_mask = &bcm2708_emmc_dmamask,
2393 + .coherent_dma_mask = 0xffffffffUL},
2394 +};
2395 +#endif /* CONFIG_MMC_SDHCI_BCM2708 */
2396 +
2397 +static struct resource bcm2708_powerman_resources[] = {
2398 + [0] = {
2399 + .start = PM_BASE,
2400 + .end = PM_BASE + SZ_256 - 1,
2401 + .flags = IORESOURCE_MEM,
2402 + },
2403 +};
2404 +
2405 +static u64 powerman_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON);
2406 +
2407 +struct platform_device bcm2708_powerman_device = {
2408 + .name = "bcm2708_powerman",
2409 + .id = 0,
2410 + .num_resources = ARRAY_SIZE(bcm2708_powerman_resources),
2411 + .resource = bcm2708_powerman_resources,
2412 + .dev = {
2413 + .dma_mask = &powerman_dmamask,
2414 + .coherent_dma_mask = 0xffffffffUL},
2415 +};
2416 +
2417 +int __init bcm_register_device(struct platform_device *pdev)
2418 +{
2419 + int ret;
2420 +
2421 + ret = platform_device_register(pdev);
2422 + if (ret)
2423 + pr_debug("Unable to register platform device '%s': %d\n",
2424 + pdev->name, ret);
2425 +
2426 + return ret;
2427 +}
2428 +
2429 +int calc_rsts(int partition)
2430 +{
2431 + return PM_PASSWORD |
2432 + ((partition & (1 << 0)) << 0) |
2433 + ((partition & (1 << 1)) << 1) |
2434 + ((partition & (1 << 2)) << 2) |
2435 + ((partition & (1 << 3)) << 3) |
2436 + ((partition & (1 << 4)) << 4) |
2437 + ((partition & (1 << 5)) << 5);
2438 +}
2439 +
2440 +static void bcm2708_restart(char mode, const char *cmd)
2441 +{
2442 + uint32_t pm_rstc, pm_wdog;
2443 + uint32_t timeout = 10;
2444 + uint32_t pm_rsts = 0;
2445 +
2446 + if(mode == 'q')
2447 + {
2448 + // NOOBS < 1.3 booting with reboot=q
2449 + pm_rsts = readl(__io_address(PM_RSTS));
2450 + pm_rsts = PM_PASSWORD | pm_rsts | PM_RSTS_HADWRQ_SET;
2451 + }
2452 + else if(mode == 'p')
2453 + {
2454 + // NOOBS < 1.3 halting
2455 + pm_rsts = readl(__io_address(PM_RSTS));
2456 + pm_rsts = PM_PASSWORD | pm_rsts | PM_RSTS_HADWRH_SET;
2457 + }
2458 + else
2459 + {
2460 + pm_rsts = calc_rsts(reboot_part);
2461 + }
2462 +
2463 + writel(pm_rsts, __io_address(PM_RSTS));
2464 +
2465 + /* Setup watchdog for reset */
2466 + pm_rstc = readl(__io_address(PM_RSTC));
2467 +
2468 + pm_wdog = PM_PASSWORD | (timeout & PM_WDOG_TIME_SET); // watchdog timer = timer clock / 16; need password (31:16) + value (11:0)
2469 + pm_rstc = PM_PASSWORD | (pm_rstc & PM_RSTC_WRCFG_CLR) | PM_RSTC_WRCFG_FULL_RESET;
2470 +
2471 + writel(pm_wdog, __io_address(PM_WDOG));
2472 + writel(pm_rstc, __io_address(PM_RSTC));
2473 +}
2474 +
2475 +/* We can't really power off, but if we do the normal reset scheme, and indicate to bootcode.bin not to reboot, then most of the chip will be powered off */
2476 +static void bcm2708_power_off(void)
2477 +{
2478 + extern char reboot_mode;
2479 +
2480 + if(reboot_mode == 'q')
2481 + {
2482 + // NOOBS < v1.3
2483 + bcm2708_restart('p', "");
2484 + }
2485 + else
2486 + {
2487 + /* partition 63 is special code for HALT the bootloader knows not to boot*/
2488 + reboot_part = 63;
2489 + /* continue with normal reset mechanism */
2490 + bcm2708_restart(0, "");
2491 + }
2492 +}
2493 +
2494 +void __init bcm2708_init(void)
2495 +{
2496 + int i;
2497 +
2498 + printk("bcm2708.uart_clock = %d\n", uart_clock);
2499 + pm_power_off = bcm2708_power_off;
2500 +
2501 + if (uart_clock)
2502 + lookups[0].clk->rate = uart_clock;
2503 +
2504 + for (i = 0; i < ARRAY_SIZE(lookups); i++)
2505 + clkdev_add(&lookups[i]);
2506 +
2507 + bcm_register_device(&bcm2708_dmaman_device);
2508 + bcm_register_device(&bcm2708_vcio_device);
2509 +#ifdef CONFIG_BCM2708_GPIO
2510 + bcm_register_device(&bcm2708_gpio_device);
2511 +#endif
2512 + bcm_register_device(&bcm2708_systemtimer_device);
2513 + bcm_register_device(&bcm2708_fb_device);
2514 + bcm_register_device(&bcm2708_usb_device);
2515 + bcm_register_device(&bcm2708_uart1_device);
2516 + bcm_register_device(&bcm2708_powerman_device);
2517 +
2518 +#ifdef CONFIG_MMC_SDHCI_BCM2708
2519 + bcm_register_device(&bcm2708_emmc_device);
2520 +#endif
2521 + bcm2708_init_led();
2522 +
2523 + for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
2524 + struct amba_device *d = amba_devs[i];
2525 + amba_device_register(d, &iomem_resource);
2526 + }
2527 + system_rev = boardrev;
2528 + system_serial_low = serial;
2529 +}
2530 +
2531 +static void timer_set_mode(enum clock_event_mode mode,
2532 + struct clock_event_device *clk)
2533 +{
2534 + switch (mode) {
2535 + case CLOCK_EVT_MODE_ONESHOT: /* Leave the timer disabled, .set_next_event will enable it */
2536 + case CLOCK_EVT_MODE_SHUTDOWN:
2537 + break;
2538 + case CLOCK_EVT_MODE_PERIODIC:
2539 +
2540 + case CLOCK_EVT_MODE_UNUSED:
2541 + case CLOCK_EVT_MODE_RESUME:
2542 +
2543 + default:
2544 + printk(KERN_ERR "timer_set_mode: unhandled mode:%d\n",
2545 + (int)mode);
2546 + break;
2547 + }
2548 +
2549 +}
2550 +
2551 +static int timer_set_next_event(unsigned long cycles,
2552 + struct clock_event_device *unused)
2553 +{
2554 + unsigned long stc;
2555 +
2556 + stc = readl(__io_address(ST_BASE + 0x04));
2557 + writel(stc + cycles, __io_address(ST_BASE + 0x18)); /* stc3 */
2558 + return 0;
2559 +}
2560 +
2561 +static struct clock_event_device timer0_clockevent = {
2562 + .name = "timer0",
2563 + .shift = 32,
2564 + .features = CLOCK_EVT_FEAT_ONESHOT,
2565 + .set_mode = timer_set_mode,
2566 + .set_next_event = timer_set_next_event,
2567 +};
2568 +
2569 +/*
2570 + * IRQ handler for the timer
2571 + */
2572 +static irqreturn_t bcm2708_timer_interrupt(int irq, void *dev_id)
2573 +{
2574 + struct clock_event_device *evt = &timer0_clockevent;
2575 +
2576 + writel(1 << 3, __io_address(ST_BASE + 0x00)); /* stcs clear timer int */
2577 +
2578 + evt->event_handler(evt);
2579 +
2580 + return IRQ_HANDLED;
2581 +}
2582 +
2583 +static struct irqaction bcm2708_timer_irq = {
2584 + .name = "BCM2708 Timer Tick",
2585 + .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
2586 + .handler = bcm2708_timer_interrupt,
2587 +};
2588 +
2589 +/*
2590 + * Set up timer interrupt, and return the current time in seconds.
2591 + */
2592 +
2593 +static struct delay_timer bcm2708_delay_timer = {
2594 + .read_current_timer = bcm2708_read_current_timer,
2595 + .freq = STC_FREQ_HZ,
2596 +};
2597 +
2598 +static void __init bcm2708_timer_init(void)
2599 +{
2600 + /* init high res timer */
2601 + bcm2708_clocksource_init();
2602 +
2603 + /*
2604 + * Initialise to a known state (all timers off)
2605 + */
2606 + writel(0, __io_address(ARM_T_CONTROL));
2607 + /*
2608 + * Make irqs happen for the system timer
2609 + */
2610 + setup_irq(IRQ_TIMER3, &bcm2708_timer_irq);
2611 +
2612 + setup_sched_clock(bcm2708_read_sched_clock, 32, STC_FREQ_HZ);
2613 +
2614 + timer0_clockevent.mult =
2615 + div_sc(STC_FREQ_HZ, NSEC_PER_SEC, timer0_clockevent.shift);
2616 + timer0_clockevent.max_delta_ns =
2617 + clockevent_delta2ns(0xffffffff, &timer0_clockevent);
2618 + timer0_clockevent.min_delta_ns =
2619 + clockevent_delta2ns(0xf, &timer0_clockevent);
2620 +
2621 + timer0_clockevent.cpumask = cpumask_of(0);
2622 + clockevents_register_device(&timer0_clockevent);
2623 +
2624 + register_current_timer_delay(&bcm2708_delay_timer);
2625 +}
2626 +
2627 +#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
2628 +#include <linux/leds.h>
2629 +
2630 +static struct gpio_led bcm2708_leds[] = {
2631 + [0] = {
2632 + .gpio = 16,
2633 + .name = "led0",
2634 + .default_trigger = "mmc0",
2635 + .active_low = 1,
2636 + },
2637 +};
2638 +
2639 +static struct gpio_led_platform_data bcm2708_led_pdata = {
2640 + .num_leds = ARRAY_SIZE(bcm2708_leds),
2641 + .leds = bcm2708_leds,
2642 +};
2643 +
2644 +static struct platform_device bcm2708_led_device = {
2645 + .name = "leds-gpio",
2646 + .id = -1,
2647 + .dev = {
2648 + .platform_data = &bcm2708_led_pdata,
2649 + },
2650 +};
2651 +
2652 +static void __init bcm2708_init_led(void)
2653 +{
2654 + platform_device_register(&bcm2708_led_device);
2655 +}
2656 +#else
2657 +static inline void bcm2708_init_led(void)
2658 +{
2659 +}
2660 +#endif
2661 +
2662 +void __init bcm2708_init_early(void)
2663 +{
2664 + /*
2665 + * Some devices allocate their coherent buffers from atomic
2666 + * context. Increase size of atomic coherent pool to make sure such
2667 + * the allocations won't fail.
2668 + */
2669 + init_dma_coherent_pool_size(SZ_4M);
2670 +}
2671 +
2672 +MACHINE_START(BCM2708, "BCM2708")
2673 + /* Maintainer: Broadcom Europe Ltd. */
2674 + .map_io = bcm2708_map_io,
2675 + .init_irq = bcm2708_init_irq,
2676 + .init_time = bcm2708_timer_init,
2677 + .init_machine = bcm2708_init,
2678 + .init_early = bcm2708_init_early,
2679 + .restart = bcm2708_restart,
2680 +MACHINE_END
2681 +
2682 +module_param(boardrev, uint, 0644);
2683 +module_param(serial, uint, 0644);
2684 +module_param(uart_clock, uint, 0644);
2685 +module_param(reboot_part, uint, 0644);
2686 --- /dev/null
2687 +++ b/arch/arm/mach-bcm2708/bcm2708.h
2688 @@ -0,0 +1,51 @@
2689 +/*
2690 + * linux/arch/arm/mach-bcm2708/bcm2708.h
2691 + *
2692 + * BCM2708 machine support header
2693 + *
2694 + * Copyright (C) 2010 Broadcom
2695 + *
2696 + * This program is free software; you can redistribute it and/or modify
2697 + * it under the terms of the GNU General Public License as published by
2698 + * the Free Software Foundation; either version 2 of the License, or
2699 + * (at your option) any later version.
2700 + *
2701 + * This program is distributed in the hope that it will be useful,
2702 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2703 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2704 + * GNU General Public License for more details.
2705 + *
2706 + * You should have received a copy of the GNU General Public License
2707 + * along with this program; if not, write to the Free Software
2708 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
2709 + */
2710 +
2711 +#ifndef __BCM2708_BCM2708_H
2712 +#define __BCM2708_BCM2708_H
2713 +
2714 +#include <linux/amba/bus.h>
2715 +
2716 +extern void __init bcm2708_init(void);
2717 +extern void __init bcm2708_init_irq(void);
2718 +extern void __init bcm2708_map_io(void);
2719 +extern struct sys_timer bcm2708_timer;
2720 +extern unsigned int mmc_status(struct device *dev);
2721 +
2722 +#define AMBA_DEVICE(name, busid, base, plat) \
2723 +static struct amba_device name##_device = { \
2724 + .dev = { \
2725 + .coherent_dma_mask = ~0, \
2726 + .init_name = busid, \
2727 + .platform_data = plat, \
2728 + }, \
2729 + .res = { \
2730 + .start = base##_BASE, \
2731 + .end = (base##_BASE) + SZ_4K - 1,\
2732 + .flags = IORESOURCE_MEM, \
2733 + }, \
2734 + .dma_mask = ~0, \
2735 + .irq = base##_IRQ, \
2736 + /* .dma = base##_DMA,*/ \
2737 +}
2738 +
2739 +#endif
2740 --- /dev/null
2741 +++ b/arch/arm/mach-bcm2708/bcm2708_gpio.c
2742 @@ -0,0 +1,339 @@
2743 +/*
2744 + * linux/arch/arm/mach-bcm2708/bcm2708_gpio.c
2745 + *
2746 + * Copyright (C) 2010 Broadcom
2747 + *
2748 + * This program is free software; you can redistribute it and/or modify
2749 + * it under the terms of the GNU General Public License version 2 as
2750 + * published by the Free Software Foundation.
2751 + *
2752 + */
2753 +
2754 +#include <linux/spinlock.h>
2755 +#include <linux/module.h>
2756 +#include <linux/list.h>
2757 +#include <linux/io.h>
2758 +#include <linux/irq.h>
2759 +#include <linux/interrupt.h>
2760 +#include <linux/slab.h>
2761 +#include <mach/gpio.h>
2762 +#include <linux/gpio.h>
2763 +#include <linux/platform_device.h>
2764 +#include <mach/platform.h>
2765 +
2766 +#define BCM_GPIO_DRIVER_NAME "bcm2708_gpio"
2767 +#define DRIVER_NAME BCM_GPIO_DRIVER_NAME
2768 +#define BCM_GPIO_USE_IRQ 1
2769 +
2770 +#define GPIOFSEL(x) (0x00+(x)*4)
2771 +#define GPIOSET(x) (0x1c+(x)*4)
2772 +#define GPIOCLR(x) (0x28+(x)*4)
2773 +#define GPIOLEV(x) (0x34+(x)*4)
2774 +#define GPIOEDS(x) (0x40+(x)*4)
2775 +#define GPIOREN(x) (0x4c+(x)*4)
2776 +#define GPIOFEN(x) (0x58+(x)*4)
2777 +#define GPIOHEN(x) (0x64+(x)*4)
2778 +#define GPIOLEN(x) (0x70+(x)*4)
2779 +#define GPIOAREN(x) (0x7c+(x)*4)
2780 +#define GPIOAFEN(x) (0x88+(x)*4)
2781 +#define GPIOUD(x) (0x94+(x)*4)
2782 +#define GPIOUDCLK(x) (0x98+(x)*4)
2783 +
2784 +enum { GPIO_FSEL_INPUT, GPIO_FSEL_OUTPUT,
2785 + GPIO_FSEL_ALT5, GPIO_FSEL_ALT_4,
2786 + GPIO_FSEL_ALT0, GPIO_FSEL_ALT1,
2787 + GPIO_FSEL_ALT2, GPIO_FSEL_ALT3,
2788 +};
2789 +
2790 + /* Each of the two spinlocks protects a different set of hardware
2791 + * regiters and data structurs. This decouples the code of the IRQ from
2792 + * the GPIO code. This also makes the case of a GPIO routine call from
2793 + * the IRQ code simpler.
2794 + */
2795 +static DEFINE_SPINLOCK(lock); /* GPIO registers */
2796 +
2797 +struct bcm2708_gpio {
2798 + struct list_head list;
2799 + void __iomem *base;
2800 + struct gpio_chip gc;
2801 + unsigned long rising;
2802 + unsigned long falling;
2803 +};
2804 +
2805 +static int bcm2708_set_function(struct gpio_chip *gc, unsigned offset,
2806 + int function)
2807 +{
2808 + struct bcm2708_gpio *gpio = container_of(gc, struct bcm2708_gpio, gc);
2809 + unsigned long flags;
2810 + unsigned gpiodir;
2811 + unsigned gpio_bank = offset / 10;
2812 + unsigned gpio_field_offset = (offset - 10 * gpio_bank) * 3;
2813 +
2814 +//printk(KERN_ERR DRIVER_NAME ": bcm2708_gpio_set_function %p (%d,%d)\n", gc, offset, function);
2815 + if (offset >= ARCH_NR_GPIOS)
2816 + return -EINVAL;
2817 +
2818 + spin_lock_irqsave(&lock, flags);
2819 +
2820 + gpiodir = readl(gpio->base + GPIOFSEL(gpio_bank));
2821 + gpiodir &= ~(7 << gpio_field_offset);
2822 + gpiodir |= function << gpio_field_offset;
2823 + writel(gpiodir, gpio->base + GPIOFSEL(gpio_bank));
2824 + spin_unlock_irqrestore(&lock, flags);
2825 + gpiodir = readl(gpio->base + GPIOFSEL(gpio_bank));
2826 +
2827 + return 0;
2828 +}
2829 +
2830 +static int bcm2708_gpio_dir_in(struct gpio_chip *gc, unsigned offset)
2831 +{
2832 + return bcm2708_set_function(gc, offset, GPIO_FSEL_INPUT);
2833 +}
2834 +
2835 +static void bcm2708_gpio_set(struct gpio_chip *gc, unsigned offset, int value);
2836 +static int bcm2708_gpio_dir_out(struct gpio_chip *gc, unsigned offset,
2837 + int value)
2838 +{
2839 + int ret;
2840 + ret = bcm2708_set_function(gc, offset, GPIO_FSEL_OUTPUT);
2841 + if (ret >= 0)
2842 + bcm2708_gpio_set(gc, offset, value);
2843 + return ret;
2844 +}
2845 +
2846 +static int bcm2708_gpio_get(struct gpio_chip *gc, unsigned offset)
2847 +{
2848 + struct bcm2708_gpio *gpio = container_of(gc, struct bcm2708_gpio, gc);
2849 + unsigned gpio_bank = offset / 32;
2850 + unsigned gpio_field_offset = (offset - 32 * gpio_bank);
2851 + unsigned lev;
2852 +
2853 + if (offset >= ARCH_NR_GPIOS)
2854 + return 0;
2855 + lev = readl(gpio->base + GPIOLEV(gpio_bank));
2856 +//printk(KERN_ERR DRIVER_NAME ": bcm2708_gpio_get %p (%d)=%d\n", gc, offset, 0x1 & (lev>>gpio_field_offset));
2857 + return 0x1 & (lev >> gpio_field_offset);
2858 +}
2859 +
2860 +static void bcm2708_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
2861 +{
2862 + struct bcm2708_gpio *gpio = container_of(gc, struct bcm2708_gpio, gc);
2863 + unsigned gpio_bank = offset / 32;
2864 + unsigned gpio_field_offset = (offset - 32 * gpio_bank);
2865 +//printk(KERN_ERR DRIVER_NAME ": bcm2708_gpio_set %p (%d=%d)\n", gc, offset, value);
2866 + if (offset >= ARCH_NR_GPIOS)
2867 + return;
2868 + if (value)
2869 + writel(1 << gpio_field_offset, gpio->base + GPIOSET(gpio_bank));
2870 + else
2871 + writel(1 << gpio_field_offset, gpio->base + GPIOCLR(gpio_bank));
2872 +}
2873 +
2874 +/*************************************************************************************************************************
2875 + * bcm2708 GPIO IRQ
2876 + */
2877 +
2878 +#if BCM_GPIO_USE_IRQ
2879 +
2880 +static int bcm2708_gpio_to_irq(struct gpio_chip *chip, unsigned gpio)
2881 +{
2882 + return gpio_to_irq(gpio);
2883 +}
2884 +
2885 +static int bcm2708_gpio_irq_set_type(struct irq_data *d, unsigned type)
2886 +{
2887 + unsigned irq = d->irq;
2888 + struct bcm2708_gpio *gpio = irq_get_chip_data(irq);
2889 +
2890 + if (type & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
2891 + return -EINVAL;
2892 +
2893 + if (type & IRQ_TYPE_EDGE_RISING) {
2894 + gpio->rising |= (1 << irq_to_gpio(irq));
2895 + } else {
2896 + gpio->rising &= ~(1 << irq_to_gpio(irq));
2897 + }
2898 +
2899 + if (type & IRQ_TYPE_EDGE_FALLING) {
2900 + gpio->falling |= (1 << irq_to_gpio(irq));
2901 + } else {
2902 + gpio->falling &= ~(1 << irq_to_gpio(irq));
2903 + }
2904 + return 0;
2905 +}
2906 +
2907 +static void bcm2708_gpio_irq_mask(struct irq_data *d)
2908 +{
2909 + unsigned irq = d->irq;
2910 + struct bcm2708_gpio *gpio = irq_get_chip_data(irq);
2911 + unsigned gn = irq_to_gpio(irq);
2912 + unsigned gb = gn / 32;
2913 + unsigned long rising = readl(gpio->base + GPIOREN(gb));
2914 + unsigned long falling = readl(gpio->base + GPIOFEN(gb));
2915 +
2916 + gn = gn % 32;
2917 +
2918 + writel(rising & ~(1 << gn), gpio->base + GPIOREN(gb));
2919 + writel(falling & ~(1 << gn), gpio->base + GPIOFEN(gb));
2920 +}
2921 +
2922 +static void bcm2708_gpio_irq_unmask(struct irq_data *d)
2923 +{
2924 + unsigned irq = d->irq;
2925 + struct bcm2708_gpio *gpio = irq_get_chip_data(irq);
2926 + unsigned gn = irq_to_gpio(irq);
2927 + unsigned gb = gn / 32;
2928 + unsigned long rising = readl(gpio->base + GPIOREN(gb));
2929 + unsigned long falling = readl(gpio->base + GPIOFEN(gb));
2930 +
2931 + gn = gn % 32;
2932 +
2933 + writel(1 << gn, gpio->base + GPIOEDS(gb));
2934 +
2935 + if (gpio->rising & (1 << gn)) {
2936 + writel(rising | (1 << gn), gpio->base + GPIOREN(gb));
2937 + } else {
2938 + writel(rising & ~(1 << gn), gpio->base + GPIOREN(gb));
2939 + }
2940 +
2941 + if (gpio->falling & (1 << gn)) {
2942 + writel(falling | (1 << gn), gpio->base + GPIOFEN(gb));
2943 + } else {
2944 + writel(falling & ~(1 << gn), gpio->base + GPIOFEN(gb));
2945 + }
2946 +}
2947 +
2948 +static struct irq_chip bcm2708_irqchip = {
2949 + .name = "GPIO",
2950 + .irq_enable = bcm2708_gpio_irq_unmask,
2951 + .irq_disable = bcm2708_gpio_irq_mask,
2952 + .irq_unmask = bcm2708_gpio_irq_unmask,
2953 + .irq_mask = bcm2708_gpio_irq_mask,
2954 + .irq_set_type = bcm2708_gpio_irq_set_type,
2955 +};
2956 +
2957 +static irqreturn_t bcm2708_gpio_interrupt(int irq, void *dev_id)
2958 +{
2959 + unsigned long edsr;
2960 + unsigned bank;
2961 + int i;
2962 + unsigned gpio;
2963 + for (bank = 0; bank <= 1; bank++) {
2964 + edsr = readl(__io_address(GPIO_BASE) + GPIOEDS(bank));
2965 + for_each_set_bit(i, &edsr, 32) {
2966 + gpio = i + bank * 32;
2967 + generic_handle_irq(gpio_to_irq(gpio));
2968 + }
2969 + writel(0xffffffff, __io_address(GPIO_BASE) + GPIOEDS(bank));
2970 + }
2971 + return IRQ_HANDLED;
2972 +}
2973 +
2974 +static struct irqaction bcm2708_gpio_irq = {
2975 + .name = "BCM2708 GPIO catchall handler",
2976 + .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
2977 + .handler = bcm2708_gpio_interrupt,
2978 +};
2979 +
2980 +static void bcm2708_gpio_irq_init(struct bcm2708_gpio *ucb)
2981 +{
2982 + unsigned irq;
2983 +
2984 + ucb->gc.to_irq = bcm2708_gpio_to_irq;
2985 +
2986 + for (irq = GPIO_IRQ_START; irq < (GPIO_IRQ_START + GPIO_IRQS); irq++) {
2987 + irq_set_chip_data(irq, ucb);
2988 + irq_set_chip(irq, &bcm2708_irqchip);
2989 + set_irq_flags(irq, IRQF_VALID);
2990 + }
2991 + setup_irq(IRQ_GPIO3, &bcm2708_gpio_irq);
2992 +}
2993 +
2994 +#else
2995 +
2996 +static void bcm2708_gpio_irq_init(struct bcm2708_gpio *ucb)
2997 +{
2998 +}
2999 +
3000 +#endif /* #if BCM_GPIO_USE_IRQ ***************************************************************************************************************** */
3001 +
3002 +static int bcm2708_gpio_probe(struct platform_device *dev)
3003 +{
3004 + struct bcm2708_gpio *ucb;
3005 + struct resource *res;
3006 + int err = 0;
3007 +
3008 + printk(KERN_INFO DRIVER_NAME ": bcm2708_gpio_probe %p\n", dev);
3009 +
3010 + ucb = kzalloc(sizeof(*ucb), GFP_KERNEL);
3011 + if (NULL == ucb) {
3012 + printk(KERN_ERR DRIVER_NAME ": failed to allocate "
3013 + "mailbox memory\n");
3014 + err = -ENOMEM;
3015 + goto err;
3016 + }
3017 +
3018 + res = platform_get_resource(dev, IORESOURCE_MEM, 0);
3019 +
3020 + platform_set_drvdata(dev, ucb);
3021 + ucb->base = __io_address(GPIO_BASE);
3022 +
3023 + ucb->gc.label = "bcm2708_gpio";
3024 + ucb->gc.base = 0;
3025 + ucb->gc.ngpio = ARCH_NR_GPIOS;
3026 + ucb->gc.owner = THIS_MODULE;
3027 +
3028 + ucb->gc.direction_input = bcm2708_gpio_dir_in;
3029 + ucb->gc.direction_output = bcm2708_gpio_dir_out;
3030 + ucb->gc.get = bcm2708_gpio_get;
3031 + ucb->gc.set = bcm2708_gpio_set;
3032 + ucb->gc.can_sleep = 0;
3033 +
3034 + bcm2708_gpio_irq_init(ucb);
3035 +
3036 + err = gpiochip_add(&ucb->gc);
3037 + if (err)
3038 + goto err;
3039 +
3040 +err:
3041 + return err;
3042 +
3043 +}
3044 +
3045 +static int bcm2708_gpio_remove(struct platform_device *dev)
3046 +{
3047 + int err = 0;
3048 + struct bcm2708_gpio *ucb = platform_get_drvdata(dev);
3049 +
3050 + printk(KERN_ERR DRIVER_NAME ": bcm2708_gpio_remove %p\n", dev);
3051 +
3052 + err = gpiochip_remove(&ucb->gc);
3053 +
3054 + platform_set_drvdata(dev, NULL);
3055 + kfree(ucb);
3056 +
3057 + return err;
3058 +}
3059 +
3060 +static struct platform_driver bcm2708_gpio_driver = {
3061 + .probe = bcm2708_gpio_probe,
3062 + .remove = bcm2708_gpio_remove,
3063 + .driver = {
3064 + .name = "bcm2708_gpio"},
3065 +};
3066 +
3067 +static int __init bcm2708_gpio_init(void)
3068 +{
3069 + return platform_driver_register(&bcm2708_gpio_driver);
3070 +}
3071 +
3072 +static void __exit bcm2708_gpio_exit(void)
3073 +{
3074 + platform_driver_unregister(&bcm2708_gpio_driver);
3075 +}
3076 +
3077 +module_init(bcm2708_gpio_init);
3078 +module_exit(bcm2708_gpio_exit);
3079 +
3080 +MODULE_DESCRIPTION("Broadcom BCM2708 GPIO driver");
3081 +MODULE_LICENSE("GPL");
3082 --- /dev/null
3083 +++ b/arch/arm/mach-bcm2708/clock.c
3084 @@ -0,0 +1,61 @@
3085 +/*
3086 + * linux/arch/arm/mach-bcm2708/clock.c
3087 + *
3088 + * Copyright (C) 2010 Broadcom
3089 + *
3090 + * This program is free software; you can redistribute it and/or modify
3091 + * it under the terms of the GNU General Public License as published by
3092 + * the Free Software Foundation; either version 2 of the License, or
3093 + * (at your option) any later version.
3094 + *
3095 + * This program is distributed in the hope that it will be useful,
3096 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
3097 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3098 + * GNU General Public License for more details.
3099 + *
3100 + * You should have received a copy of the GNU General Public License
3101 + * along with this program; if not, write to the Free Software
3102 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
3103 + */
3104 +#include <linux/module.h>
3105 +#include <linux/kernel.h>
3106 +#include <linux/device.h>
3107 +#include <linux/list.h>
3108 +#include <linux/errno.h>
3109 +#include <linux/err.h>
3110 +#include <linux/string.h>
3111 +#include <linux/clk.h>
3112 +#include <linux/mutex.h>
3113 +
3114 +#include <asm/clkdev.h>
3115 +
3116 +#include "clock.h"
3117 +
3118 +int clk_enable(struct clk *clk)
3119 +{
3120 + return 0;
3121 +}
3122 +EXPORT_SYMBOL(clk_enable);
3123 +
3124 +void clk_disable(struct clk *clk)
3125 +{
3126 +}
3127 +EXPORT_SYMBOL(clk_disable);
3128 +
3129 +unsigned long clk_get_rate(struct clk *clk)
3130 +{
3131 + return clk->rate;
3132 +}
3133 +EXPORT_SYMBOL(clk_get_rate);
3134 +
3135 +long clk_round_rate(struct clk *clk, unsigned long rate)
3136 +{
3137 + return clk->rate;
3138 +}
3139 +EXPORT_SYMBOL(clk_round_rate);
3140 +
3141 +int clk_set_rate(struct clk *clk, unsigned long rate)
3142 +{
3143 + return -EIO;
3144 +}
3145 +EXPORT_SYMBOL(clk_set_rate);
3146 --- /dev/null
3147 +++ b/arch/arm/mach-bcm2708/clock.h
3148 @@ -0,0 +1,24 @@
3149 +/*
3150 + * linux/arch/arm/mach-bcm2708/clock.h
3151 + *
3152 + * Copyright (C) 2010 Broadcom
3153 + *
3154 + * This program is free software; you can redistribute it and/or modify
3155 + * it under the terms of the GNU General Public License as published by
3156 + * the Free Software Foundation; either version 2 of the License, or
3157 + * (at your option) any later version.
3158 + *
3159 + * This program is distributed in the hope that it will be useful,
3160 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
3161 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3162 + * GNU General Public License for more details.
3163 + *
3164 + * You should have received a copy of the GNU General Public License
3165 + * along with this program; if not, write to the Free Software
3166 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
3167 + */
3168 +struct module;
3169 +
3170 +struct clk {
3171 + unsigned long rate;
3172 +};
3173 --- /dev/null
3174 +++ b/arch/arm/mach-bcm2708/dma.c
3175 @@ -0,0 +1,399 @@
3176 +/*
3177 + * linux/arch/arm/mach-bcm2708/dma.c
3178 + *
3179 + * Copyright (C) 2010 Broadcom
3180 + *
3181 + * This program is free software; you can redistribute it and/or modify
3182 + * it under the terms of the GNU General Public License version 2 as
3183 + * published by the Free Software Foundation.
3184 + */
3185 +
3186 +#include <linux/slab.h>
3187 +#include <linux/device.h>
3188 +#include <linux/platform_device.h>
3189 +#include <linux/module.h>
3190 +#include <linux/scatterlist.h>
3191 +
3192 +#include <mach/dma.h>
3193 +#include <mach/irqs.h>
3194 +
3195 +/*****************************************************************************\
3196 + * *
3197 + * Configuration *
3198 + * *
3199 +\*****************************************************************************/
3200 +
3201 +#define CACHE_LINE_MASK 31
3202 +#define DRIVER_NAME BCM_DMAMAN_DRIVER_NAME
3203 +#define DEFAULT_DMACHAN_BITMAP 0x10 /* channel 4 only */
3204 +
3205 +/* valid only for channels 0 - 14, 15 has its own base address */
3206 +#define BCM2708_DMA_CHAN(n) ((n)<<8) /* base address */
3207 +#define BCM2708_DMA_CHANIO(dma_base, n) \
3208 + ((void __iomem *)((char *)(dma_base)+BCM2708_DMA_CHAN(n)))
3209 +
3210 +
3211 +/*****************************************************************************\
3212 + * *
3213 + * DMA Auxilliary Functions *
3214 + * *
3215 +\*****************************************************************************/
3216 +
3217 +/* A DMA buffer on an arbitrary boundary may separate a cache line into a
3218 + section inside the DMA buffer and another section outside it.
3219 + Even if we flush DMA buffers from the cache there is always the chance that
3220 + during a DMA someone will access the part of a cache line that is outside
3221 + the DMA buffer - which will then bring in unwelcome data.
3222 + Without being able to dictate our own buffer pools we must insist that
3223 + DMA buffers consist of a whole number of cache lines.
3224 +*/
3225 +
3226 +extern int
3227 +bcm_sg_suitable_for_dma(struct scatterlist *sg_ptr, int sg_len)
3228 +{
3229 + int i;
3230 +
3231 + for (i = 0; i < sg_len; i++) {
3232 + if (sg_ptr[i].offset & CACHE_LINE_MASK ||
3233 + sg_ptr[i].length & CACHE_LINE_MASK)
3234 + return 0;
3235 + }
3236 +
3237 + return 1;
3238 +}
3239 +EXPORT_SYMBOL_GPL(bcm_sg_suitable_for_dma);
3240 +
3241 +extern void
3242 +bcm_dma_start(void __iomem *dma_chan_base, dma_addr_t control_block)
3243 +{
3244 + dsb(); /* ARM data synchronization (push) operation */
3245 +
3246 + writel(control_block, dma_chan_base + BCM2708_DMA_ADDR);
3247 + writel(BCM2708_DMA_ACTIVE, dma_chan_base + BCM2708_DMA_CS);
3248 +}
3249 +
3250 +extern void bcm_dma_wait_idle(void __iomem *dma_chan_base)
3251 +{
3252 + dsb();
3253 +
3254 + /* ugly busy wait only option for now */
3255 + while (readl(dma_chan_base + BCM2708_DMA_CS) & BCM2708_DMA_ACTIVE)
3256 + cpu_relax();
3257 +}
3258 +
3259 +EXPORT_SYMBOL_GPL(bcm_dma_start);
3260 +
3261 +/* Complete an ongoing DMA (assuming its results are to be ignored)
3262 + Does nothing if there is no DMA in progress.
3263 + This routine waits for the current AXI transfer to complete before
3264 + terminating the current DMA. If the current transfer is hung on a DREQ used
3265 + by an uncooperative peripheral the AXI transfer may never complete. In this
3266 + case the routine times out and return a non-zero error code.
3267 + Use of this routine doesn't guarantee that the ongoing or aborted DMA
3268 + does not produce an interrupt.
3269 +*/
3270 +extern int
3271 +bcm_dma_abort(void __iomem *dma_chan_base)
3272 +{
3273 + unsigned long int cs;
3274 + int rc = 0;
3275 +
3276 + cs = readl(dma_chan_base + BCM2708_DMA_CS);
3277 +
3278 + if (BCM2708_DMA_ACTIVE & cs) {
3279 + long int timeout = 10000;
3280 +
3281 + /* write 0 to the active bit - pause the DMA */
3282 + writel(0, dma_chan_base + BCM2708_DMA_CS);
3283 +
3284 + /* wait for any current AXI transfer to complete */
3285 + while (0 != (cs & BCM2708_DMA_ISPAUSED) && --timeout >= 0)
3286 + cs = readl(dma_chan_base + BCM2708_DMA_CS);
3287 +
3288 + if (0 != (cs & BCM2708_DMA_ISPAUSED)) {
3289 + /* we'll un-pause when we set of our next DMA */
3290 + rc = -ETIMEDOUT;
3291 +
3292 + } else if (BCM2708_DMA_ACTIVE & cs) {
3293 + /* terminate the control block chain */
3294 + writel(0, dma_chan_base + BCM2708_DMA_NEXTCB);
3295 +
3296 + /* abort the whole DMA */
3297 + writel(BCM2708_DMA_ABORT | BCM2708_DMA_ACTIVE,
3298 + dma_chan_base + BCM2708_DMA_CS);
3299 + }
3300 + }
3301 +
3302 + return rc;
3303 +}
3304 +EXPORT_SYMBOL_GPL(bcm_dma_abort);
3305 +
3306 +
3307 +/***************************************************************************** \
3308 + * *
3309 + * DMA Manager Device Methods *
3310 + * *
3311 +\*****************************************************************************/
3312 +
3313 +struct vc_dmaman {
3314 + void __iomem *dma_base;
3315 + u32 chan_available; /* bitmap of available channels */
3316 + u32 has_feature[BCM_DMA_FEATURE_COUNT]; /* bitmap of feature presence */
3317 +};
3318 +
3319 +static void vc_dmaman_init(struct vc_dmaman *dmaman, void __iomem *dma_base,
3320 + u32 chans_available)
3321 +{
3322 + dmaman->dma_base = dma_base;
3323 + dmaman->chan_available = chans_available;
3324 + dmaman->has_feature[BCM_DMA_FEATURE_FAST_ORD] = 0x0c; /* chans 2 & 3 */
3325 + dmaman->has_feature[BCM_DMA_FEATURE_BULK_ORD] = 0x01; /* chan 0 */
3326 +}
3327 +
3328 +static int vc_dmaman_chan_alloc(struct vc_dmaman *dmaman,
3329 + unsigned preferred_feature_set)
3330 +{
3331 + u32 chans;
3332 + int feature;
3333 +
3334 + chans = dmaman->chan_available;
3335 + for (feature = 0; feature < BCM_DMA_FEATURE_COUNT; feature++)
3336 + /* select the subset of available channels with the desired
3337 + feature so long as some of the candidate channels have that
3338 + feature */
3339 + if ((preferred_feature_set & (1 << feature)) &&
3340 + (chans & dmaman->has_feature[feature]))
3341 + chans &= dmaman->has_feature[feature];
3342 +
3343 + if (chans) {
3344 + int chan = 0;
3345 + /* return the ordinal of the first channel in the bitmap */
3346 + while (chans != 0 && (chans & 1) == 0) {
3347 + chans >>= 1;
3348 + chan++;
3349 + }
3350 + /* claim the channel */
3351 + dmaman->chan_available &= ~(1 << chan);
3352 + return chan;
3353 + } else
3354 + return -ENOMEM;
3355 +}
3356 +
3357 +static int vc_dmaman_chan_free(struct vc_dmaman *dmaman, int chan)
3358 +{
3359 + if (chan < 0)
3360 + return -EINVAL;
3361 + else if ((1 << chan) & dmaman->chan_available)
3362 + return -EIDRM;
3363 + else {
3364 + dmaman->chan_available |= (1 << chan);
3365 + return 0;
3366 + }
3367 +}
3368 +
3369 +/*****************************************************************************\
3370 + * *
3371 + * DMA IRQs *
3372 + * *
3373 +\*****************************************************************************/
3374 +
3375 +static unsigned char bcm_dma_irqs[] = {
3376 + IRQ_DMA0,
3377 + IRQ_DMA1,
3378 + IRQ_DMA2,
3379 + IRQ_DMA3,
3380 + IRQ_DMA4,
3381 + IRQ_DMA5,
3382 + IRQ_DMA6,
3383 + IRQ_DMA7,
3384 + IRQ_DMA8,
3385 + IRQ_DMA9,
3386 + IRQ_DMA10,
3387 + IRQ_DMA11,
3388 + IRQ_DMA12
3389 +};
3390 +
3391 +
3392 +/***************************************************************************** \
3393 + * *
3394 + * DMA Manager Monitor *
3395 + * *
3396 +\*****************************************************************************/
3397 +
3398 +static struct device *dmaman_dev; /* we assume there's only one! */
3399 +
3400 +extern int bcm_dma_chan_alloc(unsigned preferred_feature_set,
3401 + void __iomem **out_dma_base, int *out_dma_irq)
3402 +{
3403 + if (!dmaman_dev)
3404 + return -ENODEV;
3405 + else {
3406 + struct vc_dmaman *dmaman = dev_get_drvdata(dmaman_dev);
3407 + int rc;
3408 +
3409 + device_lock(dmaman_dev);
3410 + rc = vc_dmaman_chan_alloc(dmaman, preferred_feature_set);
3411 + if (rc >= 0) {
3412 + *out_dma_base = BCM2708_DMA_CHANIO(dmaman->dma_base,
3413 + rc);
3414 + *out_dma_irq = bcm_dma_irqs[rc];
3415 + }
3416 + device_unlock(dmaman_dev);
3417 +
3418 + return rc;
3419 + }
3420 +}
3421 +EXPORT_SYMBOL_GPL(bcm_dma_chan_alloc);
3422 +
3423 +extern int bcm_dma_chan_free(int channel)
3424 +{
3425 + if (dmaman_dev) {
3426 + struct vc_dmaman *dmaman = dev_get_drvdata(dmaman_dev);
3427 + int rc;
3428 +
3429 + device_lock(dmaman_dev);