target/linux/brcm2708/patches-3.10/0038-Lazy-CRC-quirk-Implemented-retrying-mechanisms-for-S.patch

   1 From d94e2bd60b27f2ff7d6e9ff7ee43848bb2090c06 Mon Sep 17 00:00:00 2001
   2 From: dero <de@ro>
   3 Date: Mon, 19 Nov 2012 12:46:06 +0100
   4 Subject: [PATCH 038/196] Lazy CRC quirk: Implemented retrying mechanisms for
   5  SD SSR and SCR, disabled missing_status and spurious CRC ACMD51 quirks by
   6  default (should be fixed by the retrying-mechanishm)
   7
   8 ---
   9  drivers/mmc/core/sd.c            | 115 +++++++++++++++++++++++++++++++++------
  10  drivers/mmc/host/sdhci-bcm2708.c |  11 +++-
  11  2 files changed, 108 insertions(+), 18 deletions(-)
  12
  13 diff --git a/drivers/mmc/core/sd.c b/drivers/mmc/core/sd.c
  14 index 9e645e1..1ee6cf3 100644
  15 --- a/drivers/mmc/core/sd.c
  16 +++ b/drivers/mmc/core/sd.c
  17 @@ -13,6 +13,8 @@
  18  #include <linux/err.h>
  19  #include <linux/slab.h>
  20  #include <linux/stat.h>
  21 +#include <linux/jiffies.h>
  22 +#include <linux/nmi.h>
  23
  24  #include <linux/mmc/host.h>
  25  #include <linux/mmc/card.h>
  26 @@ -58,6 +60,15 @@ static const unsigned int tacc_mant[] = {
  27                 __res & __mask;                                         \
  28         })
  29
  30 +// timeout for tries
  31 +static const unsigned long retry_timeout_ms= 10*1000;
  32 +
  33 +// try at least 10 times, even if timeout is reached
  34 +static const int retry_min_tries= 10;
  35 +
  36 +// delay between tries
  37 +static const unsigned long retry_delay_ms= 10;
  38 +
  39  /*
  40   * Given the decoded CSD structure, decode the raw CID to our CID structure.
  41   */
  42 @@ -210,12 +221,62 @@ static int mmc_decode_scr(struct mmc_card *card)
  43  }
  44
  45  /*
  46 - * Fetch and process SD Status register.
  47 + * Fetch and process SD Configuration Register.
  48 + */
  49 +static int mmc_read_scr(struct mmc_card *card)
  50 +{
  51 +       unsigned long timeout_at;
  52 +       int err, tries;
  53 +
  54 +       timeout_at= jiffies + msecs_to_jiffies( retry_timeout_ms );
  55 +       tries=          0;
  56 +
  57 +       while( tries < retry_min_tries || time_before( jiffies, timeout_at ) )
  58 +       {
  59 +               unsigned long delay_at;
  60 +               tries++;
  61 +
  62 +               err = mmc_app_send_scr(card, card->raw_scr);
  63 +               if( !err )
  64 +                       break; // sucess!!!
  65 +
  66 +               touch_nmi_watchdog();     // we are still alive!
  67 +
  68 +               // delay
  69 +               delay_at= jiffies + msecs_to_jiffies( retry_delay_ms );
  70 +               while( time_before( jiffies, delay_at ) )
  71 +               {
  72 +                       mdelay( 1 );
  73 +                       touch_nmi_watchdog();     // we are still alive!
  74 +               }
  75 +       }
  76 +
  77 +       if( err)
  78 +       {
  79 +               pr_err("%s: failed to read SD Configuration register (SCR) after %d tries during %lu ms, error %d\n", mmc_hostname(card->host), tries, retry_timeout_ms, err );
  80 +               return err;
  81 +       }
  82 +
  83 +       if( tries > 1 )
  84 +       {
  85 +               pr_info("%s: could read SD Configuration register (SCR) at the %dth attempt\n", mmc_hostname(card->host), tries );
  86 +       }
  87 +
  88 +       err = mmc_decode_scr(card);
  89 +       if (err)
  90 +               return err;
  91 +
  92 +       return err;
  93 +}
  94 +
  95 +/*
  96 + * Fetch and process SD Status Register.
  97   */
  98  static int mmc_read_ssr(struct mmc_card *card)
  99  {
 100 +       unsigned long timeout_at;
 101         unsigned int au, es, et, eo;
 102 -       int err, i;
 103 +       int err, i, tries;
 104         u32 *ssr;
 105
 106         if (!(card->csd.cmdclass & CCC_APP_SPEC)) {
 107 @@ -227,15 +288,41 @@ static int mmc_read_ssr(struct mmc_card *card)
 108         ssr = kmalloc(64, GFP_KERNEL);
 109         if (!ssr)
 110                 return -ENOMEM;
 111 -
 112 -       err = mmc_app_sd_status(card, ssr);
 113 -       if (err) {
 114 -               pr_warning("%s: problem reading SD Status "
 115 -                       "register.\n", mmc_hostname(card->host));
 116 -               err = 0;
 117 +
 118 +       timeout_at= jiffies + msecs_to_jiffies( retry_timeout_ms );
 119 +       tries=          0;
 120 +
 121 +       while( tries < retry_min_tries || time_before( jiffies, timeout_at ) )
 122 +       {
 123 +               unsigned long delay_at;
 124 +               tries++;
 125 +
 126 +               err= mmc_app_sd_status(card, ssr);
 127 +               if( !err )
 128 +                       break; // sucess!!!
 129 +
 130 +               touch_nmi_watchdog();     // we are still alive!
 131 +
 132 +               // delay
 133 +               delay_at= jiffies + msecs_to_jiffies( retry_delay_ms );
 134 +               while( time_before( jiffies, delay_at ) )
 135 +               {
 136 +                       mdelay( 1 );
 137 +                       touch_nmi_watchdog();     // we are still alive!
 138 +               }
 139 +       }
 140 +
 141 +       if( err)
 142 +       {
 143 +               pr_err("%s: failed to read SD Status register (SSR) after %d tries during %lu ms, error %d\n", mmc_hostname(card->host), tries, retry_timeout_ms, err );
 144                 goto out;
 145         }
 146
 147 +       if( tries > 1 )
 148 +       {
 149 +               pr_info("%s: could read SD Status register (SSR) at the %dth attempt\n", mmc_hostname(card->host), tries );
 150 +       }
 151 +
 152         for (i = 0; i < 16; i++)
 153                 ssr[i] = be32_to_cpu(ssr[i]);
 154
 155 @@ -808,15 +895,11 @@ int mmc_sd_setup_card(struct mmc_host *host, struct mmc_card *card,
 156
 157         if (!reinit) {
 158                 /*
 159 -                * Fetch SCR from card.
 160 +                * Fetch and decode SD Configuration register.
 161                  */
 162 -               err = mmc_app_send_scr(card, card->raw_scr);
 163 -               if (err)
 164 -                       return err;
 165 -
 166 -               err = mmc_decode_scr(card);
 167 -               if (err)
 168 -                       return err;
 169 +               err = mmc_read_scr(card);
 170 +               if( err )
 171 +                       return err;
 172
 173                 /*
 174                  * Fetch and process SD Status register.
 175 diff --git a/drivers/mmc/host/sdhci-bcm2708.c b/drivers/mmc/host/sdhci-bcm2708.c
 176 index ffd7310..3556ed3 100644
 177 --- a/drivers/mmc/host/sdhci-bcm2708.c
 178 +++ b/drivers/mmc/host/sdhci-bcm2708.c
 179 @@ -137,6 +137,7 @@ static bool allow_highspeed = 1;
 180  static int emmc_clock_freq = BCM2708_EMMC_CLOCK_FREQ;
 181  static bool sync_after_dma = 1;
 182  static bool missing_status = 1;
 183 +static bool spurious_crc_acmd51 = 0;
 184  bool enable_llm = 1;
 185
 186  #if 0
 187 @@ -1103,7 +1104,7 @@ static unsigned int sdhci_bcm2708_quirk_extra_ints(struct sdhci_host *host)
 188          return 1;
 189  }
 190
 191 -static unsigned int sdhci_bcm2708_quirk_spurious_crc(struct sdhci_host *host)
 192 +static unsigned int sdhci_bcm2708_quirk_spurious_crc_acmd51(struct sdhci_host *host)
 193  {
 194          return 1;
 195  }
 196 @@ -1149,7 +1150,6 @@ static struct sdhci_ops sdhci_bcm2708_ops = {
 197         .pdma_reset = sdhci_bcm2708_platdma_reset,
 198  #endif
 199         .extra_ints = sdhci_bcm2708_quirk_extra_ints,
 200 -       .spurious_crc_acmd51 = sdhci_bcm2708_quirk_spurious_crc,
 201         .voltage_broken = sdhci_bcm2708_quirk_voltage_broken,
 202         .uhs_broken = sdhci_bcm2708_uhs_broken,
 203  };
 204 @@ -1194,6 +1194,11 @@ static int sdhci_bcm2708_probe(struct platform_device *pdev)
 205                 sdhci_bcm2708_ops.missing_status = sdhci_bcm2708_missing_status;
 206         }
 207
 208 +       if( spurious_crc_acmd51 ) {
 209 +               sdhci_bcm2708_ops.spurious_crc_acmd51 = sdhci_bcm2708_quirk_spurious_crc_acmd51;
 210 +       }
 211 +
 212 +
 213         printk("sdhci: %s low-latency mode\n",enable_llm?"Enable":"Disable");
 214
 215         host->hw_name = "BCM2708_Arasan";
 216 @@ -1389,6 +1394,7 @@ module_param(allow_highspeed, bool, 0444);
 217  module_param(emmc_clock_freq, int, 0444);
 218  module_param(sync_after_dma, bool, 0444);
 219  module_param(missing_status, bool, 0444);
 220 +module_param(spurious_crc_acmd51, bool, 0444);
 221  module_param(enable_llm, bool, 0444);
 222  module_param(cycle_delay, int, 0444);
 223
 224 @@ -1401,6 +1407,7 @@ MODULE_PARM_DESC(allow_highspeed, "Allow high speed transfers modes");
 225  MODULE_PARM_DESC(emmc_clock_freq, "Specify the speed of emmc clock");
 226  MODULE_PARM_DESC(sync_after_dma, "Block in driver until dma complete");
 227  MODULE_PARM_DESC(missing_status, "Use the missing status quirk");
 228 +MODULE_PARM_DESC(spurious_crc_acmd51, "Use the spurious crc quirk for reading SCR (ACMD51)");
 229  MODULE_PARM_DESC(enable_llm, "Enable low-latency mode");
 230
 231
 232 --
 233 1.9.1
 234