target/linux/brcm2708/patches-3.10/0078-dwc_otg-mask-correct-interrupts-after-transaction-er.patch

   1 From 5608eaff0f301e9bf73998da020644f1673b66e4 Mon Sep 17 00:00:00 2001
   2 From: P33M <P33M@github.com>
   3 Date: Sat, 13 Jul 2013 20:41:26 +0100
   4 Subject: [PATCH 078/196] dwc_otg: mask correct interrupts after transaction
   5  error recovery
   6
   7 The dwc_otg driver will unmask certain interrupts on a transaction
   8 that previously halted in the error state in order to reset the
   9 QTD error count. The various fine-grained interrupt handlers do not
  10 consider that other interrupts besides themselves were unmasked.
  11
  12 By disabling the two other interrupts only ever enabled in DMA mode
  13 for this purpose, we can avoid unnecessary function calls in the
  14 IRQ handler. This will also prevent an unneccesary FIQ interrupt
  15 from being generated if the FIQ is enabled.
  16 ---
  17  drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c | 21 +++++++++++++++++++++
  18  1 file changed, 21 insertions(+)
  19
  20 diff --git a/drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c b/drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c
  21 index e8b4d35..27b673f 100644
  22 --- a/drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c
  23 +++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c
  24 @@ -1851,7 +1851,11 @@ static int32_t handle_hc_nak_intr(dwc_otg_hcd_t * hcd,
  25                          * transfers in DMA mode for the sole purpose of
  26                          * resetting the error count after a transaction error
  27                          * occurs. The core will continue transferring data.
  28 +                        * Disable other interrupts unmasked for the same
  29 +                        * reason.
  30                          */
  31 +                       disable_hc_int(hc_regs, datatglerr);
  32 +                       disable_hc_int(hc_regs, ack);
  33                         qtd->error_count = 0;
  34                         goto handle_nak_done;
  35                 }
  36 @@ -1963,6 +1967,15 @@ static int32_t handle_hc_ack_intr(dwc_otg_hcd_t * hcd,
  37                         halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_ACK);
  38                 }
  39         } else {
  40 +               /*
  41 +                * An unmasked ACK on a non-split DMA transaction is
  42 +                * for the sole purpose of resetting error counts. Disable other
  43 +                * interrupts unmasked for the same reason.
  44 +                */
  45 +               if(hcd->core_if->dma_enable) {
  46 +                       disable_hc_int(hc_regs, datatglerr);
  47 +                       disable_hc_int(hc_regs, nak);
  48 +               }
  49                 qtd->error_count = 0;
  50
  51                 if (hc->qh->ping_state) {
  52 @@ -2328,6 +2341,14 @@ static int32_t handle_hc_datatglerr_intr(dwc_otg_hcd_t * hcd,
  53                         qtd->urb, qtd, DWC_OTG_HC_XFER_XACT_ERR);
  54                 halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_XACT_ERR);
  55         } else if (hc->ep_is_in) {
  56 +               /* An unmasked data toggle error on a non-split DMA transaction is
  57 +                * for the sole purpose of resetting error counts. Disable other
  58 +                * interrupts unmasked for the same reason.
  59 +                */
  60 +               if(hcd->core_if->dma_enable) {
  61 +                       disable_hc_int(hc_regs, ack);
  62 +                       disable_hc_int(hc_regs, nak);
  63 +               }
  64                 qtd->error_count = 0;
  65         }
  66
  67 --
  68 1.9.1
  69