brcm2708: update against latest rpi-3.10.y branch
[openwrt/svn-archive/archive.git] / target / linux / brcm2708 / patches-3.10 / 0078-dwc_otg-mask-correct-interrupts-after-transaction-er.patch
1 From cb902630ae7ef709c8f40ca3f506cf5052077701 Mon Sep 17 00:00:00 2001
2 From: P33M <P33M@github.com>
3 Date: Sat, 13 Jul 2013 20:41:26 +0100
4 Subject: [PATCH 078/174] dwc_otg: mask correct interrupts after transaction
5 error recovery
6
7 The dwc_otg driver will unmask certain interrupts on a transaction
8 that previously halted in the error state in order to reset the
9 QTD error count. The various fine-grained interrupt handlers do not
10 consider that other interrupts besides themselves were unmasked.
11
12 By disabling the two other interrupts only ever enabled in DMA mode
13 for this purpose, we can avoid unnecessary function calls in the
14 IRQ handler. This will also prevent an unneccesary FIQ interrupt
15 from being generated if the FIQ is enabled.
16 ---
17 drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c | 21 +++++++++++++++++++++
18 1 file changed, 21 insertions(+)
19
20 --- a/drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c
21 +++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c
22 @@ -1851,7 +1851,11 @@ static int32_t handle_hc_nak_intr(dwc_ot
23 * transfers in DMA mode for the sole purpose of
24 * resetting the error count after a transaction error
25 * occurs. The core will continue transferring data.
26 + * Disable other interrupts unmasked for the same
27 + * reason.
28 */
29 + disable_hc_int(hc_regs, datatglerr);
30 + disable_hc_int(hc_regs, ack);
31 qtd->error_count = 0;
32 goto handle_nak_done;
33 }
34 @@ -1963,6 +1967,15 @@ static int32_t handle_hc_ack_intr(dwc_ot
35 halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_ACK);
36 }
37 } else {
38 + /*
39 + * An unmasked ACK on a non-split DMA transaction is
40 + * for the sole purpose of resetting error counts. Disable other
41 + * interrupts unmasked for the same reason.
42 + */
43 + if(hcd->core_if->dma_enable) {
44 + disable_hc_int(hc_regs, datatglerr);
45 + disable_hc_int(hc_regs, nak);
46 + }
47 qtd->error_count = 0;
48
49 if (hc->qh->ping_state) {
50 @@ -2328,6 +2341,14 @@ static int32_t handle_hc_datatglerr_intr
51 qtd->urb, qtd, DWC_OTG_HC_XFER_XACT_ERR);
52 halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_XACT_ERR);
53 } else if (hc->ep_is_in) {
54 + /* An unmasked data toggle error on a non-split DMA transaction is
55 + * for the sole purpose of resetting error counts. Disable other
56 + * interrupts unmasked for the same reason.
57 + */
58 + if(hcd->core_if->dma_enable) {
59 + disable_hc_int(hc_regs, ack);
60 + disable_hc_int(hc_regs, nak);
61 + }
62 qtd->error_count = 0;
63 }
64