brcm2708: update against latest rpi-3.10.y branch
[openwrt/svn-archive/archive.git] / target / linux / brcm2708 / patches-3.10 / 0116-ASoC-Add-support-for-BCM2708.patch
1 From f3c21ba6458e497638d4a006645f055b63288168 Mon Sep 17 00:00:00 2001
2 From: Florian Meier <florian.meier@koalo.de>
3 Date: Fri, 22 Nov 2013 14:33:38 +0100
4 Subject: [PATCH 116/174] ASoC: Add support for BCM2708
5
6 This driver adds support for digital audio (I2S)
7 for the BCM2708 SoC that is used by the
8 Raspberry Pi. External audio codecs can be
9 connected to the Raspberry Pi via P5 header.
10
11 It relies on cyclic DMA engine support for BCM2708.
12
13 Signed-off-by: Florian Meier <florian.meier@koalo.de>
14 ---
15 sound/soc/Kconfig | 1 +
16 sound/soc/Makefile | 1 +
17 sound/soc/bcm/Kconfig | 10 +
18 sound/soc/bcm/Makefile | 4 +
19 sound/soc/bcm/bcm2708-i2s.c | 940 ++++++++++++++++++++++++++++++++++++++++++++
20 5 files changed, 956 insertions(+)
21 create mode 100644 sound/soc/bcm/Kconfig
22 create mode 100644 sound/soc/bcm/Makefile
23 create mode 100644 sound/soc/bcm/bcm2708-i2s.c
24
25 --- a/sound/soc/Kconfig
26 +++ b/sound/soc/Kconfig
27 @@ -36,6 +36,7 @@ config SND_SOC_GENERIC_DMAENGINE_PCM
28 # All the supported SoCs
29 source "sound/soc/atmel/Kconfig"
30 source "sound/soc/au1x/Kconfig"
31 +source "sound/soc/bcm/Kconfig"
32 source "sound/soc/blackfin/Kconfig"
33 source "sound/soc/cirrus/Kconfig"
34 source "sound/soc/davinci/Kconfig"
35 --- a/sound/soc/Makefile
36 +++ b/sound/soc/Makefile
37 @@ -14,6 +14,7 @@ obj-$(CONFIG_SND_SOC) += codecs/
38 obj-$(CONFIG_SND_SOC) += generic/
39 obj-$(CONFIG_SND_SOC) += atmel/
40 obj-$(CONFIG_SND_SOC) += au1x/
41 +obj-$(CONFIG_SND_SOC) += bcm/
42 obj-$(CONFIG_SND_SOC) += blackfin/
43 obj-$(CONFIG_SND_SOC) += cirrus/
44 obj-$(CONFIG_SND_SOC) += davinci/
45 --- /dev/null
46 +++ b/sound/soc/bcm/Kconfig
47 @@ -0,0 +1,10 @@
48 +config SND_BCM2708_SOC_I2S
49 + tristate "SoC Audio support for the Broadcom BCM2708 I2S module"
50 + depends on MACH_BCM2708
51 + select REGMAP_MMIO
52 + select SND_SOC_DMAENGINE_PCM
53 + select SND_SOC_GENERIC_DMAENGINE_PCM
54 + help
55 + Say Y or M if you want to add support for codecs attached to
56 + the BCM2708 I2S interface. You will also need
57 + to select the audio interfaces to support below.
58 --- /dev/null
59 +++ b/sound/soc/bcm/Makefile
60 @@ -0,0 +1,4 @@
61 +# BCM2708 Platform Support
62 +snd-soc-bcm2708-i2s-objs := bcm2708-i2s.o
63 +
64 +obj-$(CONFIG_SND_BCM2708_SOC_I2S) += snd-soc-bcm2708-i2s.o
65 --- /dev/null
66 +++ b/sound/soc/bcm/bcm2708-i2s.c
67 @@ -0,0 +1,940 @@
68 +/*
69 + * ALSA SoC I2S Audio Layer for Broadcom BCM2708 SoC
70 + *
71 + * Author: Florian Meier <florian.meier@koalo.de>
72 + * Copyright 2013
73 + *
74 + * Based on
75 + * Raspberry Pi PCM I2S ALSA Driver
76 + * Copyright (c) by Phil Poole 2013
77 + *
78 + * ALSA SoC I2S (McBSP) Audio Layer for TI DAVINCI processor
79 + * Vladimir Barinov, <vbarinov@embeddedalley.com>
80 + * Copyright (C) 2007 MontaVista Software, Inc., <source@mvista.com>
81 + *
82 + * OMAP ALSA SoC DAI driver using McBSP port
83 + * Copyright (C) 2008 Nokia Corporation
84 + * Contact: Jarkko Nikula <jarkko.nikula@bitmer.com>
85 + * Peter Ujfalusi <peter.ujfalusi@ti.com>
86 + *
87 + * Freescale SSI ALSA SoC Digital Audio Interface (DAI) driver
88 + * Author: Timur Tabi <timur@freescale.com>
89 + * Copyright 2007-2010 Freescale Semiconductor, Inc.
90 + *
91 + * This program is free software; you can redistribute it and/or
92 + * modify it under the terms of the GNU General Public License
93 + * version 2 as published by the Free Software Foundation.
94 + *
95 + * This program is distributed in the hope that it will be useful, but
96 + * WITHOUT ANY WARRANTY; without even the implied warranty of
97 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
98 + * General Public License for more details.
99 + */
100 +
101 +#include <linux/init.h>
102 +#include <linux/module.h>
103 +#include <linux/device.h>
104 +#include <linux/slab.h>
105 +#include <linux/delay.h>
106 +#include <linux/io.h>
107 +#include <linux/clk.h>
108 +
109 +#include <sound/core.h>
110 +#include <sound/pcm.h>
111 +#include <sound/pcm_params.h>
112 +#include <sound/initval.h>
113 +#include <sound/soc.h>
114 +#include <sound/dmaengine_pcm.h>
115 +
116 +/* Clock registers */
117 +#define BCM2708_CLK_PCMCTL_REG 0x00
118 +#define BCM2708_CLK_PCMDIV_REG 0x04
119 +
120 +/* Clock register settings */
121 +#define BCM2708_CLK_PASSWD (0x5a000000)
122 +#define BCM2708_CLK_PASSWD_MASK (0xff000000)
123 +#define BCM2708_CLK_MASH(v) ((v) << 9)
124 +#define BCM2708_CLK_FLIP BIT(8)
125 +#define BCM2708_CLK_BUSY BIT(7)
126 +#define BCM2708_CLK_KILL BIT(5)
127 +#define BCM2708_CLK_ENAB BIT(4)
128 +#define BCM2708_CLK_SRC(v) (v)
129 +
130 +#define BCM2708_CLK_SHIFT (12)
131 +#define BCM2708_CLK_DIVI(v) ((v) << BCM2708_CLK_SHIFT)
132 +#define BCM2708_CLK_DIVF(v) (v)
133 +#define BCM2708_CLK_DIVF_MASK (0xFFF)
134 +
135 +enum {
136 + BCM2708_CLK_MASH_0 = 0,
137 + BCM2708_CLK_MASH_1,
138 + BCM2708_CLK_MASH_2,
139 + BCM2708_CLK_MASH_3,
140 +};
141 +
142 +enum {
143 + BCM2708_CLK_SRC_GND = 0,
144 + BCM2708_CLK_SRC_OSC,
145 + BCM2708_CLK_SRC_DBG0,
146 + BCM2708_CLK_SRC_DBG1,
147 + BCM2708_CLK_SRC_PLLA,
148 + BCM2708_CLK_SRC_PLLC,
149 + BCM2708_CLK_SRC_PLLD,
150 + BCM2708_CLK_SRC_HDMI,
151 +};
152 +
153 +/* Most clocks are not useable (freq = 0) */
154 +static const unsigned int bcm2708_clk_freq[BCM2708_CLK_SRC_HDMI+1] = {
155 + [BCM2708_CLK_SRC_GND] = 0,
156 + [BCM2708_CLK_SRC_OSC] = 19200000,
157 + [BCM2708_CLK_SRC_DBG0] = 0,
158 + [BCM2708_CLK_SRC_DBG1] = 0,
159 + [BCM2708_CLK_SRC_PLLA] = 0,
160 + [BCM2708_CLK_SRC_PLLC] = 0,
161 + [BCM2708_CLK_SRC_PLLD] = 500000000,
162 + [BCM2708_CLK_SRC_HDMI] = 0,
163 +};
164 +
165 +/* I2S registers */
166 +#define BCM2708_I2S_CS_A_REG 0x00
167 +#define BCM2708_I2S_FIFO_A_REG 0x04
168 +#define BCM2708_I2S_MODE_A_REG 0x08
169 +#define BCM2708_I2S_RXC_A_REG 0x0c
170 +#define BCM2708_I2S_TXC_A_REG 0x10
171 +#define BCM2708_I2S_DREQ_A_REG 0x14
172 +#define BCM2708_I2S_INTEN_A_REG 0x18
173 +#define BCM2708_I2S_INTSTC_A_REG 0x1c
174 +#define BCM2708_I2S_GRAY_REG 0x20
175 +
176 +/* I2S register settings */
177 +#define BCM2708_I2S_STBY BIT(25)
178 +#define BCM2708_I2S_SYNC BIT(24)
179 +#define BCM2708_I2S_RXSEX BIT(23)
180 +#define BCM2708_I2S_RXF BIT(22)
181 +#define BCM2708_I2S_TXE BIT(21)
182 +#define BCM2708_I2S_RXD BIT(20)
183 +#define BCM2708_I2S_TXD BIT(19)
184 +#define BCM2708_I2S_RXR BIT(18)
185 +#define BCM2708_I2S_TXW BIT(17)
186 +#define BCM2708_I2S_CS_RXERR BIT(16)
187 +#define BCM2708_I2S_CS_TXERR BIT(15)
188 +#define BCM2708_I2S_RXSYNC BIT(14)
189 +#define BCM2708_I2S_TXSYNC BIT(13)
190 +#define BCM2708_I2S_DMAEN BIT(9)
191 +#define BCM2708_I2S_RXTHR(v) ((v) << 7)
192 +#define BCM2708_I2S_TXTHR(v) ((v) << 5)
193 +#define BCM2708_I2S_RXCLR BIT(4)
194 +#define BCM2708_I2S_TXCLR BIT(3)
195 +#define BCM2708_I2S_TXON BIT(2)
196 +#define BCM2708_I2S_RXON BIT(1)
197 +#define BCM2708_I2S_EN (1)
198 +
199 +#define BCM2708_I2S_CLKDIS BIT(28)
200 +#define BCM2708_I2S_PDMN BIT(27)
201 +#define BCM2708_I2S_PDME BIT(26)
202 +#define BCM2708_I2S_FRXP BIT(25)
203 +#define BCM2708_I2S_FTXP BIT(24)
204 +#define BCM2708_I2S_CLKM BIT(23)
205 +#define BCM2708_I2S_CLKI BIT(22)
206 +#define BCM2708_I2S_FSM BIT(21)
207 +#define BCM2708_I2S_FSI BIT(20)
208 +#define BCM2708_I2S_FLEN(v) ((v) << 10)
209 +#define BCM2708_I2S_FSLEN(v) (v)
210 +
211 +#define BCM2708_I2S_CHWEX BIT(15)
212 +#define BCM2708_I2S_CHEN BIT(14)
213 +#define BCM2708_I2S_CHPOS(v) ((v) << 4)
214 +#define BCM2708_I2S_CHWID(v) (v)
215 +#define BCM2708_I2S_CH1(v) ((v) << 16)
216 +#define BCM2708_I2S_CH2(v) (v)
217 +
218 +#define BCM2708_I2S_TX_PANIC(v) ((v) << 24)
219 +#define BCM2708_I2S_RX_PANIC(v) ((v) << 16)
220 +#define BCM2708_I2S_TX(v) ((v) << 8)
221 +#define BCM2708_I2S_RX(v) (v)
222 +
223 +#define BCM2708_I2S_INT_RXERR BIT(3)
224 +#define BCM2708_I2S_INT_TXERR BIT(2)
225 +#define BCM2708_I2S_INT_RXR BIT(1)
226 +#define BCM2708_I2S_INT_TXW BIT(0)
227 +
228 +/* I2S DMA interface */
229 +#define BCM2708_I2S_FIFO_PHYSICAL_ADDR 0x7E203004
230 +#define BCM2708_DMA_DREQ_PCM_TX 2
231 +#define BCM2708_DMA_DREQ_PCM_RX 3
232 +
233 +/* General device struct */
234 +struct bcm2708_i2s_dev {
235 + struct device *dev;
236 + struct snd_dmaengine_dai_dma_data dma_data[2];
237 + unsigned int fmt;
238 + unsigned int bclk_ratio;
239 +
240 + struct regmap *i2s_regmap;
241 + struct regmap *clk_regmap;
242 +};
243 +
244 +static void bcm2708_i2s_start_clock(struct bcm2708_i2s_dev *dev)
245 +{
246 + /* Start the clock if in master mode */
247 + unsigned int master = dev->fmt & SND_SOC_DAIFMT_MASTER_MASK;
248 +
249 + switch (master) {
250 + case SND_SOC_DAIFMT_CBS_CFS:
251 + case SND_SOC_DAIFMT_CBS_CFM:
252 + regmap_update_bits(dev->clk_regmap, BCM2708_CLK_PCMCTL_REG,
253 + BCM2708_CLK_PASSWD_MASK | BCM2708_CLK_ENAB,
254 + BCM2708_CLK_PASSWD | BCM2708_CLK_ENAB);
255 + break;
256 + default:
257 + break;
258 + }
259 +}
260 +
261 +static void bcm2708_i2s_stop_clock(struct bcm2708_i2s_dev *dev)
262 +{
263 + uint32_t clkreg;
264 + int timeout = 1000;
265 +
266 + /* Stop clock */
267 + regmap_update_bits(dev->clk_regmap, BCM2708_CLK_PCMCTL_REG,
268 + BCM2708_CLK_PASSWD_MASK | BCM2708_CLK_ENAB,
269 + BCM2708_CLK_PASSWD);
270 +
271 + /* Wait for the BUSY flag going down */
272 + while (--timeout) {
273 + regmap_read(dev->clk_regmap, BCM2708_CLK_PCMCTL_REG, &clkreg);
274 + if (!(clkreg & BCM2708_CLK_BUSY))
275 + break;
276 + }
277 +
278 + if (!timeout) {
279 + /* KILL the clock */
280 + dev_err(dev->dev, "I2S clock didn't stop. Kill the clock!\n");
281 + regmap_update_bits(dev->clk_regmap, BCM2708_CLK_PCMCTL_REG,
282 + BCM2708_CLK_KILL | BCM2708_CLK_PASSWD_MASK,
283 + BCM2708_CLK_KILL | BCM2708_CLK_PASSWD);
284 + }
285 +}
286 +
287 +static void bcm2708_i2s_clear_fifos(struct bcm2708_i2s_dev *dev,
288 + bool tx, bool rx)
289 +{
290 + int timeout = 1000;
291 + uint32_t syncval;
292 + uint32_t csreg;
293 + uint32_t i2s_active_state;
294 + uint32_t clkreg;
295 + uint32_t clk_active_state;
296 + uint32_t off;
297 + uint32_t clr;
298 +
299 + off = tx ? BCM2708_I2S_TXON : 0;
300 + off |= rx ? BCM2708_I2S_RXON : 0;
301 +
302 + clr = tx ? BCM2708_I2S_TXCLR : 0;
303 + clr |= rx ? BCM2708_I2S_RXCLR : 0;
304 +
305 + /* Backup the current state */
306 + regmap_read(dev->i2s_regmap, BCM2708_I2S_CS_A_REG, &csreg);
307 + i2s_active_state = csreg & (BCM2708_I2S_RXON | BCM2708_I2S_TXON);
308 +
309 + regmap_read(dev->clk_regmap, BCM2708_CLK_PCMCTL_REG, &clkreg);
310 + clk_active_state = clkreg & BCM2708_CLK_ENAB;
311 +
312 + /* Start clock if not running */
313 + if (!clk_active_state) {
314 + regmap_update_bits(dev->clk_regmap, BCM2708_CLK_PCMCTL_REG,
315 + BCM2708_CLK_PASSWD_MASK | BCM2708_CLK_ENAB,
316 + BCM2708_CLK_PASSWD | BCM2708_CLK_ENAB);
317 + }
318 +
319 + /* Stop I2S module */
320 + regmap_update_bits(dev->i2s_regmap, BCM2708_I2S_CS_A_REG, off, 0);
321 +
322 + /*
323 + * Clear the FIFOs
324 + * Requires at least 2 PCM clock cycles to take effect
325 + */
326 + regmap_update_bits(dev->i2s_regmap, BCM2708_I2S_CS_A_REG, clr, clr);
327 +
328 + /* Wait for 2 PCM clock cycles */
329 +
330 + /*
331 + * Toggle the SYNC flag. After 2 PCM clock cycles it can be read back
332 + * FIXME: This does not seem to work for slave mode!
333 + */
334 + regmap_read(dev->i2s_regmap, BCM2708_I2S_CS_A_REG, &syncval);
335 + syncval &= BCM2708_I2S_SYNC;
336 +
337 + regmap_update_bits(dev->i2s_regmap, BCM2708_I2S_CS_A_REG,
338 + BCM2708_I2S_SYNC, ~syncval);
339 +
340 + /* Wait for the SYNC flag changing it's state */
341 + while (--timeout) {
342 + regmap_read(dev->i2s_regmap, BCM2708_I2S_CS_A_REG, &csreg);
343 + if ((csreg & BCM2708_I2S_SYNC) != syncval)
344 + break;
345 + }
346 +
347 + if (!timeout)
348 + dev_err(dev->dev, "I2S SYNC error!\n");
349 +
350 + /* Stop clock if it was not running before */
351 + if (!clk_active_state)
352 + bcm2708_i2s_stop_clock(dev);
353 +
354 + /* Restore I2S state */
355 + regmap_update_bits(dev->i2s_regmap, BCM2708_I2S_CS_A_REG,
356 + BCM2708_I2S_RXON | BCM2708_I2S_TXON, i2s_active_state);
357 +}
358 +
359 +static int bcm2708_i2s_set_dai_fmt(struct snd_soc_dai *dai,
360 + unsigned int fmt)
361 +{
362 + struct bcm2708_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
363 + dev->fmt = fmt;
364 + return 0;
365 +}
366 +
367 +static int bcm2708_i2s_set_dai_bclk_ratio(struct snd_soc_dai *dai,
368 + unsigned int ratio)
369 +{
370 + struct bcm2708_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
371 + dev->bclk_ratio = ratio;
372 + return 0;
373 +}
374 +
375 +static int bcm2708_i2s_hw_params(struct snd_pcm_substream *substream,
376 + struct snd_pcm_hw_params *params,
377 + struct snd_soc_dai *dai)
378 +{
379 + struct bcm2708_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
380 +
381 + unsigned int sampling_rate = params_rate(params);
382 + unsigned int data_length, data_delay, bclk_ratio;
383 + unsigned int ch1pos, ch2pos, mode, format;
384 + unsigned int mash = BCM2708_CLK_MASH_1;
385 + unsigned int divi, divf, target_frequency;
386 + int clk_src = -1;
387 + unsigned int master = dev->fmt & SND_SOC_DAIFMT_MASTER_MASK;
388 + bool bit_master = (master == SND_SOC_DAIFMT_CBS_CFS
389 + || master == SND_SOC_DAIFMT_CBS_CFM);
390 +
391 + bool frame_master = (master == SND_SOC_DAIFMT_CBS_CFS
392 + || master == SND_SOC_DAIFMT_CBM_CFS);
393 + uint32_t csreg;
394 +
395 + /*
396 + * If a stream is already enabled,
397 + * the registers are already set properly.
398 + */
399 + regmap_read(dev->i2s_regmap, BCM2708_I2S_CS_A_REG, &csreg);
400 +
401 + if (csreg & (BCM2708_I2S_TXON | BCM2708_I2S_RXON))
402 + return 0;
403 +
404 + /*
405 + * Adjust the data length according to the format.
406 + * We prefill the half frame length with an integer
407 + * divider of 2400 as explained at the clock settings.
408 + * Maybe it is overwritten there, if the Integer mode
409 + * does not apply.
410 + */
411 + switch (params_format(params)) {
412 + case SNDRV_PCM_FORMAT_S16_LE:
413 + data_length = 16;
414 + bclk_ratio = 40;
415 + break;
416 + case SNDRV_PCM_FORMAT_S32_LE:
417 + data_length = 32;
418 + bclk_ratio = 80;
419 + break;
420 + default:
421 + return -EINVAL;
422 + }
423 +
424 + /* If bclk_ratio already set, use that one. */
425 + if (dev->bclk_ratio)
426 + bclk_ratio = dev->bclk_ratio;
427 +
428 + /*
429 + * Clock Settings
430 + *
431 + * The target frequency of the bit clock is
432 + * sampling rate * frame length
433 + *
434 + * Integer mode:
435 + * Sampling rates that are multiples of 8000 kHz
436 + * can be driven by the oscillator of 19.2 MHz
437 + * with an integer divider as long as the frame length
438 + * is an integer divider of 19200000/8000=2400 as set up above.
439 + * This is no longer possible if the sampling rate
440 + * is too high (e.g. 192 kHz), because the oscillator is too slow.
441 + *
442 + * MASH mode:
443 + * For all other sampling rates, it is not possible to
444 + * have an integer divider. Approximate the clock
445 + * with the MASH module that induces a slight frequency
446 + * variance. To minimize that it is best to have the fastest
447 + * clock here. That is PLLD with 500 MHz.
448 + */
449 + target_frequency = sampling_rate * bclk_ratio;
450 + clk_src = BCM2708_CLK_SRC_OSC;
451 + mash = BCM2708_CLK_MASH_0;
452 +
453 + if (bcm2708_clk_freq[clk_src] % target_frequency == 0
454 + && bit_master && frame_master) {
455 + divi = bcm2708_clk_freq[clk_src] / target_frequency;
456 + divf = 0;
457 + } else {
458 + uint64_t dividend;
459 +
460 + if (!dev->bclk_ratio) {
461 + /*
462 + * Overwrite bclk_ratio, because the
463 + * above trick is not needed or can
464 + * not be used.
465 + */
466 + bclk_ratio = 2 * data_length;
467 + }
468 +
469 + target_frequency = sampling_rate * bclk_ratio;
470 +
471 + clk_src = BCM2708_CLK_SRC_PLLD;
472 + mash = BCM2708_CLK_MASH_1;
473 +
474 + dividend = bcm2708_clk_freq[clk_src];
475 + dividend <<= BCM2708_CLK_SHIFT;
476 + do_div(dividend, target_frequency);
477 + divi = dividend >> BCM2708_CLK_SHIFT;
478 + divf = dividend & BCM2708_CLK_DIVF_MASK;
479 + }
480 +
481 + /* Set clock divider */
482 + regmap_write(dev->clk_regmap, BCM2708_CLK_PCMDIV_REG, BCM2708_CLK_PASSWD
483 + | BCM2708_CLK_DIVI(divi)
484 + | BCM2708_CLK_DIVF(divf));
485 +
486 + /* Setup clock, but don't start it yet */
487 + regmap_write(dev->clk_regmap, BCM2708_CLK_PCMCTL_REG, BCM2708_CLK_PASSWD
488 + | BCM2708_CLK_MASH(mash)
489 + | BCM2708_CLK_SRC(clk_src));
490 +
491 + /* Setup the frame format */
492 + format = BCM2708_I2S_CHEN;
493 +
494 + if (data_length > 24)
495 + format |= BCM2708_I2S_CHWEX;
496 +
497 + format |= BCM2708_I2S_CHWID((data_length-8)&0xf);
498 +
499 + switch (dev->fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
500 + case SND_SOC_DAIFMT_I2S:
501 + data_delay = 1;
502 + break;
503 + default:
504 + /*
505 + * TODO
506 + * Others are possible but are not implemented at the moment.
507 + */
508 + dev_err(dev->dev, "%s:bad format\n", __func__);
509 + return -EINVAL;
510 + }
511 +
512 + ch1pos = data_delay;
513 + ch2pos = bclk_ratio / 2 + data_delay;
514 +
515 + switch (params_channels(params)) {
516 + case 2:
517 + format = BCM2708_I2S_CH1(format) | BCM2708_I2S_CH2(format);
518 + format |= BCM2708_I2S_CH1(BCM2708_I2S_CHPOS(ch1pos));
519 + format |= BCM2708_I2S_CH2(BCM2708_I2S_CHPOS(ch2pos));
520 + break;
521 + default:
522 + return -EINVAL;
523 + }
524 +
525 + /*
526 + * Set format for both streams.
527 + * We cannot set another frame length
528 + * (and therefore word length) anyway,
529 + * so the format will be the same.
530 + */
531 + regmap_write(dev->i2s_regmap, BCM2708_I2S_RXC_A_REG, format);
532 + regmap_write(dev->i2s_regmap, BCM2708_I2S_TXC_A_REG, format);
533 +
534 + /* Setup the I2S mode */
535 + mode = 0;
536 +
537 + if (data_length <= 16) {
538 + /*
539 + * Use frame packed mode (2 channels per 32 bit word)
540 + * We cannot set another frame length in the second stream
541 + * (and therefore word length) anyway,
542 + * so the format will be the same.
543 + */
544 + mode |= BCM2708_I2S_FTXP | BCM2708_I2S_FRXP;
545 + }
546 +
547 + mode |= BCM2708_I2S_FLEN(bclk_ratio - 1);
548 + mode |= BCM2708_I2S_FSLEN(bclk_ratio / 2);
549 +
550 + /* Master or slave? */
551 + switch (dev->fmt & SND_SOC_DAIFMT_MASTER_MASK) {
552 + case SND_SOC_DAIFMT_CBS_CFS:
553 + /* CPU is master */
554 + break;
555 + case SND_SOC_DAIFMT_CBM_CFS:
556 + /*
557 + * CODEC is bit clock master
558 + * CPU is frame master
559 + */
560 + mode |= BCM2708_I2S_CLKM;
561 + break;
562 + case SND_SOC_DAIFMT_CBS_CFM:
563 + /*
564 + * CODEC is frame master
565 + * CPU is bit clock master
566 + */
567 + mode |= BCM2708_I2S_FSM;
568 + break;
569 + case SND_SOC_DAIFMT_CBM_CFM:
570 + /* CODEC is master */
571 + mode |= BCM2708_I2S_CLKM;
572 + mode |= BCM2708_I2S_FSM;
573 + break;
574 + default:
575 + dev_err(dev->dev, "%s:bad master\n", __func__);
576 + return -EINVAL;
577 + }
578 +
579 + /*
580 + * Invert clocks?
581 + *
582 + * The BCM approach seems to be inverted to the classical I2S approach.
583 + */
584 + switch (dev->fmt & SND_SOC_DAIFMT_INV_MASK) {
585 + case SND_SOC_DAIFMT_NB_NF:
586 + /* None. Therefore, both for BCM */
587 + mode |= BCM2708_I2S_CLKI;
588 + mode |= BCM2708_I2S_FSI;
589 + break;
590 + case SND_SOC_DAIFMT_IB_IF:
591 + /* Both. Therefore, none for BCM */
592 + break;
593 + case SND_SOC_DAIFMT_NB_IF:
594 + /*
595 + * Invert only frame sync. Therefore,
596 + * invert only bit clock for BCM
597 + */
598 + mode |= BCM2708_I2S_CLKI;
599 + break;
600 + case SND_SOC_DAIFMT_IB_NF:
601 + /*
602 + * Invert only bit clock. Therefore,
603 + * invert only frame sync for BCM
604 + */
605 + mode |= BCM2708_I2S_FSI;
606 + break;
607 + default:
608 + return -EINVAL;
609 + }
610 +
611 + regmap_write(dev->i2s_regmap, BCM2708_I2S_MODE_A_REG, mode);
612 +
613 + /* Setup the DMA parameters */
614 + regmap_update_bits(dev->i2s_regmap, BCM2708_I2S_CS_A_REG,
615 + BCM2708_I2S_RXTHR(1)
616 + | BCM2708_I2S_TXTHR(1)
617 + | BCM2708_I2S_DMAEN, 0xffffffff);
618 +
619 + regmap_update_bits(dev->i2s_regmap, BCM2708_I2S_DREQ_A_REG,
620 + BCM2708_I2S_TX_PANIC(0x10)
621 + | BCM2708_I2S_RX_PANIC(0x30)
622 + | BCM2708_I2S_TX(0x30)
623 + | BCM2708_I2S_RX(0x20), 0xffffffff);
624 +
625 + /* Clear FIFOs */
626 + bcm2708_i2s_clear_fifos(dev, true, true);
627 +
628 + return 0;
629 +}
630 +
631 +static int bcm2708_i2s_prepare(struct snd_pcm_substream *substream,
632 + struct snd_soc_dai *dai)
633 +{
634 + struct bcm2708_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
635 + uint32_t cs_reg;
636 +
637 + bcm2708_i2s_start_clock(dev);
638 +
639 + /*
640 + * Clear both FIFOs if the one that should be started
641 + * is not empty at the moment. This should only happen
642 + * after overrun. Otherwise, hw_params would have cleared
643 + * the FIFO.
644 + */
645 + regmap_read(dev->i2s_regmap, BCM2708_I2S_CS_A_REG, &cs_reg);
646 +
647 + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK
648 + && !(cs_reg & BCM2708_I2S_TXE))
649 + bcm2708_i2s_clear_fifos(dev, true, false);
650 + else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE
651 + && (cs_reg & BCM2708_I2S_RXD))
652 + bcm2708_i2s_clear_fifos(dev, false, true);
653 +
654 + return 0;
655 +}
656 +
657 +static void bcm2708_i2s_stop(struct bcm2708_i2s_dev *dev,
658 + struct snd_pcm_substream *substream,
659 + struct snd_soc_dai *dai)
660 +{
661 + uint32_t mask;
662 +
663 + if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
664 + mask = BCM2708_I2S_RXON;
665 + else
666 + mask = BCM2708_I2S_TXON;
667 +
668 + regmap_update_bits(dev->i2s_regmap,
669 + BCM2708_I2S_CS_A_REG, mask, 0);
670 +
671 + /* Stop also the clock when not SND_SOC_DAIFMT_CONT */
672 + if (!dai->active && !(dev->fmt & SND_SOC_DAIFMT_CONT))
673 + bcm2708_i2s_stop_clock(dev);
674 +}
675 +
676 +static int bcm2708_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
677 + struct snd_soc_dai *dai)
678 +{
679 + struct bcm2708_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
680 + uint32_t mask;
681 +
682 + switch (cmd) {
683 + case SNDRV_PCM_TRIGGER_START:
684 + case SNDRV_PCM_TRIGGER_RESUME:
685 + case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
686 + bcm2708_i2s_start_clock(dev);
687 +
688 + if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
689 + mask = BCM2708_I2S_RXON;
690 + else
691 + mask = BCM2708_I2S_TXON;
692 +
693 + regmap_update_bits(dev->i2s_regmap,
694 + BCM2708_I2S_CS_A_REG, mask, mask);
695 + break;
696 +
697 + case SNDRV_PCM_TRIGGER_STOP:
698 + case SNDRV_PCM_TRIGGER_SUSPEND:
699 + case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
700 + bcm2708_i2s_stop(dev, substream, dai);
701 + break;
702 + default:
703 + return -EINVAL;
704 + }
705 +
706 + return 0;
707 +}
708 +
709 +static int bcm2708_i2s_startup(struct snd_pcm_substream *substream,
710 + struct snd_soc_dai *dai)
711 +{
712 + struct bcm2708_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
713 +
714 + if (dai->active)
715 + return 0;
716 +
717 + /* Should this still be running stop it */
718 + bcm2708_i2s_stop_clock(dev);
719 +
720 + /* Enable PCM block */
721 + regmap_update_bits(dev->i2s_regmap, BCM2708_I2S_CS_A_REG,
722 + BCM2708_I2S_EN, BCM2708_I2S_EN);
723 +
724 + /*
725 + * Disable STBY.
726 + * Requires at least 4 PCM clock cycles to take effect.
727 + */
728 + regmap_update_bits(dev->i2s_regmap, BCM2708_I2S_CS_A_REG,
729 + BCM2708_I2S_STBY, BCM2708_I2S_STBY);
730 +
731 + return 0;
732 +}
733 +
734 +static void bcm2708_i2s_shutdown(struct snd_pcm_substream *substream,
735 + struct snd_soc_dai *dai)
736 +{
737 + struct bcm2708_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
738 +
739 + bcm2708_i2s_stop(dev, substream, dai);
740 +
741 + /* If both streams are stopped, disable module and clock */
742 + if (dai->active)
743 + return;
744 +
745 + /* Disable the module */
746 + regmap_update_bits(dev->i2s_regmap, BCM2708_I2S_CS_A_REG,
747 + BCM2708_I2S_EN, 0);
748 +
749 + /*
750 + * Stopping clock is necessary, because stop does
751 + * not stop the clock when SND_SOC_DAIFMT_CONT
752 + */
753 + bcm2708_i2s_stop_clock(dev);
754 +}
755 +
756 +static const struct snd_soc_dai_ops bcm2708_i2s_dai_ops = {
757 + .startup = bcm2708_i2s_startup,
758 + .shutdown = bcm2708_i2s_shutdown,
759 + .prepare = bcm2708_i2s_prepare,
760 + .trigger = bcm2708_i2s_trigger,
761 + .hw_params = bcm2708_i2s_hw_params,
762 + .set_fmt = bcm2708_i2s_set_dai_fmt,
763 + .set_bclk_ratio = bcm2708_i2s_set_dai_bclk_ratio
764 +};
765 +
766 +static int bcm2708_i2s_dai_probe(struct snd_soc_dai *dai)
767 +{
768 + struct bcm2708_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
769 +
770 + dai->playback_dma_data = &dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK];
771 + dai->capture_dma_data = &dev->dma_data[SNDRV_PCM_STREAM_CAPTURE];
772 +
773 + return 0;
774 +}
775 +
776 +static struct snd_soc_dai_driver bcm2708_i2s_dai = {
777 + .name = "bcm2708-i2s",
778 + .probe = bcm2708_i2s_dai_probe,
779 + .playback = {
780 + .channels_min = 2,
781 + .channels_max = 2,
782 + .rates = SNDRV_PCM_RATE_8000_192000,
783 + .formats = SNDRV_PCM_FMTBIT_S16_LE
784 + | SNDRV_PCM_FMTBIT_S32_LE
785 + },
786 + .capture = {
787 + .channels_min = 2,
788 + .channels_max = 2,
789 + .rates = SNDRV_PCM_RATE_8000_192000,
790 + .formats = SNDRV_PCM_FMTBIT_S16_LE
791 + | SNDRV_PCM_FMTBIT_S32_LE
792 + },
793 + .ops = &bcm2708_i2s_dai_ops,
794 + .symmetric_rates = 1
795 +};
796 +
797 +static bool bcm2708_i2s_volatile_reg(struct device *dev, unsigned int reg)
798 +{
799 + switch (reg) {
800 + case BCM2708_I2S_CS_A_REG:
801 + case BCM2708_I2S_FIFO_A_REG:
802 + case BCM2708_I2S_INTSTC_A_REG:
803 + case BCM2708_I2S_GRAY_REG:
804 + return true;
805 + default:
806 + return false;
807 + };
808 +}
809 +
810 +static bool bcm2708_i2s_precious_reg(struct device *dev, unsigned int reg)
811 +{
812 + switch (reg) {
813 + case BCM2708_I2S_FIFO_A_REG:
814 + return true;
815 + default:
816 + return false;
817 + };
818 +}
819 +
820 +static bool bcm2708_clk_volatile_reg(struct device *dev, unsigned int reg)
821 +{
822 + switch (reg) {
823 + case BCM2708_CLK_PCMCTL_REG:
824 + return true;
825 + default:
826 + return false;
827 + };
828 +}
829 +
830 +static const struct regmap_config bcm2708_regmap_config[] = {
831 + {
832 + .reg_bits = 32,
833 + .reg_stride = 4,
834 + .val_bits = 32,
835 + .max_register = BCM2708_I2S_GRAY_REG,
836 + .precious_reg = bcm2708_i2s_precious_reg,
837 + .volatile_reg = bcm2708_i2s_volatile_reg,
838 + .cache_type = REGCACHE_RBTREE,
839 + },
840 + {
841 + .reg_bits = 32,
842 + .reg_stride = 4,
843 + .val_bits = 32,
844 + .max_register = BCM2708_CLK_PCMDIV_REG,
845 + .volatile_reg = bcm2708_clk_volatile_reg,
846 + .cache_type = REGCACHE_RBTREE,
847 + },
848 +};
849 +
850 +static const struct snd_soc_component_driver bcm2708_i2s_component = {
851 + .name = "bcm2708-i2s-comp",
852 +};
853 +
854 +
855 +static void bcm2708_i2s_setup_gpio(void)
856 +{
857 + /*
858 + * This is the common way to handle the GPIO pins for
859 + * the Raspberry Pi.
860 + * TODO Better way would be to handle
861 + * this in the device tree!
862 + */
863 +#define INP_GPIO(g) *(gpio+((g)/10)) &= ~(7<<(((g)%10)*3))
864 +#define SET_GPIO_ALT(g,a) *(gpio+(((g)/10))) |= (((a)<=3?(a)+4:(a)==4?3:2)<<(((g)%10)*3))
865 +
866 + unsigned int *gpio;
867 + int pin;
868 + gpio = ioremap(GPIO_BASE, SZ_16K);
869 +
870 + /* SPI is on GPIO 7..11 */
871 + for (pin = 28; pin <= 31; pin++) {
872 + INP_GPIO(pin); /* set mode to GPIO input first */
873 + SET_GPIO_ALT(pin, 2); /* set mode to ALT 0 */
874 + }
875 +#undef INP_GPIO
876 +#undef SET_GPIO_ALT
877 +}
878 +
879 +static const struct snd_pcm_hardware bcm2708_pcm_hardware = {
880 + .info = SNDRV_PCM_INFO_MMAP |
881 + SNDRV_PCM_INFO_MMAP_VALID |
882 + SNDRV_PCM_INFO_INTERLEAVED |
883 + SNDRV_PCM_INFO_JOINT_DUPLEX,
884 + .formats = SNDRV_PCM_FMTBIT_S16_LE |
885 + SNDRV_PCM_FMTBIT_S32_LE,
886 + .period_bytes_min = 32,
887 + .period_bytes_max = 64 * PAGE_SIZE,
888 + .periods_min = 2,
889 + .periods_max = 255,
890 + .buffer_bytes_max = 128 * PAGE_SIZE,
891 +};
892 +
893 +static const struct snd_dmaengine_pcm_config bcm2708_dmaengine_pcm_config = {
894 + .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
895 + .pcm_hardware = &bcm2708_pcm_hardware,
896 + .prealloc_buffer_size = 256 * PAGE_SIZE,
897 +};
898 +
899 +
900 +static int bcm2708_i2s_probe(struct platform_device *pdev)
901 +{
902 + struct bcm2708_i2s_dev *dev;
903 + int i;
904 + int ret;
905 + struct regmap *regmap[2];
906 + struct resource *mem[2];
907 +
908 + /* Request both ioareas */
909 + for (i = 0; i <= 1; i++) {
910 + void __iomem *base;
911 +
912 + mem[i] = platform_get_resource(pdev, IORESOURCE_MEM, i);
913 + base = devm_ioremap_resource(&pdev->dev, mem[i]);
914 + if (IS_ERR(base))
915 + return PTR_ERR(base);
916 +
917 + regmap[i] = devm_regmap_init_mmio(&pdev->dev, base,
918 + &bcm2708_regmap_config[i]);
919 + if (IS_ERR(regmap[i])) {
920 + dev_err(&pdev->dev, "I2S probe: regmap init failed\n");
921 + return PTR_ERR(regmap[i]);
922 + }
923 + }
924 +
925 + dev = devm_kzalloc(&pdev->dev, sizeof(*dev),
926 + GFP_KERNEL);
927 + if (IS_ERR(dev))
928 + return PTR_ERR(dev);
929 +
930 + bcm2708_i2s_setup_gpio();
931 +
932 + dev->i2s_regmap = regmap[0];
933 + dev->clk_regmap = regmap[1];
934 +
935 + /* Set the DMA address */
936 + dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK].addr =
937 + (dma_addr_t)BCM2708_I2S_FIFO_PHYSICAL_ADDR;
938 +
939 + dev->dma_data[SNDRV_PCM_STREAM_CAPTURE].addr =
940 + (dma_addr_t)BCM2708_I2S_FIFO_PHYSICAL_ADDR;
941 +
942 + /* Set the DREQ */
943 + dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK].slave_id =
944 + BCM2708_DMA_DREQ_PCM_TX;
945 + dev->dma_data[SNDRV_PCM_STREAM_CAPTURE].slave_id =
946 + BCM2708_DMA_DREQ_PCM_RX;
947 +
948 + /* Set the bus width */
949 + dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK].addr_width =
950 + DMA_SLAVE_BUSWIDTH_4_BYTES;
951 + dev->dma_data[SNDRV_PCM_STREAM_CAPTURE].addr_width =
952 + DMA_SLAVE_BUSWIDTH_4_BYTES;
953 +
954 + /* Set burst */
955 + dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK].maxburst = 2;
956 + dev->dma_data[SNDRV_PCM_STREAM_CAPTURE].maxburst = 2;
957 +
958 + /* BCLK ratio - use default */
959 + dev->bclk_ratio = 0;
960 +
961 + /* Store the pdev */
962 + dev->dev = &pdev->dev;
963 + dev_set_drvdata(&pdev->dev, dev);
964 +
965 + ret = snd_soc_register_component(&pdev->dev,
966 + &bcm2708_i2s_component, &bcm2708_i2s_dai, 1);
967 +
968 + if (ret) {
969 + dev_err(&pdev->dev, "Could not register DAI: %d\n", ret);
970 + ret = -ENOMEM;
971 + return ret;
972 + }
973 +
974 + ret = snd_dmaengine_pcm_register(&pdev->dev,
975 + &bcm2708_dmaengine_pcm_config,
976 + SND_DMAENGINE_PCM_FLAG_COMPAT);
977 + if (ret) {
978 + dev_err(&pdev->dev, "Could not register PCM: %d\n", ret);
979 + snd_soc_unregister_component(&pdev->dev);
980 + return ret;
981 + }
982 +
983 + return 0;
984 +}
985 +
986 +static int bcm2708_i2s_remove(struct platform_device *pdev)
987 +{
988 + snd_dmaengine_pcm_unregister(&pdev->dev);
989 + snd_soc_unregister_component(&pdev->dev);
990 + return 0;
991 +}
992 +
993 +static struct platform_driver bcm2708_i2s_driver = {
994 + .probe = bcm2708_i2s_probe,
995 + .remove = bcm2708_i2s_remove,
996 + .driver = {
997 + .name = "bcm2708-i2s",
998 + .owner = THIS_MODULE,
999 + },
1000 +};
1001 +
1002 +module_platform_driver(bcm2708_i2s_driver);
1003 +
1004 +MODULE_ALIAS("platform:bcm2708-i2s");
1005 +MODULE_DESCRIPTION("BCM2708 I2S interface");
1006 +MODULE_AUTHOR("Florian Meier <florian.meier@koalo.de>");
1007 +MODULE_LICENSE("GPL v2");