target/linux/brcm2708/patches-3.14/0033-dmaengine-Add-support-for-BCM2708.patch

   1 From 568b7292b8e7e1fe3d852db8b463d989d06b5adf Mon Sep 17 00:00:00 2001
   2 From: Florian Meier <florian.meier@koalo.de>
   3 Date: Fri, 22 Nov 2013 14:22:53 +0100
   4 Subject: [PATCH 33/54] dmaengine: Add support for BCM2708
   5
   6 Add support for DMA controller of BCM2708 as used in the Raspberry Pi.
   7 Currently it only supports cyclic DMA.
   8
   9 Signed-off-by: Florian Meier <florian.meier@koalo.de>
  10 ---
  11  drivers/dma/Kconfig             |   6 +
  12  drivers/dma/Makefile            |   1 +
  13  drivers/dma/bcm2708-dmaengine.c | 588 ++++++++++++++++++++++++++++++++++++++++
  14  3 files changed, 595 insertions(+)
  15  create mode 100644 drivers/dma/bcm2708-dmaengine.c
  16
  17 --- a/drivers/dma/Kconfig
  18 +++ b/drivers/dma/Kconfig
  19 @@ -312,6 +312,12 @@ config DMA_BCM2835
  20         select DMA_ENGINE
  21         select DMA_VIRTUAL_CHANNELS
  22
  23 +config DMA_BCM2708
  24 +       tristate "BCM2708 DMA engine support"
  25 +       depends on MACH_BCM2708
  26 +       select DMA_ENGINE
  27 +       select DMA_VIRTUAL_CHANNELS
  28 +
  29  config TI_CPPI41
  30         tristate "AM33xx CPPI41 DMA support"
  31         depends on ARCH_OMAP
  32 --- a/drivers/dma/Makefile
  33 +++ b/drivers/dma/Makefile
  34 @@ -39,6 +39,7 @@ obj-$(CONFIG_DMA_SA11X0) += sa11x0-dma.o
  35  obj-$(CONFIG_MMP_TDMA) += mmp_tdma.o
  36  obj-$(CONFIG_DMA_OMAP) += omap-dma.o
  37  obj-$(CONFIG_DMA_BCM2835) += bcm2835-dma.o
  38 +obj-$(CONFIG_DMA_BCM2708) += bcm2708-dmaengine.o
  39  obj-$(CONFIG_MMP_PDMA) += mmp_pdma.o
  40  obj-$(CONFIG_DMA_JZ4740) += dma-jz4740.o
  41  obj-$(CONFIG_TI_CPPI41) += cppi41.o
  42 --- /dev/null
  43 +++ b/drivers/dma/bcm2708-dmaengine.c
  44 @@ -0,0 +1,588 @@
  45 +/*
  46 + * BCM2708 DMA engine support
  47 + *
  48 + * This driver only supports cyclic DMA transfers
  49 + * as needed for the I2S module.
  50 + *
  51 + * Author:      Florian Meier <florian.meier@koalo.de>
  52 + *              Copyright 2013
  53 + *
  54 + * Based on
  55 + *     OMAP DMAengine support by Russell King
  56 + *
  57 + *     BCM2708 DMA Driver
  58 + *     Copyright (C) 2010 Broadcom
  59 + *
  60 + *     Raspberry Pi PCM I2S ALSA Driver
  61 + *     Copyright (c) by Phil Poole 2013
  62 + *
  63 + *     MARVELL MMP Peripheral DMA Driver
  64 + *     Copyright 2012 Marvell International Ltd.
  65 + *
  66 + * This program is free software; you can redistribute it and/or modify
  67 + * it under the terms of the GNU General Public License as published by
  68 + * the Free Software Foundation; either version 2 of the License, or
  69 + * (at your option) any later version.
  70 + *
  71 + * This program is distributed in the hope that it will be useful,
  72 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  73 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  74 + * GNU General Public License for more details.
  75 + */
  76 +#include <linux/dmaengine.h>
  77 +#include <linux/dma-mapping.h>
  78 +#include <linux/err.h>
  79 +#include <linux/init.h>
  80 +#include <linux/interrupt.h>
  81 +#include <linux/list.h>
  82 +#include <linux/module.h>
  83 +#include <linux/platform_device.h>
  84 +#include <linux/slab.h>
  85 +#include <linux/io.h>
  86 +#include <linux/spinlock.h>
  87 +#include <linux/irq.h>
  88 +
  89 +#include "virt-dma.h"
  90 +
  91 +#include <mach/dma.h>
  92 +#include <mach/irqs.h>
  93 +
  94 +struct bcm2708_dmadev {
  95 +       struct dma_device ddev;
  96 +       spinlock_t lock;
  97 +       void __iomem *base;
  98 +       struct device_dma_parameters dma_parms;
  99 +};
 100 +
 101 +struct bcm2708_chan {
 102 +       struct virt_dma_chan vc;
 103 +       struct list_head node;
 104 +
 105 +       struct dma_slave_config cfg;
 106 +       bool cyclic;
 107 +
 108 +       int ch;
 109 +       struct bcm2708_desc *desc;
 110 +
 111 +       void __iomem *chan_base;
 112 +       int irq_number;
 113 +};
 114 +
 115 +struct bcm2708_desc {
 116 +       struct virt_dma_desc vd;
 117 +       enum dma_transfer_direction dir;
 118 +
 119 +       unsigned int control_block_size;
 120 +       struct bcm2708_dma_cb *control_block_base;
 121 +       dma_addr_t control_block_base_phys;
 122 +
 123 +       unsigned frames;
 124 +       size_t size;
 125 +};
 126 +
 127 +#define BCM2708_DMA_DATA_TYPE_S8       1
 128 +#define BCM2708_DMA_DATA_TYPE_S16      2
 129 +#define BCM2708_DMA_DATA_TYPE_S32      4
 130 +#define BCM2708_DMA_DATA_TYPE_S128     16
 131 +
 132 +static inline struct bcm2708_dmadev *to_bcm2708_dma_dev(struct dma_device *d)
 133 +{
 134 +       return container_of(d, struct bcm2708_dmadev, ddev);
 135 +}
 136 +
 137 +static inline struct bcm2708_chan *to_bcm2708_dma_chan(struct dma_chan *c)
 138 +{
 139 +       return container_of(c, struct bcm2708_chan, vc.chan);
 140 +}
 141 +
 142 +static inline struct bcm2708_desc *to_bcm2708_dma_desc(
 143 +               struct dma_async_tx_descriptor *t)
 144 +{
 145 +       return container_of(t, struct bcm2708_desc, vd.tx);
 146 +}
 147 +
 148 +static void bcm2708_dma_desc_free(struct virt_dma_desc *vd)
 149 +{
 150 +       struct bcm2708_desc *desc = container_of(vd, struct bcm2708_desc, vd);
 151 +       dma_free_coherent(desc->vd.tx.chan->device->dev,
 152 +                       desc->control_block_size,
 153 +                       desc->control_block_base,
 154 +                       desc->control_block_base_phys);
 155 +       kfree(desc);
 156 +}
 157 +
 158 +static void bcm2708_dma_start_desc(struct bcm2708_chan *c)
 159 +{
 160 +       struct virt_dma_desc *vd = vchan_next_desc(&c->vc);
 161 +       struct bcm2708_desc *d;
 162 +
 163 +       if (!vd) {
 164 +               c->desc = NULL;
 165 +               return;
 166 +       }
 167 +
 168 +       list_del(&vd->node);
 169 +
 170 +       c->desc = d = to_bcm2708_dma_desc(&vd->tx);
 171 +
 172 +       bcm_dma_start(c->chan_base, d->control_block_base_phys);
 173 +}
 174 +
 175 +static irqreturn_t bcm2708_dma_callback(int irq, void *data)
 176 +{
 177 +       struct bcm2708_chan *c = data;
 178 +       struct bcm2708_desc *d;
 179 +       unsigned long flags;
 180 +
 181 +       spin_lock_irqsave(&c->vc.lock, flags);
 182 +
 183 +       /* Acknowledge interrupt */
 184 +       writel(BCM2708_DMA_INT, c->chan_base + BCM2708_DMA_CS);
 185 +
 186 +       d = c->desc;
 187 +
 188 +       if (d) {
 189 +               /* TODO Only works for cyclic DMA */
 190 +               vchan_cyclic_callback(&d->vd);
 191 +       }
 192 +
 193 +       /* Keep the DMA engine running */
 194 +       dsb(); /* ARM synchronization barrier */
 195 +       writel(BCM2708_DMA_ACTIVE, c->chan_base + BCM2708_DMA_CS);
 196 +
 197 +       spin_unlock_irqrestore(&c->vc.lock, flags);
 198 +
 199 +       return IRQ_HANDLED;
 200 +}
 201 +
 202 +static int bcm2708_dma_alloc_chan_resources(struct dma_chan *chan)
 203 +{
 204 +       struct bcm2708_chan *c = to_bcm2708_dma_chan(chan);
 205 +
 206 +       return request_irq(c->irq_number,
 207 +                       bcm2708_dma_callback, 0, "DMA IRQ", c);
 208 +}
 209 +
 210 +static void bcm2708_dma_free_chan_resources(struct dma_chan *chan)
 211 +{
 212 +       struct bcm2708_chan *c = to_bcm2708_dma_chan(chan);
 213 +
 214 +       vchan_free_chan_resources(&c->vc);
 215 +       free_irq(c->irq_number, c);
 216 +
 217 +       dev_dbg(c->vc.chan.device->dev, "Freeing DMA channel %u\n", c->ch);
 218 +}
 219 +
 220 +static size_t bcm2708_dma_desc_size(struct bcm2708_desc *d)
 221 +{
 222 +       return d->size;
 223 +}
 224 +
 225 +static size_t bcm2708_dma_desc_size_pos(struct bcm2708_desc *d, dma_addr_t addr)
 226 +{
 227 +       unsigned i;
 228 +       size_t size;
 229 +
 230 +       for (size = i = 0; i < d->frames; i++) {
 231 +               struct bcm2708_dma_cb *control_block =
 232 +                       &d->control_block_base[i];
 233 +               size_t this_size = control_block->length;
 234 +               dma_addr_t dma;
 235 +
 236 +               if (d->dir == DMA_DEV_TO_MEM)
 237 +                       dma = control_block->dst;
 238 +               else
 239 +                       dma = control_block->src;
 240 +
 241 +               if (size)
 242 +                       size += this_size;
 243 +               else if (addr >= dma && addr < dma + this_size)
 244 +                       size += dma + this_size - addr;
 245 +       }
 246 +
 247 +       return size;
 248 +}
 249 +
 250 +static enum dma_status bcm2708_dma_tx_status(struct dma_chan *chan,
 251 +       dma_cookie_t cookie, struct dma_tx_state *txstate)
 252 +{
 253 +       struct bcm2708_chan *c = to_bcm2708_dma_chan(chan);
 254 +       struct virt_dma_desc *vd;
 255 +       enum dma_status ret;
 256 +       unsigned long flags;
 257 +
 258 +       ret = dma_cookie_status(chan, cookie, txstate);
 259 +       if (ret == DMA_COMPLETE || !txstate)
 260 +               return ret;
 261 +
 262 +       spin_lock_irqsave(&c->vc.lock, flags);
 263 +       vd = vchan_find_desc(&c->vc, cookie);
 264 +       if (vd) {
 265 +               txstate->residue =
 266 +                       bcm2708_dma_desc_size(to_bcm2708_dma_desc(&vd->tx));
 267 +       } else if (c->desc && c->desc->vd.tx.cookie == cookie) {
 268 +               struct bcm2708_desc *d = c->desc;
 269 +               dma_addr_t pos;
 270 +
 271 +               if (d->dir == DMA_MEM_TO_DEV)
 272 +                       pos = readl(c->chan_base + BCM2708_DMA_SOURCE_AD);
 273 +               else if (d->dir == DMA_DEV_TO_MEM)
 274 +                       pos = readl(c->chan_base + BCM2708_DMA_DEST_AD);
 275 +               else
 276 +                       pos = 0;
 277 +
 278 +               txstate->residue = bcm2708_dma_desc_size_pos(d, pos);
 279 +       } else {
 280 +               txstate->residue = 0;
 281 +       }
 282 +
 283 +       spin_unlock_irqrestore(&c->vc.lock, flags);
 284 +
 285 +       return ret;
 286 +}
 287 +
 288 +static void bcm2708_dma_issue_pending(struct dma_chan *chan)
 289 +{
 290 +       struct bcm2708_chan *c = to_bcm2708_dma_chan(chan);
 291 +       unsigned long flags;
 292 +
 293 +       c->cyclic = true; /* Nothing else is implemented */
 294 +
 295 +       spin_lock_irqsave(&c->vc.lock, flags);
 296 +       if (vchan_issue_pending(&c->vc) && !c->desc)
 297 +               bcm2708_dma_start_desc(c);
 298 +
 299 +       spin_unlock_irqrestore(&c->vc.lock, flags);
 300 +}
 301 +
 302 +static struct dma_async_tx_descriptor *bcm2708_dma_prep_dma_cyclic(
 303 +       struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
 304 +       size_t period_len, enum dma_transfer_direction direction,
 305 +       unsigned long flags, void *context)
 306 +{
 307 +       struct bcm2708_chan *c = to_bcm2708_dma_chan(chan);
 308 +       enum dma_slave_buswidth dev_width;
 309 +       struct bcm2708_desc *d;
 310 +       dma_addr_t dev_addr;
 311 +       unsigned es, sync_type;
 312 +       unsigned frame;
 313 +
 314 +       /* Grab configuration */
 315 +       if (direction == DMA_DEV_TO_MEM) {
 316 +               dev_addr = c->cfg.src_addr;
 317 +               dev_width = c->cfg.src_addr_width;
 318 +               sync_type = BCM2708_DMA_S_DREQ;
 319 +       } else if (direction == DMA_MEM_TO_DEV) {
 320 +               dev_addr = c->cfg.dst_addr;
 321 +               dev_width = c->cfg.dst_addr_width;
 322 +               sync_type = BCM2708_DMA_D_DREQ;
 323 +       } else {
 324 +               dev_err(chan->device->dev, "%s: bad direction?\n", __func__);
 325 +               return NULL;
 326 +       }
 327 +
 328 +       /* Bus width translates to the element size (ES) */
 329 +       switch (dev_width) {
 330 +       case DMA_SLAVE_BUSWIDTH_4_BYTES:
 331 +               es = BCM2708_DMA_DATA_TYPE_S32;
 332 +               break;
 333 +       default:
 334 +               return NULL;
 335 +       }
 336 +
 337 +       /* Now allocate and setup the descriptor. */
 338 +       d = kzalloc(sizeof(*d), GFP_NOWAIT);
 339 +       if (!d)
 340 +               return NULL;
 341 +
 342 +       d->dir = direction;
 343 +       d->frames = buf_len / period_len;
 344 +
 345 +       /* Allocate memory for control blocks */
 346 +       d->control_block_size = d->frames * sizeof(struct bcm2708_dma_cb);
 347 +       d->control_block_base = dma_zalloc_coherent(chan->device->dev,
 348 +                       d->control_block_size, &d->control_block_base_phys,
 349 +                       GFP_NOWAIT);
 350 +
 351 +       if (!d->control_block_base) {
 352 +               kfree(d);
 353 +               return NULL;
 354 +       }
 355 +
 356 +       /*
 357 +        * Iterate over all frames, create a control block
 358 +        * for each frame and link them together.
 359 +        */
 360 +       for (frame = 0; frame < d->frames; frame++) {
 361 +               struct bcm2708_dma_cb *control_block =
 362 +                       &d->control_block_base[frame];
 363 +
 364 +               /* Setup adresses */
 365 +               if (d->dir == DMA_DEV_TO_MEM) {
 366 +                       control_block->info = BCM2708_DMA_D_INC;
 367 +                       control_block->src = dev_addr;
 368 +                       control_block->dst = buf_addr + frame * period_len;
 369 +               } else {
 370 +                       control_block->info = BCM2708_DMA_S_INC;
 371 +                       control_block->src = buf_addr + frame * period_len;
 372 +                       control_block->dst = dev_addr;
 373 +               }
 374 +
 375 +               /* Enable interrupt */
 376 +               control_block->info |= BCM2708_DMA_INT_EN;
 377 +
 378 +               /* Setup synchronization */
 379 +               if (sync_type != 0)
 380 +                       control_block->info |= sync_type;
 381 +
 382 +               /* Setup DREQ channel */
 383 +               if (c->cfg.slave_id != 0)
 384 +                       control_block->info |=
 385 +                               BCM2708_DMA_PER_MAP(c->cfg.slave_id);
 386 +
 387 +               /* Length of a frame */
 388 +               control_block->length = period_len;
 389 +               d->size += control_block->length;
 390 +
 391 +               /*
 392 +                * Next block is the next frame.
 393 +                * This DMA engine driver currently only supports cyclic DMA.
 394 +                * Therefore, wrap around at number of frames.
 395 +                */
 396 +               control_block->next = d->control_block_base_phys +
 397 +                       sizeof(struct bcm2708_dma_cb)
 398 +                       * ((frame + 1) % d->frames);
 399 +       }
 400 +
 401 +       return vchan_tx_prep(&c->vc, &d->vd, flags);
 402 +}
 403 +
 404 +static int bcm2708_dma_slave_config(struct bcm2708_chan *c,
 405 +               struct dma_slave_config *cfg)
 406 +{
 407 +       if ((cfg->direction == DMA_DEV_TO_MEM &&
 408 +            cfg->src_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES) ||
 409 +           (cfg->direction == DMA_MEM_TO_DEV &&
 410 +            cfg->dst_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES) ||
 411 +           !is_slave_direction(cfg->direction)) {
 412 +               return -EINVAL;
 413 +       }
 414 +
 415 +       c->cfg = *cfg;
 416 +
 417 +       return 0;
 418 +}
 419 +
 420 +static int bcm2708_dma_terminate_all(struct bcm2708_chan *c)
 421 +{
 422 +       struct bcm2708_dmadev *d = to_bcm2708_dma_dev(c->vc.chan.device);
 423 +       unsigned long flags;
 424 +       int timeout = 10000;
 425 +       LIST_HEAD(head);
 426 +
 427 +       spin_lock_irqsave(&c->vc.lock, flags);
 428 +
 429 +       /* Prevent this channel being scheduled */
 430 +       spin_lock(&d->lock);
 431 +       list_del_init(&c->node);
 432 +       spin_unlock(&d->lock);
 433 +
 434 +       /*
 435 +        * Stop DMA activity: we assume the callback will not be called
 436 +        * after bcm_dma_abort() returns (even if it does, it will see
 437 +        * c->desc is NULL and exit.)
 438 +        */
 439 +       if (c->desc) {
 440 +               c->desc = NULL;
 441 +               bcm_dma_abort(c->chan_base);
 442 +
 443 +               /* Wait for stopping */
 444 +               while (timeout > 0) {
 445 +                       timeout--;
 446 +                       if (!(readl(c->chan_base + BCM2708_DMA_CS) &
 447 +                                               BCM2708_DMA_ACTIVE))
 448 +                               break;
 449 +
 450 +                       cpu_relax();
 451 +               }
 452 +
 453 +               if (timeout <= 0)
 454 +                       dev_err(d->ddev.dev, "DMA transfer could not be terminated\n");
 455 +       }
 456 +
 457 +       vchan_get_all_descriptors(&c->vc, &head);
 458 +       spin_unlock_irqrestore(&c->vc.lock, flags);
 459 +       vchan_dma_desc_free_list(&c->vc, &head);
 460 +
 461 +       return 0;
 462 +}
 463 +
 464 +static int bcm2708_dma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
 465 +       unsigned long arg)
 466 +{
 467 +       struct bcm2708_chan *c = to_bcm2708_dma_chan(chan);
 468 +
 469 +       switch (cmd) {
 470 +       case DMA_SLAVE_CONFIG:
 471 +               return bcm2708_dma_slave_config(c,
 472 +                               (struct dma_slave_config *)arg);
 473 +
 474 +       case DMA_TERMINATE_ALL:
 475 +               return bcm2708_dma_terminate_all(c);
 476 +
 477 +       default:
 478 +               return -ENXIO;
 479 +       }
 480 +}
 481 +
 482 +static int bcm2708_dma_chan_init(struct bcm2708_dmadev *d, void __iomem* chan_base,
 483 +                                                                       int chan_id, int irq)
 484 +{
 485 +       struct bcm2708_chan *c;
 486 +
 487 +       c = devm_kzalloc(d->ddev.dev, sizeof(*c), GFP_KERNEL);
 488 +       if (!c)
 489 +               return -ENOMEM;
 490 +
 491 +       c->vc.desc_free = bcm2708_dma_desc_free;
 492 +       vchan_init(&c->vc, &d->ddev);
 493 +       INIT_LIST_HEAD(&c->node);
 494 +
 495 +       d->ddev.chancnt++;
 496 +
 497 +       c->chan_base = chan_base;
 498 +       c->ch = chan_id;
 499 +       c->irq_number = irq;
 500 +
 501 +       return 0;
 502 +}
 503 +
 504 +static void bcm2708_dma_free(struct bcm2708_dmadev *od)
 505 +{
 506 +       while (!list_empty(&od->ddev.channels)) {
 507 +               struct bcm2708_chan *c = list_first_entry(&od->ddev.channels,
 508 +                       struct bcm2708_chan, vc.chan.device_node);
 509 +
 510 +               list_del(&c->vc.chan.device_node);
 511 +               tasklet_kill(&c->vc.task);
 512 +       }
 513 +}
 514 +
 515 +static int bcm2708_dma_probe(struct platform_device *pdev)
 516 +{
 517 +       struct bcm2708_dmadev *od;
 518 +       int rc, i;
 519 +
 520 +       if (!pdev->dev.dma_mask)
 521 +               pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask;
 522 +
 523 +       rc = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
 524 +       if (rc)
 525 +               return rc;
 526 +       dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
 527 +
 528 +       od = devm_kzalloc(&pdev->dev, sizeof(*od), GFP_KERNEL);
 529 +       if (!od)
 530 +               return -ENOMEM;
 531 +
 532 +       pdev->dev.dma_parms = &od->dma_parms;
 533 +       dma_set_max_seg_size(&pdev->dev, 0x3FFFFFFF);
 534 +
 535 +       dma_cap_set(DMA_SLAVE, od->ddev.cap_mask);
 536 +       dma_cap_set(DMA_CYCLIC, od->ddev.cap_mask);
 537 +       od->ddev.device_alloc_chan_resources = bcm2708_dma_alloc_chan_resources;
 538 +       od->ddev.device_free_chan_resources = bcm2708_dma_free_chan_resources;
 539 +       od->ddev.device_tx_status = bcm2708_dma_tx_status;
 540 +       od->ddev.device_issue_pending = bcm2708_dma_issue_pending;
 541 +       od->ddev.device_prep_dma_cyclic = bcm2708_dma_prep_dma_cyclic;
 542 +       od->ddev.device_control = bcm2708_dma_control;
 543 +       od->ddev.dev = &pdev->dev;
 544 +       INIT_LIST_HEAD(&od->ddev.channels);
 545 +       spin_lock_init(&od->lock);
 546 +
 547 +       platform_set_drvdata(pdev, od);
 548 +
 549 +       for (i = 0; i < 16; i++) {
 550 +               void __iomem* chan_base;
 551 +               int chan_id, irq;
 552 +
 553 +               chan_id = bcm_dma_chan_alloc(BCM_DMA_FEATURE_FAST,
 554 +                       &chan_base,
 555 +                       &irq);
 556 +
 557 +               if (chan_id < 0)
 558 +                       break;
 559 +
 560 +               rc = bcm2708_dma_chan_init(od, chan_base, chan_id, irq);
 561 +               if (rc) {
 562 +                       bcm2708_dma_free(od);
 563 +                       return rc;
 564 +               }
 565 +       }
 566 +
 567 +       rc = dma_async_device_register(&od->ddev);
 568 +       if (rc) {
 569 +               dev_err(&pdev->dev,
 570 +                       "Failed to register slave DMA engine device: %d\n", rc);
 571 +               bcm2708_dma_free(od);
 572 +               return rc;
 573 +       }
 574 +
 575 +       dev_dbg(&pdev->dev, "Load BCM2708 DMA engine driver\n");
 576 +
 577 +       return rc;
 578 +}
 579 +
 580 +static int bcm2708_dma_remove(struct platform_device *pdev)
 581 +{
 582 +       struct bcm2708_dmadev *od = platform_get_drvdata(pdev);
 583 +
 584 +       dma_async_device_unregister(&od->ddev);
 585 +       bcm2708_dma_free(od);
 586 +
 587 +       return 0;
 588 +}
 589 +
 590 +static struct platform_driver bcm2708_dma_driver = {
 591 +       .probe  = bcm2708_dma_probe,
 592 +       .remove = bcm2708_dma_remove,
 593 +       .driver = {
 594 +               .name = "bcm2708-dmaengine",
 595 +               .owner = THIS_MODULE,
 596 +       },
 597 +};
 598 +
 599 +static struct platform_device *pdev;
 600 +
 601 +static const struct platform_device_info bcm2708_dma_dev_info = {
 602 +       .name = "bcm2708-dmaengine",
 603 +       .id = -1,
 604 +};
 605 +
 606 +static int bcm2708_dma_init(void)
 607 +{
 608 +       int rc = platform_driver_register(&bcm2708_dma_driver);
 609 +
 610 +       if (rc == 0) {
 611 +               pdev = platform_device_register_full(&bcm2708_dma_dev_info);
 612 +               if (IS_ERR(pdev)) {
 613 +                       platform_driver_unregister(&bcm2708_dma_driver);
 614 +                       rc = PTR_ERR(pdev);
 615 +               }
 616 +       }
 617 +
 618 +       return rc;
 619 +}
 620 +subsys_initcall(bcm2708_dma_init);
 621 +
 622 +static void __exit bcm2708_dma_exit(void)
 623 +{
 624 +       platform_device_unregister(pdev);
 625 +       platform_driver_unregister(&bcm2708_dma_driver);
 626 +}
 627 +module_exit(bcm2708_dma_exit);
 628 +
 629 +MODULE_ALIAS("platform:bcm2708-dma");
 630 +MODULE_DESCRIPTION("BCM2708 DMA engine driver");
 631 +MODULE_AUTHOR("Florian Meier <florian.meier@koalo.de>");
 632 +MODULE_LICENSE("GPL v2");