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kernel: update 3.18 to 3.18.14
[openwrt/svn-archive/archive.git] / target / linux / brcm2708 / patches-3.18 / 0001-Main-bcm2708-linux-port.patch
1 From 95293790045ab4ae5c357460372dd1b57fc74f29 Mon Sep 17 00:00:00 2001
2 From: popcornmix <popcornmix@gmail.com>
3 Date: Sun, 12 May 2013 12:24:19 +0100
4 Subject: [PATCH 001/114] Main bcm2708 linux port
5
6 Signed-off-by: popcornmix <popcornmix@gmail.com>
7 ---
8 arch/arm/Kconfig | 17 +
9 arch/arm/Kconfig.debug | 8 +
10 arch/arm/Makefile | 1 +
11 arch/arm/configs/bcmrpi_defconfig | 464 ++++++++++++++++
12 arch/arm/kernel/process.c | 10 +
13 arch/arm/mach-bcm2708/Kconfig | 26 +
14 arch/arm/mach-bcm2708/Makefile | 6 +
15 arch/arm/mach-bcm2708/Makefile.boot | 3 +
16 arch/arm/mach-bcm2708/armctrl.c | 208 +++++++
17 arch/arm/mach-bcm2708/armctrl.h | 27 +
18 arch/arm/mach-bcm2708/bcm2708.c | 662 +++++++++++++++++++++++
19 arch/arm/mach-bcm2708/bcm2708.h | 49 ++
20 arch/arm/mach-bcm2708/clock.c | 61 +++
21 arch/arm/mach-bcm2708/clock.h | 24 +
22 arch/arm/mach-bcm2708/dma.c | 399 ++++++++++++++
23 arch/arm/mach-bcm2708/include/mach/arm_control.h | 419 ++++++++++++++
24 arch/arm/mach-bcm2708/include/mach/arm_power.h | 62 +++
25 arch/arm/mach-bcm2708/include/mach/clkdev.h | 7 +
26 arch/arm/mach-bcm2708/include/mach/debug-macro.S | 22 +
27 arch/arm/mach-bcm2708/include/mach/dma.h | 88 +++
28 arch/arm/mach-bcm2708/include/mach/entry-macro.S | 69 +++
29 arch/arm/mach-bcm2708/include/mach/frc.h | 38 ++
30 arch/arm/mach-bcm2708/include/mach/hardware.h | 28 +
31 arch/arm/mach-bcm2708/include/mach/io.h | 27 +
32 arch/arm/mach-bcm2708/include/mach/irqs.h | 196 +++++++
33 arch/arm/mach-bcm2708/include/mach/memory.h | 57 ++
34 arch/arm/mach-bcm2708/include/mach/platform.h | 228 ++++++++
35 arch/arm/mach-bcm2708/include/mach/power.h | 26 +
36 arch/arm/mach-bcm2708/include/mach/system.h | 38 ++
37 arch/arm/mach-bcm2708/include/mach/timex.h | 23 +
38 arch/arm/mach-bcm2708/include/mach/uncompress.h | 84 +++
39 arch/arm/mach-bcm2708/include/mach/vc_mem.h | 35 ++
40 arch/arm/mach-bcm2708/include/mach/vcio.h | 165 ++++++
41 arch/arm/mach-bcm2708/include/mach/vmalloc.h | 20 +
42 arch/arm/mach-bcm2708/power.c | 197 +++++++
43 arch/arm/mach-bcm2708/vc_mem.c | 431 +++++++++++++++
44 arch/arm/mach-bcm2708/vcio.c | 474 ++++++++++++++++
45 arch/arm/mm/Kconfig | 2 +-
46 arch/arm/mm/proc-v6.S | 15 +-
47 arch/arm/tools/mach-types | 1 +
48 drivers/tty/serial/amba-pl011.c | 2 +-
49 include/linux/mmc/host.h | 1 +
50 include/linux/mmc/sdhci.h | 1 +
51 43 files changed, 4716 insertions(+), 5 deletions(-)
52 create mode 100644 arch/arm/configs/bcmrpi_defconfig
53 create mode 100644 arch/arm/mach-bcm2708/Kconfig
54 create mode 100644 arch/arm/mach-bcm2708/Makefile
55 create mode 100644 arch/arm/mach-bcm2708/Makefile.boot
56 create mode 100644 arch/arm/mach-bcm2708/armctrl.c
57 create mode 100644 arch/arm/mach-bcm2708/armctrl.h
58 create mode 100644 arch/arm/mach-bcm2708/bcm2708.c
59 create mode 100644 arch/arm/mach-bcm2708/bcm2708.h
60 create mode 100644 arch/arm/mach-bcm2708/clock.c
61 create mode 100644 arch/arm/mach-bcm2708/clock.h
62 create mode 100644 arch/arm/mach-bcm2708/dma.c
63 create mode 100644 arch/arm/mach-bcm2708/include/mach/arm_control.h
64 create mode 100644 arch/arm/mach-bcm2708/include/mach/arm_power.h
65 create mode 100644 arch/arm/mach-bcm2708/include/mach/clkdev.h
66 create mode 100644 arch/arm/mach-bcm2708/include/mach/debug-macro.S
67 create mode 100644 arch/arm/mach-bcm2708/include/mach/dma.h
68 create mode 100644 arch/arm/mach-bcm2708/include/mach/entry-macro.S
69 create mode 100644 arch/arm/mach-bcm2708/include/mach/frc.h
70 create mode 100644 arch/arm/mach-bcm2708/include/mach/hardware.h
71 create mode 100644 arch/arm/mach-bcm2708/include/mach/io.h
72 create mode 100644 arch/arm/mach-bcm2708/include/mach/irqs.h
73 create mode 100644 arch/arm/mach-bcm2708/include/mach/memory.h
74 create mode 100644 arch/arm/mach-bcm2708/include/mach/platform.h
75 create mode 100644 arch/arm/mach-bcm2708/include/mach/power.h
76 create mode 100644 arch/arm/mach-bcm2708/include/mach/system.h
77 create mode 100644 arch/arm/mach-bcm2708/include/mach/timex.h
78 create mode 100644 arch/arm/mach-bcm2708/include/mach/uncompress.h
79 create mode 100644 arch/arm/mach-bcm2708/include/mach/vc_mem.h
80 create mode 100644 arch/arm/mach-bcm2708/include/mach/vcio.h
81 create mode 100644 arch/arm/mach-bcm2708/include/mach/vmalloc.h
82 create mode 100644 arch/arm/mach-bcm2708/power.c
83 create mode 100644 arch/arm/mach-bcm2708/vc_mem.c
84 create mode 100644 arch/arm/mach-bcm2708/vcio.c
85
86 --- a/arch/arm/Kconfig
87 +++ b/arch/arm/Kconfig
88 @@ -381,6 +381,22 @@ config ARCH_AT91
89 This enables support for systems based on Atmel
90 AT91RM9200 and AT91SAM9* processors.
91
92 +config ARCH_BCM2708
93 + bool "Broadcom BCM2708 family"
94 + select CPU_V6
95 + select ARM_AMBA
96 + select HAVE_CLK
97 + select HAVE_SCHED_CLOCK
98 + select NEED_MACH_GPIO_H
99 + select NEED_MACH_MEMORY_H
100 + select CLKDEV_LOOKUP
101 + select GENERIC_CLOCKEVENTS
102 + select ARM_ERRATA_411920
103 + select MACH_BCM2708
104 + select VC4
105 + help
106 + This enables support for Broadcom BCM2708 boards.
107 +
108 config ARCH_CLPS711X
109 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
110 select ARCH_REQUIRE_GPIOLIB
111 @@ -972,6 +988,7 @@ source "arch/arm/plat-versatile/Kconfig"
112 source "arch/arm/mach-vt8500/Kconfig"
113
114 source "arch/arm/mach-w90x900/Kconfig"
115 +source "arch/arm/mach-bcm2708/Kconfig"
116
117 source "arch/arm/mach-zynq/Kconfig"
118
119 --- a/arch/arm/Kconfig.debug
120 +++ b/arch/arm/Kconfig.debug
121 @@ -985,6 +985,14 @@ choice
122 options; the platform specific options are deprecated
123 and will be soon removed.
124
125 + config DEBUG_BCM2708_UART0
126 + bool "Broadcom BCM2708 UART0 (PL011)"
127 + depends on MACH_BCM2708
128 + help
129 + Say Y here if you want the debug print routines to direct
130 + their output to UART 0. The port must have been initialised
131 + by the boot-loader before use.
132 +
133 endchoice
134
135 config DEBUG_EXYNOS_UART
136 --- a/arch/arm/Makefile
137 +++ b/arch/arm/Makefile
138 @@ -151,6 +151,7 @@ textofs-$(CONFIG_ARCH_AXXIA) := 0x003080
139 machine-$(CONFIG_ARCH_AT91) += at91
140 machine-$(CONFIG_ARCH_AXXIA) += axxia
141 machine-$(CONFIG_ARCH_BCM) += bcm
142 +machine-$(CONFIG_ARCH_BCM2708) += bcm2708
143 machine-$(CONFIG_ARCH_BERLIN) += berlin
144 machine-$(CONFIG_ARCH_CLPS711X) += clps711x
145 machine-$(CONFIG_ARCH_CNS3XXX) += cns3xxx
146 --- /dev/null
147 +++ b/arch/arm/configs/bcmrpi_defconfig
148 @@ -0,0 +1,464 @@
149 +# CONFIG_LOCALVERSION_AUTO is not set
150 +CONFIG_SYSVIPC=y
151 +CONFIG_POSIX_MQUEUE=y
152 +CONFIG_FHANDLE=y
153 +CONFIG_AUDIT=y
154 +CONFIG_NO_HZ=y
155 +CONFIG_HIGH_RES_TIMERS=y
156 +CONFIG_BSD_PROCESS_ACCT=y
157 +CONFIG_BSD_PROCESS_ACCT_V3=y
158 +CONFIG_IKCONFIG=y
159 +CONFIG_IKCONFIG_PROC=y
160 +CONFIG_CGROUP_FREEZER=y
161 +CONFIG_CGROUP_DEVICE=y
162 +CONFIG_CGROUP_CPUACCT=y
163 +CONFIG_RESOURCE_COUNTERS=y
164 +CONFIG_BLK_CGROUP=y
165 +CONFIG_NAMESPACES=y
166 +CONFIG_SCHED_AUTOGROUP=y
167 +CONFIG_EMBEDDED=y
168 +# CONFIG_COMPAT_BRK is not set
169 +CONFIG_SLAB=y
170 +CONFIG_PROFILING=y
171 +CONFIG_OPROFILE=m
172 +CONFIG_KPROBES=y
173 +CONFIG_MODULES=y
174 +CONFIG_MODULE_UNLOAD=y
175 +CONFIG_MODVERSIONS=y
176 +CONFIG_MODULE_SRCVERSION_ALL=y
177 +# CONFIG_BLK_DEV_BSG is not set
178 +CONFIG_BLK_DEV_THROTTLING=y
179 +CONFIG_PARTITION_ADVANCED=y
180 +CONFIG_MAC_PARTITION=y
181 +CONFIG_CFQ_GROUP_IOSCHED=y
182 +CONFIG_ARCH_BCM2708=y
183 +CONFIG_AEABI=y
184 +CONFIG_SECCOMP=y
185 +CONFIG_ZBOOT_ROM_TEXT=0x0
186 +CONFIG_ZBOOT_ROM_BSS=0x0
187 +CONFIG_CMDLINE="dwc_otg.lpm_enable=0 console=ttyAMA0,115200 kgdboc=ttyAMA0,115200 root=/dev/mmcblk0p2 rootfstype=ext3 rootwait"
188 +CONFIG_KEXEC=y
189 +CONFIG_CPU_IDLE=y
190 +CONFIG_VFP=y
191 +CONFIG_BINFMT_MISC=m
192 +CONFIG_NET=y
193 +CONFIG_PACKET=y
194 +CONFIG_UNIX=y
195 +CONFIG_XFRM_USER=y
196 +CONFIG_NET_KEY=m
197 +CONFIG_INET=y
198 +CONFIG_IP_MULTICAST=y
199 +CONFIG_IP_PNP=y
200 +CONFIG_IP_PNP_DHCP=y
201 +CONFIG_IP_PNP_RARP=y
202 +CONFIG_SYN_COOKIES=y
203 +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
204 +# CONFIG_INET_XFRM_MODE_TUNNEL is not set
205 +# CONFIG_INET_XFRM_MODE_BEET is not set
206 +# CONFIG_INET_LRO is not set
207 +# CONFIG_INET_DIAG is not set
208 +# CONFIG_IPV6 is not set
209 +CONFIG_NET_PKTGEN=m
210 +CONFIG_IRDA=m
211 +CONFIG_IRLAN=m
212 +CONFIG_IRCOMM=m
213 +CONFIG_IRDA_ULTRA=y
214 +CONFIG_IRDA_CACHE_LAST_LSAP=y
215 +CONFIG_IRDA_FAST_RR=y
216 +CONFIG_IRTTY_SIR=m
217 +CONFIG_KINGSUN_DONGLE=m
218 +CONFIG_KSDAZZLE_DONGLE=m
219 +CONFIG_KS959_DONGLE=m
220 +CONFIG_USB_IRDA=m
221 +CONFIG_SIGMATEL_FIR=m
222 +CONFIG_MCS_FIR=m
223 +CONFIG_BT=m
224 +CONFIG_BT_RFCOMM=m
225 +CONFIG_BT_RFCOMM_TTY=y
226 +CONFIG_BT_BNEP=m
227 +CONFIG_BT_BNEP_MC_FILTER=y
228 +CONFIG_BT_BNEP_PROTO_FILTER=y
229 +CONFIG_BT_HIDP=m
230 +CONFIG_BT_HCIBTUSB=m
231 +CONFIG_BT_HCIBCM203X=m
232 +CONFIG_BT_HCIBPA10X=m
233 +CONFIG_BT_HCIBFUSB=m
234 +CONFIG_BT_HCIVHCI=m
235 +CONFIG_BT_MRVL=m
236 +CONFIG_BT_MRVL_SDIO=m
237 +CONFIG_BT_ATH3K=m
238 +CONFIG_CFG80211=m
239 +CONFIG_MAC80211=m
240 +CONFIG_MAC80211_MESH=y
241 +CONFIG_WIMAX=m
242 +CONFIG_NET_9P=m
243 +CONFIG_NFC=m
244 +CONFIG_NFC_PN533=m
245 +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
246 +CONFIG_BLK_DEV_LOOP=y
247 +CONFIG_BLK_DEV_CRYPTOLOOP=m
248 +CONFIG_BLK_DEV_NBD=m
249 +CONFIG_BLK_DEV_RAM=y
250 +CONFIG_CDROM_PKTCDVD=m
251 +CONFIG_SCSI=y
252 +# CONFIG_SCSI_PROC_FS is not set
253 +CONFIG_BLK_DEV_SD=m
254 +CONFIG_BLK_DEV_SR=m
255 +# CONFIG_SCSI_LOWLEVEL is not set
256 +CONFIG_MD=y
257 +CONFIG_NETDEVICES=y
258 +CONFIG_NETCONSOLE=m
259 +CONFIG_TUN=m
260 +CONFIG_MDIO_BITBANG=m
261 +CONFIG_PPP=m
262 +CONFIG_PPP_BSDCOMP=m
263 +CONFIG_PPP_DEFLATE=m
264 +CONFIG_PPP_ASYNC=m
265 +CONFIG_PPP_SYNC_TTY=m
266 +CONFIG_SLIP=m
267 +CONFIG_SLIP_COMPRESSED=y
268 +CONFIG_USB_CATC=m
269 +CONFIG_USB_KAWETH=m
270 +CONFIG_USB_PEGASUS=m
271 +CONFIG_USB_RTL8150=m
272 +CONFIG_USB_USBNET=y
273 +CONFIG_USB_NET_AX8817X=m
274 +CONFIG_USB_NET_CDCETHER=m
275 +CONFIG_USB_NET_CDC_EEM=m
276 +CONFIG_USB_NET_DM9601=m
277 +CONFIG_USB_NET_SMSC75XX=m
278 +CONFIG_USB_NET_SMSC95XX=y
279 +CONFIG_USB_NET_GL620A=m
280 +CONFIG_USB_NET_NET1080=m
281 +CONFIG_USB_NET_PLUSB=m
282 +CONFIG_USB_NET_MCS7830=m
283 +CONFIG_USB_NET_CDC_SUBSET=m
284 +CONFIG_USB_ALI_M5632=y
285 +CONFIG_USB_AN2720=y
286 +CONFIG_USB_KC2190=y
287 +# CONFIG_USB_NET_ZAURUS is not set
288 +CONFIG_USB_NET_CX82310_ETH=m
289 +CONFIG_USB_NET_KALMIA=m
290 +CONFIG_USB_NET_INT51X1=m
291 +CONFIG_USB_IPHETH=m
292 +CONFIG_USB_SIERRA_NET=m
293 +CONFIG_USB_VL600=m
294 +CONFIG_LIBERTAS_THINFIRM=m
295 +CONFIG_LIBERTAS_THINFIRM_USB=m
296 +CONFIG_AT76C50X_USB=m
297 +CONFIG_USB_ZD1201=m
298 +CONFIG_USB_NET_RNDIS_WLAN=m
299 +CONFIG_RTL8187=m
300 +CONFIG_MAC80211_HWSIM=m
301 +CONFIG_B43=m
302 +CONFIG_B43LEGACY=m
303 +CONFIG_HOSTAP=m
304 +CONFIG_LIBERTAS=m
305 +CONFIG_LIBERTAS_USB=m
306 +CONFIG_LIBERTAS_SDIO=m
307 +CONFIG_P54_COMMON=m
308 +CONFIG_P54_USB=m
309 +CONFIG_RT2X00=m
310 +CONFIG_RT2500USB=m
311 +CONFIG_RT73USB=m
312 +CONFIG_RT2800USB=m
313 +CONFIG_RT2800USB_RT53XX=y
314 +CONFIG_RTL8192CU=m
315 +CONFIG_ZD1211RW=m
316 +CONFIG_MWIFIEX=m
317 +CONFIG_MWIFIEX_SDIO=m
318 +CONFIG_WIMAX_I2400M_USB=m
319 +CONFIG_INPUT_POLLDEV=m
320 +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
321 +CONFIG_INPUT_JOYDEV=m
322 +CONFIG_INPUT_EVDEV=m
323 +# CONFIG_INPUT_KEYBOARD is not set
324 +# CONFIG_INPUT_MOUSE is not set
325 +CONFIG_INPUT_MISC=y
326 +CONFIG_INPUT_AD714X=m
327 +CONFIG_INPUT_ATI_REMOTE2=m
328 +CONFIG_INPUT_KEYSPAN_REMOTE=m
329 +CONFIG_INPUT_POWERMATE=m
330 +CONFIG_INPUT_YEALINK=m
331 +CONFIG_INPUT_CM109=m
332 +CONFIG_INPUT_UINPUT=m
333 +CONFIG_INPUT_ADXL34X=m
334 +CONFIG_INPUT_CMA3000=m
335 +CONFIG_SERIO=m
336 +CONFIG_SERIO_RAW=m
337 +CONFIG_GAMEPORT=m
338 +CONFIG_GAMEPORT_NS558=m
339 +CONFIG_GAMEPORT_L4=m
340 +# CONFIG_LEGACY_PTYS is not set
341 +# CONFIG_DEVKMEM is not set
342 +CONFIG_SERIAL_AMBA_PL011=y
343 +CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
344 +# CONFIG_HW_RANDOM is not set
345 +CONFIG_RAW_DRIVER=y
346 +# CONFIG_HWMON is not set
347 +CONFIG_WATCHDOG=y
348 +CONFIG_FB=y
349 +CONFIG_FRAMEBUFFER_CONSOLE=y
350 +CONFIG_LOGO=y
351 +# CONFIG_LOGO_LINUX_MONO is not set
352 +# CONFIG_LOGO_LINUX_VGA16 is not set
353 +CONFIG_HID_A4TECH=m
354 +CONFIG_HID_ACRUX=m
355 +CONFIG_HID_APPLE=m
356 +CONFIG_HID_BELKIN=m
357 +CONFIG_HID_CHERRY=m
358 +CONFIG_HID_CHICONY=m
359 +CONFIG_HID_CYPRESS=m
360 +CONFIG_HID_DRAGONRISE=m
361 +CONFIG_HID_EMS_FF=m
362 +CONFIG_HID_ELECOM=m
363 +CONFIG_HID_EZKEY=m
364 +CONFIG_HID_HOLTEK=m
365 +CONFIG_HID_KEYTOUCH=m
366 +CONFIG_HID_KYE=m
367 +CONFIG_HID_UCLOGIC=m
368 +CONFIG_HID_WALTOP=m
369 +CONFIG_HID_GYRATION=m
370 +CONFIG_HID_TWINHAN=m
371 +CONFIG_HID_KENSINGTON=m
372 +CONFIG_HID_LCPOWER=m
373 +CONFIG_HID_LOGITECH=m
374 +CONFIG_HID_MAGICMOUSE=m
375 +CONFIG_HID_MICROSOFT=m
376 +CONFIG_HID_MONTEREY=m
377 +CONFIG_HID_MULTITOUCH=m
378 +CONFIG_HID_NTRIG=m
379 +CONFIG_HID_ORTEK=m
380 +CONFIG_HID_PANTHERLORD=m
381 +CONFIG_HID_PETALYNX=m
382 +CONFIG_HID_PICOLCD=m
383 +CONFIG_HID_ROCCAT=m
384 +CONFIG_HID_SAMSUNG=m
385 +CONFIG_HID_SONY=m
386 +CONFIG_HID_SPEEDLINK=m
387 +CONFIG_HID_SUNPLUS=m
388 +CONFIG_HID_GREENASIA=m
389 +CONFIG_HID_SMARTJOYPLUS=m
390 +CONFIG_HID_TOPSEED=m
391 +CONFIG_HID_THRUSTMASTER=m
392 +CONFIG_HID_WACOM=m
393 +CONFIG_HID_WIIMOTE=m
394 +CONFIG_HID_ZEROPLUS=m
395 +CONFIG_HID_ZYDACRON=m
396 +CONFIG_HID_PID=y
397 +CONFIG_USB_HIDDEV=y
398 +CONFIG_USB=y
399 +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
400 +CONFIG_USB_MON=m
401 +CONFIG_USB_STORAGE=y
402 +CONFIG_USB_STORAGE_REALTEK=m
403 +CONFIG_USB_STORAGE_DATAFAB=m
404 +CONFIG_USB_STORAGE_FREECOM=m
405 +CONFIG_USB_STORAGE_ISD200=m
406 +CONFIG_USB_STORAGE_USBAT=m
407 +CONFIG_USB_STORAGE_SDDR09=m
408 +CONFIG_USB_STORAGE_SDDR55=m
409 +CONFIG_USB_STORAGE_JUMPSHOT=m
410 +CONFIG_USB_STORAGE_ALAUDA=m
411 +CONFIG_USB_STORAGE_ONETOUCH=m
412 +CONFIG_USB_STORAGE_KARMA=m
413 +CONFIG_USB_STORAGE_CYPRESS_ATACB=m
414 +CONFIG_USB_STORAGE_ENE_UB6250=m
415 +CONFIG_USB_UAS=m
416 +CONFIG_USB_MDC800=m
417 +CONFIG_USB_MICROTEK=m
418 +CONFIG_USB_SERIAL=m
419 +CONFIG_USB_SERIAL_GENERIC=y
420 +CONFIG_USB_SERIAL_AIRCABLE=m
421 +CONFIG_USB_SERIAL_ARK3116=m
422 +CONFIG_USB_SERIAL_BELKIN=m
423 +CONFIG_USB_SERIAL_CH341=m
424 +CONFIG_USB_SERIAL_WHITEHEAT=m
425 +CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
426 +CONFIG_USB_SERIAL_CP210X=m
427 +CONFIG_USB_SERIAL_CYPRESS_M8=m
428 +CONFIG_USB_SERIAL_EMPEG=m
429 +CONFIG_USB_SERIAL_FTDI_SIO=m
430 +CONFIG_USB_SERIAL_VISOR=m
431 +CONFIG_USB_SERIAL_IPAQ=m
432 +CONFIG_USB_SERIAL_IR=m
433 +CONFIG_USB_SERIAL_EDGEPORT=m
434 +CONFIG_USB_SERIAL_EDGEPORT_TI=m
435 +CONFIG_USB_SERIAL_GARMIN=m
436 +CONFIG_USB_SERIAL_IPW=m
437 +CONFIG_USB_SERIAL_IUU=m
438 +CONFIG_USB_SERIAL_KEYSPAN_PDA=m
439 +CONFIG_USB_SERIAL_KEYSPAN=m
440 +CONFIG_USB_SERIAL_KLSI=m
441 +CONFIG_USB_SERIAL_KOBIL_SCT=m
442 +CONFIG_USB_SERIAL_MCT_U232=m
443 +CONFIG_USB_SERIAL_MOS7720=m
444 +CONFIG_USB_SERIAL_MOS7840=m
445 +CONFIG_USB_SERIAL_NAVMAN=m
446 +CONFIG_USB_SERIAL_PL2303=m
447 +CONFIG_USB_SERIAL_OTI6858=m
448 +CONFIG_USB_SERIAL_QCAUX=m
449 +CONFIG_USB_SERIAL_QUALCOMM=m
450 +CONFIG_USB_SERIAL_SPCP8X5=m
451 +CONFIG_USB_SERIAL_SAFE=m
452 +CONFIG_USB_SERIAL_SIERRAWIRELESS=m
453 +CONFIG_USB_SERIAL_SYMBOL=m
454 +CONFIG_USB_SERIAL_TI=m
455 +CONFIG_USB_SERIAL_CYBERJACK=m
456 +CONFIG_USB_SERIAL_XIRCOM=m
457 +CONFIG_USB_SERIAL_OPTION=m
458 +CONFIG_USB_SERIAL_OMNINET=m
459 +CONFIG_USB_SERIAL_OPTICON=m
460 +CONFIG_USB_SERIAL_SSU100=m
461 +CONFIG_USB_SERIAL_DEBUG=m
462 +CONFIG_USB_EMI62=m
463 +CONFIG_USB_EMI26=m
464 +CONFIG_USB_ADUTUX=m
465 +CONFIG_USB_SEVSEG=m
466 +CONFIG_USB_RIO500=m
467 +CONFIG_USB_LEGOTOWER=m
468 +CONFIG_USB_LCD=m
469 +CONFIG_USB_LED=m
470 +CONFIG_USB_CYPRESS_CY7C63=m
471 +CONFIG_USB_CYTHERM=m
472 +CONFIG_USB_IDMOUSE=m
473 +CONFIG_USB_FTDI_ELAN=m
474 +CONFIG_USB_APPLEDISPLAY=m
475 +CONFIG_USB_LD=m
476 +CONFIG_USB_TRANCEVIBRATOR=m
477 +CONFIG_USB_IOWARRIOR=m
478 +CONFIG_USB_TEST=m
479 +CONFIG_USB_ISIGHTFW=m
480 +CONFIG_USB_YUREX=m
481 +CONFIG_MMC=y
482 +CONFIG_MMC_SDHCI=y
483 +CONFIG_MMC_SDHCI_PLTFM=y
484 +CONFIG_UIO=m
485 +CONFIG_UIO_PDRV_GENIRQ=m
486 +# CONFIG_IOMMU_SUPPORT is not set
487 +CONFIG_EXT4_FS=y
488 +CONFIG_EXT4_FS_POSIX_ACL=y
489 +CONFIG_EXT4_FS_SECURITY=y
490 +CONFIG_REISERFS_FS=m
491 +CONFIG_REISERFS_FS_XATTR=y
492 +CONFIG_REISERFS_FS_POSIX_ACL=y
493 +CONFIG_REISERFS_FS_SECURITY=y
494 +CONFIG_JFS_FS=m
495 +CONFIG_JFS_POSIX_ACL=y
496 +CONFIG_JFS_SECURITY=y
497 +CONFIG_JFS_STATISTICS=y
498 +CONFIG_XFS_FS=m
499 +CONFIG_XFS_QUOTA=y
500 +CONFIG_XFS_POSIX_ACL=y
501 +CONFIG_XFS_RT=y
502 +CONFIG_GFS2_FS=m
503 +CONFIG_OCFS2_FS=m
504 +CONFIG_BTRFS_FS=m
505 +CONFIG_BTRFS_FS_POSIX_ACL=y
506 +CONFIG_NILFS2_FS=m
507 +CONFIG_FANOTIFY=y
508 +CONFIG_AUTOFS4_FS=y
509 +CONFIG_FUSE_FS=m
510 +CONFIG_CUSE=m
511 +CONFIG_FSCACHE=y
512 +CONFIG_FSCACHE_STATS=y
513 +CONFIG_FSCACHE_HISTOGRAM=y
514 +CONFIG_CACHEFILES=y
515 +CONFIG_ISO9660_FS=m
516 +CONFIG_JOLIET=y
517 +CONFIG_ZISOFS=y
518 +CONFIG_UDF_FS=m
519 +CONFIG_MSDOS_FS=y
520 +CONFIG_VFAT_FS=y
521 +CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
522 +CONFIG_NTFS_FS=m
523 +CONFIG_TMPFS=y
524 +CONFIG_TMPFS_POSIX_ACL=y
525 +CONFIG_CONFIGFS_FS=y
526 +CONFIG_SQUASHFS=m
527 +CONFIG_SQUASHFS_XATTR=y
528 +CONFIG_SQUASHFS_LZO=y
529 +CONFIG_SQUASHFS_XZ=y
530 +CONFIG_NFS_FS=y
531 +CONFIG_NFS_V3_ACL=y
532 +CONFIG_NFS_V4=y
533 +CONFIG_ROOT_NFS=y
534 +CONFIG_NFS_FSCACHE=y
535 +CONFIG_CIFS=m
536 +CONFIG_CIFS_WEAK_PW_HASH=y
537 +CONFIG_CIFS_XATTR=y
538 +CONFIG_CIFS_POSIX=y
539 +CONFIG_9P_FS=m
540 +CONFIG_9P_FS_POSIX_ACL=y
541 +CONFIG_NLS_DEFAULT="utf8"
542 +CONFIG_NLS_CODEPAGE_437=y
543 +CONFIG_NLS_CODEPAGE_737=m
544 +CONFIG_NLS_CODEPAGE_775=m
545 +CONFIG_NLS_CODEPAGE_850=m
546 +CONFIG_NLS_CODEPAGE_852=m
547 +CONFIG_NLS_CODEPAGE_855=m
548 +CONFIG_NLS_CODEPAGE_857=m
549 +CONFIG_NLS_CODEPAGE_860=m
550 +CONFIG_NLS_CODEPAGE_861=m
551 +CONFIG_NLS_CODEPAGE_862=m
552 +CONFIG_NLS_CODEPAGE_863=m
553 +CONFIG_NLS_CODEPAGE_864=m
554 +CONFIG_NLS_CODEPAGE_865=m
555 +CONFIG_NLS_CODEPAGE_866=m
556 +CONFIG_NLS_CODEPAGE_869=m
557 +CONFIG_NLS_CODEPAGE_936=m
558 +CONFIG_NLS_CODEPAGE_950=m
559 +CONFIG_NLS_CODEPAGE_932=m
560 +CONFIG_NLS_CODEPAGE_949=m
561 +CONFIG_NLS_CODEPAGE_874=m
562 +CONFIG_NLS_ISO8859_8=m
563 +CONFIG_NLS_CODEPAGE_1250=m
564 +CONFIG_NLS_CODEPAGE_1251=m
565 +CONFIG_NLS_ASCII=y
566 +CONFIG_NLS_ISO8859_1=m
567 +CONFIG_NLS_ISO8859_2=m
568 +CONFIG_NLS_ISO8859_3=m
569 +CONFIG_NLS_ISO8859_4=m
570 +CONFIG_NLS_ISO8859_5=m
571 +CONFIG_NLS_ISO8859_6=m
572 +CONFIG_NLS_ISO8859_7=m
573 +CONFIG_NLS_ISO8859_9=m
574 +CONFIG_NLS_ISO8859_13=m
575 +CONFIG_NLS_ISO8859_14=m
576 +CONFIG_NLS_ISO8859_15=m
577 +CONFIG_NLS_KOI8_R=m
578 +CONFIG_NLS_KOI8_U=m
579 +CONFIG_NLS_UTF8=m
580 +CONFIG_PRINTK_TIME=y
581 +CONFIG_BOOT_PRINTK_DELAY=y
582 +CONFIG_DEBUG_INFO=y
583 +CONFIG_DEBUG_STACK_USAGE=y
584 +CONFIG_DEBUG_MEMORY_INIT=y
585 +CONFIG_DETECT_HUNG_TASK=y
586 +CONFIG_TIMER_STATS=y
587 +CONFIG_LATENCYTOP=y
588 +CONFIG_IRQSOFF_TRACER=y
589 +CONFIG_SCHED_TRACER=y
590 +CONFIG_STACK_TRACER=y
591 +CONFIG_BLK_DEV_IO_TRACE=y
592 +CONFIG_FUNCTION_PROFILER=y
593 +CONFIG_KGDB=y
594 +CONFIG_KGDB_KDB=y
595 +CONFIG_KDB_KEYBOARD=y
596 +CONFIG_STRICT_DEVMEM=y
597 +CONFIG_CRYPTO_AUTHENC=m
598 +CONFIG_CRYPTO_CBC=y
599 +CONFIG_CRYPTO_HMAC=y
600 +CONFIG_CRYPTO_XCBC=m
601 +CONFIG_CRYPTO_MD5=y
602 +CONFIG_CRYPTO_SHA1=y
603 +CONFIG_CRYPTO_SHA512=m
604 +CONFIG_CRYPTO_TGR192=m
605 +CONFIG_CRYPTO_WP512=m
606 +CONFIG_CRYPTO_CAST5=m
607 +CONFIG_CRYPTO_DES=y
608 +CONFIG_CRYPTO_DEFLATE=m
609 +# CONFIG_CRYPTO_ANSI_CPRNG is not set
610 +# CONFIG_CRYPTO_HW is not set
611 +CONFIG_CRC_ITU_T=y
612 +CONFIG_LIBCRC32C=y
613 --- a/arch/arm/kernel/process.c
614 +++ b/arch/arm/kernel/process.c
615 @@ -172,6 +172,16 @@ void arch_cpu_idle_dead(void)
616 }
617 #endif
618
619 +char bcm2708_reboot_mode = 'h';
620 +
621 +int __init reboot_setup(char *str)
622 +{
623 + bcm2708_reboot_mode = str[0];
624 + return 1;
625 +}
626 +
627 +__setup("reboot=", reboot_setup);
628 +
629 /*
630 * Called by kexec, immediately prior to machine_kexec().
631 *
632 --- /dev/null
633 +++ b/arch/arm/mach-bcm2708/Kconfig
634 @@ -0,0 +1,26 @@
635 +menu "Broadcom BCM2708 Implementations"
636 + depends on ARCH_BCM2708
637 +
638 +config MACH_BCM2708
639 + bool "Broadcom BCM2708 Development Platform"
640 + select NEED_MACH_MEMORY_H
641 + select NEED_MACH_IO_H
642 + select CPU_V6
643 + help
644 + Include support for the Broadcom(R) BCM2708 platform.
645 +
646 +config BCM2708_VCMEM
647 + bool "Videocore Memory"
648 + depends on MACH_BCM2708
649 + default y
650 + help
651 + Helper for videocore memory access and total size allocation.
652 +
653 +config BCM2708_NOL2CACHE
654 + bool "Videocore L2 cache disable"
655 + depends on MACH_BCM2708
656 + default n
657 + help
658 + Do not allow ARM to use GPU's L2 cache. Requires disable_l2cache in config.txt.
659 +
660 +endmenu
661 --- /dev/null
662 +++ b/arch/arm/mach-bcm2708/Makefile
663 @@ -0,0 +1,6 @@
664 +#
665 +# Makefile for the linux kernel.
666 +#
667 +
668 +obj-$(CONFIG_MACH_BCM2708) += clock.o bcm2708.o armctrl.o vcio.o power.o dma.o
669 +obj-$(CONFIG_BCM2708_VCMEM) += vc_mem.o
670 --- /dev/null
671 +++ b/arch/arm/mach-bcm2708/Makefile.boot
672 @@ -0,0 +1,3 @@
673 + zreladdr-y := 0x00008000
674 +params_phys-y := 0x00000100
675 +initrd_phys-y := 0x00800000
676 --- /dev/null
677 +++ b/arch/arm/mach-bcm2708/armctrl.c
678 @@ -0,0 +1,208 @@
679 +/*
680 + * linux/arch/arm/mach-bcm2708/armctrl.c
681 + *
682 + * Copyright (C) 2010 Broadcom
683 + *
684 + * This program is free software; you can redistribute it and/or modify
685 + * it under the terms of the GNU General Public License as published by
686 + * the Free Software Foundation; either version 2 of the License, or
687 + * (at your option) any later version.
688 + *
689 + * This program is distributed in the hope that it will be useful,
690 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
691 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
692 + * GNU General Public License for more details.
693 + *
694 + * You should have received a copy of the GNU General Public License
695 + * along with this program; if not, write to the Free Software
696 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
697 + */
698 +#include <linux/init.h>
699 +#include <linux/list.h>
700 +#include <linux/io.h>
701 +#include <linux/version.h>
702 +#include <linux/syscore_ops.h>
703 +#include <linux/interrupt.h>
704 +
705 +#include <asm/mach/irq.h>
706 +#include <mach/hardware.h>
707 +#include "armctrl.h"
708 +
709 +/* For support of kernels >= 3.0 assume only one VIC for now*/
710 +static unsigned int remap_irqs[(INTERRUPT_ARASANSDIO + 1) - INTERRUPT_JPEG] = {
711 + INTERRUPT_VC_JPEG,
712 + INTERRUPT_VC_USB,
713 + INTERRUPT_VC_3D,
714 + INTERRUPT_VC_DMA2,
715 + INTERRUPT_VC_DMA3,
716 + INTERRUPT_VC_I2C,
717 + INTERRUPT_VC_SPI,
718 + INTERRUPT_VC_I2SPCM,
719 + INTERRUPT_VC_SDIO,
720 + INTERRUPT_VC_UART,
721 + INTERRUPT_VC_ARASANSDIO
722 +};
723 +
724 +static void armctrl_mask_irq(struct irq_data *d)
725 +{
726 + static const unsigned int disables[4] = {
727 + ARM_IRQ_DIBL1,
728 + ARM_IRQ_DIBL2,
729 + ARM_IRQ_DIBL3,
730 + 0
731 + };
732 +
733 + unsigned int data = (unsigned int)irq_get_chip_data(d->irq);
734 + writel(1 << (data & 0x1f), __io_address(disables[(data >> 5) & 0x3]));
735 +}
736 +
737 +static void armctrl_unmask_irq(struct irq_data *d)
738 +{
739 + static const unsigned int enables[4] = {
740 + ARM_IRQ_ENBL1,
741 + ARM_IRQ_ENBL2,
742 + ARM_IRQ_ENBL3,
743 + 0
744 + };
745 +
746 + unsigned int data = (unsigned int)irq_get_chip_data(d->irq);
747 + writel(1 << (data & 0x1f), __io_address(enables[(data >> 5) & 0x3]));
748 +}
749 +
750 +#if defined(CONFIG_PM)
751 +
752 +/* for kernels 3.xx use the new syscore_ops apis but for older kernels use the sys dev class */
753 +
754 +/* Static defines
755 + * struct armctrl_device - VIC PM device (< 3.xx)
756 + * @sysdev: The system device which is registered. (< 3.xx)
757 + * @irq: The IRQ number for the base of the VIC.
758 + * @base: The register base for the VIC.
759 + * @resume_sources: A bitmask of interrupts for resume.
760 + * @resume_irqs: The IRQs enabled for resume.
761 + * @int_select: Save for VIC_INT_SELECT.
762 + * @int_enable: Save for VIC_INT_ENABLE.
763 + * @soft_int: Save for VIC_INT_SOFT.
764 + * @protect: Save for VIC_PROTECT.
765 + */
766 +struct armctrl_info {
767 + void __iomem *base;
768 + int irq;
769 + u32 resume_sources;
770 + u32 resume_irqs;
771 + u32 int_select;
772 + u32 int_enable;
773 + u32 soft_int;
774 + u32 protect;
775 +} armctrl;
776 +
777 +static int armctrl_suspend(void)
778 +{
779 + return 0;
780 +}
781 +
782 +static void armctrl_resume(void)
783 +{
784 + return;
785 +}
786 +
787 +/**
788 + * armctrl_pm_register - Register a VIC for later power management control
789 + * @base: The base address of the VIC.
790 + * @irq: The base IRQ for the VIC.
791 + * @resume_sources: bitmask of interrupts allowed for resume sources.
792 + *
793 + * For older kernels (< 3.xx) do -
794 + * Register the VIC with the system device tree so that it can be notified
795 + * of suspend and resume requests and ensure that the correct actions are
796 + * taken to re-instate the settings on resume.
797 + */
798 +static void __init armctrl_pm_register(void __iomem * base, unsigned int irq,
799 + u32 resume_sources)
800 +{
801 + armctrl.base = base;
802 + armctrl.resume_sources = resume_sources;
803 + armctrl.irq = irq;
804 +}
805 +
806 +static int armctrl_set_wake(struct irq_data *d, unsigned int on)
807 +{
808 + unsigned int off = d->irq & 31;
809 + u32 bit = 1 << off;
810 +
811 + if (!(bit & armctrl.resume_sources))
812 + return -EINVAL;
813 +
814 + if (on)
815 + armctrl.resume_irqs |= bit;
816 + else
817 + armctrl.resume_irqs &= ~bit;
818 +
819 + return 0;
820 +}
821 +
822 +#else
823 +static inline void armctrl_pm_register(void __iomem * base, unsigned int irq,
824 + u32 arg1)
825 +{
826 +}
827 +
828 +#define armctrl_suspend NULL
829 +#define armctrl_resume NULL
830 +#define armctrl_set_wake NULL
831 +#endif /* CONFIG_PM */
832 +
833 +static struct syscore_ops armctrl_syscore_ops = {
834 + .suspend = armctrl_suspend,
835 + .resume = armctrl_resume,
836 +};
837 +
838 +/**
839 + * armctrl_syscore_init - initicall to register VIC pm functions
840 + *
841 + * This is called via late_initcall() to register
842 + * the resources for the VICs due to the early
843 + * nature of the VIC's registration.
844 +*/
845 +static int __init armctrl_syscore_init(void)
846 +{
847 + register_syscore_ops(&armctrl_syscore_ops);
848 + return 0;
849 +}
850 +
851 +late_initcall(armctrl_syscore_init);
852 +
853 +static struct irq_chip armctrl_chip = {
854 + .name = "ARMCTRL",
855 + .irq_ack = NULL,
856 + .irq_mask = armctrl_mask_irq,
857 + .irq_unmask = armctrl_unmask_irq,
858 + .irq_set_wake = armctrl_set_wake,
859 +};
860 +
861 +/**
862 + * armctrl_init - initialise a vectored interrupt controller
863 + * @base: iomem base address
864 + * @irq_start: starting interrupt number, must be muliple of 32
865 + * @armctrl_sources: bitmask of interrupt sources to allow
866 + * @resume_sources: bitmask of interrupt sources to allow for resume
867 + */
868 +int __init armctrl_init(void __iomem * base, unsigned int irq_start,
869 + u32 armctrl_sources, u32 resume_sources)
870 +{
871 + unsigned int irq;
872 +
873 + for (irq = 0; irq < BCM2708_ALLOC_IRQS; irq++) {
874 + unsigned int data = irq;
875 + if (irq >= INTERRUPT_JPEG && irq <= INTERRUPT_ARASANSDIO)
876 + data = remap_irqs[irq - INTERRUPT_JPEG];
877 +
878 + irq_set_chip(irq, &armctrl_chip);
879 + irq_set_chip_data(irq, (void *)data);
880 + irq_set_handler(irq, handle_level_irq);
881 + set_irq_flags(irq, IRQF_VALID | IRQF_PROBE | IRQF_DISABLED);
882 + }
883 +
884 + armctrl_pm_register(base, irq_start, resume_sources);
885 + return 0;
886 +}
887 --- /dev/null
888 +++ b/arch/arm/mach-bcm2708/armctrl.h
889 @@ -0,0 +1,27 @@
890 +/*
891 + * linux/arch/arm/mach-bcm2708/armctrl.h
892 + *
893 + * Copyright (C) 2010 Broadcom
894 + *
895 + * This program is free software; you can redistribute it and/or modify
896 + * it under the terms of the GNU General Public License as published by
897 + * the Free Software Foundation; either version 2 of the License, or
898 + * (at your option) any later version.
899 + *
900 + * This program is distributed in the hope that it will be useful,
901 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
902 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
903 + * GNU General Public License for more details.
904 + *
905 + * You should have received a copy of the GNU General Public License
906 + * along with this program; if not, write to the Free Software
907 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
908 + */
909 +
910 +#ifndef __BCM2708_ARMCTRL_H
911 +#define __BCM2708_ARMCTRL_H
912 +
913 +extern int __init armctrl_init(void __iomem * base, unsigned int irq_start,
914 + u32 armctrl_sources, u32 resume_sources);
915 +
916 +#endif
917 --- /dev/null
918 +++ b/arch/arm/mach-bcm2708/bcm2708.c
919 @@ -0,0 +1,662 @@
920 +/*
921 + * linux/arch/arm/mach-bcm2708/bcm2708.c
922 + *
923 + * Copyright (C) 2010 Broadcom
924 + *
925 + * This program is free software; you can redistribute it and/or modify
926 + * it under the terms of the GNU General Public License as published by
927 + * the Free Software Foundation; either version 2 of the License, or
928 + * (at your option) any later version.
929 + *
930 + * This program is distributed in the hope that it will be useful,
931 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
932 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
933 + * GNU General Public License for more details.
934 + *
935 + * You should have received a copy of the GNU General Public License
936 + * along with this program; if not, write to the Free Software
937 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
938 + */
939 +
940 +#include <linux/init.h>
941 +#include <linux/device.h>
942 +#include <linux/dma-mapping.h>
943 +#include <linux/serial_8250.h>
944 +#include <linux/platform_device.h>
945 +#include <linux/syscore_ops.h>
946 +#include <linux/interrupt.h>
947 +#include <linux/amba/bus.h>
948 +#include <linux/amba/clcd.h>
949 +#include <linux/clockchips.h>
950 +#include <linux/cnt32_to_63.h>
951 +#include <linux/io.h>
952 +#include <linux/module.h>
953 +
954 +#include <linux/version.h>
955 +#include <linux/clkdev.h>
956 +#include <asm/system_info.h>
957 +#include <mach/hardware.h>
958 +#include <asm/irq.h>
959 +#include <linux/leds.h>
960 +#include <asm/mach-types.h>
961 +#include <linux/sched_clock.h>
962 +
963 +#include <asm/mach/arch.h>
964 +#include <asm/mach/flash.h>
965 +#include <asm/mach/irq.h>
966 +#include <asm/mach/time.h>
967 +#include <asm/mach/map.h>
968 +
969 +#include <mach/timex.h>
970 +#include <mach/dma.h>
971 +#include <mach/vcio.h>
972 +#include <mach/system.h>
973 +
974 +#include <linux/delay.h>
975 +
976 +#include "bcm2708.h"
977 +#include "armctrl.h"
978 +#include "clock.h"
979 +
980 +#ifdef CONFIG_BCM_VC_CMA
981 +#include <linux/broadcom/vc_cma.h>
982 +#endif
983 +
984 +
985 +/* Effectively we have an IOMMU (ARM<->VideoCore map) that is set up to
986 + * give us IO access only to 64Mbytes of physical memory (26 bits). We could
987 + * represent this window by setting our dmamasks to 26 bits but, in fact
988 + * we're not going to use addresses outside this range (they're not in real
989 + * memory) so we don't bother.
990 + *
991 + * In the future we might include code to use this IOMMU to remap other
992 + * physical addresses onto VideoCore memory then the use of 32-bits would be
993 + * more legitimate.
994 + */
995 +#define DMA_MASK_BITS_COMMON 32
996 +
997 +/* command line parameters */
998 +static unsigned boardrev, serial;
999 +static unsigned uart_clock;
1000 +static unsigned disk_led_gpio = 16;
1001 +static unsigned disk_led_active_low = 1;
1002 +static unsigned reboot_part = 0;
1003 +
1004 +static void __init bcm2708_init_led(void);
1005 +
1006 +void __init bcm2708_init_irq(void)
1007 +{
1008 + armctrl_init(__io_address(ARMCTRL_IC_BASE), 0, 0, 0);
1009 +}
1010 +
1011 +static struct map_desc bcm2708_io_desc[] __initdata = {
1012 + {
1013 + .virtual = IO_ADDRESS(ARMCTRL_BASE),
1014 + .pfn = __phys_to_pfn(ARMCTRL_BASE),
1015 + .length = SZ_4K,
1016 + .type = MT_DEVICE},
1017 + {
1018 + .virtual = IO_ADDRESS(UART0_BASE),
1019 + .pfn = __phys_to_pfn(UART0_BASE),
1020 + .length = SZ_4K,
1021 + .type = MT_DEVICE},
1022 + {
1023 + .virtual = IO_ADDRESS(UART1_BASE),
1024 + .pfn = __phys_to_pfn(UART1_BASE),
1025 + .length = SZ_4K,
1026 + .type = MT_DEVICE},
1027 + {
1028 + .virtual = IO_ADDRESS(DMA_BASE),
1029 + .pfn = __phys_to_pfn(DMA_BASE),
1030 + .length = SZ_4K,
1031 + .type = MT_DEVICE},
1032 + {
1033 + .virtual = IO_ADDRESS(MCORE_BASE),
1034 + .pfn = __phys_to_pfn(MCORE_BASE),
1035 + .length = SZ_4K,
1036 + .type = MT_DEVICE},
1037 + {
1038 + .virtual = IO_ADDRESS(ST_BASE),
1039 + .pfn = __phys_to_pfn(ST_BASE),
1040 + .length = SZ_4K,
1041 + .type = MT_DEVICE},
1042 + {
1043 + .virtual = IO_ADDRESS(USB_BASE),
1044 + .pfn = __phys_to_pfn(USB_BASE),
1045 + .length = SZ_128K,
1046 + .type = MT_DEVICE},
1047 + {
1048 + .virtual = IO_ADDRESS(PM_BASE),
1049 + .pfn = __phys_to_pfn(PM_BASE),
1050 + .length = SZ_4K,
1051 + .type = MT_DEVICE},
1052 + {
1053 + .virtual = IO_ADDRESS(GPIO_BASE),
1054 + .pfn = __phys_to_pfn(GPIO_BASE),
1055 + .length = SZ_4K,
1056 + .type = MT_DEVICE}
1057 +};
1058 +
1059 +void __init bcm2708_map_io(void)
1060 +{
1061 + iotable_init(bcm2708_io_desc, ARRAY_SIZE(bcm2708_io_desc));
1062 +}
1063 +
1064 +/* The STC is a free running counter that increments at the rate of 1MHz */
1065 +#define STC_FREQ_HZ 1000000
1066 +
1067 +static inline uint32_t timer_read(void)
1068 +{
1069 + /* STC: a free running counter that increments at the rate of 1MHz */
1070 + return readl(__io_address(ST_BASE + 0x04));
1071 +}
1072 +
1073 +static unsigned long bcm2708_read_current_timer(void)
1074 +{
1075 + return timer_read();
1076 +}
1077 +
1078 +static u64 notrace bcm2708_read_sched_clock(void)
1079 +{
1080 + return timer_read();
1081 +}
1082 +
1083 +static cycle_t clksrc_read(struct clocksource *cs)
1084 +{
1085 + return timer_read();
1086 +}
1087 +
1088 +static struct clocksource clocksource_stc = {
1089 + .name = "stc",
1090 + .rating = 300,
1091 + .read = clksrc_read,
1092 + .mask = CLOCKSOURCE_MASK(32),
1093 + .flags = CLOCK_SOURCE_IS_CONTINUOUS,
1094 +};
1095 +
1096 +unsigned long frc_clock_ticks32(void)
1097 +{
1098 + return timer_read();
1099 +}
1100 +
1101 +static void __init bcm2708_clocksource_init(void)
1102 +{
1103 + if (clocksource_register_hz(&clocksource_stc, STC_FREQ_HZ)) {
1104 + printk(KERN_ERR "timer: failed to initialize clock "
1105 + "source %s\n", clocksource_stc.name);
1106 + }
1107 +}
1108 +
1109 +
1110 +/*
1111 + * These are fixed clocks.
1112 + */
1113 +static struct clk ref24_clk = {
1114 + .rate = UART0_CLOCK, /* The UART is clocked at 3MHz via APB_CLK */
1115 +};
1116 +
1117 +static struct clk osc_clk = {
1118 +#ifdef CONFIG_ARCH_BCM2708_CHIPIT
1119 + .rate = 27000000,
1120 +#else
1121 + .rate = 500000000, /* ARM clock is set from the VideoCore booter */
1122 +#endif
1123 +};
1124 +
1125 +/* warning - the USB needs a clock > 34MHz */
1126 +
1127 +#ifdef CONFIG_MMC_BCM2708
1128 +static struct clk sdhost_clk = {
1129 +#ifdef CONFIG_ARCH_BCM2708_CHIPIT
1130 + .rate = 4000000, /* 4MHz */
1131 +#else
1132 + .rate = 250000000, /* 250MHz */
1133 +#endif
1134 +};
1135 +#endif
1136 +
1137 +static struct clk_lookup lookups[] = {
1138 + { /* UART0 */
1139 + .dev_id = "dev:f1",
1140 + .clk = &ref24_clk,
1141 + },
1142 + { /* USB */
1143 + .dev_id = "bcm2708_usb",
1144 + .clk = &osc_clk,
1145 + }
1146 +};
1147 +
1148 +#define UART0_IRQ { IRQ_UART, 0 /*NO_IRQ*/ }
1149 +#define UART0_DMA { 15, 14 }
1150 +
1151 +AMBA_DEVICE(uart0, "dev:f1", UART0, NULL);
1152 +
1153 +static struct amba_device *amba_devs[] __initdata = {
1154 + &uart0_device,
1155 +};
1156 +
1157 +static struct resource bcm2708_dmaman_resources[] = {
1158 + {
1159 + .start = DMA_BASE,
1160 + .end = DMA_BASE + SZ_4K - 1,
1161 + .flags = IORESOURCE_MEM,
1162 + }
1163 +};
1164 +
1165 +static struct platform_device bcm2708_dmaman_device = {
1166 + .name = BCM_DMAMAN_DRIVER_NAME,
1167 + .id = 0, /* first bcm2708_dma */
1168 + .resource = bcm2708_dmaman_resources,
1169 + .num_resources = ARRAY_SIZE(bcm2708_dmaman_resources),
1170 +};
1171 +
1172 +static u64 fb_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON);
1173 +
1174 +static struct platform_device bcm2708_fb_device = {
1175 + .name = "bcm2708_fb",
1176 + .id = -1, /* only one bcm2708_fb */
1177 + .resource = NULL,
1178 + .num_resources = 0,
1179 + .dev = {
1180 + .dma_mask = &fb_dmamask,
1181 + .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON),
1182 + },
1183 +};
1184 +
1185 +static struct plat_serial8250_port bcm2708_uart1_platform_data[] = {
1186 + {
1187 + .mapbase = UART1_BASE + 0x40,
1188 + .irq = IRQ_AUX,
1189 + .uartclk = 125000000,
1190 + .regshift = 2,
1191 + .iotype = UPIO_MEM,
1192 + .flags = UPF_FIXED_TYPE | UPF_IOREMAP | UPF_SKIP_TEST,
1193 + .type = PORT_8250,
1194 + },
1195 + {},
1196 +};
1197 +
1198 +static struct platform_device bcm2708_uart1_device = {
1199 + .name = "serial8250",
1200 + .id = PLAT8250_DEV_PLATFORM,
1201 + .dev = {
1202 + .platform_data = bcm2708_uart1_platform_data,
1203 + },
1204 +};
1205 +
1206 +static struct resource bcm2708_usb_resources[] = {
1207 + [0] = {
1208 + .start = USB_BASE,
1209 + .end = USB_BASE + SZ_128K - 1,
1210 + .flags = IORESOURCE_MEM,
1211 + },
1212 + [1] = {
1213 + .start = IRQ_USB,
1214 + .end = IRQ_USB,
1215 + .flags = IORESOURCE_IRQ,
1216 + },
1217 +};
1218 +
1219 +static u64 usb_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON);
1220 +
1221 +static struct platform_device bcm2708_usb_device = {
1222 + .name = "bcm2708_usb",
1223 + .id = -1, /* only one bcm2708_usb */
1224 + .resource = bcm2708_usb_resources,
1225 + .num_resources = ARRAY_SIZE(bcm2708_usb_resources),
1226 + .dev = {
1227 + .dma_mask = &usb_dmamask,
1228 + .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON),
1229 + },
1230 +};
1231 +
1232 +static struct resource bcm2708_vcio_resources[] = {
1233 + [0] = { /* mailbox/semaphore/doorbell access */
1234 + .start = MCORE_BASE,
1235 + .end = MCORE_BASE + SZ_4K - 1,
1236 + .flags = IORESOURCE_MEM,
1237 + },
1238 +};
1239 +
1240 +static u64 vcio_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON);
1241 +
1242 +static struct platform_device bcm2708_vcio_device = {
1243 + .name = BCM_VCIO_DRIVER_NAME,
1244 + .id = -1, /* only one VideoCore I/O area */
1245 + .resource = bcm2708_vcio_resources,
1246 + .num_resources = ARRAY_SIZE(bcm2708_vcio_resources),
1247 + .dev = {
1248 + .dma_mask = &vcio_dmamask,
1249 + .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON),
1250 + },
1251 +};
1252 +
1253 +static struct resource bcm2708_systemtimer_resources[] = {
1254 + [0] = { /* system timer access */
1255 + .start = ST_BASE,
1256 + .end = ST_BASE + SZ_4K - 1,
1257 + .flags = IORESOURCE_MEM,
1258 + },
1259 + {
1260 + .start = IRQ_TIMER3,
1261 + .end = IRQ_TIMER3,
1262 + .flags = IORESOURCE_IRQ,
1263 + }
1264 +
1265 +};
1266 +
1267 +static u64 systemtimer_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON);
1268 +
1269 +static struct platform_device bcm2708_systemtimer_device = {
1270 + .name = "bcm2708_systemtimer",
1271 + .id = -1, /* only one VideoCore I/O area */
1272 + .resource = bcm2708_systemtimer_resources,
1273 + .num_resources = ARRAY_SIZE(bcm2708_systemtimer_resources),
1274 + .dev = {
1275 + .dma_mask = &systemtimer_dmamask,
1276 + .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON),
1277 + },
1278 +};
1279 +
1280 +static struct resource bcm2708_powerman_resources[] = {
1281 + [0] = {
1282 + .start = PM_BASE,
1283 + .end = PM_BASE + SZ_256 - 1,
1284 + .flags = IORESOURCE_MEM,
1285 + },
1286 +};
1287 +
1288 +static u64 powerman_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON);
1289 +
1290 +struct platform_device bcm2708_powerman_device = {
1291 + .name = "bcm2708_powerman",
1292 + .id = 0,
1293 + .num_resources = ARRAY_SIZE(bcm2708_powerman_resources),
1294 + .resource = bcm2708_powerman_resources,
1295 + .dev = {
1296 + .dma_mask = &powerman_dmamask,
1297 + .coherent_dma_mask = 0xffffffffUL},
1298 +};
1299 +
1300 +int __init bcm_register_device(struct platform_device *pdev)
1301 +{
1302 + int ret;
1303 +
1304 + ret = platform_device_register(pdev);
1305 + if (ret)
1306 + pr_debug("Unable to register platform device '%s': %d\n",
1307 + pdev->name, ret);
1308 +
1309 + return ret;
1310 +}
1311 +
1312 +int calc_rsts(int partition)
1313 +{
1314 + return PM_PASSWORD |
1315 + ((partition & (1 << 0)) << 0) |
1316 + ((partition & (1 << 1)) << 1) |
1317 + ((partition & (1 << 2)) << 2) |
1318 + ((partition & (1 << 3)) << 3) |
1319 + ((partition & (1 << 4)) << 4) |
1320 + ((partition & (1 << 5)) << 5);
1321 +}
1322 +
1323 +static void bcm2708_restart(enum reboot_mode mode, const char *cmd)
1324 +{
1325 + extern char bcm2708_reboot_mode;
1326 + uint32_t pm_rstc, pm_wdog;
1327 + uint32_t timeout = 10;
1328 + uint32_t pm_rsts = 0;
1329 +
1330 + if(bcm2708_reboot_mode == 'q')
1331 + {
1332 + // NOOBS < 1.3 booting with reboot=q
1333 + pm_rsts = readl(__io_address(PM_RSTS));
1334 + pm_rsts = PM_PASSWORD | pm_rsts | PM_RSTS_HADWRQ_SET;
1335 + }
1336 + else if(bcm2708_reboot_mode == 'p')
1337 + {
1338 + // NOOBS < 1.3 halting
1339 + pm_rsts = readl(__io_address(PM_RSTS));
1340 + pm_rsts = PM_PASSWORD | pm_rsts | PM_RSTS_HADWRH_SET;
1341 + }
1342 + else
1343 + {
1344 + pm_rsts = calc_rsts(reboot_part);
1345 + }
1346 +
1347 + writel(pm_rsts, __io_address(PM_RSTS));
1348 +
1349 + /* Setup watchdog for reset */
1350 + pm_rstc = readl(__io_address(PM_RSTC));
1351 +
1352 + pm_wdog = PM_PASSWORD | (timeout & PM_WDOG_TIME_SET); // watchdog timer = timer clock / 16; need password (31:16) + value (11:0)
1353 + pm_rstc = PM_PASSWORD | (pm_rstc & PM_RSTC_WRCFG_CLR) | PM_RSTC_WRCFG_FULL_RESET;
1354 +
1355 + writel(pm_wdog, __io_address(PM_WDOG));
1356 + writel(pm_rstc, __io_address(PM_RSTC));
1357 +}
1358 +
1359 +/* We can't really power off, but if we do the normal reset scheme, and indicate to bootcode.bin not to reboot, then most of the chip will be powered off */
1360 +static void bcm2708_power_off(void)
1361 +{
1362 + extern char bcm2708_reboot_mode;
1363 + if(bcm2708_reboot_mode == 'q')
1364 + {
1365 + // NOOBS < v1.3
1366 + bcm2708_restart('p', "");
1367 + }
1368 + else
1369 + {
1370 + /* partition 63 is special code for HALT the bootloader knows not to boot*/
1371 + reboot_part = 63;
1372 + /* continue with normal reset mechanism */
1373 + bcm2708_restart(0, "");
1374 + }
1375 +}
1376 +
1377 +void __init bcm2708_init(void)
1378 +{
1379 + int i;
1380 +
1381 +#if defined(CONFIG_BCM_VC_CMA)
1382 + vc_cma_early_init();
1383 +#endif
1384 + printk("bcm2708.uart_clock = %d\n", uart_clock);
1385 + pm_power_off = bcm2708_power_off;
1386 +
1387 + if (uart_clock)
1388 + lookups[0].clk->rate = uart_clock;
1389 +
1390 + for (i = 0; i < ARRAY_SIZE(lookups); i++)
1391 + clkdev_add(&lookups[i]);
1392 +
1393 + bcm_register_device(&bcm2708_dmaman_device);
1394 + bcm_register_device(&bcm2708_vcio_device);
1395 + bcm_register_device(&bcm2708_systemtimer_device);
1396 + bcm_register_device(&bcm2708_fb_device);
1397 + bcm_register_device(&bcm2708_usb_device);
1398 + bcm_register_device(&bcm2708_uart1_device);
1399 + bcm_register_device(&bcm2708_powerman_device);
1400 +
1401 + bcm2708_init_led();
1402 +
1403 + for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
1404 + struct amba_device *d = amba_devs[i];
1405 + amba_device_register(d, &iomem_resource);
1406 + }
1407 + system_rev = boardrev;
1408 + system_serial_low = serial;
1409 +}
1410 +
1411 +static void timer_set_mode(enum clock_event_mode mode,
1412 + struct clock_event_device *clk)
1413 +{
1414 + switch (mode) {
1415 + case CLOCK_EVT_MODE_ONESHOT: /* Leave the timer disabled, .set_next_event will enable it */
1416 + case CLOCK_EVT_MODE_SHUTDOWN:
1417 + break;
1418 + case CLOCK_EVT_MODE_PERIODIC:
1419 +
1420 + case CLOCK_EVT_MODE_UNUSED:
1421 + case CLOCK_EVT_MODE_RESUME:
1422 +
1423 + default:
1424 + printk(KERN_ERR "timer_set_mode: unhandled mode:%d\n",
1425 + (int)mode);
1426 + break;
1427 + }
1428 +
1429 +}
1430 +
1431 +static int timer_set_next_event(unsigned long cycles,
1432 + struct clock_event_device *unused)
1433 +{
1434 + unsigned long stc;
1435 + do {
1436 + stc = readl(__io_address(ST_BASE + 0x04));
1437 + /* We could take a FIQ here, which may push ST above STC3 */
1438 + writel(stc + cycles, __io_address(ST_BASE + 0x18));
1439 + } while ((signed long) cycles >= 0 &&
1440 + (signed long) (readl(__io_address(ST_BASE + 0x04)) - stc)
1441 + >= (signed long) cycles);
1442 + return 0;
1443 +}
1444 +
1445 +static struct clock_event_device timer0_clockevent = {
1446 + .name = "timer0",
1447 + .shift = 32,
1448 + .features = CLOCK_EVT_FEAT_ONESHOT,
1449 + .set_mode = timer_set_mode,
1450 + .set_next_event = timer_set_next_event,
1451 +};
1452 +
1453 +/*
1454 + * IRQ handler for the timer
1455 + */
1456 +static irqreturn_t bcm2708_timer_interrupt(int irq, void *dev_id)
1457 +{
1458 + struct clock_event_device *evt = &timer0_clockevent;
1459 +
1460 + writel(1 << 3, __io_address(ST_BASE + 0x00)); /* stcs clear timer int */
1461 +
1462 + evt->event_handler(evt);
1463 +
1464 + return IRQ_HANDLED;
1465 +}
1466 +
1467 +static struct irqaction bcm2708_timer_irq = {
1468 + .name = "BCM2708 Timer Tick",
1469 + .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
1470 + .handler = bcm2708_timer_interrupt,
1471 +};
1472 +
1473 +/*
1474 + * Set up timer interrupt, and return the current time in seconds.
1475 + */
1476 +
1477 +static struct delay_timer bcm2708_delay_timer = {
1478 + .read_current_timer = bcm2708_read_current_timer,
1479 + .freq = STC_FREQ_HZ,
1480 +};
1481 +
1482 +static void __init bcm2708_timer_init(void)
1483 +{
1484 + /* init high res timer */
1485 + bcm2708_clocksource_init();
1486 +
1487 + /*
1488 + * Initialise to a known state (all timers off)
1489 + */
1490 + writel(0, __io_address(ARM_T_CONTROL));
1491 + /*
1492 + * Make irqs happen for the system timer
1493 + */
1494 + setup_irq(IRQ_TIMER3, &bcm2708_timer_irq);
1495 +
1496 + sched_clock_register(bcm2708_read_sched_clock, 32, STC_FREQ_HZ);
1497 +
1498 + timer0_clockevent.mult =
1499 + div_sc(STC_FREQ_HZ, NSEC_PER_SEC, timer0_clockevent.shift);
1500 + timer0_clockevent.max_delta_ns =
1501 + clockevent_delta2ns(0xffffffff, &timer0_clockevent);
1502 + timer0_clockevent.min_delta_ns =
1503 + clockevent_delta2ns(0xf, &timer0_clockevent);
1504 +
1505 + timer0_clockevent.cpumask = cpumask_of(0);
1506 + clockevents_register_device(&timer0_clockevent);
1507 +
1508 + register_current_timer_delay(&bcm2708_delay_timer);
1509 +}
1510 +
1511 +#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
1512 +#include <linux/leds.h>
1513 +
1514 +static struct gpio_led bcm2708_leds[] = {
1515 + [0] = {
1516 + .gpio = 16,
1517 + .name = "led0",
1518 + .default_trigger = "mmc0",
1519 + .active_low = 1,
1520 + },
1521 +};
1522 +
1523 +static struct gpio_led_platform_data bcm2708_led_pdata = {
1524 + .num_leds = ARRAY_SIZE(bcm2708_leds),
1525 + .leds = bcm2708_leds,
1526 +};
1527 +
1528 +static struct platform_device bcm2708_led_device = {
1529 + .name = "leds-gpio",
1530 + .id = -1,
1531 + .dev = {
1532 + .platform_data = &bcm2708_led_pdata,
1533 + },
1534 +};
1535 +
1536 +static void __init bcm2708_init_led(void)
1537 +{
1538 + bcm2708_leds[0].gpio = disk_led_gpio;
1539 + bcm2708_leds[0].active_low = disk_led_active_low;
1540 + platform_device_register(&bcm2708_led_device);
1541 +}
1542 +#else
1543 +static inline void bcm2708_init_led(void)
1544 +{
1545 +}
1546 +#endif
1547 +
1548 +void __init bcm2708_init_early(void)
1549 +{
1550 + /*
1551 + * Some devices allocate their coherent buffers from atomic
1552 + * context. Increase size of atomic coherent pool to make sure such
1553 + * the allocations won't fail.
1554 + */
1555 + init_dma_coherent_pool_size(SZ_4M);
1556 +}
1557 +
1558 +static void __init board_reserve(void)
1559 +{
1560 +#if defined(CONFIG_BCM_VC_CMA)
1561 + vc_cma_reserve();
1562 +#endif
1563 +}
1564 +
1565 +MACHINE_START(BCM2708, "BCM2708")
1566 + /* Maintainer: Broadcom Europe Ltd. */
1567 + .map_io = bcm2708_map_io,
1568 + .init_irq = bcm2708_init_irq,
1569 + .init_time = bcm2708_timer_init,
1570 + .init_machine = bcm2708_init,
1571 + .init_early = bcm2708_init_early,
1572 + .reserve = board_reserve,
1573 + .restart = bcm2708_restart,
1574 +MACHINE_END
1575 +
1576 +module_param(boardrev, uint, 0644);
1577 +module_param(serial, uint, 0644);
1578 +module_param(uart_clock, uint, 0644);
1579 +module_param(disk_led_gpio, uint, 0644);
1580 +module_param(disk_led_active_low, uint, 0644);
1581 +module_param(reboot_part, uint, 0644);
1582 --- /dev/null
1583 +++ b/arch/arm/mach-bcm2708/bcm2708.h
1584 @@ -0,0 +1,49 @@
1585 +/*
1586 + * linux/arch/arm/mach-bcm2708/bcm2708.h
1587 + *
1588 + * BCM2708 machine support header
1589 + *
1590 + * Copyright (C) 2010 Broadcom
1591 + *
1592 + * This program is free software; you can redistribute it and/or modify
1593 + * it under the terms of the GNU General Public License as published by
1594 + * the Free Software Foundation; either version 2 of the License, or
1595 + * (at your option) any later version.
1596 + *
1597 + * This program is distributed in the hope that it will be useful,
1598 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1599 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1600 + * GNU General Public License for more details.
1601 + *
1602 + * You should have received a copy of the GNU General Public License
1603 + * along with this program; if not, write to the Free Software
1604 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
1605 + */
1606 +
1607 +#ifndef __BCM2708_BCM2708_H
1608 +#define __BCM2708_BCM2708_H
1609 +
1610 +#include <linux/amba/bus.h>
1611 +
1612 +extern void __init bcm2708_init(void);
1613 +extern void __init bcm2708_init_irq(void);
1614 +extern void __init bcm2708_map_io(void);
1615 +extern struct sys_timer bcm2708_timer;
1616 +extern unsigned int mmc_status(struct device *dev);
1617 +
1618 +#define AMBA_DEVICE(name, busid, base, plat) \
1619 +static struct amba_device name##_device = { \
1620 + .dev = { \
1621 + .coherent_dma_mask = ~0, \
1622 + .init_name = busid, \
1623 + .platform_data = plat, \
1624 + }, \
1625 + .res = { \
1626 + .start = base##_BASE, \
1627 + .end = (base##_BASE) + SZ_4K - 1,\
1628 + .flags = IORESOURCE_MEM, \
1629 + }, \
1630 + .irq = base##_IRQ, \
1631 +}
1632 +
1633 +#endif
1634 --- /dev/null
1635 +++ b/arch/arm/mach-bcm2708/clock.c
1636 @@ -0,0 +1,61 @@
1637 +/*
1638 + * linux/arch/arm/mach-bcm2708/clock.c
1639 + *
1640 + * Copyright (C) 2010 Broadcom
1641 + *
1642 + * This program is free software; you can redistribute it and/or modify
1643 + * it under the terms of the GNU General Public License as published by
1644 + * the Free Software Foundation; either version 2 of the License, or
1645 + * (at your option) any later version.
1646 + *
1647 + * This program is distributed in the hope that it will be useful,
1648 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1649 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1650 + * GNU General Public License for more details.
1651 + *
1652 + * You should have received a copy of the GNU General Public License
1653 + * along with this program; if not, write to the Free Software
1654 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
1655 + */
1656 +#include <linux/module.h>
1657 +#include <linux/kernel.h>
1658 +#include <linux/device.h>
1659 +#include <linux/list.h>
1660 +#include <linux/errno.h>
1661 +#include <linux/err.h>
1662 +#include <linux/string.h>
1663 +#include <linux/clk.h>
1664 +#include <linux/mutex.h>
1665 +
1666 +#include <asm/clkdev.h>
1667 +
1668 +#include "clock.h"
1669 +
1670 +int clk_enable(struct clk *clk)
1671 +{
1672 + return 0;
1673 +}
1674 +EXPORT_SYMBOL(clk_enable);
1675 +
1676 +void clk_disable(struct clk *clk)
1677 +{
1678 +}
1679 +EXPORT_SYMBOL(clk_disable);
1680 +
1681 +unsigned long clk_get_rate(struct clk *clk)
1682 +{
1683 + return clk->rate;
1684 +}
1685 +EXPORT_SYMBOL(clk_get_rate);
1686 +
1687 +long clk_round_rate(struct clk *clk, unsigned long rate)
1688 +{
1689 + return clk->rate;
1690 +}
1691 +EXPORT_SYMBOL(clk_round_rate);
1692 +
1693 +int clk_set_rate(struct clk *clk, unsigned long rate)
1694 +{
1695 + return -EIO;
1696 +}
1697 +EXPORT_SYMBOL(clk_set_rate);
1698 --- /dev/null
1699 +++ b/arch/arm/mach-bcm2708/clock.h
1700 @@ -0,0 +1,24 @@
1701 +/*
1702 + * linux/arch/arm/mach-bcm2708/clock.h
1703 + *
1704 + * Copyright (C) 2010 Broadcom
1705 + *
1706 + * This program is free software; you can redistribute it and/or modify
1707 + * it under the terms of the GNU General Public License as published by
1708 + * the Free Software Foundation; either version 2 of the License, or
1709 + * (at your option) any later version.
1710 + *
1711 + * This program is distributed in the hope that it will be useful,
1712 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1713 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1714 + * GNU General Public License for more details.
1715 + *
1716 + * You should have received a copy of the GNU General Public License
1717 + * along with this program; if not, write to the Free Software
1718 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
1719 + */
1720 +struct module;
1721 +
1722 +struct clk {
1723 + unsigned long rate;
1724 +};
1725 --- /dev/null
1726 +++ b/arch/arm/mach-bcm2708/dma.c
1727 @@ -0,0 +1,399 @@
1728 +/*
1729 + * linux/arch/arm/mach-bcm2708/dma.c
1730 + *
1731 + * Copyright (C) 2010 Broadcom
1732 + *
1733 + * This program is free software; you can redistribute it and/or modify
1734 + * it under the terms of the GNU General Public License version 2 as
1735 + * published by the Free Software Foundation.
1736 + */
1737 +
1738 +#include <linux/slab.h>
1739 +#include <linux/device.h>
1740 +#include <linux/platform_device.h>
1741 +#include <linux/module.h>
1742 +#include <linux/scatterlist.h>
1743 +
1744 +#include <mach/dma.h>
1745 +#include <mach/irqs.h>
1746 +
1747 +/*****************************************************************************\
1748 + * *
1749 + * Configuration *
1750 + * *
1751 +\*****************************************************************************/
1752 +
1753 +#define CACHE_LINE_MASK 31
1754 +#define DRIVER_NAME BCM_DMAMAN_DRIVER_NAME
1755 +#define DEFAULT_DMACHAN_BITMAP 0x10 /* channel 4 only */
1756 +
1757 +/* valid only for channels 0 - 14, 15 has its own base address */
1758 +#define BCM2708_DMA_CHAN(n) ((n)<<8) /* base address */
1759 +#define BCM2708_DMA_CHANIO(dma_base, n) \
1760 + ((void __iomem *)((char *)(dma_base)+BCM2708_DMA_CHAN(n)))
1761 +
1762 +
1763 +/*****************************************************************************\
1764 + * *
1765 + * DMA Auxilliary Functions *
1766 + * *
1767 +\*****************************************************************************/
1768 +
1769 +/* A DMA buffer on an arbitrary boundary may separate a cache line into a
1770 + section inside the DMA buffer and another section outside it.
1771 + Even if we flush DMA buffers from the cache there is always the chance that
1772 + during a DMA someone will access the part of a cache line that is outside
1773 + the DMA buffer - which will then bring in unwelcome data.
1774 + Without being able to dictate our own buffer pools we must insist that
1775 + DMA buffers consist of a whole number of cache lines.
1776 +*/
1777 +
1778 +extern int
1779 +bcm_sg_suitable_for_dma(struct scatterlist *sg_ptr, int sg_len)
1780 +{
1781 + int i;
1782 +
1783 + for (i = 0; i < sg_len; i++) {
1784 + if (sg_ptr[i].offset & CACHE_LINE_MASK ||
1785 + sg_ptr[i].length & CACHE_LINE_MASK)
1786 + return 0;
1787 + }
1788 +
1789 + return 1;
1790 +}
1791 +EXPORT_SYMBOL_GPL(bcm_sg_suitable_for_dma);
1792 +
1793 +extern void
1794 +bcm_dma_start(void __iomem *dma_chan_base, dma_addr_t control_block)
1795 +{
1796 + dsb(); /* ARM data synchronization (push) operation */
1797 +
1798 + writel(control_block, dma_chan_base + BCM2708_DMA_ADDR);
1799 + writel(BCM2708_DMA_ACTIVE, dma_chan_base + BCM2708_DMA_CS);
1800 +}
1801 +
1802 +extern void bcm_dma_wait_idle(void __iomem *dma_chan_base)
1803 +{
1804 + dsb();
1805 +
1806 + /* ugly busy wait only option for now */
1807 + while (readl(dma_chan_base + BCM2708_DMA_CS) & BCM2708_DMA_ACTIVE)
1808 + cpu_relax();
1809 +}
1810 +
1811 +EXPORT_SYMBOL_GPL(bcm_dma_start);
1812 +
1813 +/* Complete an ongoing DMA (assuming its results are to be ignored)
1814 + Does nothing if there is no DMA in progress.
1815 + This routine waits for the current AXI transfer to complete before
1816 + terminating the current DMA. If the current transfer is hung on a DREQ used
1817 + by an uncooperative peripheral the AXI transfer may never complete. In this
1818 + case the routine times out and return a non-zero error code.
1819 + Use of this routine doesn't guarantee that the ongoing or aborted DMA
1820 + does not produce an interrupt.
1821 +*/
1822 +extern int
1823 +bcm_dma_abort(void __iomem *dma_chan_base)
1824 +{
1825 + unsigned long int cs;
1826 + int rc = 0;
1827 +
1828 + cs = readl(dma_chan_base + BCM2708_DMA_CS);
1829 +
1830 + if (BCM2708_DMA_ACTIVE & cs) {
1831 + long int timeout = 10000;
1832 +
1833 + /* write 0 to the active bit - pause the DMA */
1834 + writel(0, dma_chan_base + BCM2708_DMA_CS);
1835 +
1836 + /* wait for any current AXI transfer to complete */
1837 + while (0 != (cs & BCM2708_DMA_ISPAUSED) && --timeout >= 0)
1838 + cs = readl(dma_chan_base + BCM2708_DMA_CS);
1839 +
1840 + if (0 != (cs & BCM2708_DMA_ISPAUSED)) {
1841 + /* we'll un-pause when we set of our next DMA */
1842 + rc = -ETIMEDOUT;
1843 +
1844 + } else if (BCM2708_DMA_ACTIVE & cs) {
1845 + /* terminate the control block chain */
1846 + writel(0, dma_chan_base + BCM2708_DMA_NEXTCB);
1847 +
1848 + /* abort the whole DMA */
1849 + writel(BCM2708_DMA_ABORT | BCM2708_DMA_ACTIVE,
1850 + dma_chan_base + BCM2708_DMA_CS);
1851 + }
1852 + }
1853 +
1854 + return rc;
1855 +}
1856 +EXPORT_SYMBOL_GPL(bcm_dma_abort);
1857 +
1858 +
1859 +/***************************************************************************** \
1860 + * *
1861 + * DMA Manager Device Methods *
1862 + * *
1863 +\*****************************************************************************/
1864 +
1865 +struct vc_dmaman {
1866 + void __iomem *dma_base;
1867 + u32 chan_available; /* bitmap of available channels */
1868 + u32 has_feature[BCM_DMA_FEATURE_COUNT]; /* bitmap of feature presence */
1869 +};
1870 +
1871 +static void vc_dmaman_init(struct vc_dmaman *dmaman, void __iomem *dma_base,
1872 + u32 chans_available)
1873 +{
1874 + dmaman->dma_base = dma_base;
1875 + dmaman->chan_available = chans_available;
1876 + dmaman->has_feature[BCM_DMA_FEATURE_FAST_ORD] = 0x0c; /* chans 2 & 3 */
1877 + dmaman->has_feature[BCM_DMA_FEATURE_BULK_ORD] = 0x01; /* chan 0 */
1878 +}
1879 +
1880 +static int vc_dmaman_chan_alloc(struct vc_dmaman *dmaman,
1881 + unsigned preferred_feature_set)
1882 +{
1883 + u32 chans;
1884 + int feature;
1885 +
1886 + chans = dmaman->chan_available;
1887 + for (feature = 0; feature < BCM_DMA_FEATURE_COUNT; feature++)
1888 + /* select the subset of available channels with the desired
1889 + feature so long as some of the candidate channels have that
1890 + feature */
1891 + if ((preferred_feature_set & (1 << feature)) &&
1892 + (chans & dmaman->has_feature[feature]))
1893 + chans &= dmaman->has_feature[feature];
1894 +
1895 + if (chans) {
1896 + int chan = 0;
1897 + /* return the ordinal of the first channel in the bitmap */
1898 + while (chans != 0 && (chans & 1) == 0) {
1899 + chans >>= 1;
1900 + chan++;
1901 + }
1902 + /* claim the channel */
1903 + dmaman->chan_available &= ~(1 << chan);
1904 + return chan;
1905 + } else
1906 + return -ENOMEM;
1907 +}
1908 +
1909 +static int vc_dmaman_chan_free(struct vc_dmaman *dmaman, int chan)
1910 +{
1911 + if (chan < 0)
1912 + return -EINVAL;
1913 + else if ((1 << chan) & dmaman->chan_available)
1914 + return -EIDRM;
1915 + else {
1916 + dmaman->chan_available |= (1 << chan);
1917 + return 0;
1918 + }
1919 +}
1920 +
1921 +/*****************************************************************************\
1922 + * *
1923 + * DMA IRQs *
1924 + * *
1925 +\*****************************************************************************/
1926 +
1927 +static unsigned char bcm_dma_irqs[] = {
1928 + IRQ_DMA0,
1929 + IRQ_DMA1,
1930 + IRQ_DMA2,
1931 + IRQ_DMA3,
1932 + IRQ_DMA4,
1933 + IRQ_DMA5,
1934 + IRQ_DMA6,
1935 + IRQ_DMA7,
1936 + IRQ_DMA8,
1937 + IRQ_DMA9,
1938 + IRQ_DMA10,
1939 + IRQ_DMA11,
1940 + IRQ_DMA12
1941 +};
1942 +
1943 +
1944 +/***************************************************************************** \
1945 + * *
1946 + * DMA Manager Monitor *
1947 + * *
1948 +\*****************************************************************************/
1949 +
1950 +static struct device *dmaman_dev; /* we assume there's only one! */
1951 +
1952 +extern int bcm_dma_chan_alloc(unsigned preferred_feature_set,
1953 + void __iomem **out_dma_base, int *out_dma_irq)
1954 +{
1955 + if (!dmaman_dev)
1956 + return -ENODEV;
1957 + else {
1958 + struct vc_dmaman *dmaman = dev_get_drvdata(dmaman_dev);
1959 + int rc;
1960 +
1961 + device_lock(dmaman_dev);
1962 + rc = vc_dmaman_chan_alloc(dmaman, preferred_feature_set);
1963 + if (rc >= 0) {
1964 + *out_dma_base = BCM2708_DMA_CHANIO(dmaman->dma_base,
1965 + rc);
1966 + *out_dma_irq = bcm_dma_irqs[rc];
1967 + }
1968 + device_unlock(dmaman_dev);
1969 +
1970 + return rc;
1971 + }
1972 +}
1973 +EXPORT_SYMBOL_GPL(bcm_dma_chan_alloc);
1974 +
1975 +extern int bcm_dma_chan_free(int channel)
1976 +{
1977 + if (dmaman_dev) {
1978 + struct vc_dmaman *dmaman = dev_get_drvdata(dmaman_dev);
1979 + int rc;
1980 +
1981 + device_lock(dmaman_dev);
1982 + rc = vc_dmaman_chan_free(dmaman, channel);
1983 + device_unlock(dmaman_dev);
1984 +
1985 + return rc;
1986 + } else
1987 + return -ENODEV;
1988 +}
1989 +EXPORT_SYMBOL_GPL(bcm_dma_chan_free);
1990 +
1991 +static int dev_dmaman_register(const char *dev_name, struct device *dev)
1992 +{
1993 + int rc = dmaman_dev ? -EINVAL : 0;
1994 + dmaman_dev = dev;
1995 + return rc;
1996 +}
1997 +
1998 +static void dev_dmaman_deregister(const char *dev_name, struct device *dev)
1999 +{
2000 + dmaman_dev = NULL;
2001 +}
2002 +
2003 +/*****************************************************************************\
2004 + * *
2005 + * DMA Device *
2006 + * *
2007 +\*****************************************************************************/
2008 +
2009 +static int dmachans = -1; /* module parameter */
2010 +
2011 +static int bcm_dmaman_probe(struct platform_device *pdev)
2012 +{
2013 + int ret = 0;
2014 + struct vc_dmaman *dmaman;
2015 + struct resource *dma_res = NULL;
2016 + void __iomem *dma_base = NULL;
2017 + int have_dma_region = 0;
2018 +
2019 + dmaman = kzalloc(sizeof(*dmaman), GFP_KERNEL);
2020 + if (NULL == dmaman) {
2021 + printk(KERN_ERR DRIVER_NAME ": failed to allocate "
2022 + "DMA management memory\n");
2023 + ret = -ENOMEM;
2024 + } else {
2025 +
2026 + dma_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2027 + if (dma_res == NULL) {
2028 + printk(KERN_ERR DRIVER_NAME ": failed to obtain memory "
2029 + "resource\n");
2030 + ret = -ENODEV;
2031 + } else if (!request_mem_region(dma_res->start,
2032 + resource_size(dma_res),
2033 + DRIVER_NAME)) {
2034 + dev_err(&pdev->dev, "cannot obtain DMA region\n");
2035 + ret = -EBUSY;
2036 + } else {
2037 + have_dma_region = 1;
2038 + dma_base = ioremap(dma_res->start,
2039 + resource_size(dma_res));
2040 + if (!dma_base) {
2041 + dev_err(&pdev->dev, "cannot map DMA region\n");
2042 + ret = -ENOMEM;
2043 + } else {
2044 + /* use module parameter if one was provided */
2045 + if (dmachans > 0)
2046 + vc_dmaman_init(dmaman, dma_base,
2047 + dmachans);
2048 + else
2049 + vc_dmaman_init(dmaman, dma_base,
2050 + DEFAULT_DMACHAN_BITMAP);
2051 +
2052 + platform_set_drvdata(pdev, dmaman);
2053 + dev_dmaman_register(DRIVER_NAME, &pdev->dev);
2054 +
2055 + printk(KERN_INFO DRIVER_NAME ": DMA manager "
2056 + "at %p\n", dma_base);
2057 + }
2058 + }
2059 + }
2060 + if (ret != 0) {
2061 + if (dma_base)
2062 + iounmap(dma_base);
2063 + if (dma_res && have_dma_region)
2064 + release_mem_region(dma_res->start,
2065 + resource_size(dma_res));
2066 + if (dmaman)
2067 + kfree(dmaman);
2068 + }
2069 + return ret;
2070 +}
2071 +
2072 +static int bcm_dmaman_remove(struct platform_device *pdev)
2073 +{
2074 + struct vc_dmaman *dmaman = platform_get_drvdata(pdev);
2075 +
2076 + platform_set_drvdata(pdev, NULL);
2077 + dev_dmaman_deregister(DRIVER_NAME, &pdev->dev);
2078 + kfree(dmaman);
2079 +
2080 + return 0;
2081 +}
2082 +
2083 +static struct platform_driver bcm_dmaman_driver = {
2084 + .probe = bcm_dmaman_probe,
2085 + .remove = bcm_dmaman_remove,
2086 +
2087 + .driver = {
2088 + .name = DRIVER_NAME,
2089 + .owner = THIS_MODULE,
2090 + },
2091 +};
2092 +
2093 +/*****************************************************************************\
2094 + * *
2095 + * Driver init/exit *
2096 + * *
2097 +\*****************************************************************************/
2098 +
2099 +static int __init bcm_dmaman_drv_init(void)
2100 +{
2101 + int ret;
2102 +
2103 + ret = platform_driver_register(&bcm_dmaman_driver);
2104 + if (ret != 0) {
2105 + printk(KERN_ERR DRIVER_NAME ": failed to register "
2106 + "on platform\n");
2107 + }
2108 +
2109 + return ret;
2110 +}
2111 +
2112 +static void __exit bcm_dmaman_drv_exit(void)
2113 +{
2114 + platform_driver_unregister(&bcm_dmaman_driver);
2115 +}
2116 +
2117 +module_init(bcm_dmaman_drv_init);
2118 +module_exit(bcm_dmaman_drv_exit);
2119 +
2120 +module_param(dmachans, int, 0644);
2121 +
2122 +MODULE_AUTHOR("Gray Girling <grayg@broadcom.com>");
2123 +MODULE_DESCRIPTION("DMA channel manager driver");
2124 +MODULE_LICENSE("GPL");
2125 +
2126 +MODULE_PARM_DESC(dmachans, "Bitmap of DMA channels available to the ARM");
2127 --- /dev/null
2128 +++ b/arch/arm/mach-bcm2708/include/mach/arm_control.h
2129 @@ -0,0 +1,419 @@
2130 +/*
2131 + * linux/arch/arm/mach-bcm2708/arm_control.h
2132 + *
2133 + * Copyright (C) 2010 Broadcom
2134 + *
2135 + * This program is free software; you can redistribute it and/or modify
2136 + * it under the terms of the GNU General Public License as published by
2137 + * the Free Software Foundation; either version 2 of the License, or
2138 + * (at your option) any later version.
2139 + *
2140 + * This program is distributed in the hope that it will be useful,
2141 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2142 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2143 + * GNU General Public License for more details.
2144 + *
2145 + * You should have received a copy of the GNU General Public License
2146 + * along with this program; if not, write to the Free Software
2147 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
2148 + */
2149 +
2150 +#ifndef __BCM2708_ARM_CONTROL_H
2151 +#define __BCM2708_ARM_CONTROL_H
2152 +
2153 +/*
2154 + * Definitions and addresses for the ARM CONTROL logic
2155 + * This file is manually generated.
2156 + */
2157 +
2158 +#define ARM_BASE 0x7E00B000
2159 +
2160 +/* Basic configuration */
2161 +#define ARM_CONTROL0 HW_REGISTER_RW(ARM_BASE+0x000)
2162 +#define ARM_C0_SIZ128M 0x00000000
2163 +#define ARM_C0_SIZ256M 0x00000001
2164 +#define ARM_C0_SIZ512M 0x00000002
2165 +#define ARM_C0_SIZ1G 0x00000003
2166 +#define ARM_C0_BRESP0 0x00000000
2167 +#define ARM_C0_BRESP1 0x00000004
2168 +#define ARM_C0_BRESP2 0x00000008
2169 +#define ARM_C0_BOOTHI 0x00000010
2170 +#define ARM_C0_UNUSED05 0x00000020 /* free */
2171 +#define ARM_C0_FULLPERI 0x00000040
2172 +#define ARM_C0_UNUSED78 0x00000180 /* free */
2173 +#define ARM_C0_JTAGMASK 0x00000E00
2174 +#define ARM_C0_JTAGOFF 0x00000000
2175 +#define ARM_C0_JTAGBASH 0x00000800 /* Debug on GPIO off */
2176 +#define ARM_C0_JTAGGPIO 0x00000C00 /* Debug on GPIO on */
2177 +#define ARM_C0_APROTMSK 0x0000F000
2178 +#define ARM_C0_DBG0SYNC 0x00010000 /* VPU0 halt sync */
2179 +#define ARM_C0_DBG1SYNC 0x00020000 /* VPU1 halt sync */
2180 +#define ARM_C0_SWDBGREQ 0x00040000 /* HW debug request */
2181 +#define ARM_C0_PASSHALT 0x00080000 /* ARM halt passed to debugger */
2182 +#define ARM_C0_PRIO_PER 0x00F00000 /* per priority mask */
2183 +#define ARM_C0_PRIO_L2 0x0F000000
2184 +#define ARM_C0_PRIO_UC 0xF0000000
2185 +
2186 +#define ARM_C0_APROTPASS 0x0000A000 /* Translate 1:1 */
2187 +#define ARM_C0_APROTUSER 0x00000000 /* Only user mode */
2188 +#define ARM_C0_APROTSYST 0x0000F000 /* Only system mode */
2189 +
2190 +
2191 +#define ARM_CONTROL1 HW_REGISTER_RW(ARM_BASE+0x440)
2192 +#define ARM_C1_TIMER 0x00000001 /* re-route timer IRQ to VC */
2193 +#define ARM_C1_MAIL 0x00000002 /* re-route Mail IRQ to VC */
2194 +#define ARM_C1_BELL0 0x00000004 /* re-route Doorbell 0 to VC */
2195 +#define ARM_C1_BELL1 0x00000008 /* re-route Doorbell 1 to VC */
2196 +#define ARM_C1_PERSON 0x00000100 /* peripherals on */
2197 +#define ARM_C1_REQSTOP 0x00000200 /* ASYNC bridge request stop */
2198 +
2199 +#define ARM_STATUS HW_REGISTER_RW(ARM_BASE+0x444)
2200 +#define ARM_S_ACKSTOP 0x80000000 /* Bridge stopped */
2201 +#define ARM_S_READPEND 0x000003FF /* pending reads counter */
2202 +#define ARM_S_WRITPEND 0x000FFC00 /* pending writes counter */
2203 +
2204 +#define ARM_ERRHALT HW_REGISTER_RW(ARM_BASE+0x448)
2205 +#define ARM_EH_PERIBURST 0x00000001 /* Burst write seen on peri bus */
2206 +#define ARM_EH_ILLADDRS1 0x00000002 /* Address bits 25-27 error */
2207 +#define ARM_EH_ILLADDRS2 0x00000004 /* Address bits 31-28 error */
2208 +#define ARM_EH_VPU0HALT 0x00000008 /* VPU0 halted & in debug mode */
2209 +#define ARM_EH_VPU1HALT 0x00000010 /* VPU1 halted & in debug mode */
2210 +#define ARM_EH_ARMHALT 0x00000020 /* ARM in halted debug mode */
2211 +
2212 +#define ARM_ID_SECURE HW_REGISTER_RW(ARM_BASE+0x00C)
2213 +#define ARM_ID HW_REGISTER_RW(ARM_BASE+0x44C)
2214 +#define ARM_IDVAL 0x364D5241
2215 +
2216 +/* Translation memory */
2217 +#define ARM_TRANSLATE HW_REGISTER_RW(ARM_BASE+0x100)
2218 +/* 32 locations: 0x100.. 0x17F */
2219 +/* 32 spare means we CAN go to 64 pages.... */
2220 +
2221 +
2222 +/* Interrupts */
2223 +#define ARM_IRQ_PEND0 HW_REGISTER_RW(ARM_BASE+0x200) /* Top IRQ bits */
2224 +#define ARM_I0_TIMER 0x00000001 /* timer IRQ */
2225 +#define ARM_I0_MAIL 0x00000002 /* Mail IRQ */
2226 +#define ARM_I0_BELL0 0x00000004 /* Doorbell 0 */
2227 +#define ARM_I0_BELL1 0x00000008 /* Doorbell 1 */
2228 +#define ARM_I0_BANK1 0x00000100 /* Bank1 IRQ */
2229 +#define ARM_I0_BANK2 0x00000200 /* Bank2 IRQ */
2230 +
2231 +#define ARM_IRQ_PEND1 HW_REGISTER_RW(ARM_BASE+0x204) /* All bank1 IRQ bits */
2232 +/* todo: all I1_interrupt sources */
2233 +#define ARM_IRQ_PEND2 HW_REGISTER_RW(ARM_BASE+0x208) /* All bank2 IRQ bits */
2234 +/* todo: all I2_interrupt sources */
2235 +
2236 +#define ARM_IRQ_FAST HW_REGISTER_RW(ARM_BASE+0x20C) /* FIQ control */
2237 +#define ARM_IF_INDEX 0x0000007F /* FIQ select */
2238 +#define ARM_IF_ENABLE 0x00000080 /* FIQ enable */
2239 +#define ARM_IF_VCMASK 0x0000003F /* FIQ = (index from VC source) */
2240 +#define ARM_IF_TIMER 0x00000040 /* FIQ = ARM timer */
2241 +#define ARM_IF_MAIL 0x00000041 /* FIQ = ARM Mail */
2242 +#define ARM_IF_BELL0 0x00000042 /* FIQ = ARM Doorbell 0 */
2243 +#define ARM_IF_BELL1 0x00000043 /* FIQ = ARM Doorbell 1 */
2244 +#define ARM_IF_VP0HALT 0x00000044 /* FIQ = VPU0 Halt seen */
2245 +#define ARM_IF_VP1HALT 0x00000045 /* FIQ = VPU1 Halt seen */
2246 +#define ARM_IF_ILLEGAL 0x00000046 /* FIQ = Illegal access seen */
2247 +
2248 +#define ARM_IRQ_ENBL1 HW_REGISTER_RW(ARM_BASE+0x210) /* Bank1 enable bits */
2249 +#define ARM_IRQ_ENBL2 HW_REGISTER_RW(ARM_BASE+0x214) /* Bank2 enable bits */
2250 +#define ARM_IRQ_ENBL3 HW_REGISTER_RW(ARM_BASE+0x218) /* ARM irqs enable bits */
2251 +#define ARM_IRQ_DIBL1 HW_REGISTER_RW(ARM_BASE+0x21C) /* Bank1 disable bits */
2252 +#define ARM_IRQ_DIBL2 HW_REGISTER_RW(ARM_BASE+0x220) /* Bank2 disable bits */
2253 +#define ARM_IRQ_DIBL3 HW_REGISTER_RW(ARM_BASE+0x224) /* ARM irqs disable bits */
2254 +#define ARM_IE_TIMER 0x00000001 /* Timer IRQ */
2255 +#define ARM_IE_MAIL 0x00000002 /* Mail IRQ */
2256 +#define ARM_IE_BELL0 0x00000004 /* Doorbell 0 */
2257 +#define ARM_IE_BELL1 0x00000008 /* Doorbell 1 */
2258 +#define ARM_IE_VP0HALT 0x00000010 /* VPU0 Halt */
2259 +#define ARM_IE_VP1HALT 0x00000020 /* VPU1 Halt */
2260 +#define ARM_IE_ILLEGAL 0x00000040 /* Illegal access seen */
2261 +
2262 +/* Timer */
2263 +/* For reg. fields see sp804 spec. */
2264 +#define ARM_T_LOAD HW_REGISTER_RW(ARM_BASE+0x400)
2265 +#define ARM_T_VALUE HW_REGISTER_RW(ARM_BASE+0x404)
2266 +#define ARM_T_CONTROL HW_REGISTER_RW(ARM_BASE+0x408)
2267 +#define ARM_T_IRQCNTL HW_REGISTER_RW(ARM_BASE+0x40C)
2268 +#define ARM_T_RAWIRQ HW_REGISTER_RW(ARM_BASE+0x410)
2269 +#define ARM_T_MSKIRQ HW_REGISTER_RW(ARM_BASE+0x414)
2270 +#define ARM_T_RELOAD HW_REGISTER_RW(ARM_BASE+0x418)
2271 +#define ARM_T_PREDIV HW_REGISTER_RW(ARM_BASE+0x41c)
2272 +#define ARM_T_FREECNT HW_REGISTER_RW(ARM_BASE+0x420)
2273 +
2274 +#define TIMER_CTRL_ONESHOT (1 << 0)
2275 +#define TIMER_CTRL_32BIT (1 << 1)
2276 +#define TIMER_CTRL_DIV1 (0 << 2)
2277 +#define TIMER_CTRL_DIV16 (1 << 2)
2278 +#define TIMER_CTRL_DIV256 (2 << 2)
2279 +#define TIMER_CTRL_IE (1 << 5)
2280 +#define TIMER_CTRL_PERIODIC (1 << 6)
2281 +#define TIMER_CTRL_ENABLE (1 << 7)
2282 +#define TIMER_CTRL_DBGHALT (1 << 8)
2283 +#define TIMER_CTRL_ENAFREE (1 << 9)
2284 +#define TIMER_CTRL_FREEDIV_SHIFT 16)
2285 +#define TIMER_CTRL_FREEDIV_MASK 0xff
2286 +
2287 +/* Semaphores, Doorbells, Mailboxes */
2288 +#define ARM_SBM_OWN0 (ARM_BASE+0x800)
2289 +#define ARM_SBM_OWN1 (ARM_BASE+0x900)
2290 +#define ARM_SBM_OWN2 (ARM_BASE+0xA00)
2291 +#define ARM_SBM_OWN3 (ARM_BASE+0xB00)
2292 +
2293 +/* MAILBOXES
2294 + * Register flags are common across all
2295 + * owner registers. See end of this section
2296 + *
2297 + * Semaphores, Doorbells, Mailboxes Owner 0
2298 + *
2299 + */
2300 +
2301 +#define ARM_0_SEMS HW_REGISTER_RW(ARM_SBM_OWN0+0x00)
2302 +#define ARM_0_SEM0 HW_REGISTER_RW(ARM_SBM_OWN0+0x00)
2303 +#define ARM_0_SEM1 HW_REGISTER_RW(ARM_SBM_OWN0+0x04)
2304 +#define ARM_0_SEM2 HW_REGISTER_RW(ARM_SBM_OWN0+0x08)
2305 +#define ARM_0_SEM3 HW_REGISTER_RW(ARM_SBM_OWN0+0x0C)
2306 +#define ARM_0_SEM4 HW_REGISTER_RW(ARM_SBM_OWN0+0x10)
2307 +#define ARM_0_SEM5 HW_REGISTER_RW(ARM_SBM_OWN0+0x14)
2308 +#define ARM_0_SEM6 HW_REGISTER_RW(ARM_SBM_OWN0+0x18)
2309 +#define ARM_0_SEM7 HW_REGISTER_RW(ARM_SBM_OWN0+0x1C)
2310 +#define ARM_0_BELL0 HW_REGISTER_RW(ARM_SBM_OWN0+0x40)
2311 +#define ARM_0_BELL1 HW_REGISTER_RW(ARM_SBM_OWN0+0x44)
2312 +#define ARM_0_BELL2 HW_REGISTER_RW(ARM_SBM_OWN0+0x48)
2313 +#define ARM_0_BELL3 HW_REGISTER_RW(ARM_SBM_OWN0+0x4C)
2314 +/* MAILBOX 0 access in Owner 0 area */
2315 +/* Some addresses should ONLY be used by owner 0 */
2316 +#define ARM_0_MAIL0_WRT HW_REGISTER_RW(ARM_SBM_OWN0+0x80) /* .. 0x8C (4 locations) */
2317 +#define ARM_0_MAIL0_RD HW_REGISTER_RW(ARM_SBM_OWN0+0x80) /* .. 0x8C (4 locations) Normal read */
2318 +#define ARM_0_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN0+0x90) /* none-pop read */
2319 +#define ARM_0_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN0+0x94) /* Sender read (only LS 2 bits) */
2320 +#define ARM_0_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN0+0x98) /* Status read */
2321 +#define ARM_0_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN0+0x9C) /* Config read/write */
2322 +/* MAILBOX 1 access in Owner 0 area */
2323 +/* Owner 0 should only WRITE to this mailbox */
2324 +#define ARM_0_MAIL1_WRT HW_REGISTER_RW(ARM_SBM_OWN0+0xA0) /* .. 0xAC (4 locations) */
2325 +/*#define ARM_0_MAIL1_RD HW_REGISTER_RW(ARM_SBM_OWN0+0xA0) */ /* DO NOT USE THIS !!!!! */
2326 +/*#define ARM_0_MAIL1_POL HW_REGISTER_RW(ARM_SBM_OWN0+0xB0) */ /* DO NOT USE THIS !!!!! */
2327 +/*#define ARM_0_MAIL1_SND HW_REGISTER_RW(ARM_SBM_OWN0+0xB4) */ /* DO NOT USE THIS !!!!! */
2328 +#define ARM_0_MAIL1_STA HW_REGISTER_RW(ARM_SBM_OWN0+0xB8) /* Status read */
2329 +/*#define ARM_0_MAIL1_CNF HW_REGISTER_RW(ARM_SBM_OWN0+0xBC) */ /* DO NOT USE THIS !!!!! */
2330 +/* General SEM, BELL, MAIL config/status */
2331 +#define ARM_0_SEMCLRDBG HW_REGISTER_RW(ARM_SBM_OWN0+0xE0) /* semaphore clear/debug register */
2332 +#define ARM_0_BELLCLRDBG HW_REGISTER_RW(ARM_SBM_OWN0+0xE4) /* Doorbells clear/debug register */
2333 +#define ARM_0_ALL_IRQS HW_REGISTER_RW(ARM_SBM_OWN0+0xF8) /* ALL interrupts */
2334 +#define ARM_0_MY_IRQS HW_REGISTER_RW(ARM_SBM_OWN0+0xFC) /* IRQS pending for owner 0 */
2335 +
2336 +/* Semaphores, Doorbells, Mailboxes Owner 1 */
2337 +#define ARM_1_SEMS HW_REGISTER_RW(ARM_SBM_OWN1+0x00)
2338 +#define ARM_1_SEM0 HW_REGISTER_RW(ARM_SBM_OWN1+0x00)
2339 +#define ARM_1_SEM1 HW_REGISTER_RW(ARM_SBM_OWN1+0x04)
2340 +#define ARM_1_SEM2 HW_REGISTER_RW(ARM_SBM_OWN1+0x08)
2341 +#define ARM_1_SEM3 HW_REGISTER_RW(ARM_SBM_OWN1+0x0C)
2342 +#define ARM_1_SEM4 HW_REGISTER_RW(ARM_SBM_OWN1+0x10)
2343 +#define ARM_1_SEM5 HW_REGISTER_RW(ARM_SBM_OWN1+0x14)
2344 +#define ARM_1_SEM6 HW_REGISTER_RW(ARM_SBM_OWN1+0x18)
2345 +#define ARM_1_SEM7 HW_REGISTER_RW(ARM_SBM_OWN1+0x1C)
2346 +#define ARM_1_BELL0 HW_REGISTER_RW(ARM_SBM_OWN1+0x40)
2347 +#define ARM_1_BELL1 HW_REGISTER_RW(ARM_SBM_OWN1+0x44)
2348 +#define ARM_1_BELL2 HW_REGISTER_RW(ARM_SBM_OWN1+0x48)
2349 +#define ARM_1_BELL3 HW_REGISTER_RW(ARM_SBM_OWN1+0x4C)
2350 +/* MAILBOX 0 access in Owner 0 area */
2351 +/* Owner 1 should only WRITE to this mailbox */
2352 +#define ARM_1_MAIL0_WRT HW_REGISTER_RW(ARM_SBM_OWN1+0x80) /* .. 0x8C (4 locations) */
2353 +/*#define ARM_1_MAIL0_RD HW_REGISTER_RW(ARM_SBM_OWN1+0x80) */ /* DO NOT USE THIS !!!!! */
2354 +/*#define ARM_1_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN1+0x90) */ /* DO NOT USE THIS !!!!! */
2355 +/*#define ARM_1_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN1+0x94) */ /* DO NOT USE THIS !!!!! */
2356 +#define ARM_1_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN1+0x98) /* Status read */
2357 +/*#define ARM_1_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN1+0x9C) */ /* DO NOT USE THIS !!!!! */
2358 +/* MAILBOX 1 access in Owner 0 area */
2359 +#define ARM_1_MAIL1_WRT HW_REGISTER_RW(ARM_SBM_OWN1+0xA0) /* .. 0xAC (4 locations) */
2360 +#define ARM_1_MAIL1_RD HW_REGISTER_RW(ARM_SBM_OWN1+0xA0) /* .. 0xAC (4 locations) Normal read */
2361 +#define ARM_1_MAIL1_POL HW_REGISTER_RW(ARM_SBM_OWN1+0xB0) /* none-pop read */
2362 +#define ARM_1_MAIL1_SND HW_REGISTER_RW(ARM_SBM_OWN1+0xB4) /* Sender read (only LS 2 bits) */
2363 +#define ARM_1_MAIL1_STA HW_REGISTER_RW(ARM_SBM_OWN1+0xB8) /* Status read */
2364 +#define ARM_1_MAIL1_CNF HW_REGISTER_RW(ARM_SBM_OWN1+0xBC)
2365 +/* General SEM, BELL, MAIL config/status */
2366 +#define ARM_1_SEMCLRDBG HW_REGISTER_RW(ARM_SBM_OWN1+0xE0) /* semaphore clear/debug register */
2367 +#define ARM_1_BELLCLRDBG HW_REGISTER_RW(ARM_SBM_OWN1+0xE4) /* Doorbells clear/debug register */
2368 +#define ARM_1_MY_IRQS HW_REGISTER_RW(ARM_SBM_OWN1+0xFC) /* IRQS pending for owner 1 */
2369 +#define ARM_1_ALL_IRQS HW_REGISTER_RW(ARM_SBM_OWN1+0xF8) /* ALL interrupts */
2370 +
2371 +/* Semaphores, Doorbells, Mailboxes Owner 2 */
2372 +#define ARM_2_SEMS HW_REGISTER_RW(ARM_SBM_OWN2+0x00)
2373 +#define ARM_2_SEM0 HW_REGISTER_RW(ARM_SBM_OWN2+0x00)
2374 +#define ARM_2_SEM1 HW_REGISTER_RW(ARM_SBM_OWN2+0x04)
2375 +#define ARM_2_SEM2 HW_REGISTER_RW(ARM_SBM_OWN2+0x08)
2376 +#define ARM_2_SEM3 HW_REGISTER_RW(ARM_SBM_OWN2+0x0C)
2377 +#define ARM_2_SEM4 HW_REGISTER_RW(ARM_SBM_OWN2+0x10)
2378 +#define ARM_2_SEM5 HW_REGISTER_RW(ARM_SBM_OWN2+0x14)
2379 +#define ARM_2_SEM6 HW_REGISTER_RW(ARM_SBM_OWN2+0x18)
2380 +#define ARM_2_SEM7 HW_REGISTER_RW(ARM_SBM_OWN2+0x1C)
2381 +#define ARM_2_BELL0 HW_REGISTER_RW(ARM_SBM_OWN2+0x40)
2382 +#define ARM_2_BELL1 HW_REGISTER_RW(ARM_SBM_OWN2+0x44)
2383 +#define ARM_2_BELL2 HW_REGISTER_RW(ARM_SBM_OWN2+0x48)
2384 +#define ARM_2_BELL3 HW_REGISTER_RW(ARM_SBM_OWN2+0x4C)
2385 +/* MAILBOX 0 access in Owner 2 area */
2386 +/* Owner 2 should only WRITE to this mailbox */
2387 +#define ARM_2_MAIL0_WRT HW_REGISTER_RW(ARM_SBM_OWN2+0x80) /* .. 0x8C (4 locations) */
2388 +/*#define ARM_2_MAIL0_RD HW_REGISTER_RW(ARM_SBM_OWN2+0x80) */ /* DO NOT USE THIS !!!!! */
2389 +/*#define ARM_2_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN2+0x90) */ /* DO NOT USE THIS !!!!! */
2390 +/*#define ARM_2_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN2+0x94) */ /* DO NOT USE THIS !!!!! */
2391 +#define ARM_2_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN2+0x98) /* Status read */
2392 +/*#define ARM_2_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN2+0x9C) */ /* DO NOT USE THIS !!!!! */
2393 +/* MAILBOX 1 access in Owner 2 area */
2394 +/* Owner 2 should only WRITE to this mailbox */
2395 +#define ARM_2_MAIL1_WRT HW_REGISTER_RW(ARM_SBM_OWN2+0xA0) /* .. 0xAC (4 locations) */
2396 +/*#define ARM_2_MAIL1_RD HW_REGISTER_RW(ARM_SBM_OWN2+0xA0) */ /* DO NOT USE THIS !!!!! */
2397 +/*#define ARM_2_MAIL1_POL HW_REGISTER_RW(ARM_SBM_OWN2+0xB0) */ /* DO NOT USE THIS !!!!! */
2398 +/*#define ARM_2_MAIL1_SND HW_REGISTER_RW(ARM_SBM_OWN2+0xB4) */ /* DO NOT USE THIS !!!!! */
2399 +#define ARM_2_MAIL1_STA HW_REGISTER_RW(ARM_SBM_OWN2+0xB8) /* Status read */
2400 +/*#define ARM_2_MAIL1_CNF HW_REGISTER_RW(ARM_SBM_OWN2+0xBC) */ /* DO NOT USE THIS !!!!! */
2401 +/* General SEM, BELL, MAIL config/status */
2402 +#define ARM_2_SEMCLRDBG HW_REGISTER_RW(ARM_SBM_OWN2+0xE0) /* semaphore clear/debug register */
2403 +#define ARM_2_BELLCLRDBG HW_REGISTER_RW(ARM_SBM_OWN2+0xE4) /* Doorbells clear/debug register */
2404 +#define ARM_2_MY_IRQS HW_REGISTER_RW(ARM_SBM_OWN2+0xFC) /* IRQS pending for owner 2 */
2405 +#define ARM_2_ALL_IRQS HW_REGISTER_RW(ARM_SBM_OWN2+0xF8) /* ALL interrupts */
2406 +
2407 +/* Semaphores, Doorbells, Mailboxes Owner 3 */
2408 +#define ARM_3_SEMS HW_REGISTER_RW(ARM_SBM_OWN3+0x00)
2409 +#define ARM_3_SEM0 HW_REGISTER_RW(ARM_SBM_OWN3+0x00)
2410 +#define ARM_3_SEM1 HW_REGISTER_RW(ARM_SBM_OWN3+0x04)
2411 +#define ARM_3_SEM2 HW_REGISTER_RW(ARM_SBM_OWN3+0x08)
2412 +#define ARM_3_SEM3 HW_REGISTER_RW(ARM_SBM_OWN3+0x0C)
2413 +#define ARM_3_SEM4 HW_REGISTER_RW(ARM_SBM_OWN3+0x10)
2414 +#define ARM_3_SEM5 HW_REGISTER_RW(ARM_SBM_OWN3+0x14)
2415 +#define ARM_3_SEM6 HW_REGISTER_RW(ARM_SBM_OWN3+0x18)
2416 +#define ARM_3_SEM7 HW_REGISTER_RW(ARM_SBM_OWN3+0x1C)
2417 +#define ARM_3_BELL0 HW_REGISTER_RW(ARM_SBM_OWN3+0x40)
2418 +#define ARM_3_BELL1 HW_REGISTER_RW(ARM_SBM_OWN3+0x44)
2419 +#define ARM_3_BELL2 HW_REGISTER_RW(ARM_SBM_OWN3+0x48)
2420 +#define ARM_3_BELL3 HW_REGISTER_RW(ARM_SBM_OWN3+0x4C)
2421 +/* MAILBOX 0 access in Owner 3 area */
2422 +/* Owner 3 should only WRITE to this mailbox */
2423 +#define ARM_3_MAIL0_WRT HW_REGISTER_RW(ARM_SBM_OWN3+0x80) /* .. 0x8C (4 locations) */
2424 +/*#define ARM_3_MAIL0_RD HW_REGISTER_RW(ARM_SBM_OWN3+0x80) */ /* DO NOT USE THIS !!!!! */
2425 +/*#define ARM_3_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN3+0x90) */ /* DO NOT USE THIS !!!!! */
2426 +/*#define ARM_3_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN3+0x94) */ /* DO NOT USE THIS !!!!! */
2427 +#define ARM_3_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN3+0x98) /* Status read */
2428 +/*#define ARM_3_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN3+0x9C) */ /* DO NOT USE THIS !!!!! */
2429 +/* MAILBOX 1 access in Owner 3 area */
2430 +/* Owner 3 should only WRITE to this mailbox */
2431 +#define ARM_3_MAIL1_WRT HW_REGISTER_RW(ARM_SBM_OWN3+0xA0) /* .. 0xAC (4 locations) */
2432 +/*#define ARM_3_MAIL1_RD HW_REGISTER_RW(ARM_SBM_OWN3+0xA0) */ /* DO NOT USE THIS !!!!! */
2433 +/*#define ARM_3_MAIL1_POL HW_REGISTER_RW(ARM_SBM_OWN3+0xB0) */ /* DO NOT USE THIS !!!!! */
2434 +/*#define ARM_3_MAIL1_SND HW_REGISTER_RW(ARM_SBM_OWN3+0xB4) */ /* DO NOT USE THIS !!!!! */
2435 +#define ARM_3_MAIL1_STA HW_REGISTER_RW(ARM_SBM_OWN3+0xB8) /* Status read */
2436 +/*#define ARM_3_MAIL1_CNF HW_REGISTER_RW(ARM_SBM_OWN3+0xBC) */ /* DO NOT USE THIS !!!!! */
2437 +/* General SEM, BELL, MAIL config/status */
2438 +#define ARM_3_SEMCLRDBG HW_REGISTER_RW(ARM_SBM_OWN3+0xE0) /* semaphore clear/debug register */
2439 +#define ARM_3_BELLCLRDBG HW_REGISTER_RW(ARM_SBM_OWN3+0xE4) /* Doorbells clear/debug register */
2440 +#define ARM_3_MY_IRQS HW_REGISTER_RW(ARM_SBM_OWN3+0xFC) /* IRQS pending for owner 3 */
2441 +#define ARM_3_ALL_IRQS HW_REGISTER_RW(ARM_SBM_OWN3+0xF8) /* ALL interrupts */
2442 +
2443 +
2444 +
2445 +/* Mailbox flags. Valid for all owners */
2446 +
2447 +/* Mailbox status register (...0x98) */
2448 +#define ARM_MS_FULL 0x80000000
2449 +#define ARM_MS_EMPTY 0x40000000
2450 +#define ARM_MS_LEVEL 0x400000FF /* Max. value depdnds on mailbox depth parameter */
2451 +
2452 +/* MAILBOX config/status register (...0x9C) */
2453 +/* ANY write to this register clears the error bits! */
2454 +#define ARM_MC_IHAVEDATAIRQEN 0x00000001 /* mailbox irq enable: has data */
2455 +#define ARM_MC_IHAVESPACEIRQEN 0x00000002 /* mailbox irq enable: has space */
2456 +#define ARM_MC_OPPISEMPTYIRQEN 0x00000004 /* mailbox irq enable: Opp. is empty */
2457 +#define ARM_MC_MAIL_CLEAR 0x00000008 /* mailbox clear write 1, then 0 */
2458 +#define ARM_MC_IHAVEDATAIRQPEND 0x00000010 /* mailbox irq pending: has space */
2459 +#define ARM_MC_IHAVESPACEIRQPEND 0x00000020 /* mailbox irq pending: Opp. is empty */
2460 +#define ARM_MC_OPPISEMPTYIRQPEND 0x00000040 /* mailbox irq pending */
2461 +/* Bit 7 is unused */
2462 +#define ARM_MC_ERRNOOWN 0x00000100 /* error : none owner read from mailbox */
2463 +#define ARM_MC_ERROVERFLW 0x00000200 /* error : write to fill mailbox */
2464 +#define ARM_MC_ERRUNDRFLW 0x00000400 /* error : read from empty mailbox */
2465 +
2466 +/* Semaphore clear/debug register (...0xE0) */
2467 +#define ARM_SD_OWN0 0x00000003 /* Owner of sem 0 */
2468 +#define ARM_SD_OWN1 0x0000000C /* Owner of sem 1 */
2469 +#define ARM_SD_OWN2 0x00000030 /* Owner of sem 2 */
2470 +#define ARM_SD_OWN3 0x000000C0 /* Owner of sem 3 */
2471 +#define ARM_SD_OWN4 0x00000300 /* Owner of sem 4 */
2472 +#define ARM_SD_OWN5 0x00000C00 /* Owner of sem 5 */
2473 +#define ARM_SD_OWN6 0x00003000 /* Owner of sem 6 */
2474 +#define ARM_SD_OWN7 0x0000C000 /* Owner of sem 7 */
2475 +#define ARM_SD_SEM0 0x00010000 /* Status of sem 0 */
2476 +#define ARM_SD_SEM1 0x00020000 /* Status of sem 1 */
2477 +#define ARM_SD_SEM2 0x00040000 /* Status of sem 2 */
2478 +#define ARM_SD_SEM3 0x00080000 /* Status of sem 3 */
2479 +#define ARM_SD_SEM4 0x00100000 /* Status of sem 4 */
2480 +#define ARM_SD_SEM5 0x00200000 /* Status of sem 5 */
2481 +#define ARM_SD_SEM6 0x00400000 /* Status of sem 6 */
2482 +#define ARM_SD_SEM7 0x00800000 /* Status of sem 7 */
2483 +
2484 +/* Doorbells clear/debug register (...0xE4) */
2485 +#define ARM_BD_OWN0 0x00000003 /* Owner of doorbell 0 */
2486 +#define ARM_BD_OWN1 0x0000000C /* Owner of doorbell 1 */
2487 +#define ARM_BD_OWN2 0x00000030 /* Owner of doorbell 2 */
2488 +#define ARM_BD_OWN3 0x000000C0 /* Owner of doorbell 3 */
2489 +#define ARM_BD_BELL0 0x00000100 /* Status of doorbell 0 */
2490 +#define ARM_BD_BELL1 0x00000200 /* Status of doorbell 1 */
2491 +#define ARM_BD_BELL2 0x00000400 /* Status of doorbell 2 */
2492 +#define ARM_BD_BELL3 0x00000800 /* Status of doorbell 3 */
2493 +
2494 +/* MY IRQS register (...0xF8) */
2495 +#define ARM_MYIRQ_BELL 0x00000001 /* This owner has a doorbell IRQ */
2496 +#define ARM_MYIRQ_MAIL 0x00000002 /* This owner has a mailbox IRQ */
2497 +
2498 +/* ALL IRQS register (...0xF8) */
2499 +#define ARM_AIS_BELL0 0x00000001 /* Doorbell 0 IRQ pending */
2500 +#define ARM_AIS_BELL1 0x00000002 /* Doorbell 1 IRQ pending */
2501 +#define ARM_AIS_BELL2 0x00000004 /* Doorbell 2 IRQ pending */
2502 +#define ARM_AIS_BELL3 0x00000008 /* Doorbell 3 IRQ pending */
2503 +#define ARM_AIS0_HAVEDATA 0x00000010 /* MAIL 0 has data IRQ pending */
2504 +#define ARM_AIS0_HAVESPAC 0x00000020 /* MAIL 0 has space IRQ pending */
2505 +#define ARM_AIS0_OPPEMPTY 0x00000040 /* MAIL 0 opposite is empty IRQ */
2506 +#define ARM_AIS1_HAVEDATA 0x00000080 /* MAIL 1 has data IRQ pending */
2507 +#define ARM_AIS1_HAVESPAC 0x00000100 /* MAIL 1 has space IRQ pending */
2508 +#define ARM_AIS1_OPPEMPTY 0x00000200 /* MAIL 1 opposite is empty IRQ */
2509 +/* Note that bell-0, bell-1 and MAIL0 IRQ go only to the ARM */
2510 +/* Whilst that bell-2, bell-3 and MAIL1 IRQ go only to the VC */
2511 +/* */
2512 +/* ARM JTAG BASH */
2513 +/* */
2514 +#define AJB_BASE 0x7e2000c0
2515 +
2516 +#define AJBCONF HW_REGISTER_RW(AJB_BASE+0x00)
2517 +#define AJB_BITS0 0x000000
2518 +#define AJB_BITS4 0x000004
2519 +#define AJB_BITS8 0x000008
2520 +#define AJB_BITS12 0x00000C
2521 +#define AJB_BITS16 0x000010
2522 +#define AJB_BITS20 0x000014
2523 +#define AJB_BITS24 0x000018
2524 +#define AJB_BITS28 0x00001C
2525 +#define AJB_BITS32 0x000020
2526 +#define AJB_BITS34 0x000022
2527 +#define AJB_OUT_MS 0x000040
2528 +#define AJB_OUT_LS 0x000000
2529 +#define AJB_INV_CLK 0x000080
2530 +#define AJB_D0_RISE 0x000100
2531 +#define AJB_D0_FALL 0x000000
2532 +#define AJB_D1_RISE 0x000200
2533 +#define AJB_D1_FALL 0x000000
2534 +#define AJB_IN_RISE 0x000400
2535 +#define AJB_IN_FALL 0x000000
2536 +#define AJB_ENABLE 0x000800
2537 +#define AJB_HOLD0 0x000000
2538 +#define AJB_HOLD1 0x001000
2539 +#define AJB_HOLD2 0x002000
2540 +#define AJB_HOLD3 0x003000
2541 +#define AJB_RESETN 0x004000
2542 +#define AJB_CLKSHFT 16
2543 +#define AJB_BUSY 0x80000000
2544 +#define AJBTMS HW_REGISTER_RW(AJB_BASE+0x04)
2545 +#define AJBTDI HW_REGISTER_RW(AJB_BASE+0x08)
2546 +#define AJBTDO HW_REGISTER_RW(AJB_BASE+0x0c)
2547 +
2548 +#endif
2549 --- /dev/null
2550 +++ b/arch/arm/mach-bcm2708/include/mach/arm_power.h
2551 @@ -0,0 +1,62 @@
2552 +/*
2553 + * linux/arch/arm/mach-bcm2708/include/mach/arm_power.h
2554 + *
2555 + * Copyright (C) 2010 Broadcom
2556 + *
2557 + * This program is free software; you can redistribute it and/or modify
2558 + * it under the terms of the GNU General Public License as published by
2559 + * the Free Software Foundation; either version 2 of the License, or
2560 + * (at your option) any later version.
2561 + *
2562 + * This program is distributed in the hope that it will be useful,
2563 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2564 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2565 + * GNU General Public License for more details.
2566 + *
2567 + * You should have received a copy of the GNU General Public License
2568 + * along with this program; if not, write to the Free Software
2569 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
2570 + */
2571 +
2572 +#ifndef _ARM_POWER_H
2573 +#define _ARM_POWER_H
2574 +
2575 +/* Use meaningful names on each side */
2576 +#ifdef __VIDEOCORE__
2577 +#define PREFIX(x) ARM_##x
2578 +#else
2579 +#define PREFIX(x) BCM_##x
2580 +#endif
2581 +
2582 +enum {
2583 + PREFIX(POWER_SDCARD_BIT),
2584 + PREFIX(POWER_UART_BIT),
2585 + PREFIX(POWER_MINIUART_BIT),
2586 + PREFIX(POWER_USB_BIT),
2587 + PREFIX(POWER_I2C0_BIT),
2588 + PREFIX(POWER_I2C1_BIT),
2589 + PREFIX(POWER_I2C2_BIT),
2590 + PREFIX(POWER_SPI_BIT),
2591 + PREFIX(POWER_CCP2TX_BIT),
2592 + PREFIX(POWER_DSI_BIT),
2593 +
2594 + PREFIX(POWER_MAX)
2595 +};
2596 +
2597 +enum {
2598 + PREFIX(POWER_SDCARD) = (1 << PREFIX(POWER_SDCARD_BIT)),
2599 + PREFIX(POWER_UART) = (1 << PREFIX(POWER_UART_BIT)),
2600 + PREFIX(POWER_MINIUART) = (1 << PREFIX(POWER_MINIUART_BIT)),
2601 + PREFIX(POWER_USB) = (1 << PREFIX(POWER_USB_BIT)),
2602 + PREFIX(POWER_I2C0) = (1 << PREFIX(POWER_I2C0_BIT)),
2603 + PREFIX(POWER_I2C1_MASK) = (1 << PREFIX(POWER_I2C1_BIT)),
2604 + PREFIX(POWER_I2C2_MASK) = (1 << PREFIX(POWER_I2C2_BIT)),
2605 + PREFIX(POWER_SPI_MASK) = (1 << PREFIX(POWER_SPI_BIT)),
2606 + PREFIX(POWER_CCP2TX_MASK) = (1 << PREFIX(POWER_CCP2TX_BIT)),
2607 + PREFIX(POWER_DSI) = (1 << PREFIX(POWER_DSI_BIT)),
2608 +
2609 + PREFIX(POWER_MASK) = (1 << PREFIX(POWER_MAX)) - 1,
2610 + PREFIX(POWER_NONE) = 0
2611 +};
2612 +
2613 +#endif
2614 --- /dev/null
2615 +++ b/arch/arm/mach-bcm2708/include/mach/clkdev.h
2616 @@ -0,0 +1,7 @@
2617 +#ifndef __ASM_MACH_CLKDEV_H
2618 +#define __ASM_MACH_CLKDEV_H
2619 +
2620 +#define __clk_get(clk) ({ 1; })
2621 +#define __clk_put(clk) do { } while (0)
2622 +
2623 +#endif
2624 --- /dev/null
2625 +++ b/arch/arm/mach-bcm2708/include/mach/debug-macro.S
2626 @@ -0,0 +1,22 @@
2627 +/* arch/arm/mach-bcm2708/include/mach/debug-macro.S
2628 + *
2629 + * Debugging macro include header
2630 + *
2631 + * Copyright (C) 2010 Broadcom
2632 + * Copyright (C) 1994-1999 Russell King
2633 + * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
2634 + *
2635 + * This program is free software; you can redistribute it and/or modify
2636 + * it under the terms of the GNU General Public License version 2 as
2637 + * published by the Free Software Foundation.
2638 + *
2639 +*/
2640 +
2641 +#include <mach/platform.h>
2642 +
2643 + .macro addruart, rp, rv, tmp
2644 + ldr \rp, =UART0_BASE
2645 + ldr \rv, =IO_ADDRESS(UART0_BASE)
2646 + .endm
2647 +
2648 +#include <debug/pl01x.S>
2649 --- /dev/null
2650 +++ b/arch/arm/mach-bcm2708/include/mach/dma.h
2651 @@ -0,0 +1,88 @@
2652 +/*
2653 + * linux/arch/arm/mach-bcm2708/include/mach/dma.h
2654 + *
2655 + * Copyright (C) 2010 Broadcom
2656 + *
2657 + * This program is free software; you can redistribute it and/or modify
2658 + * it under the terms of the GNU General Public License version 2 as
2659 + * published by the Free Software Foundation.
2660 + */
2661 +
2662 +
2663 +#ifndef _MACH_BCM2708_DMA_H
2664 +#define _MACH_BCM2708_DMA_H
2665 +
2666 +#define BCM_DMAMAN_DRIVER_NAME "bcm2708_dma"
2667 +
2668 +/* DMA CS Control and Status bits */
2669 +#define BCM2708_DMA_ACTIVE (1 << 0)
2670 +#define BCM2708_DMA_INT (1 << 2)
2671 +#define BCM2708_DMA_ISPAUSED (1 << 4) /* Pause requested or not active */
2672 +#define BCM2708_DMA_ISHELD (1 << 5) /* Is held by DREQ flow control */
2673 +#define BCM2708_DMA_ERR (1 << 8)
2674 +#define BCM2708_DMA_ABORT (1 << 30) /* stop current CB, go to next, WO */
2675 +#define BCM2708_DMA_RESET (1 << 31) /* WO, self clearing */
2676 +
2677 +/* DMA control block "info" field bits */
2678 +#define BCM2708_DMA_INT_EN (1 << 0)
2679 +#define BCM2708_DMA_TDMODE (1 << 1)
2680 +#define BCM2708_DMA_WAIT_RESP (1 << 3)
2681 +#define BCM2708_DMA_D_INC (1 << 4)
2682 +#define BCM2708_DMA_D_WIDTH (1 << 5)
2683 +#define BCM2708_DMA_D_DREQ (1 << 6)
2684 +#define BCM2708_DMA_S_INC (1 << 8)
2685 +#define BCM2708_DMA_S_WIDTH (1 << 9)
2686 +#define BCM2708_DMA_S_DREQ (1 << 10)
2687 +
2688 +#define BCM2708_DMA_BURST(x) (((x)&0xf) << 12)
2689 +#define BCM2708_DMA_PER_MAP(x) ((x) << 16)
2690 +#define BCM2708_DMA_WAITS(x) (((x)&0x1f) << 21)
2691 +
2692 +#define BCM2708_DMA_DREQ_EMMC 11
2693 +#define BCM2708_DMA_DREQ_SDHOST 13
2694 +
2695 +#define BCM2708_DMA_CS 0x00 /* Control and Status */
2696 +#define BCM2708_DMA_ADDR 0x04
2697 +/* the current control block appears in the following registers - read only */
2698 +#define BCM2708_DMA_INFO 0x08
2699 +#define BCM2708_DMA_SOURCE_AD 0x0c
2700 +#define BCM2708_DMA_DEST_AD 0x10
2701 +#define BCM2708_DMA_NEXTCB 0x1C
2702 +#define BCM2708_DMA_DEBUG 0x20
2703 +
2704 +#define BCM2708_DMA4_CS (BCM2708_DMA_CHAN(4)+BCM2708_DMA_CS)
2705 +#define BCM2708_DMA4_ADDR (BCM2708_DMA_CHAN(4)+BCM2708_DMA_ADDR)
2706 +
2707 +#define BCM2708_DMA_TDMODE_LEN(w, h) ((h) << 16 | (w))
2708 +
2709 +struct bcm2708_dma_cb {
2710 + unsigned long info;
2711 + unsigned long src;
2712 + unsigned long dst;
2713 + unsigned long length;
2714 + unsigned long stride;
2715 + unsigned long next;
2716 + unsigned long pad[2];
2717 +};
2718 +
2719 +extern int bcm_sg_suitable_for_dma(struct scatterlist *sg_ptr, int sg_len);
2720 +extern void bcm_dma_start(void __iomem *dma_chan_base,
2721 + dma_addr_t control_block);
2722 +extern void bcm_dma_wait_idle(void __iomem *dma_chan_base);
2723 +extern int /*rc*/ bcm_dma_abort(void __iomem *dma_chan_base);
2724 +
2725 +/* When listing features we can ask for when allocating DMA channels give
2726 + those with higher priority smaller ordinal numbers */
2727 +#define BCM_DMA_FEATURE_FAST_ORD 0
2728 +#define BCM_DMA_FEATURE_BULK_ORD 1
2729 +#define BCM_DMA_FEATURE_FAST (1<<BCM_DMA_FEATURE_FAST_ORD)
2730 +#define BCM_DMA_FEATURE_BULK (1<<BCM_DMA_FEATURE_BULK_ORD)
2731 +#define BCM_DMA_FEATURE_COUNT 2
2732 +
2733 +/* return channel no or -ve error */
2734 +extern int bcm_dma_chan_alloc(unsigned preferred_feature_set,
2735 + void __iomem **out_dma_base, int *out_dma_irq);
2736 +extern int bcm_dma_chan_free(int channel);
2737 +
2738 +
2739 +#endif /* _MACH_BCM2708_DMA_H */
2740 --- /dev/null
2741 +++ b/arch/arm/mach-bcm2708/include/mach/entry-macro.S
2742 @@ -0,0 +1,69 @@
2743 +/*
2744 + * arch/arm/mach-bcm2708/include/mach/entry-macro.S
2745 + *
2746 + * Low-level IRQ helper macros for BCM2708 platforms
2747 + *
2748 + * Copyright (C) 2010 Broadcom
2749 + *
2750 + * This program is free software; you can redistribute it and/or modify
2751 + * it under the terms of the GNU General Public License as published by
2752 + * the Free Software Foundation; either version 2 of the License, or
2753 + * (at your option) any later version.
2754 + *
2755 + * This program is distributed in the hope that it will be useful,
2756 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2757 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2758 + * GNU General Public License for more details.
2759 + *
2760 + * You should have received a copy of the GNU General Public License
2761 + * along with this program; if not, write to the Free Software
2762 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
2763 + */
2764 +#include <mach/hardware.h>
2765 +
2766 + .macro disable_fiq
2767 + .endm
2768 +
2769 + .macro get_irqnr_preamble, base, tmp
2770 + ldr \base, =IO_ADDRESS(ARMCTRL_IC_BASE)
2771 + .endm
2772 +
2773 + .macro arch_ret_to_user, tmp1, tmp2
2774 + .endm
2775 +
2776 + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
2777 + /* get masked status */
2778 + ldr \irqstat, [\base, #(ARM_IRQ_PEND0 - ARMCTRL_IC_BASE)]
2779 + mov \irqnr, #(ARM_IRQ0_BASE + 31)
2780 + and \tmp, \irqstat, #0x300 @ save bits 8 and 9
2781 + /* clear bits 8 and 9, and test */
2782 + bics \irqstat, \irqstat, #0x300
2783 + bne 1010f
2784 +
2785 + tst \tmp, #0x100
2786 + ldrne \irqstat, [\base, #(ARM_IRQ_PEND1 - ARMCTRL_IC_BASE)]
2787 + movne \irqnr, #(ARM_IRQ1_BASE + 31)
2788 + @ Mask out the interrupts also present in PEND0 - see SW-5809
2789 + bicne \irqstat, #((1<<7) | (1<<9) | (1<<10))
2790 + bicne \irqstat, #((1<<18) | (1<<19))
2791 + bne 1010f
2792 +
2793 + tst \tmp, #0x200
2794 + ldrne \irqstat, [\base, #(ARM_IRQ_PEND2 - ARMCTRL_IC_BASE)]
2795 + movne \irqnr, #(ARM_IRQ2_BASE + 31)
2796 + @ Mask out the interrupts also present in PEND0 - see SW-5809
2797 + bicne \irqstat, #((1<<21) | (1<<22) | (1<<23) | (1<<24) | (1<<25))
2798 + bicne \irqstat, #((1<<30))
2799 + beq 1020f
2800 +
2801 +1010:
2802 + @ For non-zero x, LSB(x) = 31 - CLZ(x^(x-1))
2803 + @ N.B. CLZ is an ARM5 instruction.
2804 + sub \tmp, \irqstat, #1
2805 + eor \irqstat, \irqstat, \tmp
2806 + clz \tmp, \irqstat
2807 + sub \irqnr, \tmp
2808 +
2809 +1020: @ EQ will be set if no irqs pending
2810 +
2811 + .endm
2812 --- /dev/null
2813 +++ b/arch/arm/mach-bcm2708/include/mach/frc.h
2814 @@ -0,0 +1,38 @@
2815 +/*
2816 + * arch/arm/mach-bcm2708/include/mach/timex.h
2817 + *
2818 + * BCM2708 free running counter (timer)
2819 + *
2820 + * Copyright (C) 2010 Broadcom
2821 + *
2822 + * This program is free software; you can redistribute it and/or modify
2823 + * it under the terms of the GNU General Public License as published by
2824 + * the Free Software Foundation; either version 2 of the License, or
2825 + * (at your option) any later version.
2826 + *
2827 + * This program is distributed in the hope that it will be useful,
2828 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2829 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2830 + * GNU General Public License for more details.
2831 + *
2832 + * You should have received a copy of the GNU General Public License
2833 + * along with this program; if not, write to the Free Software
2834 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
2835 + */
2836 +
2837 +#ifndef _MACH_FRC_H
2838 +#define _MACH_FRC_H
2839 +
2840 +#define FRC_TICK_RATE (1000000)
2841 +
2842 +/*! Free running counter incrementing at the CLOCK_TICK_RATE
2843 + (slightly faster than frc_clock_ticks63()
2844 + */
2845 +extern unsigned long frc_clock_ticks32(void);
2846 +
2847 +/*! Free running counter incrementing at the CLOCK_TICK_RATE
2848 + * Note - top bit should be ignored (see cnt32_to_63)
2849 + */
2850 +extern unsigned long long frc_clock_ticks63(void);
2851 +
2852 +#endif
2853 --- /dev/null
2854 +++ b/arch/arm/mach-bcm2708/include/mach/hardware.h
2855 @@ -0,0 +1,28 @@
2856 +/*
2857 + * arch/arm/mach-bcm2708/include/mach/hardware.h
2858 + *
2859 + * This file contains the hardware definitions of the BCM2708 devices.
2860 + *
2861 + * Copyright (C) 2010 Broadcom
2862 + *
2863 + * This program is free software; you can redistribute it and/or modify
2864 + * it under the terms of the GNU General Public License as published by
2865 + * the Free Software Foundation; either version 2 of the License, or
2866 + * (at your option) any later version.
2867 + *
2868 + * This program is distributed in the hope that it will be useful,
2869 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2870 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2871 + * GNU General Public License for more details.
2872 + *
2873 + * You should have received a copy of the GNU General Public License
2874 + * along with this program; if not, write to the Free Software
2875 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
2876 + */
2877 +#ifndef __ASM_ARCH_HARDWARE_H
2878 +#define __ASM_ARCH_HARDWARE_H
2879 +
2880 +#include <asm/sizes.h>
2881 +#include <mach/platform.h>
2882 +
2883 +#endif
2884 --- /dev/null
2885 +++ b/arch/arm/mach-bcm2708/include/mach/io.h
2886 @@ -0,0 +1,27 @@
2887 +/*
2888 + * arch/arm/mach-bcm2708/include/mach/io.h
2889 + *
2890 + * Copyright (C) 2003 ARM Limited
2891 + *
2892 + * This program is free software; you can redistribute it and/or modify
2893 + * it under the terms of the GNU General Public License as published by
2894 + * the Free Software Foundation; either version 2 of the License, or
2895 + * (at your option) any later version.
2896 + *
2897 + * This program is distributed in the hope that it will be useful,
2898 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2899 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2900 + * GNU General Public License for more details.
2901 + *
2902 + * You should have received a copy of the GNU General Public License
2903 + * along with this program; if not, write to the Free Software
2904 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
2905 + */
2906 +#ifndef __ASM_ARM_ARCH_IO_H
2907 +#define __ASM_ARM_ARCH_IO_H
2908 +
2909 +#define IO_SPACE_LIMIT 0xffffffff
2910 +
2911 +#define __io(a) __typesafe_io(a)
2912 +
2913 +#endif
2914 --- /dev/null
2915 +++ b/arch/arm/mach-bcm2708/include/mach/irqs.h
2916 @@ -0,0 +1,196 @@
2917 +/*
2918 + * arch/arm/mach-bcm2708/include/mach/irqs.h
2919 + *
2920 + * Copyright (C) 2010 Broadcom
2921 + * Copyright (C) 2003 ARM Limited
2922 + * Copyright (C) 2000 Deep Blue Solutions Ltd.
2923 + *
2924 + * This program is free software; you can redistribute it and/or modify
2925 + * it under the terms of the GNU General Public License as published by
2926 + * the Free Software Foundation; either version 2 of the License, or
2927 + * (at your option) any later version.
2928 + *
2929 + * This program is distributed in the hope that it will be useful,
2930 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2931 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2932 + * GNU General Public License for more details.
2933 + *
2934 + * You should have received a copy of the GNU General Public License
2935 + * along with this program; if not, write to the Free Software
2936 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
2937 + */
2938 +
2939 +#ifndef _BCM2708_IRQS_H_
2940 +#define _BCM2708_IRQS_H_
2941 +
2942 +#include <mach/platform.h>
2943 +
2944 +/*
2945 + * IRQ interrupts definitions are the same as the INT definitions
2946 + * held within platform.h
2947 + */
2948 +#define IRQ_ARMCTRL_START 0
2949 +#define IRQ_TIMER0 (IRQ_ARMCTRL_START + INTERRUPT_TIMER0)
2950 +#define IRQ_TIMER1 (IRQ_ARMCTRL_START + INTERRUPT_TIMER1)
2951 +#define IRQ_TIMER2 (IRQ_ARMCTRL_START + INTERRUPT_TIMER2)
2952 +#define IRQ_TIMER3 (IRQ_ARMCTRL_START + INTERRUPT_TIMER3)
2953 +#define IRQ_CODEC0 (IRQ_ARMCTRL_START + INTERRUPT_CODEC0)
2954 +#define IRQ_CODEC1 (IRQ_ARMCTRL_START + INTERRUPT_CODEC1)
2955 +#define IRQ_CODEC2 (IRQ_ARMCTRL_START + INTERRUPT_CODEC2)
2956 +#define IRQ_JPEG (IRQ_ARMCTRL_START + INTERRUPT_JPEG)
2957 +#define IRQ_ISP (IRQ_ARMCTRL_START + INTERRUPT_ISP)
2958 +#define IRQ_USB (IRQ_ARMCTRL_START + INTERRUPT_USB)
2959 +#define IRQ_3D (IRQ_ARMCTRL_START + INTERRUPT_3D)
2960 +#define IRQ_TRANSPOSER (IRQ_ARMCTRL_START + INTERRUPT_TRANSPOSER)
2961 +#define IRQ_MULTICORESYNC0 (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC0)
2962 +#define IRQ_MULTICORESYNC1 (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC1)
2963 +#define IRQ_MULTICORESYNC2 (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC2)
2964 +#define IRQ_MULTICORESYNC3 (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC3)
2965 +#define IRQ_DMA0 (IRQ_ARMCTRL_START + INTERRUPT_DMA0)
2966 +#define IRQ_DMA1 (IRQ_ARMCTRL_START + INTERRUPT_DMA1)
2967 +#define IRQ_DMA2 (IRQ_ARMCTRL_START + INTERRUPT_DMA2)
2968 +#define IRQ_DMA3 (IRQ_ARMCTRL_START + INTERRUPT_DMA3)
2969 +#define IRQ_DMA4 (IRQ_ARMCTRL_START + INTERRUPT_DMA4)
2970 +#define IRQ_DMA5 (IRQ_ARMCTRL_START + INTERRUPT_DMA5)
2971 +#define IRQ_DMA6 (IRQ_ARMCTRL_START + INTERRUPT_DMA6)
2972 +#define IRQ_DMA7 (IRQ_ARMCTRL_START + INTERRUPT_DMA7)
2973 +#define IRQ_DMA8 (IRQ_ARMCTRL_START + INTERRUPT_DMA8)
2974 +#define IRQ_DMA9 (IRQ_ARMCTRL_START + INTERRUPT_DMA9)
2975 +#define IRQ_DMA10 (IRQ_ARMCTRL_START + INTERRUPT_DMA10)
2976 +#define IRQ_DMA11 (IRQ_ARMCTRL_START + INTERRUPT_DMA11)
2977 +#define IRQ_DMA12 (IRQ_ARMCTRL_START + INTERRUPT_DMA12)
2978 +#define IRQ_AUX (IRQ_ARMCTRL_START + INTERRUPT_AUX)
2979 +#define IRQ_ARM (IRQ_ARMCTRL_START + INTERRUPT_ARM)
2980 +#define IRQ_VPUDMA (IRQ_ARMCTRL_START + INTERRUPT_VPUDMA)
2981 +#define IRQ_HOSTPORT (IRQ_ARMCTRL_START + INTERRUPT_HOSTPORT)
2982 +#define IRQ_VIDEOSCALER (IRQ_ARMCTRL_START + INTERRUPT_VIDEOSCALER)
2983 +#define IRQ_CCP2TX (IRQ_ARMCTRL_START + INTERRUPT_CCP2TX)
2984 +#define IRQ_SDC (IRQ_ARMCTRL_START + INTERRUPT_SDC)
2985 +#define IRQ_DSI0 (IRQ_ARMCTRL_START + INTERRUPT_DSI0)
2986 +#define IRQ_AVE (IRQ_ARMCTRL_START + INTERRUPT_AVE)
2987 +#define IRQ_CAM0 (IRQ_ARMCTRL_START + INTERRUPT_CAM0)
2988 +#define IRQ_CAM1 (IRQ_ARMCTRL_START + INTERRUPT_CAM1)
2989 +#define IRQ_HDMI0 (IRQ_ARMCTRL_START + INTERRUPT_HDMI0)
2990 +#define IRQ_HDMI1 (IRQ_ARMCTRL_START + INTERRUPT_HDMI1)
2991 +#define IRQ_PIXELVALVE1 (IRQ_ARMCTRL_START + INTERRUPT_PIXELVALVE1)
2992 +#define IRQ_I2CSPISLV (IRQ_ARMCTRL_START + INTERRUPT_I2CSPISLV)
2993 +#define IRQ_DSI1 (IRQ_ARMCTRL_START + INTERRUPT_DSI1)
2994 +#define IRQ_PWA0 (IRQ_ARMCTRL_START + INTERRUPT_PWA0)
2995 +#define IRQ_PWA1 (IRQ_ARMCTRL_START + INTERRUPT_PWA1)
2996 +#define IRQ_CPR (IRQ_ARMCTRL_START + INTERRUPT_CPR)
2997 +#define IRQ_SMI (IRQ_ARMCTRL_START + INTERRUPT_SMI)
2998 +#define IRQ_GPIO0 (IRQ_ARMCTRL_START + INTERRUPT_GPIO0)
2999 +#define IRQ_GPIO1 (IRQ_ARMCTRL_START + INTERRUPT_GPIO1)
3000 +#define IRQ_GPIO2 (IRQ_ARMCTRL_START + INTERRUPT_GPIO2)
3001 +#define IRQ_GPIO3 (IRQ_ARMCTRL_START + INTERRUPT_GPIO3)
3002 +#define IRQ_I2C (IRQ_ARMCTRL_START + INTERRUPT_I2C)
3003 +#define IRQ_SPI (IRQ_ARMCTRL_START + INTERRUPT_SPI)
3004 +#define IRQ_I2SPCM (IRQ_ARMCTRL_START + INTERRUPT_I2SPCM)
3005 +#define IRQ_SDIO (IRQ_ARMCTRL_START + INTERRUPT_SDIO)
3006 +#define IRQ_UART (IRQ_ARMCTRL_START + INTERRUPT_UART)
3007 +#define IRQ_SLIMBUS (IRQ_ARMCTRL_START + INTERRUPT_SLIMBUS)
3008 +#define IRQ_VEC (IRQ_ARMCTRL_START + INTERRUPT_VEC)
3009 +#define IRQ_CPG (IRQ_ARMCTRL_START + INTERRUPT_CPG)
3010 +#define IRQ_RNG (IRQ_ARMCTRL_START + INTERRUPT_RNG)
3011 +#define IRQ_ARASANSDIO (IRQ_ARMCTRL_START + INTERRUPT_ARASANSDIO)
3012 +#define IRQ_AVSPMON (IRQ_ARMCTRL_START + INTERRUPT_AVSPMON)
3013 +
3014 +#define IRQ_ARM_TIMER (IRQ_ARMCTRL_START + INTERRUPT_ARM_TIMER)
3015 +#define IRQ_ARM_MAILBOX (IRQ_ARMCTRL_START + INTERRUPT_ARM_MAILBOX)
3016 +#define IRQ_ARM_DOORBELL_0 (IRQ_ARMCTRL_START + INTERRUPT_ARM_DOORBELL_0)
3017 +#define IRQ_ARM_DOORBELL_1 (IRQ_ARMCTRL_START + INTERRUPT_ARM_DOORBELL_1)
3018 +#define IRQ_VPU0_HALTED (IRQ_ARMCTRL_START + INTERRUPT_VPU0_HALTED)
3019 +#define IRQ_VPU1_HALTED (IRQ_ARMCTRL_START + INTERRUPT_VPU1_HALTED)
3020 +#define IRQ_ILLEGAL_TYPE0 (IRQ_ARMCTRL_START + INTERRUPT_ILLEGAL_TYPE0)
3021 +#define IRQ_ILLEGAL_TYPE1 (IRQ_ARMCTRL_START + INTERRUPT_ILLEGAL_TYPE1)
3022 +#define IRQ_PENDING1 (IRQ_ARMCTRL_START + INTERRUPT_PENDING1)
3023 +#define IRQ_PENDING2 (IRQ_ARMCTRL_START + INTERRUPT_PENDING2)
3024 +
3025 +/*
3026 + * FIQ interrupts definitions are the same as the INT definitions.
3027 + */
3028 +#define FIQ_TIMER0 INT_TIMER0
3029 +#define FIQ_TIMER1 INT_TIMER1
3030 +#define FIQ_TIMER2 INT_TIMER2
3031 +#define FIQ_TIMER3 INT_TIMER3
3032 +#define FIQ_CODEC0 INT_CODEC0
3033 +#define FIQ_CODEC1 INT_CODEC1
3034 +#define FIQ_CODEC2 INT_CODEC2
3035 +#define FIQ_JPEG INT_JPEG
3036 +#define FIQ_ISP INT_ISP
3037 +#define FIQ_USB INT_USB
3038 +#define FIQ_3D INT_3D
3039 +#define FIQ_TRANSPOSER INT_TRANSPOSER
3040 +#define FIQ_MULTICORESYNC0 INT_MULTICORESYNC0
3041 +#define FIQ_MULTICORESYNC1 INT_MULTICORESYNC1
3042 +#define FIQ_MULTICORESYNC2 INT_MULTICORESYNC2
3043 +#define FIQ_MULTICORESYNC3 INT_MULTICORESYNC3
3044 +#define FIQ_DMA0 INT_DMA0
3045 +#define FIQ_DMA1 INT_DMA1
3046 +#define FIQ_DMA2 INT_DMA2
3047 +#define FIQ_DMA3 INT_DMA3
3048 +#define FIQ_DMA4 INT_DMA4
3049 +#define FIQ_DMA5 INT_DMA5
3050 +#define FIQ_DMA6 INT_DMA6
3051 +#define FIQ_DMA7 INT_DMA7
3052 +#define FIQ_DMA8 INT_DMA8
3053 +#define FIQ_DMA9 INT_DMA9
3054 +#define FIQ_DMA10 INT_DMA10
3055 +#define FIQ_DMA11 INT_DMA11
3056 +#define FIQ_DMA12 INT_DMA12
3057 +#define FIQ_AUX INT_AUX
3058 +#define FIQ_ARM INT_ARM
3059 +#define FIQ_VPUDMA INT_VPUDMA
3060 +#define FIQ_HOSTPORT INT_HOSTPORT
3061 +#define FIQ_VIDEOSCALER INT_VIDEOSCALER
3062 +#define FIQ_CCP2TX INT_CCP2TX
3063 +#define FIQ_SDC INT_SDC
3064 +#define FIQ_DSI0 INT_DSI0
3065 +#define FIQ_AVE INT_AVE
3066 +#define FIQ_CAM0 INT_CAM0
3067 +#define FIQ_CAM1 INT_CAM1
3068 +#define FIQ_HDMI0 INT_HDMI0
3069 +#define FIQ_HDMI1 INT_HDMI1
3070 +#define FIQ_PIXELVALVE1 INT_PIXELVALVE1
3071 +#define FIQ_I2CSPISLV INT_I2CSPISLV
3072 +#define FIQ_DSI1 INT_DSI1
3073 +#define FIQ_PWA0 INT_PWA0
3074 +#define FIQ_PWA1 INT_PWA1
3075 +#define FIQ_CPR INT_CPR
3076 +#define FIQ_SMI INT_SMI
3077 +#define FIQ_GPIO0 INT_GPIO0
3078 +#define FIQ_GPIO1 INT_GPIO1
3079 +#define FIQ_GPIO2 INT_GPIO2
3080 +#define FIQ_GPIO3 INT_GPIO3
3081 +#define FIQ_I2C INT_I2C
3082 +#define FIQ_SPI INT_SPI
3083 +#define FIQ_I2SPCM INT_I2SPCM
3084 +#define FIQ_SDIO INT_SDIO
3085 +#define FIQ_UART INT_UART
3086 +#define FIQ_SLIMBUS INT_SLIMBUS
3087 +#define FIQ_VEC INT_VEC
3088 +#define FIQ_CPG INT_CPG
3089 +#define FIQ_RNG INT_RNG
3090 +#define FIQ_ARASANSDIO INT_ARASANSDIO
3091 +#define FIQ_AVSPMON INT_AVSPMON
3092 +
3093 +#define FIQ_ARM_TIMER INT_ARM_TIMER
3094 +#define FIQ_ARM_MAILBOX INT_ARM_MAILBOX
3095 +#define FIQ_ARM_DOORBELL_0 INT_ARM_DOORBELL_0
3096 +#define FIQ_ARM_DOORBELL_1 INT_ARM_DOORBELL_1
3097 +#define FIQ_VPU0_HALTED INT_VPU0_HALTED
3098 +#define FIQ_VPU1_HALTED INT_VPU1_HALTED
3099 +#define FIQ_ILLEGAL_TYPE0 INT_ILLEGAL_TYPE0
3100 +#define FIQ_ILLEGAL_TYPE1 INT_ILLEGAL_TYPE1
3101 +#define FIQ_PENDING1 INT_PENDING1
3102 +#define FIQ_PENDING2 INT_PENDING2
3103 +
3104 +#define HARD_IRQS (64 + 21)
3105 +#define GPIO_IRQ_START (HARD_IRQS)
3106 +#define GPIO_IRQS (32*5)
3107 +#define SPARE_ALLOC_IRQS 64
3108 +#define BCM2708_ALLOC_IRQS (HARD_IRQS+FIQ_IRQS+GPIO_IRQS+SPARE_ALLOC_IRQS)
3109 +#define FREE_IRQS 128
3110 +#define NR_IRQS (BCM2708_ALLOC_IRQS+FREE_IRQS)
3111 +
3112 +#endif /* _BCM2708_IRQS_H_ */
3113 --- /dev/null
3114 +++ b/arch/arm/mach-bcm2708/include/mach/memory.h
3115 @@ -0,0 +1,57 @@
3116 +/*
3117 + * arch/arm/mach-bcm2708/include/mach/memory.h
3118 + *
3119 + * Copyright (C) 2010 Broadcom
3120 + *
3121 + * This program is free software; you can redistribute it and/or modify
3122 + * it under the terms of the GNU General Public License as published by
3123 + * the Free Software Foundation; either version 2 of the License, or
3124 + * (at your option) any later version.
3125 + *
3126 + * This program is distributed in the hope that it will be useful,
3127 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
3128 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3129 + * GNU General Public License for more details.
3130 + *
3131 + * You should have received a copy of the GNU General Public License
3132 + * along with this program; if not, write to the Free Software
3133 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
3134 + */
3135 +#ifndef __ASM_ARCH_MEMORY_H
3136 +#define __ASM_ARCH_MEMORY_H
3137 +
3138 +/* Memory overview:
3139 +
3140 + [ARMcore] <--virtual addr-->
3141 + [ARMmmu] <--physical addr-->
3142 + [GERTmap] <--bus add-->
3143 + [VCperiph]
3144 +
3145 +*/
3146 +
3147 +/*
3148 + * Physical DRAM offset.
3149 + */
3150 +#define BCM_PLAT_PHYS_OFFSET UL(0x00000000)
3151 +#define VC_ARMMEM_OFFSET UL(0x00000000) /* offset in VC of ARM memory */
3152 +
3153 +#ifdef CONFIG_BCM2708_NOL2CACHE
3154 + #define _REAL_BUS_OFFSET UL(0xC0000000) /* don't use L1 or L2 caches */
3155 +#else
3156 + #define _REAL_BUS_OFFSET UL(0x40000000) /* use L2 cache */
3157 +#endif
3158 +
3159 +/* We're using the memory at 64M in the VideoCore for Linux - this adjustment
3160 + * will provide the offset into this area as well as setting the bits that
3161 + * stop the L1 and L2 cache from being used
3162 + *
3163 + * WARNING: this only works because the ARM is given memory at a fixed location
3164 + * (ARMMEM_OFFSET)
3165 + */
3166 +#define BUS_OFFSET (VC_ARMMEM_OFFSET + _REAL_BUS_OFFSET)
3167 +#define __virt_to_bus(x) ((x) + (BUS_OFFSET - PAGE_OFFSET))
3168 +#define __bus_to_virt(x) ((x) - (BUS_OFFSET - PAGE_OFFSET))
3169 +#define __pfn_to_bus(x) (__pfn_to_phys(x) + (BUS_OFFSET - BCM_PLAT_PHYS_OFFSET))
3170 +#define __bus_to_pfn(x) __phys_to_pfn((x) - (BUS_OFFSET - BCM_PLAT_PHYS_OFFSET))
3171 +
3172 +#endif
3173 --- /dev/null
3174 +++ b/arch/arm/mach-bcm2708/include/mach/platform.h
3175 @@ -0,0 +1,228 @@
3176 +/*
3177 + * arch/arm/mach-bcm2708/include/mach/platform.h
3178 + *
3179 + * Copyright (C) 2010 Broadcom
3180 + *
3181 + * This program is free software; you can redistribute it and/or modify
3182 + * it under the terms of the GNU General Public License as published by
3183 + * the Free Software Foundation; either version 2 of the License, or
3184 + * (at your option) any later version.
3185 + *
3186 + * This program is distributed in the hope that it will be useful,
3187 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
3188 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3189 + * GNU General Public License for more details.
3190 + *
3191 + * You should have received a copy of the GNU General Public License
3192 + * along with this program; if not, write to the Free Software
3193 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
3194 + */
3195 +
3196 +#ifndef _BCM2708_PLATFORM_H
3197 +#define _BCM2708_PLATFORM_H
3198 +
3199 +
3200 +/* macros to get at IO space when running virtually */
3201 +#define IO_ADDRESS(x) (((x) & 0x0fffffff) + (((x) >> 4) & 0x0f000000) + 0xf0000000)
3202 +
3203 +#define __io_address(n) IOMEM(IO_ADDRESS(n))
3204 +
3205 +
3206 +/*
3207 + * SDRAM
3208 + */
3209 +#define BCM2708_SDRAM_BASE 0x00000000
3210 +
3211 +/*
3212 + * Logic expansion modules
3213 + *
3214 + */
3215 +
3216 +
3217 +/* ------------------------------------------------------------------------
3218 + * BCM2708 ARMCTRL Registers
3219 + * ------------------------------------------------------------------------
3220 + */
3221 +
3222 +#define HW_REGISTER_RW(addr) (addr)
3223 +#define HW_REGISTER_RO(addr) (addr)
3224 +
3225 +#include "arm_control.h"
3226 +#undef ARM_BASE
3227 +
3228 +/*
3229 + * Definitions and addresses for the ARM CONTROL logic
3230 + * This file is manually generated.
3231 + */
3232 +
3233 +#define BCM2708_PERI_BASE 0x20000000
3234 +#define IC0_BASE (BCM2708_PERI_BASE + 0x2000)
3235 +#define ST_BASE (BCM2708_PERI_BASE + 0x3000) /* System Timer */
3236 +#define MPHI_BASE (BCM2708_PERI_BASE + 0x6000) /* Message -based Parallel Host Interface */
3237 +#define DMA_BASE (BCM2708_PERI_BASE + 0x7000) /* DMA controller */
3238 +#define ARM_BASE (BCM2708_PERI_BASE + 0xB000) /* BCM2708 ARM control block */
3239 +#define PM_BASE (BCM2708_PERI_BASE + 0x100000) /* Power Management, Reset controller and Watchdog registers */
3240 +#define PCM_CLOCK_BASE (BCM2708_PERI_BASE + 0x101098) /* PCM Clock */
3241 +#define RNG_BASE (BCM2708_PERI_BASE + 0x104000) /* Hardware RNG */
3242 +#define GPIO_BASE (BCM2708_PERI_BASE + 0x200000) /* GPIO */
3243 +#define UART0_BASE (BCM2708_PERI_BASE + 0x201000) /* Uart 0 */
3244 +#define MMCI0_BASE (BCM2708_PERI_BASE + 0x202000) /* MMC interface */
3245 +#define I2S_BASE (BCM2708_PERI_BASE + 0x203000) /* I2S */
3246 +#define SPI0_BASE (BCM2708_PERI_BASE + 0x204000) /* SPI0 */
3247 +#define BSC0_BASE (BCM2708_PERI_BASE + 0x205000) /* BSC0 I2C/TWI */
3248 +#define UART1_BASE (BCM2708_PERI_BASE + 0x215000) /* Uart 1 */
3249 +#define EMMC_BASE (BCM2708_PERI_BASE + 0x300000) /* eMMC interface */
3250 +#define SMI_BASE (BCM2708_PERI_BASE + 0x600000) /* SMI */
3251 +#define BSC1_BASE (BCM2708_PERI_BASE + 0x804000) /* BSC1 I2C/TWI */
3252 +#define USB_BASE (BCM2708_PERI_BASE + 0x980000) /* DTC_OTG USB controller */
3253 +#define MCORE_BASE (BCM2708_PERI_BASE + 0x0000) /* Fake frame buffer device (actually the multicore sync block*/
3254 +
3255 +#define ARMCTRL_BASE (ARM_BASE + 0x000)
3256 +#define ARMCTRL_IC_BASE (ARM_BASE + 0x200) /* ARM interrupt controller */
3257 +#define ARMCTRL_TIMER0_1_BASE (ARM_BASE + 0x400) /* Timer 0 and 1 */
3258 +#define ARMCTRL_0_SBM_BASE (ARM_BASE + 0x800) /* User 0 (ARM)'s Semaphores Doorbells and Mailboxes */
3259 +
3260 +
3261 +/*
3262 + * Interrupt assignments
3263 + */
3264 +
3265 +#define ARM_IRQ1_BASE 0
3266 +#define INTERRUPT_TIMER0 (ARM_IRQ1_BASE + 0)
3267 +#define INTERRUPT_TIMER1 (ARM_IRQ1_BASE + 1)
3268 +#define INTERRUPT_TIMER2 (ARM_IRQ1_BASE + 2)
3269 +#define INTERRUPT_TIMER3 (ARM_IRQ1_BASE + 3)
3270 +#define INTERRUPT_CODEC0 (ARM_IRQ1_BASE + 4)
3271 +#define INTERRUPT_CODEC1 (ARM_IRQ1_BASE + 5)
3272 +#define INTERRUPT_CODEC2 (ARM_IRQ1_BASE + 6)
3273 +#define INTERRUPT_VC_JPEG (ARM_IRQ1_BASE + 7)
3274 +#define INTERRUPT_ISP (ARM_IRQ1_BASE + 8)
3275 +#define INTERRUPT_VC_USB (ARM_IRQ1_BASE + 9)
3276 +#define INTERRUPT_VC_3D (ARM_IRQ1_BASE + 10)
3277 +#define INTERRUPT_TRANSPOSER (ARM_IRQ1_BASE + 11)
3278 +#define INTERRUPT_MULTICORESYNC0 (ARM_IRQ1_BASE + 12)
3279 +#define INTERRUPT_MULTICORESYNC1 (ARM_IRQ1_BASE + 13)
3280 +#define INTERRUPT_MULTICORESYNC2 (ARM_IRQ1_BASE + 14)
3281 +#define INTERRUPT_MULTICORESYNC3 (ARM_IRQ1_BASE + 15)
3282 +#define INTERRUPT_DMA0 (ARM_IRQ1_BASE + 16)
3283 +#define INTERRUPT_DMA1 (ARM_IRQ1_BASE + 17)
3284 +#define INTERRUPT_VC_DMA2 (ARM_IRQ1_BASE + 18)
3285 +#define INTERRUPT_VC_DMA3 (ARM_IRQ1_BASE + 19)
3286 +#define INTERRUPT_DMA4 (ARM_IRQ1_BASE + 20)
3287 +#define INTERRUPT_DMA5 (ARM_IRQ1_BASE + 21)
3288 +#define INTERRUPT_DMA6 (ARM_IRQ1_BASE + 22)
3289 +#define INTERRUPT_DMA7 (ARM_IRQ1_BASE + 23)
3290 +#define INTERRUPT_DMA8 (ARM_IRQ1_BASE + 24)
3291 +#define INTERRUPT_DMA9 (ARM_IRQ1_BASE + 25)
3292 +#define INTERRUPT_DMA10 (ARM_IRQ1_BASE + 26)
3293 +#define INTERRUPT_DMA11 (ARM_IRQ1_BASE + 27)
3294 +#define INTERRUPT_DMA12 (ARM_IRQ1_BASE + 28)
3295 +#define INTERRUPT_AUX (ARM_IRQ1_BASE + 29)
3296 +#define INTERRUPT_ARM (ARM_IRQ1_BASE + 30)
3297 +#define INTERRUPT_VPUDMA (ARM_IRQ1_BASE + 31)
3298 +
3299 +#define ARM_IRQ2_BASE 32
3300 +#define INTERRUPT_HOSTPORT (ARM_IRQ2_BASE + 0)
3301 +#define INTERRUPT_VIDEOSCALER (ARM_IRQ2_BASE + 1)
3302 +#define INTERRUPT_CCP2TX (ARM_IRQ2_BASE + 2)
3303 +#define INTERRUPT_SDC (ARM_IRQ2_BASE + 3)
3304 +#define INTERRUPT_DSI0 (ARM_IRQ2_BASE + 4)
3305 +#define INTERRUPT_AVE (ARM_IRQ2_BASE + 5)
3306 +#define INTERRUPT_CAM0 (ARM_IRQ2_BASE + 6)
3307 +#define INTERRUPT_CAM1 (ARM_IRQ2_BASE + 7)
3308 +#define INTERRUPT_HDMI0 (ARM_IRQ2_BASE + 8)
3309 +#define INTERRUPT_HDMI1 (ARM_IRQ2_BASE + 9)
3310 +#define INTERRUPT_PIXELVALVE1 (ARM_IRQ2_BASE + 10)
3311 +#define INTERRUPT_I2CSPISLV (ARM_IRQ2_BASE + 11)
3312 +#define INTERRUPT_DSI1 (ARM_IRQ2_BASE + 12)
3313 +#define INTERRUPT_PWA0 (ARM_IRQ2_BASE + 13)
3314 +#define INTERRUPT_PWA1 (ARM_IRQ2_BASE + 14)
3315 +#define INTERRUPT_CPR (ARM_IRQ2_BASE + 15)
3316 +#define INTERRUPT_SMI (ARM_IRQ2_BASE + 16)
3317 +#define INTERRUPT_GPIO0 (ARM_IRQ2_BASE + 17)
3318 +#define INTERRUPT_GPIO1 (ARM_IRQ2_BASE + 18)
3319 +#define INTERRUPT_GPIO2 (ARM_IRQ2_BASE + 19)
3320 +#define INTERRUPT_GPIO3 (ARM_IRQ2_BASE + 20)
3321 +#define INTERRUPT_VC_I2C (ARM_IRQ2_BASE + 21)
3322 +#define INTERRUPT_VC_SPI (ARM_IRQ2_BASE + 22)
3323 +#define INTERRUPT_VC_I2SPCM (ARM_IRQ2_BASE + 23)
3324 +#define INTERRUPT_VC_SDIO (ARM_IRQ2_BASE + 24)
3325 +#define INTERRUPT_VC_UART (ARM_IRQ2_BASE + 25)
3326 +#define INTERRUPT_SLIMBUS (ARM_IRQ2_BASE + 26)
3327 +#define INTERRUPT_VEC (ARM_IRQ2_BASE + 27)
3328 +#define INTERRUPT_CPG (ARM_IRQ2_BASE + 28)
3329 +#define INTERRUPT_RNG (ARM_IRQ2_BASE + 29)
3330 +#define INTERRUPT_VC_ARASANSDIO (ARM_IRQ2_BASE + 30)
3331 +#define INTERRUPT_AVSPMON (ARM_IRQ2_BASE + 31)
3332 +
3333 +#define ARM_IRQ0_BASE 64
3334 +#define INTERRUPT_ARM_TIMER (ARM_IRQ0_BASE + 0)
3335 +#define INTERRUPT_ARM_MAILBOX (ARM_IRQ0_BASE + 1)
3336 +#define INTERRUPT_ARM_DOORBELL_0 (ARM_IRQ0_BASE + 2)
3337 +#define INTERRUPT_ARM_DOORBELL_1 (ARM_IRQ0_BASE + 3)
3338 +#define INTERRUPT_VPU0_HALTED (ARM_IRQ0_BASE + 4)
3339 +#define INTERRUPT_VPU1_HALTED (ARM_IRQ0_BASE + 5)
3340 +#define INTERRUPT_ILLEGAL_TYPE0 (ARM_IRQ0_BASE + 6)
3341 +#define INTERRUPT_ILLEGAL_TYPE1 (ARM_IRQ0_BASE + 7)
3342 +#define INTERRUPT_PENDING1 (ARM_IRQ0_BASE + 8)
3343 +#define INTERRUPT_PENDING2 (ARM_IRQ0_BASE + 9)
3344 +#define INTERRUPT_JPEG (ARM_IRQ0_BASE + 10)
3345 +#define INTERRUPT_USB (ARM_IRQ0_BASE + 11)
3346 +#define INTERRUPT_3D (ARM_IRQ0_BASE + 12)
3347 +#define INTERRUPT_DMA2 (ARM_IRQ0_BASE + 13)
3348 +#define INTERRUPT_DMA3 (ARM_IRQ0_BASE + 14)
3349 +#define INTERRUPT_I2C (ARM_IRQ0_BASE + 15)
3350 +#define INTERRUPT_SPI (ARM_IRQ0_BASE + 16)
3351 +#define INTERRUPT_I2SPCM (ARM_IRQ0_BASE + 17)
3352 +#define INTERRUPT_SDIO (ARM_IRQ0_BASE + 18)
3353 +#define INTERRUPT_UART (ARM_IRQ0_BASE + 19)
3354 +#define INTERRUPT_ARASANSDIO (ARM_IRQ0_BASE + 20)
3355 +
3356 +#define MAXIRQNUM (32 + 32 + 20)
3357 +#define MAXFIQNUM (32 + 32 + 20)
3358 +
3359 +#define MAX_TIMER 2
3360 +#define MAX_PERIOD 699050
3361 +#define TICKS_PER_uSEC 1
3362 +
3363 +/*
3364 + * These are useconds NOT ticks.
3365 + *
3366 + */
3367 +#define mSEC_1 1000
3368 +#define mSEC_5 (mSEC_1 * 5)
3369 +#define mSEC_10 (mSEC_1 * 10)
3370 +#define mSEC_25 (mSEC_1 * 25)
3371 +#define SEC_1 (mSEC_1 * 1000)
3372 +
3373 +/*
3374 + * Watchdog
3375 + */
3376 +#define PM_RSTC (PM_BASE+0x1c)
3377 +#define PM_RSTS (PM_BASE+0x20)
3378 +#define PM_WDOG (PM_BASE+0x24)
3379 +
3380 +#define PM_WDOG_RESET 0000000000
3381 +#define PM_PASSWORD 0x5a000000
3382 +#define PM_WDOG_TIME_SET 0x000fffff
3383 +#define PM_RSTC_WRCFG_CLR 0xffffffcf
3384 +#define PM_RSTC_WRCFG_SET 0x00000030
3385 +#define PM_RSTC_WRCFG_FULL_RESET 0x00000020
3386 +#define PM_RSTC_RESET 0x00000102
3387 +
3388 +#define PM_RSTS_HADPOR_SET 0x00001000
3389 +#define PM_RSTS_HADSRH_SET 0x00000400
3390 +#define PM_RSTS_HADSRF_SET 0x00000200
3391 +#define PM_RSTS_HADSRQ_SET 0x00000100
3392 +#define PM_RSTS_HADWRH_SET 0x00000040
3393 +#define PM_RSTS_HADWRF_SET 0x00000020
3394 +#define PM_RSTS_HADWRQ_SET 0x00000010
3395 +#define PM_RSTS_HADDRH_SET 0x00000004
3396 +#define PM_RSTS_HADDRF_SET 0x00000002
3397 +#define PM_RSTS_HADDRQ_SET 0x00000001
3398 +
3399 +#define UART0_CLOCK 3000000
3400 +
3401 +#endif
3402 +
3403 +/* END */
3404 --- /dev/null
3405 +++ b/arch/arm/mach-bcm2708/include/mach/power.h
3406 @@ -0,0 +1,26 @@
3407 +/*
3408 + * linux/arch/arm/mach-bcm2708/power.h
3409 + *
3410 + * Copyright (C) 2010 Broadcom
3411 + *
3412 + * This program is free software; you can redistribute it and/or modify
3413 + * it under the terms of the GNU General Public License version 2 as
3414 + * published by the Free Software Foundation.
3415 + *
3416 + * This device provides a shared mechanism for controlling the power to
3417 + * VideoCore subsystems.
3418 + */
3419 +
3420 +#ifndef _MACH_BCM2708_POWER_H
3421 +#define _MACH_BCM2708_POWER_H
3422 +
3423 +#include <linux/types.h>
3424 +#include <mach/arm_power.h>
3425 +
3426 +typedef unsigned int BCM_POWER_HANDLE_T;
3427 +
3428 +extern int bcm_power_open(BCM_POWER_HANDLE_T *handle);
3429 +extern int bcm_power_request(BCM_POWER_HANDLE_T handle, uint32_t request);
3430 +extern int bcm_power_close(BCM_POWER_HANDLE_T handle);
3431 +
3432 +#endif
3433 --- /dev/null
3434 +++ b/arch/arm/mach-bcm2708/include/mach/system.h
3435 @@ -0,0 +1,38 @@
3436 +/*
3437 + * arch/arm/mach-bcm2708/include/mach/system.h
3438 + *
3439 + * Copyright (C) 2010 Broadcom
3440 + * Copyright (C) 2003 ARM Limited
3441 + * Copyright (C) 2000 Deep Blue Solutions Ltd
3442 + *
3443 + * This program is free software; you can redistribute it and/or modify
3444 + * it under the terms of the GNU General Public License as published by
3445 + * the Free Software Foundation; either version 2 of the License, or
3446 + * (at your option) any later version.
3447 + *
3448 + * This program is distributed in the hope that it will be useful,
3449 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
3450 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3451 + * GNU General Public License for more details.
3452 + *
3453 + * You should have received a copy of the GNU General Public License
3454 + * along with this program; if not, write to the Free Software
3455 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
3456 + */
3457 +#ifndef __ASM_ARCH_SYSTEM_H
3458 +#define __ASM_ARCH_SYSTEM_H
3459 +
3460 +#include <linux/io.h>
3461 +#include <mach/hardware.h>
3462 +#include <mach/platform.h>
3463 +
3464 +static inline void arch_idle(void)
3465 +{
3466 + /*
3467 + * This should do all the clock switching
3468 + * and wait for interrupt tricks
3469 + */
3470 + cpu_do_idle();
3471 +}
3472 +
3473 +#endif
3474 --- /dev/null
3475 +++ b/arch/arm/mach-bcm2708/include/mach/timex.h
3476 @@ -0,0 +1,23 @@
3477 +/*
3478 + * arch/arm/mach-bcm2708/include/mach/timex.h
3479 + *
3480 + * BCM2708 sysem clock frequency
3481 + *
3482 + * Copyright (C) 2010 Broadcom
3483 + *
3484 + * This program is free software; you can redistribute it and/or modify
3485 + * it under the terms of the GNU General Public License as published by
3486 + * the Free Software Foundation; either version 2 of the License, or
3487 + * (at your option) any later version.
3488 + *
3489 + * This program is distributed in the hope that it will be useful,
3490 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
3491 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3492 + * GNU General Public License for more details.
3493 + *
3494 + * You should have received a copy of the GNU General Public License
3495 + * along with this program; if not, write to the Free Software
3496 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
3497 + */
3498 +
3499 +#define CLOCK_TICK_RATE (1000000)
3500 --- /dev/null
3501 +++ b/arch/arm/mach-bcm2708/include/mach/uncompress.h
3502 @@ -0,0 +1,84 @@
3503 +/*
3504 + * arch/arm/mach-bcn2708/include/mach/uncompress.h
3505 + *
3506 + * Copyright (C) 2010 Broadcom
3507 + * Copyright (C) 2003 ARM Limited
3508 + *
3509 + * This program is free software; you can redistribute it and/or modify
3510 + * it under the terms of the GNU General Public License as published by
3511 + * the Free Software Foundation; either version 2 of the License, or
3512 + * (at your option) any later version.
3513 + *
3514 + * This program is distributed in the hope that it will be useful,
3515 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
3516 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3517 + * GNU General Public License for more details.
3518 + *
3519 + * You should have received a copy of the GNU General Public License
3520 + * along with this program; if not, write to the Free Software
3521 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
3522 + */
3523 +
3524 +#include <linux/io.h>
3525 +#include <linux/amba/serial.h>
3526 +#include <mach/hardware.h>
3527 +
3528 +#define UART_BAUD 115200
3529 +
3530 +#define BCM2708_UART_DR __io(UART0_BASE + UART01x_DR)
3531 +#define BCM2708_UART_FR __io(UART0_BASE + UART01x_FR)
3532 +#define BCM2708_UART_IBRD __io(UART0_BASE + UART011_IBRD)
3533 +#define BCM2708_UART_FBRD __io(UART0_BASE + UART011_FBRD)
3534 +#define BCM2708_UART_LCRH __io(UART0_BASE + UART011_LCRH)
3535 +#define BCM2708_UART_CR __io(UART0_BASE + UART011_CR)
3536 +
3537 +/*
3538 + * This does not append a newline
3539 + */
3540 +static inline void putc(int c)
3541 +{
3542 + while (__raw_readl(BCM2708_UART_FR) & UART01x_FR_TXFF)
3543 + barrier();
3544 +
3545 + __raw_writel(c, BCM2708_UART_DR);
3546 +}
3547 +
3548 +static inline void flush(void)
3549 +{
3550 + int fr;
3551 +
3552 + do {
3553 + fr = __raw_readl(BCM2708_UART_FR);
3554 + barrier();
3555 + } while ((fr & (UART011_FR_TXFE | UART01x_FR_BUSY)) != UART011_FR_TXFE);
3556 +}
3557 +
3558 +static inline void arch_decomp_setup(void)
3559 +{
3560 + int temp, div, rem, frac;
3561 +
3562 + temp = 16 * UART_BAUD;
3563 + div = UART0_CLOCK / temp;
3564 + rem = UART0_CLOCK % temp;
3565 + temp = (8 * rem) / UART_BAUD;
3566 + frac = (temp >> 1) + (temp & 1);
3567 +
3568 + /* Make sure the UART is disabled before we start */
3569 + __raw_writel(0, BCM2708_UART_CR);
3570 +
3571 + /* Set the baud rate */
3572 + __raw_writel(div, BCM2708_UART_IBRD);
3573 + __raw_writel(frac, BCM2708_UART_FBRD);
3574 +
3575 + /* Set the UART to 8n1, FIFO enabled */
3576 + __raw_writel(UART01x_LCRH_WLEN_8 | UART01x_LCRH_FEN, BCM2708_UART_LCRH);
3577 +
3578 + /* Enable the UART */
3579 + __raw_writel(UART01x_CR_UARTEN | UART011_CR_TXE | UART011_CR_RXE,
3580 + BCM2708_UART_CR);
3581 +}
3582 +
3583 +/*
3584 + * nothing to do
3585 + */
3586 +#define arch_decomp_wdog()
3587 --- /dev/null
3588 +++ b/arch/arm/mach-bcm2708/include/mach/vc_mem.h
3589 @@ -0,0 +1,35 @@
3590 +/*****************************************************************************
3591 +* Copyright 2010 - 2011 Broadcom Corporation. All rights reserved.
3592 +*
3593 +* Unless you and Broadcom execute a separate written software license
3594 +* agreement governing use of this software, this software is licensed to you
3595 +* under the terms of the GNU General Public License version 2, available at
3596 +* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
3597 +*
3598 +* Notwithstanding the above, under no circumstances may you combine this
3599 +* software in any way with any other Broadcom software provided under a
3600 +* license other than the GPL, without Broadcom's express prior written
3601 +* consent.
3602 +*****************************************************************************/
3603 +
3604 +#if !defined( VC_MEM_H )
3605 +#define VC_MEM_H
3606 +
3607 +#include <linux/ioctl.h>
3608 +
3609 +#define VC_MEM_IOC_MAGIC 'v'
3610 +
3611 +#define VC_MEM_IOC_MEM_PHYS_ADDR _IOR( VC_MEM_IOC_MAGIC, 0, unsigned long )
3612 +#define VC_MEM_IOC_MEM_SIZE _IOR( VC_MEM_IOC_MAGIC, 1, unsigned int )
3613 +#define VC_MEM_IOC_MEM_BASE _IOR( VC_MEM_IOC_MAGIC, 2, unsigned int )
3614 +#define VC_MEM_IOC_MEM_LOAD _IOR( VC_MEM_IOC_MAGIC, 3, unsigned int )
3615 +
3616 +#if defined( __KERNEL__ )
3617 +#define VC_MEM_TO_ARM_ADDR_MASK 0x3FFFFFFF
3618 +
3619 +extern unsigned long mm_vc_mem_phys_addr;
3620 +extern unsigned int mm_vc_mem_size;
3621 +extern int vc_mem_get_current_size( void );
3622 +#endif
3623 +
3624 +#endif /* VC_MEM_H */
3625 --- /dev/null
3626 +++ b/arch/arm/mach-bcm2708/include/mach/vcio.h
3627 @@ -0,0 +1,165 @@
3628 +/*
3629 + * arch/arm/mach-bcm2708/include/mach/vcio.h
3630 + *
3631 + * Copyright (C) 2010 Broadcom
3632 + *
3633 + * This program is free software; you can redistribute it and/or modify
3634 + * it under the terms of the GNU General Public License as published by
3635 + * the Free Software Foundation; either version 2 of the License, or
3636 + * (at your option) any later version.
3637 + *
3638 + * This program is distributed in the hope that it will be useful,
3639 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
3640 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3641 + * GNU General Public License for more details.
3642 + *
3643 + * You should have received a copy of the GNU General Public License
3644 + * along with this program; if not, write to the Free Software
3645 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
3646 + */
3647 +#ifndef _MACH_BCM2708_VCIO_H
3648 +#define _MACH_BCM2708_VCIO_H
3649 +
3650 +/* Routines to handle I/O via the VideoCore "ARM control" registers
3651 + * (semaphores, doorbells, mailboxes)
3652 + */
3653 +
3654 +#define BCM_VCIO_DRIVER_NAME "bcm2708_vcio"
3655 +
3656 +/* Constants shared with the ARM identifying separate mailbox channels */
3657 +#define MBOX_CHAN_POWER 0 /* for use by the power management interface */
3658 +#define MBOX_CHAN_FB 1 /* for use by the frame buffer */
3659 +#define MBOX_CHAN_VCHIQ 3 /* for use by the VCHIQ interface */
3660 +#define MBOX_CHAN_PROPERTY 8 /* for use by the property channel */
3661 +#define MBOX_CHAN_COUNT 9
3662 +
3663 +enum {
3664 + VCMSG_PROCESS_REQUEST = 0x00000000
3665 +};
3666 +enum {
3667 + VCMSG_REQUEST_SUCCESSFUL = 0x80000000,
3668 + VCMSG_REQUEST_FAILED = 0x80000001
3669 +};
3670 +/* Mailbox property tags */
3671 +enum {
3672 + VCMSG_PROPERTY_END = 0x00000000,
3673 + VCMSG_GET_FIRMWARE_REVISION = 0x00000001,
3674 + VCMSG_GET_BOARD_MODEL = 0x00010001,
3675 + VCMSG_GET_BOARD_REVISION = 0x00010002,
3676 + VCMSG_GET_BOARD_MAC_ADDRESS = 0x00010003,
3677 + VCMSG_GET_BOARD_SERIAL = 0x00010004,
3678 + VCMSG_GET_ARM_MEMORY = 0x00010005,
3679 + VCMSG_GET_VC_MEMORY = 0x00010006,
3680 + VCMSG_GET_CLOCKS = 0x00010007,
3681 + VCMSG_GET_COMMAND_LINE = 0x00050001,
3682 + VCMSG_GET_DMA_CHANNELS = 0x00060001,
3683 + VCMSG_GET_POWER_STATE = 0x00020001,
3684 + VCMSG_GET_TIMING = 0x00020002,
3685 + VCMSG_SET_POWER_STATE = 0x00028001,
3686 + VCMSG_GET_CLOCK_STATE = 0x00030001,
3687 + VCMSG_SET_CLOCK_STATE = 0x00038001,
3688 + VCMSG_GET_CLOCK_RATE = 0x00030002,
3689 + VCMSG_SET_CLOCK_RATE = 0x00038002,
3690 + VCMSG_GET_VOLTAGE = 0x00030003,
3691 + VCMSG_SET_VOLTAGE = 0x00038003,
3692 + VCMSG_GET_MAX_CLOCK = 0x00030004,
3693 + VCMSG_GET_MAX_VOLTAGE = 0x00030005,
3694 + VCMSG_GET_TEMPERATURE = 0x00030006,
3695 + VCMSG_GET_MIN_CLOCK = 0x00030007,
3696 + VCMSG_GET_MIN_VOLTAGE = 0x00030008,
3697 + VCMSG_GET_TURBO = 0x00030009,
3698 + VCMSG_GET_MAX_TEMPERATURE = 0x0003000a,
3699 + VCMSG_GET_STC = 0x0003000b,
3700 + VCMSG_SET_TURBO = 0x00038009,
3701 + VCMSG_SET_ALLOCATE_MEM = 0x0003000c,
3702 + VCMSG_SET_LOCK_MEM = 0x0003000d,
3703 + VCMSG_SET_UNLOCK_MEM = 0x0003000e,
3704 + VCMSG_SET_RELEASE_MEM = 0x0003000f,
3705 + VCMSG_SET_EXECUTE_CODE = 0x00030010,
3706 + VCMSG_SET_EXECUTE_QPU = 0x00030011,
3707 + VCMSG_SET_ENABLE_QPU = 0x00030012,
3708 + VCMSG_GET_RESOURCE_HANDLE = 0x00030014,
3709 + VCMSG_GET_EDID_BLOCK = 0x00030020,
3710 + VCMSG_GET_CUSTOMER_OTP = 0x00030021,
3711 + VCMSG_SET_CUSTOMER_OTP = 0x00038021,
3712 + VCMSG_SET_ALLOCATE_BUFFER = 0x00040001,
3713 + VCMSG_SET_RELEASE_BUFFER = 0x00048001,
3714 + VCMSG_SET_BLANK_SCREEN = 0x00040002,
3715 + VCMSG_TST_BLANK_SCREEN = 0x00044002,
3716 + VCMSG_GET_PHYSICAL_WIDTH_HEIGHT = 0x00040003,
3717 + VCMSG_TST_PHYSICAL_WIDTH_HEIGHT = 0x00044003,
3718 + VCMSG_SET_PHYSICAL_WIDTH_HEIGHT = 0x00048003,
3719 + VCMSG_GET_VIRTUAL_WIDTH_HEIGHT = 0x00040004,
3720 + VCMSG_TST_VIRTUAL_WIDTH_HEIGHT = 0x00044004,
3721 + VCMSG_SET_VIRTUAL_WIDTH_HEIGHT = 0x00048004,
3722 + VCMSG_GET_DEPTH = 0x00040005,
3723 + VCMSG_TST_DEPTH = 0x00044005,
3724 + VCMSG_SET_DEPTH = 0x00048005,
3725 + VCMSG_GET_PIXEL_ORDER = 0x00040006,
3726 + VCMSG_TST_PIXEL_ORDER = 0x00044006,
3727 + VCMSG_SET_PIXEL_ORDER = 0x00048006,
3728 + VCMSG_GET_ALPHA_MODE = 0x00040007,
3729 + VCMSG_TST_ALPHA_MODE = 0x00044007,
3730 + VCMSG_SET_ALPHA_MODE = 0x00048007,
3731 + VCMSG_GET_PITCH = 0x00040008,
3732 + VCMSG_TST_PITCH = 0x00044008,
3733 + VCMSG_SET_PITCH = 0x00048008,
3734 + VCMSG_GET_VIRTUAL_OFFSET = 0x00040009,
3735 + VCMSG_TST_VIRTUAL_OFFSET = 0x00044009,
3736 + VCMSG_SET_VIRTUAL_OFFSET = 0x00048009,
3737 + VCMSG_GET_OVERSCAN = 0x0004000a,
3738 + VCMSG_TST_OVERSCAN = 0x0004400a,
3739 + VCMSG_SET_OVERSCAN = 0x0004800a,
3740 + VCMSG_GET_PALETTE = 0x0004000b,
3741 + VCMSG_TST_PALETTE = 0x0004400b,
3742 + VCMSG_SET_PALETTE = 0x0004800b,
3743 + VCMSG_GET_LAYER = 0x0004000c,
3744 + VCMSG_TST_LAYER = 0x0004400c,
3745 + VCMSG_SET_LAYER = 0x0004800c,
3746 + VCMSG_GET_TRANSFORM = 0x0004000d,
3747 + VCMSG_TST_TRANSFORM = 0x0004400d,
3748 + VCMSG_SET_TRANSFORM = 0x0004800d,
3749 + VCMSG_TST_VSYNC = 0x0004400e,
3750 + VCMSG_SET_VSYNC = 0x0004800e,
3751 + VCMSG_SET_CURSOR_INFO = 0x00008010,
3752 + VCMSG_SET_CURSOR_STATE = 0x00008011,
3753 +};
3754 +
3755 +extern int /*rc*/ bcm_mailbox_read(unsigned chan, uint32_t *data28);
3756 +extern int /*rc*/ bcm_mailbox_write(unsigned chan, uint32_t data28);
3757 +extern int /*rc*/ bcm_mailbox_property(void *data, int size);
3758 +
3759 +#include <linux/ioctl.h>
3760 +
3761 +/*
3762 + * The major device number. We can't rely on dynamic
3763 + * registration any more, because ioctls need to know
3764 + * it.
3765 + */
3766 +#define MAJOR_NUM 100
3767 +
3768 +/*
3769 + * Set the message of the device driver
3770 + */
3771 +#define IOCTL_MBOX_PROPERTY _IOWR(MAJOR_NUM, 0, char *)
3772 +/*
3773 + * _IOWR means that we're creating an ioctl command
3774 + * number for passing information from a user process
3775 + * to the kernel module and from the kernel module to user process
3776 + *
3777 + * The first arguments, MAJOR_NUM, is the major device
3778 + * number we're using.
3779 + *
3780 + * The second argument is the number of the command
3781 + * (there could be several with different meanings).
3782 + *
3783 + * The third argument is the type we want to get from
3784 + * the process to the kernel.
3785 + */
3786 +
3787 +/*
3788 + * The name of the device file
3789 + */
3790 +#define DEVICE_FILE_NAME "vcio"
3791 +
3792 +#endif
3793 --- /dev/null
3794 +++ b/arch/arm/mach-bcm2708/include/mach/vmalloc.h
3795 @@ -0,0 +1,20 @@
3796 +/*
3797 + * arch/arm/mach-bcm2708/include/mach/vmalloc.h
3798 + *
3799 + * Copyright (C) 2010 Broadcom
3800 + *
3801 + * This program is free software; you can redistribute it and/or modify
3802 + * it under the terms of the GNU General Public License as published by
3803 + * the Free Software Foundation; either version 2 of the License, or
3804 + * (at your option) any later version.
3805 + *
3806 + * This program is distributed in the hope that it will be useful,
3807 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
3808 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3809 + * GNU General Public License for more details.
3810 + *
3811 + * You should have received a copy of the GNU General Public License
3812 + * along with this program; if not, write to the Free Software
3813 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
3814 + */
3815 +#define VMALLOC_END (0xe8000000)
3816 --- /dev/null
3817 +++ b/arch/arm/mach-bcm2708/power.c
3818 @@ -0,0 +1,197 @@
3819 +/*
3820 + * linux/arch/arm/mach-bcm2708/power.c
3821 + *
3822 + * Copyright (C) 2010 Broadcom
3823 + *
3824 + * This program is free software; you can redistribute it and/or modify
3825 + * it under the terms of the GNU General Public License version 2 as
3826 + * published by the Free Software Foundation.
3827 + *
3828 + * This device provides a shared mechanism for controlling the power to
3829 + * VideoCore subsystems.
3830 + */
3831 +
3832 +#include <linux/module.h>
3833 +#include <linux/semaphore.h>
3834 +#include <linux/bug.h>
3835 +#include <mach/power.h>
3836 +#include <mach/vcio.h>
3837 +#include <mach/arm_power.h>
3838 +
3839 +#define DRIVER_NAME "bcm2708_power"
3840 +
3841 +#define BCM_POWER_MAXCLIENTS 4
3842 +#define BCM_POWER_NOCLIENT (1<<31)
3843 +
3844 +/* Some drivers expect there devices to be permanently powered */
3845 +
3846 +#ifdef CONFIG_USB
3847 +#define BCM_POWER_ALWAYS_ON (BCM_POWER_USB)
3848 +#endif
3849 +
3850 +#if 1
3851 +#define DPRINTK printk
3852 +#else
3853 +#define DPRINTK if (0) printk
3854 +#endif
3855 +
3856 +struct state_struct {
3857 + uint32_t global_request;
3858 + uint32_t client_request[BCM_POWER_MAXCLIENTS];
3859 + struct semaphore client_mutex;
3860 + struct semaphore mutex;
3861 +} g_state;
3862 +
3863 +int bcm_power_open(BCM_POWER_HANDLE_T *handle)
3864 +{
3865 + BCM_POWER_HANDLE_T i;
3866 + int ret = -EBUSY;
3867 +
3868 + down(&g_state.client_mutex);
3869 +
3870 + for (i = 0; i < BCM_POWER_MAXCLIENTS; i++) {
3871 + if (g_state.client_request[i] == BCM_POWER_NOCLIENT) {
3872 + g_state.client_request[i] = BCM_POWER_NONE;
3873 + *handle = i;
3874 + ret = 0;
3875 + break;
3876 + }
3877 + }
3878 +
3879 + up(&g_state.client_mutex);
3880 +
3881 + DPRINTK("bcm_power_open() -> %d\n", *handle);
3882 +
3883 + return ret;
3884 +}
3885 +EXPORT_SYMBOL_GPL(bcm_power_open);
3886 +
3887 +int bcm_power_request(BCM_POWER_HANDLE_T handle, uint32_t request)
3888 +{
3889 + int rc = 0;
3890 +
3891 + DPRINTK("bcm_power_request(%d, %x)\n", handle, request);
3892 +
3893 + if ((handle < BCM_POWER_MAXCLIENTS) &&
3894 + (g_state.client_request[handle] != BCM_POWER_NOCLIENT)) {
3895 + if (down_interruptible(&g_state.mutex) != 0) {
3896 + DPRINTK("bcm_power_request -> interrupted\n");
3897 + return -EINTR;
3898 + }
3899 +
3900 + if (request != g_state.client_request[handle]) {
3901 + uint32_t others_request = 0;
3902 + uint32_t global_request;
3903 + BCM_POWER_HANDLE_T i;
3904 +
3905 + for (i = 0; i < BCM_POWER_MAXCLIENTS; i++) {
3906 + if (i != handle)
3907 + others_request |=
3908 + g_state.client_request[i];
3909 + }
3910 + others_request &= ~BCM_POWER_NOCLIENT;
3911 +
3912 + global_request = request | others_request;
3913 + if (global_request != g_state.global_request) {
3914 + uint32_t actual;
3915 +
3916 + /* Send a request to VideoCore */
3917 + bcm_mailbox_write(MBOX_CHAN_POWER,
3918 + global_request << 4);
3919 +
3920 + /* Wait for a response during power-up */
3921 + if (global_request & ~g_state.global_request) {
3922 + rc = bcm_mailbox_read(MBOX_CHAN_POWER,
3923 + &actual);
3924 + DPRINTK
3925 + ("bcm_mailbox_read -> %08x, %d\n",
3926 + actual, rc);
3927 + actual >>= 4;
3928 + } else {
3929 + rc = 0;
3930 + actual = global_request;
3931 + }
3932 +
3933 + if (rc == 0) {
3934 + if (actual != global_request) {
3935 + printk(KERN_ERR
3936 + "%s: prev global %x, new global %x, actual %x, request %x, others_request %x\n",
3937 + __func__,
3938 + g_state.global_request,
3939 + global_request, actual, request, others_request);
3940 + /* A failure */
3941 + BUG_ON((others_request & actual)
3942 + != others_request);
3943 + request &= actual;
3944 + rc = -EIO;
3945 + }
3946 +
3947 + g_state.global_request = actual;
3948 + g_state.client_request[handle] =
3949 + request;
3950 + }
3951 + }
3952 + }
3953 + up(&g_state.mutex);
3954 + } else {
3955 + rc = -EINVAL;
3956 + }
3957 + DPRINTK("bcm_power_request -> %d\n", rc);
3958 + return rc;
3959 +}
3960 +EXPORT_SYMBOL_GPL(bcm_power_request);
3961 +
3962 +int bcm_power_close(BCM_POWER_HANDLE_T handle)
3963 +{
3964 + int rc;
3965 +
3966 + DPRINTK("bcm_power_close(%d)\n", handle);
3967 +
3968 + rc = bcm_power_request(handle, BCM_POWER_NONE);
3969 + if (rc == 0)
3970 + g_state.client_request[handle] = BCM_POWER_NOCLIENT;
3971 +
3972 + return rc;
3973 +}
3974 +EXPORT_SYMBOL_GPL(bcm_power_close);
3975 +
3976 +static int __init bcm_power_init(void)
3977 +{
3978 +#if defined(BCM_POWER_ALWAYS_ON)
3979 + BCM_POWER_HANDLE_T always_on_handle;
3980 +#endif
3981 + int rc = 0;
3982 + int i;
3983 +
3984 + printk(KERN_INFO "bcm_power: Broadcom power driver\n");
3985 + bcm_mailbox_write(MBOX_CHAN_POWER, 0);
3986 +
3987 + for (i = 0; i < BCM_POWER_MAXCLIENTS; i++)
3988 + g_state.client_request[i] = BCM_POWER_NOCLIENT;
3989 +
3990 + sema_init(&g_state.client_mutex, 1);
3991 + sema_init(&g_state.mutex, 1);
3992 +
3993 + g_state.global_request = 0;
3994 +
3995 +#if defined(BCM_POWER_ALWAYS_ON)
3996 + if (BCM_POWER_ALWAYS_ON) {
3997 + bcm_power_open(&always_on_handle);
3998 + bcm_power_request(always_on_handle, BCM_POWER_ALWAYS_ON);
3999 + }
4000 +#endif
4001 +
4002 + return rc;
4003 +}
4004 +
4005 +static void __exit bcm_power_exit(void)
4006 +{
4007 + bcm_mailbox_write(MBOX_CHAN_POWER, 0);
4008 +}
4009 +
4010 +arch_initcall(bcm_power_init); /* Initialize early */
4011 +module_exit(bcm_power_exit);
4012 +
4013 +MODULE_AUTHOR("Phil Elwell");
4014 +MODULE_DESCRIPTION("Interface to BCM2708 power management");
4015 +MODULE_LICENSE("GPL");
4016 --- /dev/null
4017 +++ b/arch/arm/mach-bcm2708/vc_mem.c
4018 @@ -0,0 +1,431 @@
4019 +/*****************************************************************************
4020 +* Copyright 2010 - 2011 Broadcom Corporation. All rights reserved.
4021 +*
4022 +* Unless you and Broadcom execute a separate written software license
4023 +* agreement governing use of this software, this software is licensed to you
4024 +* under the terms of the GNU General Public License version 2, available at
4025 +* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
4026 +*
4027 +* Notwithstanding the above, under no circumstances may you combine this
4028 +* software in any way with any other Broadcom software provided under a
4029 +* license other than the GPL, without Broadcom's express prior written
4030 +* consent.
4031 +*****************************************************************************/
4032 +
4033 +#include <linux/kernel.h>
4034 +#include <linux/module.h>
4035 +#include <linux/fs.h>
4036 +#include <linux/device.h>
4037 +#include <linux/cdev.h>
4038 +#include <linux/mm.h>
4039 +#include <linux/slab.h>
4040 +#include <linux/debugfs.h>
4041 +#include <asm/uaccess.h>
4042 +#include <linux/dma-mapping.h>
4043 +
4044 +#ifdef CONFIG_ARCH_KONA
4045 +#include <chal/chal_ipc.h>
4046 +#elif CONFIG_ARCH_BCM2708
4047 +#else
4048 +#include <csp/chal_ipc.h>
4049 +#endif
4050 +
4051 +#include "mach/vc_mem.h"
4052 +#include <mach/vcio.h>
4053 +
4054 +#define DRIVER_NAME "vc-mem"
4055 +
4056 +// Device (/dev) related variables
4057 +static dev_t vc_mem_devnum = 0;
4058 +static struct class *vc_mem_class = NULL;
4059 +static struct cdev vc_mem_cdev;
4060 +static int vc_mem_inited = 0;
4061 +
4062 +#ifdef CONFIG_DEBUG_FS
4063 +static struct dentry *vc_mem_debugfs_entry;
4064 +#endif
4065 +
4066 +/*
4067 + * Videocore memory addresses and size
4068 + *
4069 + * Drivers that wish to know the videocore memory addresses and sizes should
4070 + * use these variables instead of the MM_IO_BASE and MM_ADDR_IO defines in
4071 + * headers. This allows the other drivers to not be tied down to a a certain
4072 + * address/size at compile time.
4073 + *
4074 + * In the future, the goal is to have the videocore memory virtual address and
4075 + * size be calculated at boot time rather than at compile time. The decision of
4076 + * where the videocore memory resides and its size would be in the hands of the
4077 + * bootloader (and/or kernel). When that happens, the values of these variables
4078 + * would be calculated and assigned in the init function.
4079 + */
4080 +// in the 2835 VC in mapped above ARM, but ARM has full access to VC space
4081 +unsigned long mm_vc_mem_phys_addr = 0x00000000;
4082 +unsigned int mm_vc_mem_size = 0;
4083 +unsigned int mm_vc_mem_base = 0;
4084 +
4085 +EXPORT_SYMBOL(mm_vc_mem_phys_addr);
4086 +EXPORT_SYMBOL(mm_vc_mem_size);
4087 +EXPORT_SYMBOL(mm_vc_mem_base);
4088 +
4089 +static uint phys_addr = 0;
4090 +static uint mem_size = 0;
4091 +static uint mem_base = 0;
4092 +
4093 +
4094 +/****************************************************************************
4095 +*
4096 +* vc_mem_open
4097 +*
4098 +***************************************************************************/
4099 +
4100 +static int
4101 +vc_mem_open(struct inode *inode, struct file *file)
4102 +{
4103 + (void) inode;
4104 + (void) file;
4105 +
4106 + pr_debug("%s: called file = 0x%p\n", __func__, file);
4107 +
4108 + return 0;
4109 +}
4110 +
4111 +/****************************************************************************
4112 +*
4113 +* vc_mem_release
4114 +*
4115 +***************************************************************************/
4116 +
4117 +static int
4118 +vc_mem_release(struct inode *inode, struct file *file)
4119 +{
4120 + (void) inode;
4121 + (void) file;
4122 +
4123 + pr_debug("%s: called file = 0x%p\n", __func__, file);
4124 +
4125 + return 0;
4126 +}
4127 +
4128 +/****************************************************************************
4129 +*
4130 +* vc_mem_get_size
4131 +*
4132 +***************************************************************************/
4133 +
4134 +static void
4135 +vc_mem_get_size(void)
4136 +{
4137 +}
4138 +
4139 +/****************************************************************************
4140 +*
4141 +* vc_mem_get_base
4142 +*
4143 +***************************************************************************/
4144 +
4145 +static void
4146 +vc_mem_get_base(void)
4147 +{
4148 +}
4149 +
4150 +/****************************************************************************
4151 +*
4152 +* vc_mem_get_current_size
4153 +*
4154 +***************************************************************************/
4155 +
4156 +int
4157 +vc_mem_get_current_size(void)
4158 +{
4159 + return mm_vc_mem_size;
4160 +}
4161 +
4162 +EXPORT_SYMBOL_GPL(vc_mem_get_current_size);
4163 +
4164 +/****************************************************************************
4165 +*
4166 +* vc_mem_ioctl
4167 +*
4168 +***************************************************************************/
4169 +
4170 +static long
4171 +vc_mem_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
4172 +{
4173 + int rc = 0;
4174 +
4175 + (void) cmd;
4176 + (void) arg;
4177 +
4178 + pr_debug("%s: called file = 0x%p\n", __func__, file);
4179 +
4180 + switch (cmd) {
4181 + case VC_MEM_IOC_MEM_PHYS_ADDR:
4182 + {
4183 + pr_debug("%s: VC_MEM_IOC_MEM_PHYS_ADDR=0x%p\n",
4184 + __func__, (void *) mm_vc_mem_phys_addr);
4185 +
4186 + if (copy_to_user((void *) arg, &mm_vc_mem_phys_addr,
4187 + sizeof (mm_vc_mem_phys_addr)) != 0) {
4188 + rc = -EFAULT;
4189 + }
4190 + break;
4191 + }
4192 + case VC_MEM_IOC_MEM_SIZE:
4193 + {
4194 + // Get the videocore memory size first
4195 + vc_mem_get_size();
4196 +
4197 + pr_debug("%s: VC_MEM_IOC_MEM_SIZE=%u\n", __func__,
4198 + mm_vc_mem_size);
4199 +
4200 + if (copy_to_user((void *) arg, &mm_vc_mem_size,
4201 + sizeof (mm_vc_mem_size)) != 0) {
4202 + rc = -EFAULT;
4203 + }
4204 + break;
4205 + }
4206 + case VC_MEM_IOC_MEM_BASE:
4207 + {
4208 + // Get the videocore memory base
4209 + vc_mem_get_base();
4210 +
4211 + pr_debug("%s: VC_MEM_IOC_MEM_BASE=%u\n", __func__,
4212 + mm_vc_mem_base);
4213 +
4214 + if (copy_to_user((void *) arg, &mm_vc_mem_base,
4215 + sizeof (mm_vc_mem_base)) != 0) {
4216 + rc = -EFAULT;
4217 + }
4218 + break;
4219 + }
4220 + case VC_MEM_IOC_MEM_LOAD:
4221 + {
4222 + // Get the videocore memory base
4223 + vc_mem_get_base();
4224 +
4225 + pr_debug("%s: VC_MEM_IOC_MEM_LOAD=%u\n", __func__,
4226 + mm_vc_mem_base);
4227 +
4228 + if (copy_to_user((void *) arg, &mm_vc_mem_base,
4229 + sizeof (mm_vc_mem_base)) != 0) {
4230 + rc = -EFAULT;
4231 + }
4232 + break;
4233 + }
4234 + default:
4235 + {
4236 + return -ENOTTY;
4237 + }
4238 + }
4239 + pr_debug("%s: file = 0x%p returning %d\n", __func__, file, rc);
4240 +
4241 + return rc;
4242 +}
4243 +
4244 +/****************************************************************************
4245 +*
4246 +* vc_mem_mmap
4247 +*
4248 +***************************************************************************/
4249 +
4250 +static int
4251 +vc_mem_mmap(struct file *filp, struct vm_area_struct *vma)
4252 +{
4253 + int rc = 0;
4254 + unsigned long length = vma->vm_end - vma->vm_start;
4255 + unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
4256 +
4257 + pr_debug("%s: vm_start = 0x%08lx vm_end = 0x%08lx vm_pgoff = 0x%08lx\n",
4258 + __func__, (long) vma->vm_start, (long) vma->vm_end,
4259 + (long) vma->vm_pgoff);
4260 +
4261 + if (offset + length > mm_vc_mem_size) {
4262 + pr_err("%s: length %ld is too big\n", __func__, length);
4263 + return -EINVAL;
4264 + }
4265 + // Do not cache the memory map
4266 + vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
4267 +
4268 + rc = remap_pfn_range(vma, vma->vm_start,
4269 + (mm_vc_mem_phys_addr >> PAGE_SHIFT) +
4270 + vma->vm_pgoff, length, vma->vm_page_prot);
4271 + if (rc != 0) {
4272 + pr_err("%s: remap_pfn_range failed (rc=%d)\n", __func__, rc);
4273 + }
4274 +
4275 + return rc;
4276 +}
4277 +
4278 +/****************************************************************************
4279 +*
4280 +* File Operations for the driver.
4281 +*
4282 +***************************************************************************/
4283 +
4284 +static const struct file_operations vc_mem_fops = {
4285 + .owner = THIS_MODULE,
4286 + .open = vc_mem_open,
4287 + .release = vc_mem_release,
4288 + .unlocked_ioctl = vc_mem_ioctl,
4289 + .mmap = vc_mem_mmap,
4290 +};
4291 +
4292 +#ifdef CONFIG_DEBUG_FS
4293 +static void vc_mem_debugfs_deinit(void)
4294 +{
4295 + debugfs_remove_recursive(vc_mem_debugfs_entry);
4296 + vc_mem_debugfs_entry = NULL;
4297 +}
4298 +
4299 +
4300 +static int vc_mem_debugfs_init(
4301 + struct device *dev)
4302 +{
4303 + vc_mem_debugfs_entry = debugfs_create_dir(DRIVER_NAME, NULL);
4304 + if (!vc_mem_debugfs_entry) {
4305 + dev_warn(dev, "could not create debugfs entry\n");
4306 + return -EFAULT;
4307 + }
4308 +
4309 + if (!debugfs_create_x32("vc_mem_phys_addr",
4310 + 0444,
4311 + vc_mem_debugfs_entry,
4312 + (u32 *)&mm_vc_mem_phys_addr)) {
4313 + dev_warn(dev, "%s:could not create vc_mem_phys entry\n",
4314 + __func__);
4315 + goto fail;
4316 + }
4317 +
4318 + if (!debugfs_create_x32("vc_mem_size",
4319 + 0444,
4320 + vc_mem_debugfs_entry,
4321 + (u32 *)&mm_vc_mem_size)) {
4322 + dev_warn(dev, "%s:could not create vc_mem_size entry\n",
4323 + __func__);
4324 + goto fail;
4325 + }
4326 +
4327 + if (!debugfs_create_x32("vc_mem_base",
4328 + 0444,
4329 + vc_mem_debugfs_entry,
4330 + (u32 *)&mm_vc_mem_base)) {
4331 + dev_warn(dev, "%s:could not create vc_mem_base entry\n",
4332 + __func__);
4333 + goto fail;
4334 + }
4335 +
4336 + return 0;
4337 +
4338 +fail:
4339 + vc_mem_debugfs_deinit();
4340 + return -EFAULT;
4341 +}
4342 +
4343 +#endif /* CONFIG_DEBUG_FS */
4344 +
4345 +
4346 +/****************************************************************************
4347 +*
4348 +* vc_mem_init
4349 +*
4350 +***************************************************************************/
4351 +
4352 +static int __init
4353 +vc_mem_init(void)
4354 +{
4355 + int rc = -EFAULT;
4356 + struct device *dev;
4357 +
4358 + pr_debug("%s: called\n", __func__);
4359 +
4360 + mm_vc_mem_phys_addr = phys_addr;
4361 + mm_vc_mem_size = mem_size;
4362 + mm_vc_mem_base = mem_base;
4363 +
4364 + vc_mem_get_size();
4365 +
4366 + pr_info("vc-mem: phys_addr:0x%08lx mem_base=0x%08x mem_size:0x%08x(%u MiB)\n",
4367 + mm_vc_mem_phys_addr, mm_vc_mem_base, mm_vc_mem_size, mm_vc_mem_size / (1024 * 1024));
4368 +
4369 + if ((rc = alloc_chrdev_region(&vc_mem_devnum, 0, 1, DRIVER_NAME)) < 0) {
4370 + pr_err("%s: alloc_chrdev_region failed (rc=%d)\n",
4371 + __func__, rc);
4372 + goto out_err;
4373 + }
4374 +
4375 + cdev_init(&vc_mem_cdev, &vc_mem_fops);
4376 + if ((rc = cdev_add(&vc_mem_cdev, vc_mem_devnum, 1)) != 0) {
4377 + pr_err("%s: cdev_add failed (rc=%d)\n", __func__, rc);
4378 + goto out_unregister;
4379 + }
4380 +
4381 + vc_mem_class = class_create(THIS_MODULE, DRIVER_NAME);
4382 + if (IS_ERR(vc_mem_class)) {
4383 + rc = PTR_ERR(vc_mem_class);
4384 + pr_err("%s: class_create failed (rc=%d)\n", __func__, rc);
4385 + goto out_cdev_del;
4386 + }
4387 +
4388 + dev = device_create(vc_mem_class, NULL, vc_mem_devnum, NULL,
4389 + DRIVER_NAME);
4390 + if (IS_ERR(dev)) {
4391 + rc = PTR_ERR(dev);
4392 + pr_err("%s: device_create failed (rc=%d)\n", __func__, rc);
4393 + goto out_class_destroy;
4394 + }
4395 +
4396 +#ifdef CONFIG_DEBUG_FS
4397 + /* don't fail if the debug entries cannot be created */
4398 + vc_mem_debugfs_init(dev);
4399 +#endif
4400 +
4401 + vc_mem_inited = 1;
4402 + return 0;
4403 +
4404 + device_destroy(vc_mem_class, vc_mem_devnum);
4405 +
4406 + out_class_destroy:
4407 + class_destroy(vc_mem_class);
4408 + vc_mem_class = NULL;
4409 +
4410 + out_cdev_del:
4411 + cdev_del(&vc_mem_cdev);
4412 +
4413 + out_unregister:
4414 + unregister_chrdev_region(vc_mem_devnum, 1);
4415 +
4416 + out_err:
4417 + return -1;
4418 +}
4419 +
4420 +/****************************************************************************
4421 +*
4422 +* vc_mem_exit
4423 +*
4424 +***************************************************************************/
4425 +
4426 +static void __exit
4427 +vc_mem_exit(void)
4428 +{
4429 + pr_debug("%s: called\n", __func__);
4430 +
4431 + if (vc_mem_inited) {
4432 +#if CONFIG_DEBUG_FS
4433 + vc_mem_debugfs_deinit();
4434 +#endif
4435 + device_destroy(vc_mem_class, vc_mem_devnum);
4436 + class_destroy(vc_mem_class);
4437 + cdev_del(&vc_mem_cdev);
4438 + unregister_chrdev_region(vc_mem_devnum, 1);
4439 + }
4440 +}
4441 +
4442 +module_init(vc_mem_init);
4443 +module_exit(vc_mem_exit);
4444 +MODULE_LICENSE("GPL");
4445 +MODULE_AUTHOR("Broadcom Corporation");
4446 +
4447 +module_param(phys_addr, uint, 0644);
4448 +module_param(mem_size, uint, 0644);
4449 +module_param(mem_base, uint, 0644);
4450 --- /dev/null
4451 +++ b/arch/arm/mach-bcm2708/vcio.c
4452 @@ -0,0 +1,474 @@
4453 +/*
4454 + * linux/arch/arm/mach-bcm2708/vcio.c
4455 + *
4456 + * Copyright (C) 2010 Broadcom
4457 + *
4458 + * This program is free software; you can redistribute it and/or modify
4459 + * it under the terms of the GNU General Public License version 2 as
4460 + * published by the Free Software Foundation.
4461 + *
4462 + * This device provides a shared mechanism for writing to the mailboxes,
4463 + * semaphores, doorbells etc. that are shared between the ARM and the
4464 + * VideoCore processor
4465 + */
4466 +
4467 +#if defined(CONFIG_SERIAL_BCM_MBOX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
4468 +#define SUPPORT_SYSRQ
4469 +#endif
4470 +
4471 +#include <linux/module.h>
4472 +#include <linux/console.h>
4473 +#include <linux/serial_core.h>
4474 +#include <linux/serial.h>
4475 +#include <linux/errno.h>
4476 +#include <linux/device.h>
4477 +#include <linux/init.h>
4478 +#include <linux/mm.h>
4479 +#include <linux/dma-mapping.h>
4480 +#include <linux/platform_device.h>
4481 +#include <linux/sysrq.h>
4482 +#include <linux/delay.h>
4483 +#include <linux/slab.h>
4484 +#include <linux/interrupt.h>
4485 +#include <linux/irq.h>
4486 +
4487 +#include <linux/io.h>
4488 +
4489 +#include <mach/vcio.h>
4490 +#include <mach/platform.h>
4491 +
4492 +#include <asm/uaccess.h>
4493 +
4494 +
4495 +#define DRIVER_NAME BCM_VCIO_DRIVER_NAME
4496 +
4497 +/* ----------------------------------------------------------------------
4498 + * Mailbox
4499 + * -------------------------------------------------------------------- */
4500 +
4501 +/* offsets from a mail box base address */
4502 +#define MAIL_WRT 0x00 /* write - and next 4 words */
4503 +#define MAIL_RD 0x00 /* read - and next 4 words */
4504 +#define MAIL_POL 0x10 /* read without popping the fifo */
4505 +#define MAIL_SND 0x14 /* sender ID (bottom two bits) */
4506 +#define MAIL_STA 0x18 /* status */
4507 +#define MAIL_CNF 0x1C /* configuration */
4508 +
4509 +#define MBOX_MSG(chan, data28) (((data28) & ~0xf) | ((chan) & 0xf))
4510 +#define MBOX_MSG_LSB(chan, data28) (((data28) << 4) | ((chan) & 0xf))
4511 +#define MBOX_CHAN(msg) ((msg) & 0xf)
4512 +#define MBOX_DATA28(msg) ((msg) & ~0xf)
4513 +#define MBOX_DATA28_LSB(msg) (((uint32_t)msg) >> 4)
4514 +
4515 +#define MBOX_MAGIC 0xd0d0c0de
4516 +
4517 +struct vc_mailbox {
4518 + struct device *dev; /* parent device */
4519 + void __iomem *status;
4520 + void __iomem *config;
4521 + void __iomem *read;
4522 + void __iomem *write;
4523 + uint32_t msg[MBOX_CHAN_COUNT];
4524 + struct semaphore sema[MBOX_CHAN_COUNT];
4525 + uint32_t magic;
4526 +};
4527 +
4528 +static void mbox_init(struct vc_mailbox *mbox_out, struct device *dev,
4529 + uint32_t addr_mbox)
4530 +{
4531 + int i;
4532 +
4533 + mbox_out->dev = dev;
4534 + mbox_out->status = __io_address(addr_mbox + MAIL_STA);
4535 + mbox_out->config = __io_address(addr_mbox + MAIL_CNF);
4536 + mbox_out->read = __io_address(addr_mbox + MAIL_RD);
4537 + /* Write to the other mailbox */
4538 + mbox_out->write =
4539 + __io_address((addr_mbox ^ ARM_0_MAIL0_WRT ^ ARM_0_MAIL1_WRT) +
4540 + MAIL_WRT);
4541 +
4542 + for (i = 0; i < MBOX_CHAN_COUNT; i++) {
4543 + mbox_out->msg[i] = 0;
4544 + sema_init(&mbox_out->sema[i], 0);
4545 + }
4546 +
4547 + /* Enable the interrupt on data reception */
4548 + writel(ARM_MC_IHAVEDATAIRQEN, mbox_out->config);
4549 +
4550 + mbox_out->magic = MBOX_MAGIC;
4551 +}
4552 +
4553 +static int mbox_write(struct vc_mailbox *mbox, unsigned chan, uint32_t data28)
4554 +{
4555 + int rc;
4556 +
4557 + if (mbox->magic != MBOX_MAGIC)
4558 + rc = -EINVAL;
4559 + else {
4560 + /* wait for the mailbox FIFO to have some space in it */
4561 + while (0 != (readl(mbox->status) & ARM_MS_FULL))
4562 + cpu_relax();
4563 +
4564 + writel(MBOX_MSG(chan, data28), mbox->write);
4565 + rc = 0;
4566 + }
4567 + return rc;
4568 +}
4569 +
4570 +static int mbox_read(struct vc_mailbox *mbox, unsigned chan, uint32_t *data28)
4571 +{
4572 + int rc;
4573 +
4574 + if (mbox->magic != MBOX_MAGIC)
4575 + rc = -EINVAL;
4576 + else {
4577 + down(&mbox->sema[chan]);
4578 + *data28 = MBOX_DATA28(mbox->msg[chan]);
4579 + mbox->msg[chan] = 0;
4580 + rc = 0;
4581 + }
4582 + return rc;
4583 +}
4584 +
4585 +static irqreturn_t mbox_irq(int irq, void *dev_id)
4586 +{
4587 + /* wait for the mailbox FIFO to have some data in it */
4588 + struct vc_mailbox *mbox = (struct vc_mailbox *) dev_id;
4589 + int status = readl(mbox->status);
4590 + int ret = IRQ_NONE;
4591 +
4592 + while (!(status & ARM_MS_EMPTY)) {
4593 + uint32_t msg = readl(mbox->read);
4594 + int chan = MBOX_CHAN(msg);
4595 + if (chan < MBOX_CHAN_COUNT) {
4596 + if (mbox->msg[chan]) {
4597 + /* Overflow */
4598 + printk(KERN_ERR DRIVER_NAME
4599 + ": mbox chan %d overflow - drop %08x\n",
4600 + chan, msg);
4601 + } else {
4602 + mbox->msg[chan] = (msg | 0xf);
4603 + up(&mbox->sema[chan]);
4604 + }
4605 + } else {
4606 + printk(KERN_ERR DRIVER_NAME
4607 + ": invalid channel selector (msg %08x)\n", msg);
4608 + }
4609 + ret = IRQ_HANDLED;
4610 + status = readl(mbox->status);
4611 + }
4612 + return ret;
4613 +}
4614 +
4615 +static struct irqaction mbox_irqaction = {
4616 + .name = "ARM Mailbox IRQ",
4617 + .flags = IRQF_DISABLED | IRQF_IRQPOLL,
4618 + .handler = mbox_irq,
4619 +};
4620 +
4621 +/* ----------------------------------------------------------------------
4622 + * Mailbox Methods
4623 + * -------------------------------------------------------------------- */
4624 +
4625 +static struct device *mbox_dev; /* we assume there's only one! */
4626 +
4627 +static int dev_mbox_write(struct device *dev, unsigned chan, uint32_t data28)
4628 +{
4629 + int rc;
4630 +
4631 + struct vc_mailbox *mailbox = dev_get_drvdata(dev);
4632 + device_lock(dev);
4633 + rc = mbox_write(mailbox, chan, data28);
4634 + device_unlock(dev);
4635 +
4636 + return rc;
4637 +}
4638 +
4639 +static int dev_mbox_read(struct device *dev, unsigned chan, uint32_t *data28)
4640 +{
4641 + int rc;
4642 +
4643 + struct vc_mailbox *mailbox = dev_get_drvdata(dev);
4644 + device_lock(dev);
4645 + rc = mbox_read(mailbox, chan, data28);
4646 + device_unlock(dev);
4647 +
4648 + return rc;
4649 +}
4650 +
4651 +extern int bcm_mailbox_write(unsigned chan, uint32_t data28)
4652 +{
4653 + if (mbox_dev)
4654 + return dev_mbox_write(mbox_dev, chan, data28);
4655 + else
4656 + return -ENODEV;
4657 +}
4658 +EXPORT_SYMBOL_GPL(bcm_mailbox_write);
4659 +
4660 +extern int bcm_mailbox_read(unsigned chan, uint32_t *data28)
4661 +{
4662 + if (mbox_dev)
4663 + return dev_mbox_read(mbox_dev, chan, data28);
4664 + else
4665 + return -ENODEV;
4666 +}
4667 +EXPORT_SYMBOL_GPL(bcm_mailbox_read);
4668 +
4669 +static void dev_mbox_register(const char *dev_name, struct device *dev)
4670 +{
4671 + mbox_dev = dev;
4672 +}
4673 +
4674 +static int mbox_copy_from_user(void *dst, const void *src, int size)
4675 +{
4676 + if ( (uint32_t)src < TASK_SIZE)
4677 + {
4678 + return copy_from_user(dst, src, size);
4679 + }
4680 + else
4681 + {
4682 + memcpy( dst, src, size );
4683 + return 0;
4684 + }
4685 +}
4686 +
4687 +static int mbox_copy_to_user(void *dst, const void *src, int size)
4688 +{
4689 + if ( (uint32_t)dst < TASK_SIZE)
4690 + {
4691 + return copy_to_user(dst, src, size);
4692 + }
4693 + else
4694 + {
4695 + memcpy( dst, src, size );
4696 + return 0;
4697 + }
4698 +}
4699 +
4700 +static DEFINE_MUTEX(mailbox_lock);
4701 +extern int bcm_mailbox_property(void *data, int size)
4702 +{
4703 + uint32_t success;
4704 + dma_addr_t mem_bus; /* the memory address accessed from videocore */
4705 + void *mem_kern; /* the memory address accessed from driver */
4706 + int s = 0;
4707 +
4708 + mutex_lock(&mailbox_lock);
4709 + /* allocate some memory for the messages communicating with GPU */
4710 + mem_kern = dma_alloc_coherent(NULL, PAGE_ALIGN(size), &mem_bus, GFP_ATOMIC);
4711 + if (mem_kern) {
4712 + /* create the message */
4713 + mbox_copy_from_user(mem_kern, data, size);
4714 +
4715 + /* send the message */
4716 + wmb();
4717 + s = bcm_mailbox_write(MBOX_CHAN_PROPERTY, (uint32_t)mem_bus);
4718 + if (s == 0) {
4719 + s = bcm_mailbox_read(MBOX_CHAN_PROPERTY, &success);
4720 + }
4721 + if (s == 0) {
4722 + /* copy the response */
4723 + rmb();
4724 + mbox_copy_to_user(data, mem_kern, size);
4725 + }
4726 + dma_free_coherent(NULL, PAGE_ALIGN(size), mem_kern, mem_bus);
4727 + } else {
4728 + s = -ENOMEM;
4729 + }
4730 + if (s != 0)
4731 + printk(KERN_ERR DRIVER_NAME ": %s failed (%d)\n", __func__, s);
4732 +
4733 + mutex_unlock(&mailbox_lock);
4734 + return s;
4735 +}
4736 +EXPORT_SYMBOL_GPL(bcm_mailbox_property);
4737 +
4738 +/* ----------------------------------------------------------------------
4739 + * Platform Device for Mailbox
4740 + * -------------------------------------------------------------------- */
4741 +
4742 +/*
4743 + * Is the device open right now? Used to prevent
4744 + * concurent access into the same device
4745 + */
4746 +static int Device_Open = 0;
4747 +
4748 +/*
4749 + * This is called whenever a process attempts to open the device file
4750 + */
4751 +static int device_open(struct inode *inode, struct file *file)
4752 +{
4753 + /*
4754 + * We don't want to talk to two processes at the same time
4755 + */
4756 + if (Device_Open)
4757 + return -EBUSY;
4758 +
4759 + Device_Open++;
4760 + /*
4761 + * Initialize the message
4762 + */
4763 + try_module_get(THIS_MODULE);
4764 + return 0;
4765 +}
4766 +
4767 +static int device_release(struct inode *inode, struct file *file)
4768 +{
4769 + /*
4770 + * We're now ready for our next caller
4771 + */
4772 + Device_Open--;
4773 +
4774 + module_put(THIS_MODULE);
4775 + return 0;
4776 +}
4777 +
4778 +/*
4779 + * This function is called whenever a process tries to do an ioctl on our
4780 + * device file. We get two extra parameters (additional to the inode and file
4781 + * structures, which all device functions get): the number of the ioctl called
4782 + * and the parameter given to the ioctl function.
4783 + *
4784 + * If the ioctl is write or read/write (meaning output is returned to the
4785 + * calling process), the ioctl call returns the output of this function.
4786 + *
4787 + */
4788 +static long device_ioctl(struct file *file, /* see include/linux/fs.h */
4789 + unsigned int ioctl_num, /* number and param for ioctl */
4790 + unsigned long ioctl_param)
4791 +{
4792 + unsigned size;
4793 + /*
4794 + * Switch according to the ioctl called
4795 + */
4796 + switch (ioctl_num) {
4797 + case IOCTL_MBOX_PROPERTY:
4798 + /*
4799 + * Receive a pointer to a message (in user space) and set that
4800 + * to be the device's message. Get the parameter given to
4801 + * ioctl by the process.
4802 + */
4803 + mbox_copy_from_user(&size, (void *)ioctl_param, sizeof size);
4804 + return bcm_mailbox_property((void *)ioctl_param, size);
4805 + break;
4806 + default:
4807 + printk(KERN_ERR DRIVER_NAME "unknown ioctl: %d\n", ioctl_num);
4808 + return -EINVAL;
4809 + }
4810 +
4811 + return 0;
4812 +}
4813 +
4814 +/* Module Declarations */
4815 +
4816 +/*
4817 + * This structure will hold the functions to be called
4818 + * when a process does something to the device we
4819 + * created. Since a pointer to this structure is kept in
4820 + * the devices table, it can't be local to
4821 + * init_module. NULL is for unimplemented functios.
4822 + */
4823 +struct file_operations fops = {
4824 + .unlocked_ioctl = device_ioctl,
4825 + .open = device_open,
4826 + .release = device_release, /* a.k.a. close */
4827 +};
4828 +
4829 +static int bcm_vcio_probe(struct platform_device *pdev)
4830 +{
4831 + int ret = 0;
4832 + struct vc_mailbox *mailbox;
4833 +
4834 + mailbox = kzalloc(sizeof(*mailbox), GFP_KERNEL);
4835 + if (NULL == mailbox) {
4836 + printk(KERN_ERR DRIVER_NAME ": failed to allocate "
4837 + "mailbox memory\n");
4838 + ret = -ENOMEM;
4839 + } else {
4840 + struct resource *res;
4841 +
4842 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4843 + if (res == NULL) {
4844 + printk(KERN_ERR DRIVER_NAME ": failed to obtain memory "
4845 + "resource\n");
4846 + ret = -ENODEV;
4847 + kfree(mailbox);
4848 + } else {
4849 + /* should be based on the registers from res really */
4850 + mbox_init(mailbox, &pdev->dev, ARM_0_MAIL0_RD);
4851 +
4852 + platform_set_drvdata(pdev, mailbox);
4853 + dev_mbox_register(DRIVER_NAME, &pdev->dev);
4854 +
4855 + mbox_irqaction.dev_id = mailbox;
4856 + setup_irq(IRQ_ARM_MAILBOX, &mbox_irqaction);
4857 + printk(KERN_INFO DRIVER_NAME ": mailbox at %p\n",
4858 + __io_address(ARM_0_MAIL0_RD));
4859 + }
4860 + }
4861 +
4862 + if (ret == 0) {
4863 + /*
4864 + * Register the character device
4865 + */
4866 + ret = register_chrdev(MAJOR_NUM, DEVICE_FILE_NAME, &fops);
4867 +
4868 + /*
4869 + * Negative values signify an error
4870 + */
4871 + if (ret < 0) {
4872 + printk(KERN_ERR DRIVER_NAME
4873 + "Failed registering the character device %d\n", ret);
4874 + return ret;
4875 + }
4876 + }
4877 + return ret;
4878 +}
4879 +
4880 +static int bcm_vcio_remove(struct platform_device *pdev)
4881 +{
4882 + struct vc_mailbox *mailbox = platform_get_drvdata(pdev);
4883 +
4884 + platform_set_drvdata(pdev, NULL);
4885 + kfree(mailbox);
4886 +
4887 + return 0;
4888 +}
4889 +
4890 +static struct platform_driver bcm_mbox_driver = {
4891 + .probe = bcm_vcio_probe,
4892 + .remove = bcm_vcio_remove,
4893 +
4894 + .driver = {
4895 + .name = DRIVER_NAME,
4896 + .owner = THIS_MODULE,
4897 + },
4898 +};
4899 +
4900 +static int __init bcm_mbox_init(void)
4901 +{
4902 + int ret;
4903 +
4904 + printk(KERN_INFO "mailbox: Broadcom VideoCore Mailbox driver\n");
4905 +
4906 + ret = platform_driver_register(&bcm_mbox_driver);
4907 + if (ret != 0) {
4908 + printk(KERN_ERR DRIVER_NAME ": failed to register "
4909 + "on platform\n");
4910 + }
4911 +
4912 + return ret;
4913 +}
4914 +
4915 +static void __exit bcm_mbox_exit(void)
4916 +{
4917 + platform_driver_unregister(&bcm_mbox_driver);
4918 +}
4919 +
4920 +arch_initcall(bcm_mbox_init); /* Initialize early */
4921 +module_exit(bcm_mbox_exit);
4922 +
4923 +MODULE_AUTHOR("Gray Girling");
4924 +MODULE_DESCRIPTION("ARM I/O to VideoCore processor");
4925 +MODULE_LICENSE("GPL");
4926 +MODULE_ALIAS("platform:bcm-mbox");
4927 --- a/arch/arm/mm/Kconfig
4928 +++ b/arch/arm/mm/Kconfig
4929 @@ -358,7 +358,7 @@ config CPU_PJ4B
4930
4931 # ARMv6
4932 config CPU_V6
4933 - bool "Support ARM V6 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX
4934 + bool "Support ARM V6 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX || MACH_BCM2708
4935 select CPU_32v6
4936 select CPU_ABRT_EV6
4937 select CPU_CACHE_V6
4938 --- a/arch/arm/mm/proc-v6.S
4939 +++ b/arch/arm/mm/proc-v6.S
4940 @@ -73,10 +73,19 @@ ENDPROC(cpu_v6_reset)
4941 *
4942 * IRQs are already disabled.
4943 */
4944 +
4945 +/* See jira SW-5991 for details of this workaround */
4946 ENTRY(cpu_v6_do_idle)
4947 - mov r1, #0
4948 - mcr p15, 0, r1, c7, c10, 4 @ DWB - WFI may enter a low-power mode
4949 - mcr p15, 0, r1, c7, c0, 4 @ wait for interrupt
4950 + .align 5
4951 + mov r1, #2
4952 +1: subs r1, #1
4953 + nop
4954 + mcreq p15, 0, r1, c7, c10, 4 @ DWB - WFI may enter a low-power mode
4955 + mcreq p15, 0, r1, c7, c0, 4 @ wait for interrupt
4956 + nop
4957 + nop
4958 + nop
4959 + bne 1b
4960 ret lr
4961
4962 ENTRY(cpu_v6_dcache_clean_area)
4963 --- a/arch/arm/tools/mach-types
4964 +++ b/arch/arm/tools/mach-types
4965 @@ -522,6 +522,7 @@ torbreck MACH_TORBRECK TORBRECK 3090
4966 prima2_evb MACH_PRIMA2_EVB PRIMA2_EVB 3103
4967 paz00 MACH_PAZ00 PAZ00 3128
4968 acmenetusfoxg20 MACH_ACMENETUSFOXG20 ACMENETUSFOXG20 3129
4969 +bcm2708 MACH_BCM2708 BCM2708 3138
4970 ag5evm MACH_AG5EVM AG5EVM 3189
4971 ics_if_voip MACH_ICS_IF_VOIP ICS_IF_VOIP 3206
4972 wlf_cragg_6410 MACH_WLF_CRAGG_6410 WLF_CRAGG_6410 3207
4973 --- a/drivers/tty/serial/amba-pl011.c
4974 +++ b/drivers/tty/serial/amba-pl011.c
4975 @@ -84,7 +84,7 @@ struct vendor_data {
4976
4977 static unsigned int get_fifosize_arm(struct amba_device *dev)
4978 {
4979 - return amba_rev(dev) < 3 ? 16 : 32;
4980 + return 16; //TODO: fix: amba_rev(dev) < 3 ? 16 : 32;
4981 }
4982
4983 static struct vendor_data vendor_arm = {
4984 --- a/include/linux/mmc/host.h
4985 +++ b/include/linux/mmc/host.h
4986 @@ -290,6 +290,7 @@ struct mmc_host {
4987 #define MMC_CAP2_HS400 (MMC_CAP2_HS400_1_8V | \
4988 MMC_CAP2_HS400_1_2V)
4989 #define MMC_CAP2_SDIO_IRQ_NOTHREAD (1 << 17)
4990 +#define MMC_CAP2_FORCE_MULTIBLOCK (1 << 31) /* Always use multiblock transfers */
4991
4992 mmc_pm_flag_t pm_caps; /* supported pm features */
4993
4994 --- a/include/linux/mmc/sdhci.h
4995 +++ b/include/linux/mmc/sdhci.h
4996 @@ -130,6 +130,7 @@ struct sdhci_host {
4997 #define SDHCI_SDIO_IRQ_ENABLED (1<<9) /* SDIO irq enabled */
4998 #define SDHCI_SDR104_NEEDS_TUNING (1<<10) /* SDR104/HS200 needs tuning */
4999 #define SDHCI_USING_RETUNING_TIMER (1<<11) /* Host is using a retuning timer for the card */
5000 +#define SDHCI_USE_PLATDMA (1<<12) /* Host uses 3rd party DMA */
5001
5002 unsigned int version; /* SDHCI spec. version */
5003
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