brcm2708: update to v3.18
[openwrt/svn-archive/archive.git] / target / linux / brcm2708 / patches-3.18 / 0001-Main-bcm2708-linux-port.patch
1 From 95293790045ab4ae5c357460372dd1b57fc74f29 Mon Sep 17 00:00:00 2001
2 From: popcornmix <popcornmix@gmail.com>
3 Date: Sun, 12 May 2013 12:24:19 +0100
4 Subject: [PATCH 001/114] Main bcm2708 linux port
5
6 Signed-off-by: popcornmix <popcornmix@gmail.com>
7 ---
8 arch/arm/Kconfig | 17 +
9 arch/arm/Kconfig.debug | 8 +
10 arch/arm/Makefile | 1 +
11 arch/arm/configs/bcmrpi_defconfig | 464 ++++++++++++++++
12 arch/arm/kernel/process.c | 10 +
13 arch/arm/mach-bcm2708/Kconfig | 26 +
14 arch/arm/mach-bcm2708/Makefile | 6 +
15 arch/arm/mach-bcm2708/Makefile.boot | 3 +
16 arch/arm/mach-bcm2708/armctrl.c | 208 +++++++
17 arch/arm/mach-bcm2708/armctrl.h | 27 +
18 arch/arm/mach-bcm2708/bcm2708.c | 662 +++++++++++++++++++++++
19 arch/arm/mach-bcm2708/bcm2708.h | 49 ++
20 arch/arm/mach-bcm2708/clock.c | 61 +++
21 arch/arm/mach-bcm2708/clock.h | 24 +
22 arch/arm/mach-bcm2708/dma.c | 399 ++++++++++++++
23 arch/arm/mach-bcm2708/include/mach/arm_control.h | 419 ++++++++++++++
24 arch/arm/mach-bcm2708/include/mach/arm_power.h | 62 +++
25 arch/arm/mach-bcm2708/include/mach/clkdev.h | 7 +
26 arch/arm/mach-bcm2708/include/mach/debug-macro.S | 22 +
27 arch/arm/mach-bcm2708/include/mach/dma.h | 88 +++
28 arch/arm/mach-bcm2708/include/mach/entry-macro.S | 69 +++
29 arch/arm/mach-bcm2708/include/mach/frc.h | 38 ++
30 arch/arm/mach-bcm2708/include/mach/hardware.h | 28 +
31 arch/arm/mach-bcm2708/include/mach/io.h | 27 +
32 arch/arm/mach-bcm2708/include/mach/irqs.h | 196 +++++++
33 arch/arm/mach-bcm2708/include/mach/memory.h | 57 ++
34 arch/arm/mach-bcm2708/include/mach/platform.h | 228 ++++++++
35 arch/arm/mach-bcm2708/include/mach/power.h | 26 +
36 arch/arm/mach-bcm2708/include/mach/system.h | 38 ++
37 arch/arm/mach-bcm2708/include/mach/timex.h | 23 +
38 arch/arm/mach-bcm2708/include/mach/uncompress.h | 84 +++
39 arch/arm/mach-bcm2708/include/mach/vc_mem.h | 35 ++
40 arch/arm/mach-bcm2708/include/mach/vcio.h | 165 ++++++
41 arch/arm/mach-bcm2708/include/mach/vmalloc.h | 20 +
42 arch/arm/mach-bcm2708/power.c | 197 +++++++
43 arch/arm/mach-bcm2708/vc_mem.c | 431 +++++++++++++++
44 arch/arm/mach-bcm2708/vcio.c | 474 ++++++++++++++++
45 arch/arm/mm/Kconfig | 2 +-
46 arch/arm/mm/proc-v6.S | 15 +-
47 arch/arm/tools/mach-types | 1 +
48 drivers/tty/serial/amba-pl011.c | 2 +-
49 include/linux/mmc/host.h | 1 +
50 include/linux/mmc/sdhci.h | 1 +
51 43 files changed, 4716 insertions(+), 5 deletions(-)
52 create mode 100644 arch/arm/configs/bcmrpi_defconfig
53 create mode 100644 arch/arm/mach-bcm2708/Kconfig
54 create mode 100644 arch/arm/mach-bcm2708/Makefile
55 create mode 100644 arch/arm/mach-bcm2708/Makefile.boot
56 create mode 100644 arch/arm/mach-bcm2708/armctrl.c
57 create mode 100644 arch/arm/mach-bcm2708/armctrl.h
58 create mode 100644 arch/arm/mach-bcm2708/bcm2708.c
59 create mode 100644 arch/arm/mach-bcm2708/bcm2708.h
60 create mode 100644 arch/arm/mach-bcm2708/clock.c
61 create mode 100644 arch/arm/mach-bcm2708/clock.h
62 create mode 100644 arch/arm/mach-bcm2708/dma.c
63 create mode 100644 arch/arm/mach-bcm2708/include/mach/arm_control.h
64 create mode 100644 arch/arm/mach-bcm2708/include/mach/arm_power.h
65 create mode 100644 arch/arm/mach-bcm2708/include/mach/clkdev.h
66 create mode 100644 arch/arm/mach-bcm2708/include/mach/debug-macro.S
67 create mode 100644 arch/arm/mach-bcm2708/include/mach/dma.h
68 create mode 100644 arch/arm/mach-bcm2708/include/mach/entry-macro.S
69 create mode 100644 arch/arm/mach-bcm2708/include/mach/frc.h
70 create mode 100644 arch/arm/mach-bcm2708/include/mach/hardware.h
71 create mode 100644 arch/arm/mach-bcm2708/include/mach/io.h
72 create mode 100644 arch/arm/mach-bcm2708/include/mach/irqs.h
73 create mode 100644 arch/arm/mach-bcm2708/include/mach/memory.h
74 create mode 100644 arch/arm/mach-bcm2708/include/mach/platform.h
75 create mode 100644 arch/arm/mach-bcm2708/include/mach/power.h
76 create mode 100644 arch/arm/mach-bcm2708/include/mach/system.h
77 create mode 100644 arch/arm/mach-bcm2708/include/mach/timex.h
78 create mode 100644 arch/arm/mach-bcm2708/include/mach/uncompress.h
79 create mode 100644 arch/arm/mach-bcm2708/include/mach/vc_mem.h
80 create mode 100644 arch/arm/mach-bcm2708/include/mach/vcio.h
81 create mode 100644 arch/arm/mach-bcm2708/include/mach/vmalloc.h
82 create mode 100644 arch/arm/mach-bcm2708/power.c
83 create mode 100644 arch/arm/mach-bcm2708/vc_mem.c
84 create mode 100644 arch/arm/mach-bcm2708/vcio.c
85
86 diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
87 index 89c4b5c..4cedaf2 100644
88 --- a/arch/arm/Kconfig
89 +++ b/arch/arm/Kconfig
90 @@ -381,6 +381,22 @@ config ARCH_AT91
91 This enables support for systems based on Atmel
92 AT91RM9200 and AT91SAM9* processors.
93
94 +config ARCH_BCM2708
95 + bool "Broadcom BCM2708 family"
96 + select CPU_V6
97 + select ARM_AMBA
98 + select HAVE_CLK
99 + select HAVE_SCHED_CLOCK
100 + select NEED_MACH_GPIO_H
101 + select NEED_MACH_MEMORY_H
102 + select CLKDEV_LOOKUP
103 + select GENERIC_CLOCKEVENTS
104 + select ARM_ERRATA_411920
105 + select MACH_BCM2708
106 + select VC4
107 + help
108 + This enables support for Broadcom BCM2708 boards.
109 +
110 config ARCH_CLPS711X
111 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
112 select ARCH_REQUIRE_GPIOLIB
113 @@ -972,6 +988,7 @@ source "arch/arm/plat-versatile/Kconfig"
114 source "arch/arm/mach-vt8500/Kconfig"
115
116 source "arch/arm/mach-w90x900/Kconfig"
117 +source "arch/arm/mach-bcm2708/Kconfig"
118
119 source "arch/arm/mach-zynq/Kconfig"
120
121 diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
122 index d8f6a2e..526e50d 100644
123 --- a/arch/arm/Kconfig.debug
124 +++ b/arch/arm/Kconfig.debug
125 @@ -985,6 +985,14 @@ choice
126 options; the platform specific options are deprecated
127 and will be soon removed.
128
129 + config DEBUG_BCM2708_UART0
130 + bool "Broadcom BCM2708 UART0 (PL011)"
131 + depends on MACH_BCM2708
132 + help
133 + Say Y here if you want the debug print routines to direct
134 + their output to UART 0. The port must have been initialised
135 + by the boot-loader before use.
136 +
137 endchoice
138
139 config DEBUG_EXYNOS_UART
140 diff --git a/arch/arm/Makefile b/arch/arm/Makefile
141 index 034a949..fea9213 100644
142 --- a/arch/arm/Makefile
143 +++ b/arch/arm/Makefile
144 @@ -146,6 +146,7 @@ textofs-$(CONFIG_ARCH_AXXIA) := 0x00308000
145 machine-$(CONFIG_ARCH_AT91) += at91
146 machine-$(CONFIG_ARCH_AXXIA) += axxia
147 machine-$(CONFIG_ARCH_BCM) += bcm
148 +machine-$(CONFIG_ARCH_BCM2708) += bcm2708
149 machine-$(CONFIG_ARCH_BERLIN) += berlin
150 machine-$(CONFIG_ARCH_CLPS711X) += clps711x
151 machine-$(CONFIG_ARCH_CNS3XXX) += cns3xxx
152 diff --git a/arch/arm/configs/bcmrpi_defconfig b/arch/arm/configs/bcmrpi_defconfig
153 new file mode 100644
154 index 0000000..8950e53
155 --- /dev/null
156 +++ b/arch/arm/configs/bcmrpi_defconfig
157 @@ -0,0 +1,464 @@
158 +# CONFIG_LOCALVERSION_AUTO is not set
159 +CONFIG_SYSVIPC=y
160 +CONFIG_POSIX_MQUEUE=y
161 +CONFIG_FHANDLE=y
162 +CONFIG_AUDIT=y
163 +CONFIG_NO_HZ=y
164 +CONFIG_HIGH_RES_TIMERS=y
165 +CONFIG_BSD_PROCESS_ACCT=y
166 +CONFIG_BSD_PROCESS_ACCT_V3=y
167 +CONFIG_IKCONFIG=y
168 +CONFIG_IKCONFIG_PROC=y
169 +CONFIG_CGROUP_FREEZER=y
170 +CONFIG_CGROUP_DEVICE=y
171 +CONFIG_CGROUP_CPUACCT=y
172 +CONFIG_RESOURCE_COUNTERS=y
173 +CONFIG_BLK_CGROUP=y
174 +CONFIG_NAMESPACES=y
175 +CONFIG_SCHED_AUTOGROUP=y
176 +CONFIG_EMBEDDED=y
177 +# CONFIG_COMPAT_BRK is not set
178 +CONFIG_SLAB=y
179 +CONFIG_PROFILING=y
180 +CONFIG_OPROFILE=m
181 +CONFIG_KPROBES=y
182 +CONFIG_MODULES=y
183 +CONFIG_MODULE_UNLOAD=y
184 +CONFIG_MODVERSIONS=y
185 +CONFIG_MODULE_SRCVERSION_ALL=y
186 +# CONFIG_BLK_DEV_BSG is not set
187 +CONFIG_BLK_DEV_THROTTLING=y
188 +CONFIG_PARTITION_ADVANCED=y
189 +CONFIG_MAC_PARTITION=y
190 +CONFIG_CFQ_GROUP_IOSCHED=y
191 +CONFIG_ARCH_BCM2708=y
192 +CONFIG_AEABI=y
193 +CONFIG_SECCOMP=y
194 +CONFIG_ZBOOT_ROM_TEXT=0x0
195 +CONFIG_ZBOOT_ROM_BSS=0x0
196 +CONFIG_CMDLINE="dwc_otg.lpm_enable=0 console=ttyAMA0,115200 kgdboc=ttyAMA0,115200 root=/dev/mmcblk0p2 rootfstype=ext3 rootwait"
197 +CONFIG_KEXEC=y
198 +CONFIG_CPU_IDLE=y
199 +CONFIG_VFP=y
200 +CONFIG_BINFMT_MISC=m
201 +CONFIG_NET=y
202 +CONFIG_PACKET=y
203 +CONFIG_UNIX=y
204 +CONFIG_XFRM_USER=y
205 +CONFIG_NET_KEY=m
206 +CONFIG_INET=y
207 +CONFIG_IP_MULTICAST=y
208 +CONFIG_IP_PNP=y
209 +CONFIG_IP_PNP_DHCP=y
210 +CONFIG_IP_PNP_RARP=y
211 +CONFIG_SYN_COOKIES=y
212 +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
213 +# CONFIG_INET_XFRM_MODE_TUNNEL is not set
214 +# CONFIG_INET_XFRM_MODE_BEET is not set
215 +# CONFIG_INET_LRO is not set
216 +# CONFIG_INET_DIAG is not set
217 +# CONFIG_IPV6 is not set
218 +CONFIG_NET_PKTGEN=m
219 +CONFIG_IRDA=m
220 +CONFIG_IRLAN=m
221 +CONFIG_IRCOMM=m
222 +CONFIG_IRDA_ULTRA=y
223 +CONFIG_IRDA_CACHE_LAST_LSAP=y
224 +CONFIG_IRDA_FAST_RR=y
225 +CONFIG_IRTTY_SIR=m
226 +CONFIG_KINGSUN_DONGLE=m
227 +CONFIG_KSDAZZLE_DONGLE=m
228 +CONFIG_KS959_DONGLE=m
229 +CONFIG_USB_IRDA=m
230 +CONFIG_SIGMATEL_FIR=m
231 +CONFIG_MCS_FIR=m
232 +CONFIG_BT=m
233 +CONFIG_BT_RFCOMM=m
234 +CONFIG_BT_RFCOMM_TTY=y
235 +CONFIG_BT_BNEP=m
236 +CONFIG_BT_BNEP_MC_FILTER=y
237 +CONFIG_BT_BNEP_PROTO_FILTER=y
238 +CONFIG_BT_HIDP=m
239 +CONFIG_BT_HCIBTUSB=m
240 +CONFIG_BT_HCIBCM203X=m
241 +CONFIG_BT_HCIBPA10X=m
242 +CONFIG_BT_HCIBFUSB=m
243 +CONFIG_BT_HCIVHCI=m
244 +CONFIG_BT_MRVL=m
245 +CONFIG_BT_MRVL_SDIO=m
246 +CONFIG_BT_ATH3K=m
247 +CONFIG_CFG80211=m
248 +CONFIG_MAC80211=m
249 +CONFIG_MAC80211_MESH=y
250 +CONFIG_WIMAX=m
251 +CONFIG_NET_9P=m
252 +CONFIG_NFC=m
253 +CONFIG_NFC_PN533=m
254 +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
255 +CONFIG_BLK_DEV_LOOP=y
256 +CONFIG_BLK_DEV_CRYPTOLOOP=m
257 +CONFIG_BLK_DEV_NBD=m
258 +CONFIG_BLK_DEV_RAM=y
259 +CONFIG_CDROM_PKTCDVD=m
260 +CONFIG_SCSI=y
261 +# CONFIG_SCSI_PROC_FS is not set
262 +CONFIG_BLK_DEV_SD=m
263 +CONFIG_BLK_DEV_SR=m
264 +# CONFIG_SCSI_LOWLEVEL is not set
265 +CONFIG_MD=y
266 +CONFIG_NETDEVICES=y
267 +CONFIG_NETCONSOLE=m
268 +CONFIG_TUN=m
269 +CONFIG_MDIO_BITBANG=m
270 +CONFIG_PPP=m
271 +CONFIG_PPP_BSDCOMP=m
272 +CONFIG_PPP_DEFLATE=m
273 +CONFIG_PPP_ASYNC=m
274 +CONFIG_PPP_SYNC_TTY=m
275 +CONFIG_SLIP=m
276 +CONFIG_SLIP_COMPRESSED=y
277 +CONFIG_USB_CATC=m
278 +CONFIG_USB_KAWETH=m
279 +CONFIG_USB_PEGASUS=m
280 +CONFIG_USB_RTL8150=m
281 +CONFIG_USB_USBNET=y
282 +CONFIG_USB_NET_AX8817X=m
283 +CONFIG_USB_NET_CDCETHER=m
284 +CONFIG_USB_NET_CDC_EEM=m
285 +CONFIG_USB_NET_DM9601=m
286 +CONFIG_USB_NET_SMSC75XX=m
287 +CONFIG_USB_NET_SMSC95XX=y
288 +CONFIG_USB_NET_GL620A=m
289 +CONFIG_USB_NET_NET1080=m
290 +CONFIG_USB_NET_PLUSB=m
291 +CONFIG_USB_NET_MCS7830=m
292 +CONFIG_USB_NET_CDC_SUBSET=m
293 +CONFIG_USB_ALI_M5632=y
294 +CONFIG_USB_AN2720=y
295 +CONFIG_USB_KC2190=y
296 +# CONFIG_USB_NET_ZAURUS is not set
297 +CONFIG_USB_NET_CX82310_ETH=m
298 +CONFIG_USB_NET_KALMIA=m
299 +CONFIG_USB_NET_INT51X1=m
300 +CONFIG_USB_IPHETH=m
301 +CONFIG_USB_SIERRA_NET=m
302 +CONFIG_USB_VL600=m
303 +CONFIG_LIBERTAS_THINFIRM=m
304 +CONFIG_LIBERTAS_THINFIRM_USB=m
305 +CONFIG_AT76C50X_USB=m
306 +CONFIG_USB_ZD1201=m
307 +CONFIG_USB_NET_RNDIS_WLAN=m
308 +CONFIG_RTL8187=m
309 +CONFIG_MAC80211_HWSIM=m
310 +CONFIG_B43=m
311 +CONFIG_B43LEGACY=m
312 +CONFIG_HOSTAP=m
313 +CONFIG_LIBERTAS=m
314 +CONFIG_LIBERTAS_USB=m
315 +CONFIG_LIBERTAS_SDIO=m
316 +CONFIG_P54_COMMON=m
317 +CONFIG_P54_USB=m
318 +CONFIG_RT2X00=m
319 +CONFIG_RT2500USB=m
320 +CONFIG_RT73USB=m
321 +CONFIG_RT2800USB=m
322 +CONFIG_RT2800USB_RT53XX=y
323 +CONFIG_RTL8192CU=m
324 +CONFIG_ZD1211RW=m
325 +CONFIG_MWIFIEX=m
326 +CONFIG_MWIFIEX_SDIO=m
327 +CONFIG_WIMAX_I2400M_USB=m
328 +CONFIG_INPUT_POLLDEV=m
329 +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
330 +CONFIG_INPUT_JOYDEV=m
331 +CONFIG_INPUT_EVDEV=m
332 +# CONFIG_INPUT_KEYBOARD is not set
333 +# CONFIG_INPUT_MOUSE is not set
334 +CONFIG_INPUT_MISC=y
335 +CONFIG_INPUT_AD714X=m
336 +CONFIG_INPUT_ATI_REMOTE2=m
337 +CONFIG_INPUT_KEYSPAN_REMOTE=m
338 +CONFIG_INPUT_POWERMATE=m
339 +CONFIG_INPUT_YEALINK=m
340 +CONFIG_INPUT_CM109=m
341 +CONFIG_INPUT_UINPUT=m
342 +CONFIG_INPUT_ADXL34X=m
343 +CONFIG_INPUT_CMA3000=m
344 +CONFIG_SERIO=m
345 +CONFIG_SERIO_RAW=m
346 +CONFIG_GAMEPORT=m
347 +CONFIG_GAMEPORT_NS558=m
348 +CONFIG_GAMEPORT_L4=m
349 +# CONFIG_LEGACY_PTYS is not set
350 +# CONFIG_DEVKMEM is not set
351 +CONFIG_SERIAL_AMBA_PL011=y
352 +CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
353 +# CONFIG_HW_RANDOM is not set
354 +CONFIG_RAW_DRIVER=y
355 +# CONFIG_HWMON is not set
356 +CONFIG_WATCHDOG=y
357 +CONFIG_FB=y
358 +CONFIG_FRAMEBUFFER_CONSOLE=y
359 +CONFIG_LOGO=y
360 +# CONFIG_LOGO_LINUX_MONO is not set
361 +# CONFIG_LOGO_LINUX_VGA16 is not set
362 +CONFIG_HID_A4TECH=m
363 +CONFIG_HID_ACRUX=m
364 +CONFIG_HID_APPLE=m
365 +CONFIG_HID_BELKIN=m
366 +CONFIG_HID_CHERRY=m
367 +CONFIG_HID_CHICONY=m
368 +CONFIG_HID_CYPRESS=m
369 +CONFIG_HID_DRAGONRISE=m
370 +CONFIG_HID_EMS_FF=m
371 +CONFIG_HID_ELECOM=m
372 +CONFIG_HID_EZKEY=m
373 +CONFIG_HID_HOLTEK=m
374 +CONFIG_HID_KEYTOUCH=m
375 +CONFIG_HID_KYE=m
376 +CONFIG_HID_UCLOGIC=m
377 +CONFIG_HID_WALTOP=m
378 +CONFIG_HID_GYRATION=m
379 +CONFIG_HID_TWINHAN=m
380 +CONFIG_HID_KENSINGTON=m
381 +CONFIG_HID_LCPOWER=m
382 +CONFIG_HID_LOGITECH=m
383 +CONFIG_HID_MAGICMOUSE=m
384 +CONFIG_HID_MICROSOFT=m
385 +CONFIG_HID_MONTEREY=m
386 +CONFIG_HID_MULTITOUCH=m
387 +CONFIG_HID_NTRIG=m
388 +CONFIG_HID_ORTEK=m
389 +CONFIG_HID_PANTHERLORD=m
390 +CONFIG_HID_PETALYNX=m
391 +CONFIG_HID_PICOLCD=m
392 +CONFIG_HID_ROCCAT=m
393 +CONFIG_HID_SAMSUNG=m
394 +CONFIG_HID_SONY=m
395 +CONFIG_HID_SPEEDLINK=m
396 +CONFIG_HID_SUNPLUS=m
397 +CONFIG_HID_GREENASIA=m
398 +CONFIG_HID_SMARTJOYPLUS=m
399 +CONFIG_HID_TOPSEED=m
400 +CONFIG_HID_THRUSTMASTER=m
401 +CONFIG_HID_WACOM=m
402 +CONFIG_HID_WIIMOTE=m
403 +CONFIG_HID_ZEROPLUS=m
404 +CONFIG_HID_ZYDACRON=m
405 +CONFIG_HID_PID=y
406 +CONFIG_USB_HIDDEV=y
407 +CONFIG_USB=y
408 +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
409 +CONFIG_USB_MON=m
410 +CONFIG_USB_STORAGE=y
411 +CONFIG_USB_STORAGE_REALTEK=m
412 +CONFIG_USB_STORAGE_DATAFAB=m
413 +CONFIG_USB_STORAGE_FREECOM=m
414 +CONFIG_USB_STORAGE_ISD200=m
415 +CONFIG_USB_STORAGE_USBAT=m
416 +CONFIG_USB_STORAGE_SDDR09=m
417 +CONFIG_USB_STORAGE_SDDR55=m
418 +CONFIG_USB_STORAGE_JUMPSHOT=m
419 +CONFIG_USB_STORAGE_ALAUDA=m
420 +CONFIG_USB_STORAGE_ONETOUCH=m
421 +CONFIG_USB_STORAGE_KARMA=m
422 +CONFIG_USB_STORAGE_CYPRESS_ATACB=m
423 +CONFIG_USB_STORAGE_ENE_UB6250=m
424 +CONFIG_USB_UAS=m
425 +CONFIG_USB_MDC800=m
426 +CONFIG_USB_MICROTEK=m
427 +CONFIG_USB_SERIAL=m
428 +CONFIG_USB_SERIAL_GENERIC=y
429 +CONFIG_USB_SERIAL_AIRCABLE=m
430 +CONFIG_USB_SERIAL_ARK3116=m
431 +CONFIG_USB_SERIAL_BELKIN=m
432 +CONFIG_USB_SERIAL_CH341=m
433 +CONFIG_USB_SERIAL_WHITEHEAT=m
434 +CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
435 +CONFIG_USB_SERIAL_CP210X=m
436 +CONFIG_USB_SERIAL_CYPRESS_M8=m
437 +CONFIG_USB_SERIAL_EMPEG=m
438 +CONFIG_USB_SERIAL_FTDI_SIO=m
439 +CONFIG_USB_SERIAL_VISOR=m
440 +CONFIG_USB_SERIAL_IPAQ=m
441 +CONFIG_USB_SERIAL_IR=m
442 +CONFIG_USB_SERIAL_EDGEPORT=m
443 +CONFIG_USB_SERIAL_EDGEPORT_TI=m
444 +CONFIG_USB_SERIAL_GARMIN=m
445 +CONFIG_USB_SERIAL_IPW=m
446 +CONFIG_USB_SERIAL_IUU=m
447 +CONFIG_USB_SERIAL_KEYSPAN_PDA=m
448 +CONFIG_USB_SERIAL_KEYSPAN=m
449 +CONFIG_USB_SERIAL_KLSI=m
450 +CONFIG_USB_SERIAL_KOBIL_SCT=m
451 +CONFIG_USB_SERIAL_MCT_U232=m
452 +CONFIG_USB_SERIAL_MOS7720=m
453 +CONFIG_USB_SERIAL_MOS7840=m
454 +CONFIG_USB_SERIAL_NAVMAN=m
455 +CONFIG_USB_SERIAL_PL2303=m
456 +CONFIG_USB_SERIAL_OTI6858=m
457 +CONFIG_USB_SERIAL_QCAUX=m
458 +CONFIG_USB_SERIAL_QUALCOMM=m
459 +CONFIG_USB_SERIAL_SPCP8X5=m
460 +CONFIG_USB_SERIAL_SAFE=m
461 +CONFIG_USB_SERIAL_SIERRAWIRELESS=m
462 +CONFIG_USB_SERIAL_SYMBOL=m
463 +CONFIG_USB_SERIAL_TI=m
464 +CONFIG_USB_SERIAL_CYBERJACK=m
465 +CONFIG_USB_SERIAL_XIRCOM=m
466 +CONFIG_USB_SERIAL_OPTION=m
467 +CONFIG_USB_SERIAL_OMNINET=m
468 +CONFIG_USB_SERIAL_OPTICON=m
469 +CONFIG_USB_SERIAL_SSU100=m
470 +CONFIG_USB_SERIAL_DEBUG=m
471 +CONFIG_USB_EMI62=m
472 +CONFIG_USB_EMI26=m
473 +CONFIG_USB_ADUTUX=m
474 +CONFIG_USB_SEVSEG=m
475 +CONFIG_USB_RIO500=m
476 +CONFIG_USB_LEGOTOWER=m
477 +CONFIG_USB_LCD=m
478 +CONFIG_USB_LED=m
479 +CONFIG_USB_CYPRESS_CY7C63=m
480 +CONFIG_USB_CYTHERM=m
481 +CONFIG_USB_IDMOUSE=m
482 +CONFIG_USB_FTDI_ELAN=m
483 +CONFIG_USB_APPLEDISPLAY=m
484 +CONFIG_USB_LD=m
485 +CONFIG_USB_TRANCEVIBRATOR=m
486 +CONFIG_USB_IOWARRIOR=m
487 +CONFIG_USB_TEST=m
488 +CONFIG_USB_ISIGHTFW=m
489 +CONFIG_USB_YUREX=m
490 +CONFIG_MMC=y
491 +CONFIG_MMC_SDHCI=y
492 +CONFIG_MMC_SDHCI_PLTFM=y
493 +CONFIG_UIO=m
494 +CONFIG_UIO_PDRV_GENIRQ=m
495 +# CONFIG_IOMMU_SUPPORT is not set
496 +CONFIG_EXT4_FS=y
497 +CONFIG_EXT4_FS_POSIX_ACL=y
498 +CONFIG_EXT4_FS_SECURITY=y
499 +CONFIG_REISERFS_FS=m
500 +CONFIG_REISERFS_FS_XATTR=y
501 +CONFIG_REISERFS_FS_POSIX_ACL=y
502 +CONFIG_REISERFS_FS_SECURITY=y
503 +CONFIG_JFS_FS=m
504 +CONFIG_JFS_POSIX_ACL=y
505 +CONFIG_JFS_SECURITY=y
506 +CONFIG_JFS_STATISTICS=y
507 +CONFIG_XFS_FS=m
508 +CONFIG_XFS_QUOTA=y
509 +CONFIG_XFS_POSIX_ACL=y
510 +CONFIG_XFS_RT=y
511 +CONFIG_GFS2_FS=m
512 +CONFIG_OCFS2_FS=m
513 +CONFIG_BTRFS_FS=m
514 +CONFIG_BTRFS_FS_POSIX_ACL=y
515 +CONFIG_NILFS2_FS=m
516 +CONFIG_FANOTIFY=y
517 +CONFIG_AUTOFS4_FS=y
518 +CONFIG_FUSE_FS=m
519 +CONFIG_CUSE=m
520 +CONFIG_FSCACHE=y
521 +CONFIG_FSCACHE_STATS=y
522 +CONFIG_FSCACHE_HISTOGRAM=y
523 +CONFIG_CACHEFILES=y
524 +CONFIG_ISO9660_FS=m
525 +CONFIG_JOLIET=y
526 +CONFIG_ZISOFS=y
527 +CONFIG_UDF_FS=m
528 +CONFIG_MSDOS_FS=y
529 +CONFIG_VFAT_FS=y
530 +CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
531 +CONFIG_NTFS_FS=m
532 +CONFIG_TMPFS=y
533 +CONFIG_TMPFS_POSIX_ACL=y
534 +CONFIG_CONFIGFS_FS=y
535 +CONFIG_SQUASHFS=m
536 +CONFIG_SQUASHFS_XATTR=y
537 +CONFIG_SQUASHFS_LZO=y
538 +CONFIG_SQUASHFS_XZ=y
539 +CONFIG_NFS_FS=y
540 +CONFIG_NFS_V3_ACL=y
541 +CONFIG_NFS_V4=y
542 +CONFIG_ROOT_NFS=y
543 +CONFIG_NFS_FSCACHE=y
544 +CONFIG_CIFS=m
545 +CONFIG_CIFS_WEAK_PW_HASH=y
546 +CONFIG_CIFS_XATTR=y
547 +CONFIG_CIFS_POSIX=y
548 +CONFIG_9P_FS=m
549 +CONFIG_9P_FS_POSIX_ACL=y
550 +CONFIG_NLS_DEFAULT="utf8"
551 +CONFIG_NLS_CODEPAGE_437=y
552 +CONFIG_NLS_CODEPAGE_737=m
553 +CONFIG_NLS_CODEPAGE_775=m
554 +CONFIG_NLS_CODEPAGE_850=m
555 +CONFIG_NLS_CODEPAGE_852=m
556 +CONFIG_NLS_CODEPAGE_855=m
557 +CONFIG_NLS_CODEPAGE_857=m
558 +CONFIG_NLS_CODEPAGE_860=m
559 +CONFIG_NLS_CODEPAGE_861=m
560 +CONFIG_NLS_CODEPAGE_862=m
561 +CONFIG_NLS_CODEPAGE_863=m
562 +CONFIG_NLS_CODEPAGE_864=m
563 +CONFIG_NLS_CODEPAGE_865=m
564 +CONFIG_NLS_CODEPAGE_866=m
565 +CONFIG_NLS_CODEPAGE_869=m
566 +CONFIG_NLS_CODEPAGE_936=m
567 +CONFIG_NLS_CODEPAGE_950=m
568 +CONFIG_NLS_CODEPAGE_932=m
569 +CONFIG_NLS_CODEPAGE_949=m
570 +CONFIG_NLS_CODEPAGE_874=m
571 +CONFIG_NLS_ISO8859_8=m
572 +CONFIG_NLS_CODEPAGE_1250=m
573 +CONFIG_NLS_CODEPAGE_1251=m
574 +CONFIG_NLS_ASCII=y
575 +CONFIG_NLS_ISO8859_1=m
576 +CONFIG_NLS_ISO8859_2=m
577 +CONFIG_NLS_ISO8859_3=m
578 +CONFIG_NLS_ISO8859_4=m
579 +CONFIG_NLS_ISO8859_5=m
580 +CONFIG_NLS_ISO8859_6=m
581 +CONFIG_NLS_ISO8859_7=m
582 +CONFIG_NLS_ISO8859_9=m
583 +CONFIG_NLS_ISO8859_13=m
584 +CONFIG_NLS_ISO8859_14=m
585 +CONFIG_NLS_ISO8859_15=m
586 +CONFIG_NLS_KOI8_R=m
587 +CONFIG_NLS_KOI8_U=m
588 +CONFIG_NLS_UTF8=m
589 +CONFIG_PRINTK_TIME=y
590 +CONFIG_BOOT_PRINTK_DELAY=y
591 +CONFIG_DEBUG_INFO=y
592 +CONFIG_DEBUG_STACK_USAGE=y
593 +CONFIG_DEBUG_MEMORY_INIT=y
594 +CONFIG_DETECT_HUNG_TASK=y
595 +CONFIG_TIMER_STATS=y
596 +CONFIG_LATENCYTOP=y
597 +CONFIG_IRQSOFF_TRACER=y
598 +CONFIG_SCHED_TRACER=y
599 +CONFIG_STACK_TRACER=y
600 +CONFIG_BLK_DEV_IO_TRACE=y
601 +CONFIG_FUNCTION_PROFILER=y
602 +CONFIG_KGDB=y
603 +CONFIG_KGDB_KDB=y
604 +CONFIG_KDB_KEYBOARD=y
605 +CONFIG_STRICT_DEVMEM=y
606 +CONFIG_CRYPTO_AUTHENC=m
607 +CONFIG_CRYPTO_CBC=y
608 +CONFIG_CRYPTO_HMAC=y
609 +CONFIG_CRYPTO_XCBC=m
610 +CONFIG_CRYPTO_MD5=y
611 +CONFIG_CRYPTO_SHA1=y
612 +CONFIG_CRYPTO_SHA512=m
613 +CONFIG_CRYPTO_TGR192=m
614 +CONFIG_CRYPTO_WP512=m
615 +CONFIG_CRYPTO_CAST5=m
616 +CONFIG_CRYPTO_DES=y
617 +CONFIG_CRYPTO_DEFLATE=m
618 +# CONFIG_CRYPTO_ANSI_CPRNG is not set
619 +# CONFIG_CRYPTO_HW is not set
620 +CONFIG_CRC_ITU_T=y
621 +CONFIG_LIBCRC32C=y
622 diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
623 index fe972a2..f4f3bfd 100644
624 --- a/arch/arm/kernel/process.c
625 +++ b/arch/arm/kernel/process.c
626 @@ -166,6 +166,16 @@ void arch_cpu_idle_dead(void)
627 }
628 #endif
629
630 +char bcm2708_reboot_mode = 'h';
631 +
632 +int __init reboot_setup(char *str)
633 +{
634 + bcm2708_reboot_mode = str[0];
635 + return 1;
636 +}
637 +
638 +__setup("reboot=", reboot_setup);
639 +
640 /*
641 * Called by kexec, immediately prior to machine_kexec().
642 *
643 diff --git a/arch/arm/mach-bcm2708/Kconfig b/arch/arm/mach-bcm2708/Kconfig
644 new file mode 100644
645 index 0000000..1f11478
646 --- /dev/null
647 +++ b/arch/arm/mach-bcm2708/Kconfig
648 @@ -0,0 +1,26 @@
649 +menu "Broadcom BCM2708 Implementations"
650 + depends on ARCH_BCM2708
651 +
652 +config MACH_BCM2708
653 + bool "Broadcom BCM2708 Development Platform"
654 + select NEED_MACH_MEMORY_H
655 + select NEED_MACH_IO_H
656 + select CPU_V6
657 + help
658 + Include support for the Broadcom(R) BCM2708 platform.
659 +
660 +config BCM2708_VCMEM
661 + bool "Videocore Memory"
662 + depends on MACH_BCM2708
663 + default y
664 + help
665 + Helper for videocore memory access and total size allocation.
666 +
667 +config BCM2708_NOL2CACHE
668 + bool "Videocore L2 cache disable"
669 + depends on MACH_BCM2708
670 + default n
671 + help
672 + Do not allow ARM to use GPU's L2 cache. Requires disable_l2cache in config.txt.
673 +
674 +endmenu
675 diff --git a/arch/arm/mach-bcm2708/Makefile b/arch/arm/mach-bcm2708/Makefile
676 new file mode 100644
677 index 0000000..c76f39bc
678 --- /dev/null
679 +++ b/arch/arm/mach-bcm2708/Makefile
680 @@ -0,0 +1,6 @@
681 +#
682 +# Makefile for the linux kernel.
683 +#
684 +
685 +obj-$(CONFIG_MACH_BCM2708) += clock.o bcm2708.o armctrl.o vcio.o power.o dma.o
686 +obj-$(CONFIG_BCM2708_VCMEM) += vc_mem.o
687 diff --git a/arch/arm/mach-bcm2708/Makefile.boot b/arch/arm/mach-bcm2708/Makefile.boot
688 new file mode 100644
689 index 0000000..67039c3
690 --- /dev/null
691 +++ b/arch/arm/mach-bcm2708/Makefile.boot
692 @@ -0,0 +1,3 @@
693 + zreladdr-y := 0x00008000
694 +params_phys-y := 0x00000100
695 +initrd_phys-y := 0x00800000
696 diff --git a/arch/arm/mach-bcm2708/armctrl.c b/arch/arm/mach-bcm2708/armctrl.c
697 new file mode 100644
698 index 0000000..ef1c8d5
699 --- /dev/null
700 +++ b/arch/arm/mach-bcm2708/armctrl.c
701 @@ -0,0 +1,208 @@
702 +/*
703 + * linux/arch/arm/mach-bcm2708/armctrl.c
704 + *
705 + * Copyright (C) 2010 Broadcom
706 + *
707 + * This program is free software; you can redistribute it and/or modify
708 + * it under the terms of the GNU General Public License as published by
709 + * the Free Software Foundation; either version 2 of the License, or
710 + * (at your option) any later version.
711 + *
712 + * This program is distributed in the hope that it will be useful,
713 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
714 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
715 + * GNU General Public License for more details.
716 + *
717 + * You should have received a copy of the GNU General Public License
718 + * along with this program; if not, write to the Free Software
719 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
720 + */
721 +#include <linux/init.h>
722 +#include <linux/list.h>
723 +#include <linux/io.h>
724 +#include <linux/version.h>
725 +#include <linux/syscore_ops.h>
726 +#include <linux/interrupt.h>
727 +
728 +#include <asm/mach/irq.h>
729 +#include <mach/hardware.h>
730 +#include "armctrl.h"
731 +
732 +/* For support of kernels >= 3.0 assume only one VIC for now*/
733 +static unsigned int remap_irqs[(INTERRUPT_ARASANSDIO + 1) - INTERRUPT_JPEG] = {
734 + INTERRUPT_VC_JPEG,
735 + INTERRUPT_VC_USB,
736 + INTERRUPT_VC_3D,
737 + INTERRUPT_VC_DMA2,
738 + INTERRUPT_VC_DMA3,
739 + INTERRUPT_VC_I2C,
740 + INTERRUPT_VC_SPI,
741 + INTERRUPT_VC_I2SPCM,
742 + INTERRUPT_VC_SDIO,
743 + INTERRUPT_VC_UART,
744 + INTERRUPT_VC_ARASANSDIO
745 +};
746 +
747 +static void armctrl_mask_irq(struct irq_data *d)
748 +{
749 + static const unsigned int disables[4] = {
750 + ARM_IRQ_DIBL1,
751 + ARM_IRQ_DIBL2,
752 + ARM_IRQ_DIBL3,
753 + 0
754 + };
755 +
756 + unsigned int data = (unsigned int)irq_get_chip_data(d->irq);
757 + writel(1 << (data & 0x1f), __io_address(disables[(data >> 5) & 0x3]));
758 +}
759 +
760 +static void armctrl_unmask_irq(struct irq_data *d)
761 +{
762 + static const unsigned int enables[4] = {
763 + ARM_IRQ_ENBL1,
764 + ARM_IRQ_ENBL2,
765 + ARM_IRQ_ENBL3,
766 + 0
767 + };
768 +
769 + unsigned int data = (unsigned int)irq_get_chip_data(d->irq);
770 + writel(1 << (data & 0x1f), __io_address(enables[(data >> 5) & 0x3]));
771 +}
772 +
773 +#if defined(CONFIG_PM)
774 +
775 +/* for kernels 3.xx use the new syscore_ops apis but for older kernels use the sys dev class */
776 +
777 +/* Static defines
778 + * struct armctrl_device - VIC PM device (< 3.xx)
779 + * @sysdev: The system device which is registered. (< 3.xx)
780 + * @irq: The IRQ number for the base of the VIC.
781 + * @base: The register base for the VIC.
782 + * @resume_sources: A bitmask of interrupts for resume.
783 + * @resume_irqs: The IRQs enabled for resume.
784 + * @int_select: Save for VIC_INT_SELECT.
785 + * @int_enable: Save for VIC_INT_ENABLE.
786 + * @soft_int: Save for VIC_INT_SOFT.
787 + * @protect: Save for VIC_PROTECT.
788 + */
789 +struct armctrl_info {
790 + void __iomem *base;
791 + int irq;
792 + u32 resume_sources;
793 + u32 resume_irqs;
794 + u32 int_select;
795 + u32 int_enable;
796 + u32 soft_int;
797 + u32 protect;
798 +} armctrl;
799 +
800 +static int armctrl_suspend(void)
801 +{
802 + return 0;
803 +}
804 +
805 +static void armctrl_resume(void)
806 +{
807 + return;
808 +}
809 +
810 +/**
811 + * armctrl_pm_register - Register a VIC for later power management control
812 + * @base: The base address of the VIC.
813 + * @irq: The base IRQ for the VIC.
814 + * @resume_sources: bitmask of interrupts allowed for resume sources.
815 + *
816 + * For older kernels (< 3.xx) do -
817 + * Register the VIC with the system device tree so that it can be notified
818 + * of suspend and resume requests and ensure that the correct actions are
819 + * taken to re-instate the settings on resume.
820 + */
821 +static void __init armctrl_pm_register(void __iomem * base, unsigned int irq,
822 + u32 resume_sources)
823 +{
824 + armctrl.base = base;
825 + armctrl.resume_sources = resume_sources;
826 + armctrl.irq = irq;
827 +}
828 +
829 +static int armctrl_set_wake(struct irq_data *d, unsigned int on)
830 +{
831 + unsigned int off = d->irq & 31;
832 + u32 bit = 1 << off;
833 +
834 + if (!(bit & armctrl.resume_sources))
835 + return -EINVAL;
836 +
837 + if (on)
838 + armctrl.resume_irqs |= bit;
839 + else
840 + armctrl.resume_irqs &= ~bit;
841 +
842 + return 0;
843 +}
844 +
845 +#else
846 +static inline void armctrl_pm_register(void __iomem * base, unsigned int irq,
847 + u32 arg1)
848 +{
849 +}
850 +
851 +#define armctrl_suspend NULL
852 +#define armctrl_resume NULL
853 +#define armctrl_set_wake NULL
854 +#endif /* CONFIG_PM */
855 +
856 +static struct syscore_ops armctrl_syscore_ops = {
857 + .suspend = armctrl_suspend,
858 + .resume = armctrl_resume,
859 +};
860 +
861 +/**
862 + * armctrl_syscore_init - initicall to register VIC pm functions
863 + *
864 + * This is called via late_initcall() to register
865 + * the resources for the VICs due to the early
866 + * nature of the VIC's registration.
867 +*/
868 +static int __init armctrl_syscore_init(void)
869 +{
870 + register_syscore_ops(&armctrl_syscore_ops);
871 + return 0;
872 +}
873 +
874 +late_initcall(armctrl_syscore_init);
875 +
876 +static struct irq_chip armctrl_chip = {
877 + .name = "ARMCTRL",
878 + .irq_ack = NULL,
879 + .irq_mask = armctrl_mask_irq,
880 + .irq_unmask = armctrl_unmask_irq,
881 + .irq_set_wake = armctrl_set_wake,
882 +};
883 +
884 +/**
885 + * armctrl_init - initialise a vectored interrupt controller
886 + * @base: iomem base address
887 + * @irq_start: starting interrupt number, must be muliple of 32
888 + * @armctrl_sources: bitmask of interrupt sources to allow
889 + * @resume_sources: bitmask of interrupt sources to allow for resume
890 + */
891 +int __init armctrl_init(void __iomem * base, unsigned int irq_start,
892 + u32 armctrl_sources, u32 resume_sources)
893 +{
894 + unsigned int irq;
895 +
896 + for (irq = 0; irq < BCM2708_ALLOC_IRQS; irq++) {
897 + unsigned int data = irq;
898 + if (irq >= INTERRUPT_JPEG && irq <= INTERRUPT_ARASANSDIO)
899 + data = remap_irqs[irq - INTERRUPT_JPEG];
900 +
901 + irq_set_chip(irq, &armctrl_chip);
902 + irq_set_chip_data(irq, (void *)data);
903 + irq_set_handler(irq, handle_level_irq);
904 + set_irq_flags(irq, IRQF_VALID | IRQF_PROBE | IRQF_DISABLED);
905 + }
906 +
907 + armctrl_pm_register(base, irq_start, resume_sources);
908 + return 0;
909 +}
910 diff --git a/arch/arm/mach-bcm2708/armctrl.h b/arch/arm/mach-bcm2708/armctrl.h
911 new file mode 100644
912 index 0000000..0aa916e
913 --- /dev/null
914 +++ b/arch/arm/mach-bcm2708/armctrl.h
915 @@ -0,0 +1,27 @@
916 +/*
917 + * linux/arch/arm/mach-bcm2708/armctrl.h
918 + *
919 + * Copyright (C) 2010 Broadcom
920 + *
921 + * This program is free software; you can redistribute it and/or modify
922 + * it under the terms of the GNU General Public License as published by
923 + * the Free Software Foundation; either version 2 of the License, or
924 + * (at your option) any later version.
925 + *
926 + * This program is distributed in the hope that it will be useful,
927 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
928 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
929 + * GNU General Public License for more details.
930 + *
931 + * You should have received a copy of the GNU General Public License
932 + * along with this program; if not, write to the Free Software
933 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
934 + */
935 +
936 +#ifndef __BCM2708_ARMCTRL_H
937 +#define __BCM2708_ARMCTRL_H
938 +
939 +extern int __init armctrl_init(void __iomem * base, unsigned int irq_start,
940 + u32 armctrl_sources, u32 resume_sources);
941 +
942 +#endif
943 diff --git a/arch/arm/mach-bcm2708/bcm2708.c b/arch/arm/mach-bcm2708/bcm2708.c
944 new file mode 100644
945 index 0000000..9b4e709
946 --- /dev/null
947 +++ b/arch/arm/mach-bcm2708/bcm2708.c
948 @@ -0,0 +1,662 @@
949 +/*
950 + * linux/arch/arm/mach-bcm2708/bcm2708.c
951 + *
952 + * Copyright (C) 2010 Broadcom
953 + *
954 + * This program is free software; you can redistribute it and/or modify
955 + * it under the terms of the GNU General Public License as published by
956 + * the Free Software Foundation; either version 2 of the License, or
957 + * (at your option) any later version.
958 + *
959 + * This program is distributed in the hope that it will be useful,
960 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
961 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
962 + * GNU General Public License for more details.
963 + *
964 + * You should have received a copy of the GNU General Public License
965 + * along with this program; if not, write to the Free Software
966 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
967 + */
968 +
969 +#include <linux/init.h>
970 +#include <linux/device.h>
971 +#include <linux/dma-mapping.h>
972 +#include <linux/serial_8250.h>
973 +#include <linux/platform_device.h>
974 +#include <linux/syscore_ops.h>
975 +#include <linux/interrupt.h>
976 +#include <linux/amba/bus.h>
977 +#include <linux/amba/clcd.h>
978 +#include <linux/clockchips.h>
979 +#include <linux/cnt32_to_63.h>
980 +#include <linux/io.h>
981 +#include <linux/module.h>
982 +
983 +#include <linux/version.h>
984 +#include <linux/clkdev.h>
985 +#include <asm/system_info.h>
986 +#include <mach/hardware.h>
987 +#include <asm/irq.h>
988 +#include <linux/leds.h>
989 +#include <asm/mach-types.h>
990 +#include <linux/sched_clock.h>
991 +
992 +#include <asm/mach/arch.h>
993 +#include <asm/mach/flash.h>
994 +#include <asm/mach/irq.h>
995 +#include <asm/mach/time.h>
996 +#include <asm/mach/map.h>
997 +
998 +#include <mach/timex.h>
999 +#include <mach/dma.h>
1000 +#include <mach/vcio.h>
1001 +#include <mach/system.h>
1002 +
1003 +#include <linux/delay.h>
1004 +
1005 +#include "bcm2708.h"
1006 +#include "armctrl.h"
1007 +#include "clock.h"
1008 +
1009 +#ifdef CONFIG_BCM_VC_CMA
1010 +#include <linux/broadcom/vc_cma.h>
1011 +#endif
1012 +
1013 +
1014 +/* Effectively we have an IOMMU (ARM<->VideoCore map) that is set up to
1015 + * give us IO access only to 64Mbytes of physical memory (26 bits). We could
1016 + * represent this window by setting our dmamasks to 26 bits but, in fact
1017 + * we're not going to use addresses outside this range (they're not in real
1018 + * memory) so we don't bother.
1019 + *
1020 + * In the future we might include code to use this IOMMU to remap other
1021 + * physical addresses onto VideoCore memory then the use of 32-bits would be
1022 + * more legitimate.
1023 + */
1024 +#define DMA_MASK_BITS_COMMON 32
1025 +
1026 +/* command line parameters */
1027 +static unsigned boardrev, serial;
1028 +static unsigned uart_clock;
1029 +static unsigned disk_led_gpio = 16;
1030 +static unsigned disk_led_active_low = 1;
1031 +static unsigned reboot_part = 0;
1032 +
1033 +static void __init bcm2708_init_led(void);
1034 +
1035 +void __init bcm2708_init_irq(void)
1036 +{
1037 + armctrl_init(__io_address(ARMCTRL_IC_BASE), 0, 0, 0);
1038 +}
1039 +
1040 +static struct map_desc bcm2708_io_desc[] __initdata = {
1041 + {
1042 + .virtual = IO_ADDRESS(ARMCTRL_BASE),
1043 + .pfn = __phys_to_pfn(ARMCTRL_BASE),
1044 + .length = SZ_4K,
1045 + .type = MT_DEVICE},
1046 + {
1047 + .virtual = IO_ADDRESS(UART0_BASE),
1048 + .pfn = __phys_to_pfn(UART0_BASE),
1049 + .length = SZ_4K,
1050 + .type = MT_DEVICE},
1051 + {
1052 + .virtual = IO_ADDRESS(UART1_BASE),
1053 + .pfn = __phys_to_pfn(UART1_BASE),
1054 + .length = SZ_4K,
1055 + .type = MT_DEVICE},
1056 + {
1057 + .virtual = IO_ADDRESS(DMA_BASE),
1058 + .pfn = __phys_to_pfn(DMA_BASE),
1059 + .length = SZ_4K,
1060 + .type = MT_DEVICE},
1061 + {
1062 + .virtual = IO_ADDRESS(MCORE_BASE),
1063 + .pfn = __phys_to_pfn(MCORE_BASE),
1064 + .length = SZ_4K,
1065 + .type = MT_DEVICE},
1066 + {
1067 + .virtual = IO_ADDRESS(ST_BASE),
1068 + .pfn = __phys_to_pfn(ST_BASE),
1069 + .length = SZ_4K,
1070 + .type = MT_DEVICE},
1071 + {
1072 + .virtual = IO_ADDRESS(USB_BASE),
1073 + .pfn = __phys_to_pfn(USB_BASE),
1074 + .length = SZ_128K,
1075 + .type = MT_DEVICE},
1076 + {
1077 + .virtual = IO_ADDRESS(PM_BASE),
1078 + .pfn = __phys_to_pfn(PM_BASE),
1079 + .length = SZ_4K,
1080 + .type = MT_DEVICE},
1081 + {
1082 + .virtual = IO_ADDRESS(GPIO_BASE),
1083 + .pfn = __phys_to_pfn(GPIO_BASE),
1084 + .length = SZ_4K,
1085 + .type = MT_DEVICE}
1086 +};
1087 +
1088 +void __init bcm2708_map_io(void)
1089 +{
1090 + iotable_init(bcm2708_io_desc, ARRAY_SIZE(bcm2708_io_desc));
1091 +}
1092 +
1093 +/* The STC is a free running counter that increments at the rate of 1MHz */
1094 +#define STC_FREQ_HZ 1000000
1095 +
1096 +static inline uint32_t timer_read(void)
1097 +{
1098 + /* STC: a free running counter that increments at the rate of 1MHz */
1099 + return readl(__io_address(ST_BASE + 0x04));
1100 +}
1101 +
1102 +static unsigned long bcm2708_read_current_timer(void)
1103 +{
1104 + return timer_read();
1105 +}
1106 +
1107 +static u64 notrace bcm2708_read_sched_clock(void)
1108 +{
1109 + return timer_read();
1110 +}
1111 +
1112 +static cycle_t clksrc_read(struct clocksource *cs)
1113 +{
1114 + return timer_read();
1115 +}
1116 +
1117 +static struct clocksource clocksource_stc = {
1118 + .name = "stc",
1119 + .rating = 300,
1120 + .read = clksrc_read,
1121 + .mask = CLOCKSOURCE_MASK(32),
1122 + .flags = CLOCK_SOURCE_IS_CONTINUOUS,
1123 +};
1124 +
1125 +unsigned long frc_clock_ticks32(void)
1126 +{
1127 + return timer_read();
1128 +}
1129 +
1130 +static void __init bcm2708_clocksource_init(void)
1131 +{
1132 + if (clocksource_register_hz(&clocksource_stc, STC_FREQ_HZ)) {
1133 + printk(KERN_ERR "timer: failed to initialize clock "
1134 + "source %s\n", clocksource_stc.name);
1135 + }
1136 +}
1137 +
1138 +
1139 +/*
1140 + * These are fixed clocks.
1141 + */
1142 +static struct clk ref24_clk = {
1143 + .rate = UART0_CLOCK, /* The UART is clocked at 3MHz via APB_CLK */
1144 +};
1145 +
1146 +static struct clk osc_clk = {
1147 +#ifdef CONFIG_ARCH_BCM2708_CHIPIT
1148 + .rate = 27000000,
1149 +#else
1150 + .rate = 500000000, /* ARM clock is set from the VideoCore booter */
1151 +#endif
1152 +};
1153 +
1154 +/* warning - the USB needs a clock > 34MHz */
1155 +
1156 +#ifdef CONFIG_MMC_BCM2708
1157 +static struct clk sdhost_clk = {
1158 +#ifdef CONFIG_ARCH_BCM2708_CHIPIT
1159 + .rate = 4000000, /* 4MHz */
1160 +#else
1161 + .rate = 250000000, /* 250MHz */
1162 +#endif
1163 +};
1164 +#endif
1165 +
1166 +static struct clk_lookup lookups[] = {
1167 + { /* UART0 */
1168 + .dev_id = "dev:f1",
1169 + .clk = &ref24_clk,
1170 + },
1171 + { /* USB */
1172 + .dev_id = "bcm2708_usb",
1173 + .clk = &osc_clk,
1174 + }
1175 +};
1176 +
1177 +#define UART0_IRQ { IRQ_UART, 0 /*NO_IRQ*/ }
1178 +#define UART0_DMA { 15, 14 }
1179 +
1180 +AMBA_DEVICE(uart0, "dev:f1", UART0, NULL);
1181 +
1182 +static struct amba_device *amba_devs[] __initdata = {
1183 + &uart0_device,
1184 +};
1185 +
1186 +static struct resource bcm2708_dmaman_resources[] = {
1187 + {
1188 + .start = DMA_BASE,
1189 + .end = DMA_BASE + SZ_4K - 1,
1190 + .flags = IORESOURCE_MEM,
1191 + }
1192 +};
1193 +
1194 +static struct platform_device bcm2708_dmaman_device = {
1195 + .name = BCM_DMAMAN_DRIVER_NAME,
1196 + .id = 0, /* first bcm2708_dma */
1197 + .resource = bcm2708_dmaman_resources,
1198 + .num_resources = ARRAY_SIZE(bcm2708_dmaman_resources),
1199 +};
1200 +
1201 +static u64 fb_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON);
1202 +
1203 +static struct platform_device bcm2708_fb_device = {
1204 + .name = "bcm2708_fb",
1205 + .id = -1, /* only one bcm2708_fb */
1206 + .resource = NULL,
1207 + .num_resources = 0,
1208 + .dev = {
1209 + .dma_mask = &fb_dmamask,
1210 + .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON),
1211 + },
1212 +};
1213 +
1214 +static struct plat_serial8250_port bcm2708_uart1_platform_data[] = {
1215 + {
1216 + .mapbase = UART1_BASE + 0x40,
1217 + .irq = IRQ_AUX,
1218 + .uartclk = 125000000,
1219 + .regshift = 2,
1220 + .iotype = UPIO_MEM,
1221 + .flags = UPF_FIXED_TYPE | UPF_IOREMAP | UPF_SKIP_TEST,
1222 + .type = PORT_8250,
1223 + },
1224 + {},
1225 +};
1226 +
1227 +static struct platform_device bcm2708_uart1_device = {
1228 + .name = "serial8250",
1229 + .id = PLAT8250_DEV_PLATFORM,
1230 + .dev = {
1231 + .platform_data = bcm2708_uart1_platform_data,
1232 + },
1233 +};
1234 +
1235 +static struct resource bcm2708_usb_resources[] = {
1236 + [0] = {
1237 + .start = USB_BASE,
1238 + .end = USB_BASE + SZ_128K - 1,
1239 + .flags = IORESOURCE_MEM,
1240 + },
1241 + [1] = {
1242 + .start = IRQ_USB,
1243 + .end = IRQ_USB,
1244 + .flags = IORESOURCE_IRQ,
1245 + },
1246 +};
1247 +
1248 +static u64 usb_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON);
1249 +
1250 +static struct platform_device bcm2708_usb_device = {
1251 + .name = "bcm2708_usb",
1252 + .id = -1, /* only one bcm2708_usb */
1253 + .resource = bcm2708_usb_resources,
1254 + .num_resources = ARRAY_SIZE(bcm2708_usb_resources),
1255 + .dev = {
1256 + .dma_mask = &usb_dmamask,
1257 + .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON),
1258 + },
1259 +};
1260 +
1261 +static struct resource bcm2708_vcio_resources[] = {
1262 + [0] = { /* mailbox/semaphore/doorbell access */
1263 + .start = MCORE_BASE,
1264 + .end = MCORE_BASE + SZ_4K - 1,
1265 + .flags = IORESOURCE_MEM,
1266 + },
1267 +};
1268 +
1269 +static u64 vcio_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON);
1270 +
1271 +static struct platform_device bcm2708_vcio_device = {
1272 + .name = BCM_VCIO_DRIVER_NAME,
1273 + .id = -1, /* only one VideoCore I/O area */
1274 + .resource = bcm2708_vcio_resources,
1275 + .num_resources = ARRAY_SIZE(bcm2708_vcio_resources),
1276 + .dev = {
1277 + .dma_mask = &vcio_dmamask,
1278 + .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON),
1279 + },
1280 +};
1281 +
1282 +static struct resource bcm2708_systemtimer_resources[] = {
1283 + [0] = { /* system timer access */
1284 + .start = ST_BASE,
1285 + .end = ST_BASE + SZ_4K - 1,
1286 + .flags = IORESOURCE_MEM,
1287 + },
1288 + {
1289 + .start = IRQ_TIMER3,
1290 + .end = IRQ_TIMER3,
1291 + .flags = IORESOURCE_IRQ,
1292 + }
1293 +
1294 +};
1295 +
1296 +static u64 systemtimer_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON);
1297 +
1298 +static struct platform_device bcm2708_systemtimer_device = {
1299 + .name = "bcm2708_systemtimer",
1300 + .id = -1, /* only one VideoCore I/O area */
1301 + .resource = bcm2708_systemtimer_resources,
1302 + .num_resources = ARRAY_SIZE(bcm2708_systemtimer_resources),
1303 + .dev = {
1304 + .dma_mask = &systemtimer_dmamask,
1305 + .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON),
1306 + },
1307 +};
1308 +
1309 +static struct resource bcm2708_powerman_resources[] = {
1310 + [0] = {
1311 + .start = PM_BASE,
1312 + .end = PM_BASE + SZ_256 - 1,
1313 + .flags = IORESOURCE_MEM,
1314 + },
1315 +};
1316 +
1317 +static u64 powerman_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON);
1318 +
1319 +struct platform_device bcm2708_powerman_device = {
1320 + .name = "bcm2708_powerman",
1321 + .id = 0,
1322 + .num_resources = ARRAY_SIZE(bcm2708_powerman_resources),
1323 + .resource = bcm2708_powerman_resources,
1324 + .dev = {
1325 + .dma_mask = &powerman_dmamask,
1326 + .coherent_dma_mask = 0xffffffffUL},
1327 +};
1328 +
1329 +int __init bcm_register_device(struct platform_device *pdev)
1330 +{
1331 + int ret;
1332 +
1333 + ret = platform_device_register(pdev);
1334 + if (ret)
1335 + pr_debug("Unable to register platform device '%s': %d\n",
1336 + pdev->name, ret);
1337 +
1338 + return ret;
1339 +}
1340 +
1341 +int calc_rsts(int partition)
1342 +{
1343 + return PM_PASSWORD |
1344 + ((partition & (1 << 0)) << 0) |
1345 + ((partition & (1 << 1)) << 1) |
1346 + ((partition & (1 << 2)) << 2) |
1347 + ((partition & (1 << 3)) << 3) |
1348 + ((partition & (1 << 4)) << 4) |
1349 + ((partition & (1 << 5)) << 5);
1350 +}
1351 +
1352 +static void bcm2708_restart(enum reboot_mode mode, const char *cmd)
1353 +{
1354 + extern char bcm2708_reboot_mode;
1355 + uint32_t pm_rstc, pm_wdog;
1356 + uint32_t timeout = 10;
1357 + uint32_t pm_rsts = 0;
1358 +
1359 + if(bcm2708_reboot_mode == 'q')
1360 + {
1361 + // NOOBS < 1.3 booting with reboot=q
1362 + pm_rsts = readl(__io_address(PM_RSTS));
1363 + pm_rsts = PM_PASSWORD | pm_rsts | PM_RSTS_HADWRQ_SET;
1364 + }
1365 + else if(bcm2708_reboot_mode == 'p')
1366 + {
1367 + // NOOBS < 1.3 halting
1368 + pm_rsts = readl(__io_address(PM_RSTS));
1369 + pm_rsts = PM_PASSWORD | pm_rsts | PM_RSTS_HADWRH_SET;
1370 + }
1371 + else
1372 + {
1373 + pm_rsts = calc_rsts(reboot_part);
1374 + }
1375 +
1376 + writel(pm_rsts, __io_address(PM_RSTS));
1377 +
1378 + /* Setup watchdog for reset */
1379 + pm_rstc = readl(__io_address(PM_RSTC));
1380 +
1381 + pm_wdog = PM_PASSWORD | (timeout & PM_WDOG_TIME_SET); // watchdog timer = timer clock / 16; need password (31:16) + value (11:0)
1382 + pm_rstc = PM_PASSWORD | (pm_rstc & PM_RSTC_WRCFG_CLR) | PM_RSTC_WRCFG_FULL_RESET;
1383 +
1384 + writel(pm_wdog, __io_address(PM_WDOG));
1385 + writel(pm_rstc, __io_address(PM_RSTC));
1386 +}
1387 +
1388 +/* We can't really power off, but if we do the normal reset scheme, and indicate to bootcode.bin not to reboot, then most of the chip will be powered off */
1389 +static void bcm2708_power_off(void)
1390 +{
1391 + extern char bcm2708_reboot_mode;
1392 + if(bcm2708_reboot_mode == 'q')
1393 + {
1394 + // NOOBS < v1.3
1395 + bcm2708_restart('p', "");
1396 + }
1397 + else
1398 + {
1399 + /* partition 63 is special code for HALT the bootloader knows not to boot*/
1400 + reboot_part = 63;
1401 + /* continue with normal reset mechanism */
1402 + bcm2708_restart(0, "");
1403 + }
1404 +}
1405 +
1406 +void __init bcm2708_init(void)
1407 +{
1408 + int i;
1409 +
1410 +#if defined(CONFIG_BCM_VC_CMA)
1411 + vc_cma_early_init();
1412 +#endif
1413 + printk("bcm2708.uart_clock = %d\n", uart_clock);
1414 + pm_power_off = bcm2708_power_off;
1415 +
1416 + if (uart_clock)
1417 + lookups[0].clk->rate = uart_clock;
1418 +
1419 + for (i = 0; i < ARRAY_SIZE(lookups); i++)
1420 + clkdev_add(&lookups[i]);
1421 +
1422 + bcm_register_device(&bcm2708_dmaman_device);
1423 + bcm_register_device(&bcm2708_vcio_device);
1424 + bcm_register_device(&bcm2708_systemtimer_device);
1425 + bcm_register_device(&bcm2708_fb_device);
1426 + bcm_register_device(&bcm2708_usb_device);
1427 + bcm_register_device(&bcm2708_uart1_device);
1428 + bcm_register_device(&bcm2708_powerman_device);
1429 +
1430 + bcm2708_init_led();
1431 +
1432 + for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
1433 + struct amba_device *d = amba_devs[i];
1434 + amba_device_register(d, &iomem_resource);
1435 + }
1436 + system_rev = boardrev;
1437 + system_serial_low = serial;
1438 +}
1439 +
1440 +static void timer_set_mode(enum clock_event_mode mode,
1441 + struct clock_event_device *clk)
1442 +{
1443 + switch (mode) {
1444 + case CLOCK_EVT_MODE_ONESHOT: /* Leave the timer disabled, .set_next_event will enable it */
1445 + case CLOCK_EVT_MODE_SHUTDOWN:
1446 + break;
1447 + case CLOCK_EVT_MODE_PERIODIC:
1448 +
1449 + case CLOCK_EVT_MODE_UNUSED:
1450 + case CLOCK_EVT_MODE_RESUME:
1451 +
1452 + default:
1453 + printk(KERN_ERR "timer_set_mode: unhandled mode:%d\n",
1454 + (int)mode);
1455 + break;
1456 + }
1457 +
1458 +}
1459 +
1460 +static int timer_set_next_event(unsigned long cycles,
1461 + struct clock_event_device *unused)
1462 +{
1463 + unsigned long stc;
1464 + do {
1465 + stc = readl(__io_address(ST_BASE + 0x04));
1466 + /* We could take a FIQ here, which may push ST above STC3 */
1467 + writel(stc + cycles, __io_address(ST_BASE + 0x18));
1468 + } while ((signed long) cycles >= 0 &&
1469 + (signed long) (readl(__io_address(ST_BASE + 0x04)) - stc)
1470 + >= (signed long) cycles);
1471 + return 0;
1472 +}
1473 +
1474 +static struct clock_event_device timer0_clockevent = {
1475 + .name = "timer0",
1476 + .shift = 32,
1477 + .features = CLOCK_EVT_FEAT_ONESHOT,
1478 + .set_mode = timer_set_mode,
1479 + .set_next_event = timer_set_next_event,
1480 +};
1481 +
1482 +/*
1483 + * IRQ handler for the timer
1484 + */
1485 +static irqreturn_t bcm2708_timer_interrupt(int irq, void *dev_id)
1486 +{
1487 + struct clock_event_device *evt = &timer0_clockevent;
1488 +
1489 + writel(1 << 3, __io_address(ST_BASE + 0x00)); /* stcs clear timer int */
1490 +
1491 + evt->event_handler(evt);
1492 +
1493 + return IRQ_HANDLED;
1494 +}
1495 +
1496 +static struct irqaction bcm2708_timer_irq = {
1497 + .name = "BCM2708 Timer Tick",
1498 + .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
1499 + .handler = bcm2708_timer_interrupt,
1500 +};
1501 +
1502 +/*
1503 + * Set up timer interrupt, and return the current time in seconds.
1504 + */
1505 +
1506 +static struct delay_timer bcm2708_delay_timer = {
1507 + .read_current_timer = bcm2708_read_current_timer,
1508 + .freq = STC_FREQ_HZ,
1509 +};
1510 +
1511 +static void __init bcm2708_timer_init(void)
1512 +{
1513 + /* init high res timer */
1514 + bcm2708_clocksource_init();
1515 +
1516 + /*
1517 + * Initialise to a known state (all timers off)
1518 + */
1519 + writel(0, __io_address(ARM_T_CONTROL));
1520 + /*
1521 + * Make irqs happen for the system timer
1522 + */
1523 + setup_irq(IRQ_TIMER3, &bcm2708_timer_irq);
1524 +
1525 + sched_clock_register(bcm2708_read_sched_clock, 32, STC_FREQ_HZ);
1526 +
1527 + timer0_clockevent.mult =
1528 + div_sc(STC_FREQ_HZ, NSEC_PER_SEC, timer0_clockevent.shift);
1529 + timer0_clockevent.max_delta_ns =
1530 + clockevent_delta2ns(0xffffffff, &timer0_clockevent);
1531 + timer0_clockevent.min_delta_ns =
1532 + clockevent_delta2ns(0xf, &timer0_clockevent);
1533 +
1534 + timer0_clockevent.cpumask = cpumask_of(0);
1535 + clockevents_register_device(&timer0_clockevent);
1536 +
1537 + register_current_timer_delay(&bcm2708_delay_timer);
1538 +}
1539 +
1540 +#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
1541 +#include <linux/leds.h>
1542 +
1543 +static struct gpio_led bcm2708_leds[] = {
1544 + [0] = {
1545 + .gpio = 16,
1546 + .name = "led0",
1547 + .default_trigger = "mmc0",
1548 + .active_low = 1,
1549 + },
1550 +};
1551 +
1552 +static struct gpio_led_platform_data bcm2708_led_pdata = {
1553 + .num_leds = ARRAY_SIZE(bcm2708_leds),
1554 + .leds = bcm2708_leds,
1555 +};
1556 +
1557 +static struct platform_device bcm2708_led_device = {
1558 + .name = "leds-gpio",
1559 + .id = -1,
1560 + .dev = {
1561 + .platform_data = &bcm2708_led_pdata,
1562 + },
1563 +};
1564 +
1565 +static void __init bcm2708_init_led(void)
1566 +{
1567 + bcm2708_leds[0].gpio = disk_led_gpio;
1568 + bcm2708_leds[0].active_low = disk_led_active_low;
1569 + platform_device_register(&bcm2708_led_device);
1570 +}
1571 +#else
1572 +static inline void bcm2708_init_led(void)
1573 +{
1574 +}
1575 +#endif
1576 +
1577 +void __init bcm2708_init_early(void)
1578 +{
1579 + /*
1580 + * Some devices allocate their coherent buffers from atomic
1581 + * context. Increase size of atomic coherent pool to make sure such
1582 + * the allocations won't fail.
1583 + */
1584 + init_dma_coherent_pool_size(SZ_4M);
1585 +}
1586 +
1587 +static void __init board_reserve(void)
1588 +{
1589 +#if defined(CONFIG_BCM_VC_CMA)
1590 + vc_cma_reserve();
1591 +#endif
1592 +}
1593 +
1594 +MACHINE_START(BCM2708, "BCM2708")
1595 + /* Maintainer: Broadcom Europe Ltd. */
1596 + .map_io = bcm2708_map_io,
1597 + .init_irq = bcm2708_init_irq,
1598 + .init_time = bcm2708_timer_init,
1599 + .init_machine = bcm2708_init,
1600 + .init_early = bcm2708_init_early,
1601 + .reserve = board_reserve,
1602 + .restart = bcm2708_restart,
1603 +MACHINE_END
1604 +
1605 +module_param(boardrev, uint, 0644);
1606 +module_param(serial, uint, 0644);
1607 +module_param(uart_clock, uint, 0644);
1608 +module_param(disk_led_gpio, uint, 0644);
1609 +module_param(disk_led_active_low, uint, 0644);
1610 +module_param(reboot_part, uint, 0644);
1611 diff --git a/arch/arm/mach-bcm2708/bcm2708.h b/arch/arm/mach-bcm2708/bcm2708.h
1612 new file mode 100644
1613 index 0000000..e339a93
1614 --- /dev/null
1615 +++ b/arch/arm/mach-bcm2708/bcm2708.h
1616 @@ -0,0 +1,49 @@
1617 +/*
1618 + * linux/arch/arm/mach-bcm2708/bcm2708.h
1619 + *
1620 + * BCM2708 machine support header
1621 + *
1622 + * Copyright (C) 2010 Broadcom
1623 + *
1624 + * This program is free software; you can redistribute it and/or modify
1625 + * it under the terms of the GNU General Public License as published by
1626 + * the Free Software Foundation; either version 2 of the License, or
1627 + * (at your option) any later version.
1628 + *
1629 + * This program is distributed in the hope that it will be useful,
1630 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1631 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1632 + * GNU General Public License for more details.
1633 + *
1634 + * You should have received a copy of the GNU General Public License
1635 + * along with this program; if not, write to the Free Software
1636 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
1637 + */
1638 +
1639 +#ifndef __BCM2708_BCM2708_H
1640 +#define __BCM2708_BCM2708_H
1641 +
1642 +#include <linux/amba/bus.h>
1643 +
1644 +extern void __init bcm2708_init(void);
1645 +extern void __init bcm2708_init_irq(void);
1646 +extern void __init bcm2708_map_io(void);
1647 +extern struct sys_timer bcm2708_timer;
1648 +extern unsigned int mmc_status(struct device *dev);
1649 +
1650 +#define AMBA_DEVICE(name, busid, base, plat) \
1651 +static struct amba_device name##_device = { \
1652 + .dev = { \
1653 + .coherent_dma_mask = ~0, \
1654 + .init_name = busid, \
1655 + .platform_data = plat, \
1656 + }, \
1657 + .res = { \
1658 + .start = base##_BASE, \
1659 + .end = (base##_BASE) + SZ_4K - 1,\
1660 + .flags = IORESOURCE_MEM, \
1661 + }, \
1662 + .irq = base##_IRQ, \
1663 +}
1664 +
1665 +#endif
1666 diff --git a/arch/arm/mach-bcm2708/clock.c b/arch/arm/mach-bcm2708/clock.c
1667 new file mode 100644
1668 index 0000000..4fc556e
1669 --- /dev/null
1670 +++ b/arch/arm/mach-bcm2708/clock.c
1671 @@ -0,0 +1,61 @@
1672 +/*
1673 + * linux/arch/arm/mach-bcm2708/clock.c
1674 + *
1675 + * Copyright (C) 2010 Broadcom
1676 + *
1677 + * This program is free software; you can redistribute it and/or modify
1678 + * it under the terms of the GNU General Public License as published by
1679 + * the Free Software Foundation; either version 2 of the License, or
1680 + * (at your option) any later version.
1681 + *
1682 + * This program is distributed in the hope that it will be useful,
1683 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1684 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1685 + * GNU General Public License for more details.
1686 + *
1687 + * You should have received a copy of the GNU General Public License
1688 + * along with this program; if not, write to the Free Software
1689 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
1690 + */
1691 +#include <linux/module.h>
1692 +#include <linux/kernel.h>
1693 +#include <linux/device.h>
1694 +#include <linux/list.h>
1695 +#include <linux/errno.h>
1696 +#include <linux/err.h>
1697 +#include <linux/string.h>
1698 +#include <linux/clk.h>
1699 +#include <linux/mutex.h>
1700 +
1701 +#include <asm/clkdev.h>
1702 +
1703 +#include "clock.h"
1704 +
1705 +int clk_enable(struct clk *clk)
1706 +{
1707 + return 0;
1708 +}
1709 +EXPORT_SYMBOL(clk_enable);
1710 +
1711 +void clk_disable(struct clk *clk)
1712 +{
1713 +}
1714 +EXPORT_SYMBOL(clk_disable);
1715 +
1716 +unsigned long clk_get_rate(struct clk *clk)
1717 +{
1718 + return clk->rate;
1719 +}
1720 +EXPORT_SYMBOL(clk_get_rate);
1721 +
1722 +long clk_round_rate(struct clk *clk, unsigned long rate)
1723 +{
1724 + return clk->rate;
1725 +}
1726 +EXPORT_SYMBOL(clk_round_rate);
1727 +
1728 +int clk_set_rate(struct clk *clk, unsigned long rate)
1729 +{
1730 + return -EIO;
1731 +}
1732 +EXPORT_SYMBOL(clk_set_rate);
1733 diff --git a/arch/arm/mach-bcm2708/clock.h b/arch/arm/mach-bcm2708/clock.h
1734 new file mode 100644
1735 index 0000000..5f9d725
1736 --- /dev/null
1737 +++ b/arch/arm/mach-bcm2708/clock.h
1738 @@ -0,0 +1,24 @@
1739 +/*
1740 + * linux/arch/arm/mach-bcm2708/clock.h
1741 + *
1742 + * Copyright (C) 2010 Broadcom
1743 + *
1744 + * This program is free software; you can redistribute it and/or modify
1745 + * it under the terms of the GNU General Public License as published by
1746 + * the Free Software Foundation; either version 2 of the License, or
1747 + * (at your option) any later version.
1748 + *
1749 + * This program is distributed in the hope that it will be useful,
1750 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1751 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1752 + * GNU General Public License for more details.
1753 + *
1754 + * You should have received a copy of the GNU General Public License
1755 + * along with this program; if not, write to the Free Software
1756 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
1757 + */
1758 +struct module;
1759 +
1760 +struct clk {
1761 + unsigned long rate;
1762 +};
1763 diff --git a/arch/arm/mach-bcm2708/dma.c b/arch/arm/mach-bcm2708/dma.c
1764 new file mode 100644
1765 index 0000000..51d147a
1766 --- /dev/null
1767 +++ b/arch/arm/mach-bcm2708/dma.c
1768 @@ -0,0 +1,399 @@
1769 +/*
1770 + * linux/arch/arm/mach-bcm2708/dma.c
1771 + *
1772 + * Copyright (C) 2010 Broadcom
1773 + *
1774 + * This program is free software; you can redistribute it and/or modify
1775 + * it under the terms of the GNU General Public License version 2 as
1776 + * published by the Free Software Foundation.
1777 + */
1778 +
1779 +#include <linux/slab.h>
1780 +#include <linux/device.h>
1781 +#include <linux/platform_device.h>
1782 +#include <linux/module.h>
1783 +#include <linux/scatterlist.h>
1784 +
1785 +#include <mach/dma.h>
1786 +#include <mach/irqs.h>
1787 +
1788 +/*****************************************************************************\
1789 + * *
1790 + * Configuration *
1791 + * *
1792 +\*****************************************************************************/
1793 +
1794 +#define CACHE_LINE_MASK 31
1795 +#define DRIVER_NAME BCM_DMAMAN_DRIVER_NAME
1796 +#define DEFAULT_DMACHAN_BITMAP 0x10 /* channel 4 only */
1797 +
1798 +/* valid only for channels 0 - 14, 15 has its own base address */
1799 +#define BCM2708_DMA_CHAN(n) ((n)<<8) /* base address */
1800 +#define BCM2708_DMA_CHANIO(dma_base, n) \
1801 + ((void __iomem *)((char *)(dma_base)+BCM2708_DMA_CHAN(n)))
1802 +
1803 +
1804 +/*****************************************************************************\
1805 + * *
1806 + * DMA Auxilliary Functions *
1807 + * *
1808 +\*****************************************************************************/
1809 +
1810 +/* A DMA buffer on an arbitrary boundary may separate a cache line into a
1811 + section inside the DMA buffer and another section outside it.
1812 + Even if we flush DMA buffers from the cache there is always the chance that
1813 + during a DMA someone will access the part of a cache line that is outside
1814 + the DMA buffer - which will then bring in unwelcome data.
1815 + Without being able to dictate our own buffer pools we must insist that
1816 + DMA buffers consist of a whole number of cache lines.
1817 +*/
1818 +
1819 +extern int
1820 +bcm_sg_suitable_for_dma(struct scatterlist *sg_ptr, int sg_len)
1821 +{
1822 + int i;
1823 +
1824 + for (i = 0; i < sg_len; i++) {
1825 + if (sg_ptr[i].offset & CACHE_LINE_MASK ||
1826 + sg_ptr[i].length & CACHE_LINE_MASK)
1827 + return 0;
1828 + }
1829 +
1830 + return 1;
1831 +}
1832 +EXPORT_SYMBOL_GPL(bcm_sg_suitable_for_dma);
1833 +
1834 +extern void
1835 +bcm_dma_start(void __iomem *dma_chan_base, dma_addr_t control_block)
1836 +{
1837 + dsb(); /* ARM data synchronization (push) operation */
1838 +
1839 + writel(control_block, dma_chan_base + BCM2708_DMA_ADDR);
1840 + writel(BCM2708_DMA_ACTIVE, dma_chan_base + BCM2708_DMA_CS);
1841 +}
1842 +
1843 +extern void bcm_dma_wait_idle(void __iomem *dma_chan_base)
1844 +{
1845 + dsb();
1846 +
1847 + /* ugly busy wait only option for now */
1848 + while (readl(dma_chan_base + BCM2708_DMA_CS) & BCM2708_DMA_ACTIVE)
1849 + cpu_relax();
1850 +}
1851 +
1852 +EXPORT_SYMBOL_GPL(bcm_dma_start);
1853 +
1854 +/* Complete an ongoing DMA (assuming its results are to be ignored)
1855 + Does nothing if there is no DMA in progress.
1856 + This routine waits for the current AXI transfer to complete before
1857 + terminating the current DMA. If the current transfer is hung on a DREQ used
1858 + by an uncooperative peripheral the AXI transfer may never complete. In this
1859 + case the routine times out and return a non-zero error code.
1860 + Use of this routine doesn't guarantee that the ongoing or aborted DMA
1861 + does not produce an interrupt.
1862 +*/
1863 +extern int
1864 +bcm_dma_abort(void __iomem *dma_chan_base)
1865 +{
1866 + unsigned long int cs;
1867 + int rc = 0;
1868 +
1869 + cs = readl(dma_chan_base + BCM2708_DMA_CS);
1870 +
1871 + if (BCM2708_DMA_ACTIVE & cs) {
1872 + long int timeout = 10000;
1873 +
1874 + /* write 0 to the active bit - pause the DMA */
1875 + writel(0, dma_chan_base + BCM2708_DMA_CS);
1876 +
1877 + /* wait for any current AXI transfer to complete */
1878 + while (0 != (cs & BCM2708_DMA_ISPAUSED) && --timeout >= 0)
1879 + cs = readl(dma_chan_base + BCM2708_DMA_CS);
1880 +
1881 + if (0 != (cs & BCM2708_DMA_ISPAUSED)) {
1882 + /* we'll un-pause when we set of our next DMA */
1883 + rc = -ETIMEDOUT;
1884 +
1885 + } else if (BCM2708_DMA_ACTIVE & cs) {
1886 + /* terminate the control block chain */
1887 + writel(0, dma_chan_base + BCM2708_DMA_NEXTCB);
1888 +
1889 + /* abort the whole DMA */
1890 + writel(BCM2708_DMA_ABORT | BCM2708_DMA_ACTIVE,
1891 + dma_chan_base + BCM2708_DMA_CS);
1892 + }
1893 + }
1894 +
1895 + return rc;
1896 +}
1897 +EXPORT_SYMBOL_GPL(bcm_dma_abort);
1898 +
1899 +
1900 +/***************************************************************************** \
1901 + * *
1902 + * DMA Manager Device Methods *
1903 + * *
1904 +\*****************************************************************************/
1905 +
1906 +struct vc_dmaman {
1907 + void __iomem *dma_base;
1908 + u32 chan_available; /* bitmap of available channels */
1909 + u32 has_feature[BCM_DMA_FEATURE_COUNT]; /* bitmap of feature presence */
1910 +};
1911 +
1912 +static void vc_dmaman_init(struct vc_dmaman *dmaman, void __iomem *dma_base,
1913 + u32 chans_available)
1914 +{
1915 + dmaman->dma_base = dma_base;
1916 + dmaman->chan_available = chans_available;
1917 + dmaman->has_feature[BCM_DMA_FEATURE_FAST_ORD] = 0x0c; /* chans 2 & 3 */
1918 + dmaman->has_feature[BCM_DMA_FEATURE_BULK_ORD] = 0x01; /* chan 0 */
1919 +}
1920 +
1921 +static int vc_dmaman_chan_alloc(struct vc_dmaman *dmaman,
1922 + unsigned preferred_feature_set)
1923 +{
1924 + u32 chans;
1925 + int feature;
1926 +
1927 + chans = dmaman->chan_available;
1928 + for (feature = 0; feature < BCM_DMA_FEATURE_COUNT; feature++)
1929 + /* select the subset of available channels with the desired
1930 + feature so long as some of the candidate channels have that
1931 + feature */
1932 + if ((preferred_feature_set & (1 << feature)) &&
1933 + (chans & dmaman->has_feature[feature]))
1934 + chans &= dmaman->has_feature[feature];
1935 +
1936 + if (chans) {
1937 + int chan = 0;
1938 + /* return the ordinal of the first channel in the bitmap */
1939 + while (chans != 0 && (chans & 1) == 0) {
1940 + chans >>= 1;
1941 + chan++;
1942 + }
1943 + /* claim the channel */
1944 + dmaman->chan_available &= ~(1 << chan);
1945 + return chan;
1946 + } else
1947 + return -ENOMEM;
1948 +}
1949 +
1950 +static int vc_dmaman_chan_free(struct vc_dmaman *dmaman, int chan)
1951 +{
1952 + if (chan < 0)
1953 + return -EINVAL;
1954 + else if ((1 << chan) & dmaman->chan_available)
1955 + return -EIDRM;
1956 + else {
1957 + dmaman->chan_available |= (1 << chan);
1958 + return 0;
1959 + }
1960 +}
1961 +
1962 +/*****************************************************************************\
1963 + * *
1964 + * DMA IRQs *
1965 + * *
1966 +\*****************************************************************************/
1967 +
1968 +static unsigned char bcm_dma_irqs[] = {
1969 + IRQ_DMA0,
1970 + IRQ_DMA1,
1971 + IRQ_DMA2,
1972 + IRQ_DMA3,
1973 + IRQ_DMA4,
1974 + IRQ_DMA5,
1975 + IRQ_DMA6,
1976 + IRQ_DMA7,
1977 + IRQ_DMA8,
1978 + IRQ_DMA9,
1979 + IRQ_DMA10,
1980 + IRQ_DMA11,
1981 + IRQ_DMA12
1982 +};
1983 +
1984 +
1985 +/***************************************************************************** \
1986 + * *
1987 + * DMA Manager Monitor *
1988 + * *
1989 +\*****************************************************************************/
1990 +
1991 +static struct device *dmaman_dev; /* we assume there's only one! */
1992 +
1993 +extern int bcm_dma_chan_alloc(unsigned preferred_feature_set,
1994 + void __iomem **out_dma_base, int *out_dma_irq)
1995 +{
1996 + if (!dmaman_dev)
1997 + return -ENODEV;
1998 + else {
1999 + struct vc_dmaman *dmaman = dev_get_drvdata(dmaman_dev);
2000 + int rc;
2001 +
2002 + device_lock(dmaman_dev);
2003 + rc = vc_dmaman_chan_alloc(dmaman, preferred_feature_set);
2004 + if (rc >= 0) {
2005 + *out_dma_base = BCM2708_DMA_CHANIO(dmaman->dma_base,
2006 + rc);
2007 + *out_dma_irq = bcm_dma_irqs[rc];
2008 + }
2009 + device_unlock(dmaman_dev);
2010 +
2011 + return rc;
2012 + }
2013 +}
2014 +EXPORT_SYMBOL_GPL(bcm_dma_chan_alloc);
2015 +
2016 +extern int bcm_dma_chan_free(int channel)
2017 +{
2018 + if (dmaman_dev) {
2019 + struct vc_dmaman *dmaman = dev_get_drvdata(dmaman_dev);
2020 + int rc;
2021 +
2022 + device_lock(dmaman_dev);
2023 + rc = vc_dmaman_chan_free(dmaman, channel);
2024 + device_unlock(dmaman_dev);
2025 +
2026 + return rc;
2027 + } else
2028 + return -ENODEV;
2029 +}
2030 +EXPORT_SYMBOL_GPL(bcm_dma_chan_free);
2031 +
2032 +static int dev_dmaman_register(const char *dev_name, struct device *dev)
2033 +{
2034 + int rc = dmaman_dev ? -EINVAL : 0;
2035 + dmaman_dev = dev;
2036 + return rc;
2037 +}
2038 +
2039 +static void dev_dmaman_deregister(const char *dev_name, struct device *dev)
2040 +{
2041 + dmaman_dev = NULL;
2042 +}
2043 +
2044 +/*****************************************************************************\
2045 + * *
2046 + * DMA Device *
2047 + * *
2048 +\*****************************************************************************/
2049 +
2050 +static int dmachans = -1; /* module parameter */
2051 +
2052 +static int bcm_dmaman_probe(struct platform_device *pdev)
2053 +{
2054 + int ret = 0;
2055 + struct vc_dmaman *dmaman;
2056 + struct resource *dma_res = NULL;
2057 + void __iomem *dma_base = NULL;
2058 + int have_dma_region = 0;
2059 +
2060 + dmaman = kzalloc(sizeof(*dmaman), GFP_KERNEL);
2061 + if (NULL == dmaman) {
2062 + printk(KERN_ERR DRIVER_NAME ": failed to allocate "
2063 + "DMA management memory\n");
2064 + ret = -ENOMEM;
2065 + } else {
2066 +
2067 + dma_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2068 + if (dma_res == NULL) {
2069 + printk(KERN_ERR DRIVER_NAME ": failed to obtain memory "
2070 + "resource\n");
2071 + ret = -ENODEV;
2072 + } else if (!request_mem_region(dma_res->start,
2073 + resource_size(dma_res),
2074 + DRIVER_NAME)) {
2075 + dev_err(&pdev->dev, "cannot obtain DMA region\n");
2076 + ret = -EBUSY;
2077 + } else {
2078 + have_dma_region = 1;
2079 + dma_base = ioremap(dma_res->start,
2080 + resource_size(dma_res));
2081 + if (!dma_base) {
2082 + dev_err(&pdev->dev, "cannot map DMA region\n");
2083 + ret = -ENOMEM;
2084 + } else {
2085 + /* use module parameter if one was provided */
2086 + if (dmachans > 0)
2087 + vc_dmaman_init(dmaman, dma_base,
2088 + dmachans);
2089 + else
2090 + vc_dmaman_init(dmaman, dma_base,
2091 + DEFAULT_DMACHAN_BITMAP);
2092 +
2093 + platform_set_drvdata(pdev, dmaman);
2094 + dev_dmaman_register(DRIVER_NAME, &pdev->dev);
2095 +
2096 + printk(KERN_INFO DRIVER_NAME ": DMA manager "
2097 + "at %p\n", dma_base);
2098 + }
2099 + }
2100 + }
2101 + if (ret != 0) {
2102 + if (dma_base)
2103 + iounmap(dma_base);
2104 + if (dma_res && have_dma_region)
2105 + release_mem_region(dma_res->start,
2106 + resource_size(dma_res));
2107 + if (dmaman)
2108 + kfree(dmaman);
2109 + }
2110 + return ret;
2111 +}
2112 +
2113 +static int bcm_dmaman_remove(struct platform_device *pdev)
2114 +{
2115 + struct vc_dmaman *dmaman = platform_get_drvdata(pdev);
2116 +
2117 + platform_set_drvdata(pdev, NULL);
2118 + dev_dmaman_deregister(DRIVER_NAME, &pdev->dev);
2119 + kfree(dmaman);
2120 +
2121 + return 0;
2122 +}
2123 +
2124 +static struct platform_driver bcm_dmaman_driver = {
2125 + .probe = bcm_dmaman_probe,
2126 + .remove = bcm_dmaman_remove,
2127 +
2128 + .driver = {
2129 + .name = DRIVER_NAME,
2130 + .owner = THIS_MODULE,
2131 + },
2132 +};
2133 +
2134 +/*****************************************************************************\
2135 + * *
2136 + * Driver init/exit *
2137 + * *
2138 +\*****************************************************************************/
2139 +
2140 +static int __init bcm_dmaman_drv_init(void)
2141 +{
2142 + int ret;
2143 +
2144 + ret = platform_driver_register(&bcm_dmaman_driver);
2145 + if (ret != 0) {
2146 + printk(KERN_ERR DRIVER_NAME ": failed to register "
2147 + "on platform\n");
2148 + }
2149 +
2150 + return ret;
2151 +}
2152 +
2153 +static void __exit bcm_dmaman_drv_exit(void)
2154 +{
2155 + platform_driver_unregister(&bcm_dmaman_driver);
2156 +}
2157 +
2158 +module_init(bcm_dmaman_drv_init);
2159 +module_exit(bcm_dmaman_drv_exit);
2160 +
2161 +module_param(dmachans, int, 0644);
2162 +
2163 +MODULE_AUTHOR("Gray Girling <grayg@broadcom.com>");
2164 +MODULE_DESCRIPTION("DMA channel manager driver");
2165 +MODULE_LICENSE("GPL");
2166 +
2167 +MODULE_PARM_DESC(dmachans, "Bitmap of DMA channels available to the ARM");
2168 diff --git a/arch/arm/mach-bcm2708/include/mach/arm_control.h b/arch/arm/mach-bcm2708/include/mach/arm_control.h
2169 new file mode 100644
2170 index 0000000..a82bb92
2171 --- /dev/null
2172 +++ b/arch/arm/mach-bcm2708/include/mach/arm_control.h
2173 @@ -0,0 +1,419 @@
2174 +/*
2175 + * linux/arch/arm/mach-bcm2708/arm_control.h
2176 + *
2177 + * Copyright (C) 2010 Broadcom
2178 + *
2179 + * This program is free software; you can redistribute it and/or modify
2180 + * it under the terms of the GNU General Public License as published by
2181 + * the Free Software Foundation; either version 2 of the License, or
2182 + * (at your option) any later version.
2183 + *
2184 + * This program is distributed in the hope that it will be useful,
2185 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2186 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2187 + * GNU General Public License for more details.
2188 + *
2189 + * You should have received a copy of the GNU General Public License
2190 + * along with this program; if not, write to the Free Software
2191 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
2192 + */
2193 +
2194 +#ifndef __BCM2708_ARM_CONTROL_H
2195 +#define __BCM2708_ARM_CONTROL_H
2196 +
2197 +/*
2198 + * Definitions and addresses for the ARM CONTROL logic
2199 + * This file is manually generated.
2200 + */
2201 +
2202 +#define ARM_BASE 0x7E00B000
2203 +
2204 +/* Basic configuration */
2205 +#define ARM_CONTROL0 HW_REGISTER_RW(ARM_BASE+0x000)
2206 +#define ARM_C0_SIZ128M 0x00000000
2207 +#define ARM_C0_SIZ256M 0x00000001
2208 +#define ARM_C0_SIZ512M 0x00000002
2209 +#define ARM_C0_SIZ1G 0x00000003
2210 +#define ARM_C0_BRESP0 0x00000000
2211 +#define ARM_C0_BRESP1 0x00000004
2212 +#define ARM_C0_BRESP2 0x00000008
2213 +#define ARM_C0_BOOTHI 0x00000010
2214 +#define ARM_C0_UNUSED05 0x00000020 /* free */
2215 +#define ARM_C0_FULLPERI 0x00000040
2216 +#define ARM_C0_UNUSED78 0x00000180 /* free */
2217 +#define ARM_C0_JTAGMASK 0x00000E00
2218 +#define ARM_C0_JTAGOFF 0x00000000
2219 +#define ARM_C0_JTAGBASH 0x00000800 /* Debug on GPIO off */
2220 +#define ARM_C0_JTAGGPIO 0x00000C00 /* Debug on GPIO on */
2221 +#define ARM_C0_APROTMSK 0x0000F000
2222 +#define ARM_C0_DBG0SYNC 0x00010000 /* VPU0 halt sync */
2223 +#define ARM_C0_DBG1SYNC 0x00020000 /* VPU1 halt sync */
2224 +#define ARM_C0_SWDBGREQ 0x00040000 /* HW debug request */
2225 +#define ARM_C0_PASSHALT 0x00080000 /* ARM halt passed to debugger */
2226 +#define ARM_C0_PRIO_PER 0x00F00000 /* per priority mask */
2227 +#define ARM_C0_PRIO_L2 0x0F000000
2228 +#define ARM_C0_PRIO_UC 0xF0000000
2229 +
2230 +#define ARM_C0_APROTPASS 0x0000A000 /* Translate 1:1 */
2231 +#define ARM_C0_APROTUSER 0x00000000 /* Only user mode */
2232 +#define ARM_C0_APROTSYST 0x0000F000 /* Only system mode */
2233 +
2234 +
2235 +#define ARM_CONTROL1 HW_REGISTER_RW(ARM_BASE+0x440)
2236 +#define ARM_C1_TIMER 0x00000001 /* re-route timer IRQ to VC */
2237 +#define ARM_C1_MAIL 0x00000002 /* re-route Mail IRQ to VC */
2238 +#define ARM_C1_BELL0 0x00000004 /* re-route Doorbell 0 to VC */
2239 +#define ARM_C1_BELL1 0x00000008 /* re-route Doorbell 1 to VC */
2240 +#define ARM_C1_PERSON 0x00000100 /* peripherals on */
2241 +#define ARM_C1_REQSTOP 0x00000200 /* ASYNC bridge request stop */
2242 +
2243 +#define ARM_STATUS HW_REGISTER_RW(ARM_BASE+0x444)
2244 +#define ARM_S_ACKSTOP 0x80000000 /* Bridge stopped */
2245 +#define ARM_S_READPEND 0x000003FF /* pending reads counter */
2246 +#define ARM_S_WRITPEND 0x000FFC00 /* pending writes counter */
2247 +
2248 +#define ARM_ERRHALT HW_REGISTER_RW(ARM_BASE+0x448)
2249 +#define ARM_EH_PERIBURST 0x00000001 /* Burst write seen on peri bus */
2250 +#define ARM_EH_ILLADDRS1 0x00000002 /* Address bits 25-27 error */
2251 +#define ARM_EH_ILLADDRS2 0x00000004 /* Address bits 31-28 error */
2252 +#define ARM_EH_VPU0HALT 0x00000008 /* VPU0 halted & in debug mode */
2253 +#define ARM_EH_VPU1HALT 0x00000010 /* VPU1 halted & in debug mode */
2254 +#define ARM_EH_ARMHALT 0x00000020 /* ARM in halted debug mode */
2255 +
2256 +#define ARM_ID_SECURE HW_REGISTER_RW(ARM_BASE+0x00C)
2257 +#define ARM_ID HW_REGISTER_RW(ARM_BASE+0x44C)
2258 +#define ARM_IDVAL 0x364D5241
2259 +
2260 +/* Translation memory */
2261 +#define ARM_TRANSLATE HW_REGISTER_RW(ARM_BASE+0x100)
2262 +/* 32 locations: 0x100.. 0x17F */
2263 +/* 32 spare means we CAN go to 64 pages.... */
2264 +
2265 +
2266 +/* Interrupts */
2267 +#define ARM_IRQ_PEND0 HW_REGISTER_RW(ARM_BASE+0x200) /* Top IRQ bits */
2268 +#define ARM_I0_TIMER 0x00000001 /* timer IRQ */
2269 +#define ARM_I0_MAIL 0x00000002 /* Mail IRQ */
2270 +#define ARM_I0_BELL0 0x00000004 /* Doorbell 0 */
2271 +#define ARM_I0_BELL1 0x00000008 /* Doorbell 1 */
2272 +#define ARM_I0_BANK1 0x00000100 /* Bank1 IRQ */
2273 +#define ARM_I0_BANK2 0x00000200 /* Bank2 IRQ */
2274 +
2275 +#define ARM_IRQ_PEND1 HW_REGISTER_RW(ARM_BASE+0x204) /* All bank1 IRQ bits */
2276 +/* todo: all I1_interrupt sources */
2277 +#define ARM_IRQ_PEND2 HW_REGISTER_RW(ARM_BASE+0x208) /* All bank2 IRQ bits */
2278 +/* todo: all I2_interrupt sources */
2279 +
2280 +#define ARM_IRQ_FAST HW_REGISTER_RW(ARM_BASE+0x20C) /* FIQ control */
2281 +#define ARM_IF_INDEX 0x0000007F /* FIQ select */
2282 +#define ARM_IF_ENABLE 0x00000080 /* FIQ enable */
2283 +#define ARM_IF_VCMASK 0x0000003F /* FIQ = (index from VC source) */
2284 +#define ARM_IF_TIMER 0x00000040 /* FIQ = ARM timer */
2285 +#define ARM_IF_MAIL 0x00000041 /* FIQ = ARM Mail */
2286 +#define ARM_IF_BELL0 0x00000042 /* FIQ = ARM Doorbell 0 */
2287 +#define ARM_IF_BELL1 0x00000043 /* FIQ = ARM Doorbell 1 */
2288 +#define ARM_IF_VP0HALT 0x00000044 /* FIQ = VPU0 Halt seen */
2289 +#define ARM_IF_VP1HALT 0x00000045 /* FIQ = VPU1 Halt seen */
2290 +#define ARM_IF_ILLEGAL 0x00000046 /* FIQ = Illegal access seen */
2291 +
2292 +#define ARM_IRQ_ENBL1 HW_REGISTER_RW(ARM_BASE+0x210) /* Bank1 enable bits */
2293 +#define ARM_IRQ_ENBL2 HW_REGISTER_RW(ARM_BASE+0x214) /* Bank2 enable bits */
2294 +#define ARM_IRQ_ENBL3 HW_REGISTER_RW(ARM_BASE+0x218) /* ARM irqs enable bits */
2295 +#define ARM_IRQ_DIBL1 HW_REGISTER_RW(ARM_BASE+0x21C) /* Bank1 disable bits */
2296 +#define ARM_IRQ_DIBL2 HW_REGISTER_RW(ARM_BASE+0x220) /* Bank2 disable bits */
2297 +#define ARM_IRQ_DIBL3 HW_REGISTER_RW(ARM_BASE+0x224) /* ARM irqs disable bits */
2298 +#define ARM_IE_TIMER 0x00000001 /* Timer IRQ */
2299 +#define ARM_IE_MAIL 0x00000002 /* Mail IRQ */
2300 +#define ARM_IE_BELL0 0x00000004 /* Doorbell 0 */
2301 +#define ARM_IE_BELL1 0x00000008 /* Doorbell 1 */
2302 +#define ARM_IE_VP0HALT 0x00000010 /* VPU0 Halt */
2303 +#define ARM_IE_VP1HALT 0x00000020 /* VPU1 Halt */
2304 +#define ARM_IE_ILLEGAL 0x00000040 /* Illegal access seen */
2305 +
2306 +/* Timer */
2307 +/* For reg. fields see sp804 spec. */
2308 +#define ARM_T_LOAD HW_REGISTER_RW(ARM_BASE+0x400)
2309 +#define ARM_T_VALUE HW_REGISTER_RW(ARM_BASE+0x404)
2310 +#define ARM_T_CONTROL HW_REGISTER_RW(ARM_BASE+0x408)
2311 +#define ARM_T_IRQCNTL HW_REGISTER_RW(ARM_BASE+0x40C)
2312 +#define ARM_T_RAWIRQ HW_REGISTER_RW(ARM_BASE+0x410)
2313 +#define ARM_T_MSKIRQ HW_REGISTER_RW(ARM_BASE+0x414)
2314 +#define ARM_T_RELOAD HW_REGISTER_RW(ARM_BASE+0x418)
2315 +#define ARM_T_PREDIV HW_REGISTER_RW(ARM_BASE+0x41c)
2316 +#define ARM_T_FREECNT HW_REGISTER_RW(ARM_BASE+0x420)
2317 +
2318 +#define TIMER_CTRL_ONESHOT (1 << 0)
2319 +#define TIMER_CTRL_32BIT (1 << 1)
2320 +#define TIMER_CTRL_DIV1 (0 << 2)
2321 +#define TIMER_CTRL_DIV16 (1 << 2)
2322 +#define TIMER_CTRL_DIV256 (2 << 2)
2323 +#define TIMER_CTRL_IE (1 << 5)
2324 +#define TIMER_CTRL_PERIODIC (1 << 6)
2325 +#define TIMER_CTRL_ENABLE (1 << 7)
2326 +#define TIMER_CTRL_DBGHALT (1 << 8)
2327 +#define TIMER_CTRL_ENAFREE (1 << 9)
2328 +#define TIMER_CTRL_FREEDIV_SHIFT 16)
2329 +#define TIMER_CTRL_FREEDIV_MASK 0xff
2330 +
2331 +/* Semaphores, Doorbells, Mailboxes */
2332 +#define ARM_SBM_OWN0 (ARM_BASE+0x800)
2333 +#define ARM_SBM_OWN1 (ARM_BASE+0x900)
2334 +#define ARM_SBM_OWN2 (ARM_BASE+0xA00)
2335 +#define ARM_SBM_OWN3 (ARM_BASE+0xB00)
2336 +
2337 +/* MAILBOXES
2338 + * Register flags are common across all
2339 + * owner registers. See end of this section
2340 + *
2341 + * Semaphores, Doorbells, Mailboxes Owner 0
2342 + *
2343 + */
2344 +
2345 +#define ARM_0_SEMS HW_REGISTER_RW(ARM_SBM_OWN0+0x00)
2346 +#define ARM_0_SEM0 HW_REGISTER_RW(ARM_SBM_OWN0+0x00)
2347 +#define ARM_0_SEM1 HW_REGISTER_RW(ARM_SBM_OWN0+0x04)
2348 +#define ARM_0_SEM2 HW_REGISTER_RW(ARM_SBM_OWN0+0x08)
2349 +#define ARM_0_SEM3 HW_REGISTER_RW(ARM_SBM_OWN0+0x0C)
2350 +#define ARM_0_SEM4 HW_REGISTER_RW(ARM_SBM_OWN0+0x10)
2351 +#define ARM_0_SEM5 HW_REGISTER_RW(ARM_SBM_OWN0+0x14)
2352 +#define ARM_0_SEM6 HW_REGISTER_RW(ARM_SBM_OWN0+0x18)
2353 +#define ARM_0_SEM7 HW_REGISTER_RW(ARM_SBM_OWN0+0x1C)
2354 +#define ARM_0_BELL0 HW_REGISTER_RW(ARM_SBM_OWN0+0x40)
2355 +#define ARM_0_BELL1 HW_REGISTER_RW(ARM_SBM_OWN0+0x44)
2356 +#define ARM_0_BELL2 HW_REGISTER_RW(ARM_SBM_OWN0+0x48)
2357 +#define ARM_0_BELL3 HW_REGISTER_RW(ARM_SBM_OWN0+0x4C)
2358 +/* MAILBOX 0 access in Owner 0 area */
2359 +/* Some addresses should ONLY be used by owner 0 */
2360 +#define ARM_0_MAIL0_WRT HW_REGISTER_RW(ARM_SBM_OWN0+0x80) /* .. 0x8C (4 locations) */
2361 +#define ARM_0_MAIL0_RD HW_REGISTER_RW(ARM_SBM_OWN0+0x80) /* .. 0x8C (4 locations) Normal read */
2362 +#define ARM_0_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN0+0x90) /* none-pop read */
2363 +#define ARM_0_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN0+0x94) /* Sender read (only LS 2 bits) */
2364 +#define ARM_0_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN0+0x98) /* Status read */
2365 +#define ARM_0_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN0+0x9C) /* Config read/write */
2366 +/* MAILBOX 1 access in Owner 0 area */
2367 +/* Owner 0 should only WRITE to this mailbox */
2368 +#define ARM_0_MAIL1_WRT HW_REGISTER_RW(ARM_SBM_OWN0+0xA0) /* .. 0xAC (4 locations) */
2369 +/*#define ARM_0_MAIL1_RD HW_REGISTER_RW(ARM_SBM_OWN0+0xA0) */ /* DO NOT USE THIS !!!!! */
2370 +/*#define ARM_0_MAIL1_POL HW_REGISTER_RW(ARM_SBM_OWN0+0xB0) */ /* DO NOT USE THIS !!!!! */
2371 +/*#define ARM_0_MAIL1_SND HW_REGISTER_RW(ARM_SBM_OWN0+0xB4) */ /* DO NOT USE THIS !!!!! */
2372 +#define ARM_0_MAIL1_STA HW_REGISTER_RW(ARM_SBM_OWN0+0xB8) /* Status read */
2373 +/*#define ARM_0_MAIL1_CNF HW_REGISTER_RW(ARM_SBM_OWN0+0xBC) */ /* DO NOT USE THIS !!!!! */
2374 +/* General SEM, BELL, MAIL config/status */
2375 +#define ARM_0_SEMCLRDBG HW_REGISTER_RW(ARM_SBM_OWN0+0xE0) /* semaphore clear/debug register */
2376 +#define ARM_0_BELLCLRDBG HW_REGISTER_RW(ARM_SBM_OWN0+0xE4) /* Doorbells clear/debug register */
2377 +#define ARM_0_ALL_IRQS HW_REGISTER_RW(ARM_SBM_OWN0+0xF8) /* ALL interrupts */
2378 +#define ARM_0_MY_IRQS HW_REGISTER_RW(ARM_SBM_OWN0+0xFC) /* IRQS pending for owner 0 */
2379 +
2380 +/* Semaphores, Doorbells, Mailboxes Owner 1 */
2381 +#define ARM_1_SEMS HW_REGISTER_RW(ARM_SBM_OWN1+0x00)
2382 +#define ARM_1_SEM0 HW_REGISTER_RW(ARM_SBM_OWN1+0x00)
2383 +#define ARM_1_SEM1 HW_REGISTER_RW(ARM_SBM_OWN1+0x04)
2384 +#define ARM_1_SEM2 HW_REGISTER_RW(ARM_SBM_OWN1+0x08)
2385 +#define ARM_1_SEM3 HW_REGISTER_RW(ARM_SBM_OWN1+0x0C)
2386 +#define ARM_1_SEM4 HW_REGISTER_RW(ARM_SBM_OWN1+0x10)
2387 +#define ARM_1_SEM5 HW_REGISTER_RW(ARM_SBM_OWN1+0x14)
2388 +#define ARM_1_SEM6 HW_REGISTER_RW(ARM_SBM_OWN1+0x18)
2389 +#define ARM_1_SEM7 HW_REGISTER_RW(ARM_SBM_OWN1+0x1C)
2390 +#define ARM_1_BELL0 HW_REGISTER_RW(ARM_SBM_OWN1+0x40)
2391 +#define ARM_1_BELL1 HW_REGISTER_RW(ARM_SBM_OWN1+0x44)
2392 +#define ARM_1_BELL2 HW_REGISTER_RW(ARM_SBM_OWN1+0x48)
2393 +#define ARM_1_BELL3 HW_REGISTER_RW(ARM_SBM_OWN1+0x4C)
2394 +/* MAILBOX 0 access in Owner 0 area */
2395 +/* Owner 1 should only WRITE to this mailbox */
2396 +#define ARM_1_MAIL0_WRT HW_REGISTER_RW(ARM_SBM_OWN1+0x80) /* .. 0x8C (4 locations) */
2397 +/*#define ARM_1_MAIL0_RD HW_REGISTER_RW(ARM_SBM_OWN1+0x80) */ /* DO NOT USE THIS !!!!! */
2398 +/*#define ARM_1_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN1+0x90) */ /* DO NOT USE THIS !!!!! */
2399 +/*#define ARM_1_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN1+0x94) */ /* DO NOT USE THIS !!!!! */
2400 +#define ARM_1_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN1+0x98) /* Status read */
2401 +/*#define ARM_1_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN1+0x9C) */ /* DO NOT USE THIS !!!!! */
2402 +/* MAILBOX 1 access in Owner 0 area */
2403 +#define ARM_1_MAIL1_WRT HW_REGISTER_RW(ARM_SBM_OWN1+0xA0) /* .. 0xAC (4 locations) */
2404 +#define ARM_1_MAIL1_RD HW_REGISTER_RW(ARM_SBM_OWN1+0xA0) /* .. 0xAC (4 locations) Normal read */
2405 +#define ARM_1_MAIL1_POL HW_REGISTER_RW(ARM_SBM_OWN1+0xB0) /* none-pop read */
2406 +#define ARM_1_MAIL1_SND HW_REGISTER_RW(ARM_SBM_OWN1+0xB4) /* Sender read (only LS 2 bits) */
2407 +#define ARM_1_MAIL1_STA HW_REGISTER_RW(ARM_SBM_OWN1+0xB8) /* Status read */
2408 +#define ARM_1_MAIL1_CNF HW_REGISTER_RW(ARM_SBM_OWN1+0xBC)
2409 +/* General SEM, BELL, MAIL config/status */
2410 +#define ARM_1_SEMCLRDBG HW_REGISTER_RW(ARM_SBM_OWN1+0xE0) /* semaphore clear/debug register */
2411 +#define ARM_1_BELLCLRDBG HW_REGISTER_RW(ARM_SBM_OWN1+0xE4) /* Doorbells clear/debug register */
2412 +#define ARM_1_MY_IRQS HW_REGISTER_RW(ARM_SBM_OWN1+0xFC) /* IRQS pending for owner 1 */
2413 +#define ARM_1_ALL_IRQS HW_REGISTER_RW(ARM_SBM_OWN1+0xF8) /* ALL interrupts */
2414 +
2415 +/* Semaphores, Doorbells, Mailboxes Owner 2 */
2416 +#define ARM_2_SEMS HW_REGISTER_RW(ARM_SBM_OWN2+0x00)
2417 +#define ARM_2_SEM0 HW_REGISTER_RW(ARM_SBM_OWN2+0x00)
2418 +#define ARM_2_SEM1 HW_REGISTER_RW(ARM_SBM_OWN2+0x04)
2419 +#define ARM_2_SEM2 HW_REGISTER_RW(ARM_SBM_OWN2+0x08)
2420 +#define ARM_2_SEM3 HW_REGISTER_RW(ARM_SBM_OWN2+0x0C)
2421 +#define ARM_2_SEM4 HW_REGISTER_RW(ARM_SBM_OWN2+0x10)
2422 +#define ARM_2_SEM5 HW_REGISTER_RW(ARM_SBM_OWN2+0x14)
2423 +#define ARM_2_SEM6 HW_REGISTER_RW(ARM_SBM_OWN2+0x18)
2424 +#define ARM_2_SEM7 HW_REGISTER_RW(ARM_SBM_OWN2+0x1C)
2425 +#define ARM_2_BELL0 HW_REGISTER_RW(ARM_SBM_OWN2+0x40)
2426 +#define ARM_2_BELL1 HW_REGISTER_RW(ARM_SBM_OWN2+0x44)
2427 +#define ARM_2_BELL2 HW_REGISTER_RW(ARM_SBM_OWN2+0x48)
2428 +#define ARM_2_BELL3 HW_REGISTER_RW(ARM_SBM_OWN2+0x4C)
2429 +/* MAILBOX 0 access in Owner 2 area */
2430 +/* Owner 2 should only WRITE to this mailbox */
2431 +#define ARM_2_MAIL0_WRT HW_REGISTER_RW(ARM_SBM_OWN2+0x80) /* .. 0x8C (4 locations) */
2432 +/*#define ARM_2_MAIL0_RD HW_REGISTER_RW(ARM_SBM_OWN2+0x80) */ /* DO NOT USE THIS !!!!! */
2433 +/*#define ARM_2_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN2+0x90) */ /* DO NOT USE THIS !!!!! */
2434 +/*#define ARM_2_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN2+0x94) */ /* DO NOT USE THIS !!!!! */
2435 +#define ARM_2_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN2+0x98) /* Status read */
2436 +/*#define ARM_2_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN2+0x9C) */ /* DO NOT USE THIS !!!!! */
2437 +/* MAILBOX 1 access in Owner 2 area */
2438 +/* Owner 2 should only WRITE to this mailbox */
2439 +#define ARM_2_MAIL1_WRT HW_REGISTER_RW(ARM_SBM_OWN2+0xA0) /* .. 0xAC (4 locations) */
2440 +/*#define ARM_2_MAIL1_RD HW_REGISTER_RW(ARM_SBM_OWN2+0xA0) */ /* DO NOT USE THIS !!!!! */
2441 +/*#define ARM_2_MAIL1_POL HW_REGISTER_RW(ARM_SBM_OWN2+0xB0) */ /* DO NOT USE THIS !!!!! */
2442 +/*#define ARM_2_MAIL1_SND HW_REGISTER_RW(ARM_SBM_OWN2+0xB4) */ /* DO NOT USE THIS !!!!! */
2443 +#define ARM_2_MAIL1_STA HW_REGISTER_RW(ARM_SBM_OWN2+0xB8) /* Status read */
2444 +/*#define ARM_2_MAIL1_CNF HW_REGISTER_RW(ARM_SBM_OWN2+0xBC) */ /* DO NOT USE THIS !!!!! */
2445 +/* General SEM, BELL, MAIL config/status */
2446 +#define ARM_2_SEMCLRDBG HW_REGISTER_RW(ARM_SBM_OWN2+0xE0) /* semaphore clear/debug register */
2447 +#define ARM_2_BELLCLRDBG HW_REGISTER_RW(ARM_SBM_OWN2+0xE4) /* Doorbells clear/debug register */
2448 +#define ARM_2_MY_IRQS HW_REGISTER_RW(ARM_SBM_OWN2+0xFC) /* IRQS pending for owner 2 */
2449 +#define ARM_2_ALL_IRQS HW_REGISTER_RW(ARM_SBM_OWN2+0xF8) /* ALL interrupts */
2450 +
2451 +/* Semaphores, Doorbells, Mailboxes Owner 3 */
2452 +#define ARM_3_SEMS HW_REGISTER_RW(ARM_SBM_OWN3+0x00)
2453 +#define ARM_3_SEM0 HW_REGISTER_RW(ARM_SBM_OWN3+0x00)
2454 +#define ARM_3_SEM1 HW_REGISTER_RW(ARM_SBM_OWN3+0x04)
2455 +#define ARM_3_SEM2 HW_REGISTER_RW(ARM_SBM_OWN3+0x08)
2456 +#define ARM_3_SEM3 HW_REGISTER_RW(ARM_SBM_OWN3+0x0C)
2457 +#define ARM_3_SEM4 HW_REGISTER_RW(ARM_SBM_OWN3+0x10)
2458 +#define ARM_3_SEM5 HW_REGISTER_RW(ARM_SBM_OWN3+0x14)
2459 +#define ARM_3_SEM6 HW_REGISTER_RW(ARM_SBM_OWN3+0x18)
2460 +#define ARM_3_SEM7 HW_REGISTER_RW(ARM_SBM_OWN3+0x1C)
2461 +#define ARM_3_BELL0 HW_REGISTER_RW(ARM_SBM_OWN3+0x40)
2462 +#define ARM_3_BELL1 HW_REGISTER_RW(ARM_SBM_OWN3+0x44)
2463 +#define ARM_3_BELL2 HW_REGISTER_RW(ARM_SBM_OWN3+0x48)
2464 +#define ARM_3_BELL3 HW_REGISTER_RW(ARM_SBM_OWN3+0x4C)
2465 +/* MAILBOX 0 access in Owner 3 area */
2466 +/* Owner 3 should only WRITE to this mailbox */
2467 +#define ARM_3_MAIL0_WRT HW_REGISTER_RW(ARM_SBM_OWN3+0x80) /* .. 0x8C (4 locations) */
2468 +/*#define ARM_3_MAIL0_RD HW_REGISTER_RW(ARM_SBM_OWN3+0x80) */ /* DO NOT USE THIS !!!!! */
2469 +/*#define ARM_3_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN3+0x90) */ /* DO NOT USE THIS !!!!! */
2470 +/*#define ARM_3_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN3+0x94) */ /* DO NOT USE THIS !!!!! */
2471 +#define ARM_3_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN3+0x98) /* Status read */
2472 +/*#define ARM_3_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN3+0x9C) */ /* DO NOT USE THIS !!!!! */
2473 +/* MAILBOX 1 access in Owner 3 area */
2474 +/* Owner 3 should only WRITE to this mailbox */
2475 +#define ARM_3_MAIL1_WRT HW_REGISTER_RW(ARM_SBM_OWN3+0xA0) /* .. 0xAC (4 locations) */
2476 +/*#define ARM_3_MAIL1_RD HW_REGISTER_RW(ARM_SBM_OWN3+0xA0) */ /* DO NOT USE THIS !!!!! */
2477 +/*#define ARM_3_MAIL1_POL HW_REGISTER_RW(ARM_SBM_OWN3+0xB0) */ /* DO NOT USE THIS !!!!! */
2478 +/*#define ARM_3_MAIL1_SND HW_REGISTER_RW(ARM_SBM_OWN3+0xB4) */ /* DO NOT USE THIS !!!!! */
2479 +#define ARM_3_MAIL1_STA HW_REGISTER_RW(ARM_SBM_OWN3+0xB8) /* Status read */
2480 +/*#define ARM_3_MAIL1_CNF HW_REGISTER_RW(ARM_SBM_OWN3+0xBC) */ /* DO NOT USE THIS !!!!! */
2481 +/* General SEM, BELL, MAIL config/status */
2482 +#define ARM_3_SEMCLRDBG HW_REGISTER_RW(ARM_SBM_OWN3+0xE0) /* semaphore clear/debug register */
2483 +#define ARM_3_BELLCLRDBG HW_REGISTER_RW(ARM_SBM_OWN3+0xE4) /* Doorbells clear/debug register */
2484 +#define ARM_3_MY_IRQS HW_REGISTER_RW(ARM_SBM_OWN3+0xFC) /* IRQS pending for owner 3 */
2485 +#define ARM_3_ALL_IRQS HW_REGISTER_RW(ARM_SBM_OWN3+0xF8) /* ALL interrupts */
2486 +
2487 +
2488 +
2489 +/* Mailbox flags. Valid for all owners */
2490 +
2491 +/* Mailbox status register (...0x98) */
2492 +#define ARM_MS_FULL 0x80000000
2493 +#define ARM_MS_EMPTY 0x40000000
2494 +#define ARM_MS_LEVEL 0x400000FF /* Max. value depdnds on mailbox depth parameter */
2495 +
2496 +/* MAILBOX config/status register (...0x9C) */
2497 +/* ANY write to this register clears the error bits! */
2498 +#define ARM_MC_IHAVEDATAIRQEN 0x00000001 /* mailbox irq enable: has data */
2499 +#define ARM_MC_IHAVESPACEIRQEN 0x00000002 /* mailbox irq enable: has space */
2500 +#define ARM_MC_OPPISEMPTYIRQEN 0x00000004 /* mailbox irq enable: Opp. is empty */
2501 +#define ARM_MC_MAIL_CLEAR 0x00000008 /* mailbox clear write 1, then 0 */
2502 +#define ARM_MC_IHAVEDATAIRQPEND 0x00000010 /* mailbox irq pending: has space */
2503 +#define ARM_MC_IHAVESPACEIRQPEND 0x00000020 /* mailbox irq pending: Opp. is empty */
2504 +#define ARM_MC_OPPISEMPTYIRQPEND 0x00000040 /* mailbox irq pending */
2505 +/* Bit 7 is unused */
2506 +#define ARM_MC_ERRNOOWN 0x00000100 /* error : none owner read from mailbox */
2507 +#define ARM_MC_ERROVERFLW 0x00000200 /* error : write to fill mailbox */
2508 +#define ARM_MC_ERRUNDRFLW 0x00000400 /* error : read from empty mailbox */
2509 +
2510 +/* Semaphore clear/debug register (...0xE0) */
2511 +#define ARM_SD_OWN0 0x00000003 /* Owner of sem 0 */
2512 +#define ARM_SD_OWN1 0x0000000C /* Owner of sem 1 */
2513 +#define ARM_SD_OWN2 0x00000030 /* Owner of sem 2 */
2514 +#define ARM_SD_OWN3 0x000000C0 /* Owner of sem 3 */
2515 +#define ARM_SD_OWN4 0x00000300 /* Owner of sem 4 */
2516 +#define ARM_SD_OWN5 0x00000C00 /* Owner of sem 5 */
2517 +#define ARM_SD_OWN6 0x00003000 /* Owner of sem 6 */
2518 +#define ARM_SD_OWN7 0x0000C000 /* Owner of sem 7 */
2519 +#define ARM_SD_SEM0 0x00010000 /* Status of sem 0 */
2520 +#define ARM_SD_SEM1 0x00020000 /* Status of sem 1 */
2521 +#define ARM_SD_SEM2 0x00040000 /* Status of sem 2 */
2522 +#define ARM_SD_SEM3 0x00080000 /* Status of sem 3 */
2523 +#define ARM_SD_SEM4 0x00100000 /* Status of sem 4 */
2524 +#define ARM_SD_SEM5 0x00200000 /* Status of sem 5 */
2525 +#define ARM_SD_SEM6 0x00400000 /* Status of sem 6 */
2526 +#define ARM_SD_SEM7 0x00800000 /* Status of sem 7 */
2527 +
2528 +/* Doorbells clear/debug register (...0xE4) */
2529 +#define ARM_BD_OWN0 0x00000003 /* Owner of doorbell 0 */
2530 +#define ARM_BD_OWN1 0x0000000C /* Owner of doorbell 1 */
2531 +#define ARM_BD_OWN2 0x00000030 /* Owner of doorbell 2 */
2532 +#define ARM_BD_OWN3 0x000000C0 /* Owner of doorbell 3 */
2533 +#define ARM_BD_BELL0 0x00000100 /* Status of doorbell 0 */
2534 +#define ARM_BD_BELL1 0x00000200 /* Status of doorbell 1 */
2535 +#define ARM_BD_BELL2 0x00000400 /* Status of doorbell 2 */
2536 +#define ARM_BD_BELL3 0x00000800 /* Status of doorbell 3 */
2537 +
2538 +/* MY IRQS register (...0xF8) */
2539 +#define ARM_MYIRQ_BELL 0x00000001 /* This owner has a doorbell IRQ */
2540 +#define ARM_MYIRQ_MAIL 0x00000002 /* This owner has a mailbox IRQ */
2541 +
2542 +/* ALL IRQS register (...0xF8) */
2543 +#define ARM_AIS_BELL0 0x00000001 /* Doorbell 0 IRQ pending */
2544 +#define ARM_AIS_BELL1 0x00000002 /* Doorbell 1 IRQ pending */
2545 +#define ARM_AIS_BELL2 0x00000004 /* Doorbell 2 IRQ pending */
2546 +#define ARM_AIS_BELL3 0x00000008 /* Doorbell 3 IRQ pending */
2547 +#define ARM_AIS0_HAVEDATA 0x00000010 /* MAIL 0 has data IRQ pending */
2548 +#define ARM_AIS0_HAVESPAC 0x00000020 /* MAIL 0 has space IRQ pending */
2549 +#define ARM_AIS0_OPPEMPTY 0x00000040 /* MAIL 0 opposite is empty IRQ */
2550 +#define ARM_AIS1_HAVEDATA 0x00000080 /* MAIL 1 has data IRQ pending */
2551 +#define ARM_AIS1_HAVESPAC 0x00000100 /* MAIL 1 has space IRQ pending */
2552 +#define ARM_AIS1_OPPEMPTY 0x00000200 /* MAIL 1 opposite is empty IRQ */
2553 +/* Note that bell-0, bell-1 and MAIL0 IRQ go only to the ARM */
2554 +/* Whilst that bell-2, bell-3 and MAIL1 IRQ go only to the VC */
2555 +/* */
2556 +/* ARM JTAG BASH */
2557 +/* */
2558 +#define AJB_BASE 0x7e2000c0
2559 +
2560 +#define AJBCONF HW_REGISTER_RW(AJB_BASE+0x00)
2561 +#define AJB_BITS0 0x000000
2562 +#define AJB_BITS4 0x000004
2563 +#define AJB_BITS8 0x000008
2564 +#define AJB_BITS12 0x00000C
2565 +#define AJB_BITS16 0x000010
2566 +#define AJB_BITS20 0x000014
2567 +#define AJB_BITS24 0x000018
2568 +#define AJB_BITS28 0x00001C
2569 +#define AJB_BITS32 0x000020
2570 +#define AJB_BITS34 0x000022
2571 +#define AJB_OUT_MS 0x000040
2572 +#define AJB_OUT_LS 0x000000
2573 +#define AJB_INV_CLK 0x000080
2574 +#define AJB_D0_RISE 0x000100
2575 +#define AJB_D0_FALL 0x000000
2576 +#define AJB_D1_RISE 0x000200
2577 +#define AJB_D1_FALL 0x000000
2578 +#define AJB_IN_RISE 0x000400
2579 +#define AJB_IN_FALL 0x000000
2580 +#define AJB_ENABLE 0x000800
2581 +#define AJB_HOLD0 0x000000
2582 +#define AJB_HOLD1 0x001000
2583 +#define AJB_HOLD2 0x002000
2584 +#define AJB_HOLD3 0x003000
2585 +#define AJB_RESETN 0x004000
2586 +#define AJB_CLKSHFT 16
2587 +#define AJB_BUSY 0x80000000
2588 +#define AJBTMS HW_REGISTER_RW(AJB_BASE+0x04)
2589 +#define AJBTDI HW_REGISTER_RW(AJB_BASE+0x08)
2590 +#define AJBTDO HW_REGISTER_RW(AJB_BASE+0x0c)
2591 +
2592 +#endif
2593 diff --git a/arch/arm/mach-bcm2708/include/mach/arm_power.h b/arch/arm/mach-bcm2708/include/mach/arm_power.h
2594 new file mode 100644
2595 index 0000000..d3bf245
2596 --- /dev/null
2597 +++ b/arch/arm/mach-bcm2708/include/mach/arm_power.h
2598 @@ -0,0 +1,62 @@
2599 +/*
2600 + * linux/arch/arm/mach-bcm2708/include/mach/arm_power.h
2601 + *
2602 + * Copyright (C) 2010 Broadcom
2603 + *
2604 + * This program is free software; you can redistribute it and/or modify
2605 + * it under the terms of the GNU General Public License as published by
2606 + * the Free Software Foundation; either version 2 of the License, or
2607 + * (at your option) any later version.
2608 + *
2609 + * This program is distributed in the hope that it will be useful,
2610 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2611 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2612 + * GNU General Public License for more details.
2613 + *
2614 + * You should have received a copy of the GNU General Public License
2615 + * along with this program; if not, write to the Free Software
2616 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
2617 + */
2618 +
2619 +#ifndef _ARM_POWER_H
2620 +#define _ARM_POWER_H
2621 +
2622 +/* Use meaningful names on each side */
2623 +#ifdef __VIDEOCORE__
2624 +#define PREFIX(x) ARM_##x
2625 +#else
2626 +#define PREFIX(x) BCM_##x
2627 +#endif
2628 +
2629 +enum {
2630 + PREFIX(POWER_SDCARD_BIT),
2631 + PREFIX(POWER_UART_BIT),
2632 + PREFIX(POWER_MINIUART_BIT),
2633 + PREFIX(POWER_USB_BIT),
2634 + PREFIX(POWER_I2C0_BIT),
2635 + PREFIX(POWER_I2C1_BIT),
2636 + PREFIX(POWER_I2C2_BIT),
2637 + PREFIX(POWER_SPI_BIT),
2638 + PREFIX(POWER_CCP2TX_BIT),
2639 + PREFIX(POWER_DSI_BIT),
2640 +
2641 + PREFIX(POWER_MAX)
2642 +};
2643 +
2644 +enum {
2645 + PREFIX(POWER_SDCARD) = (1 << PREFIX(POWER_SDCARD_BIT)),
2646 + PREFIX(POWER_UART) = (1 << PREFIX(POWER_UART_BIT)),
2647 + PREFIX(POWER_MINIUART) = (1 << PREFIX(POWER_MINIUART_BIT)),
2648 + PREFIX(POWER_USB) = (1 << PREFIX(POWER_USB_BIT)),
2649 + PREFIX(POWER_I2C0) = (1 << PREFIX(POWER_I2C0_BIT)),
2650 + PREFIX(POWER_I2C1_MASK) = (1 << PREFIX(POWER_I2C1_BIT)),
2651 + PREFIX(POWER_I2C2_MASK) = (1 << PREFIX(POWER_I2C2_BIT)),
2652 + PREFIX(POWER_SPI_MASK) = (1 << PREFIX(POWER_SPI_BIT)),
2653 + PREFIX(POWER_CCP2TX_MASK) = (1 << PREFIX(POWER_CCP2TX_BIT)),
2654 + PREFIX(POWER_DSI) = (1 << PREFIX(POWER_DSI_BIT)),
2655 +
2656 + PREFIX(POWER_MASK) = (1 << PREFIX(POWER_MAX)) - 1,
2657 + PREFIX(POWER_NONE) = 0
2658 +};
2659 +
2660 +#endif
2661 diff --git a/arch/arm/mach-bcm2708/include/mach/clkdev.h b/arch/arm/mach-bcm2708/include/mach/clkdev.h
2662 new file mode 100644
2663 index 0000000..04b37a8
2664 --- /dev/null
2665 +++ b/arch/arm/mach-bcm2708/include/mach/clkdev.h
2666 @@ -0,0 +1,7 @@
2667 +#ifndef __ASM_MACH_CLKDEV_H
2668 +#define __ASM_MACH_CLKDEV_H
2669 +
2670 +#define __clk_get(clk) ({ 1; })
2671 +#define __clk_put(clk) do { } while (0)
2672 +
2673 +#endif
2674 diff --git a/arch/arm/mach-bcm2708/include/mach/debug-macro.S b/arch/arm/mach-bcm2708/include/mach/debug-macro.S
2675 new file mode 100644
2676 index 0000000..b24304a
2677 --- /dev/null
2678 +++ b/arch/arm/mach-bcm2708/include/mach/debug-macro.S
2679 @@ -0,0 +1,22 @@
2680 +/* arch/arm/mach-bcm2708/include/mach/debug-macro.S
2681 + *
2682 + * Debugging macro include header
2683 + *
2684 + * Copyright (C) 2010 Broadcom
2685 + * Copyright (C) 1994-1999 Russell King
2686 + * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
2687 + *
2688 + * This program is free software; you can redistribute it and/or modify
2689 + * it under the terms of the GNU General Public License version 2 as
2690 + * published by the Free Software Foundation.
2691 + *
2692 +*/
2693 +
2694 +#include <mach/platform.h>
2695 +
2696 + .macro addruart, rp, rv, tmp
2697 + ldr \rp, =UART0_BASE
2698 + ldr \rv, =IO_ADDRESS(UART0_BASE)
2699 + .endm
2700 +
2701 +#include <debug/pl01x.S>
2702 diff --git a/arch/arm/mach-bcm2708/include/mach/dma.h b/arch/arm/mach-bcm2708/include/mach/dma.h
2703 new file mode 100644
2704 index 0000000..f2568d4
2705 --- /dev/null
2706 +++ b/arch/arm/mach-bcm2708/include/mach/dma.h
2707 @@ -0,0 +1,88 @@
2708 +/*
2709 + * linux/arch/arm/mach-bcm2708/include/mach/dma.h
2710 + *
2711 + * Copyright (C) 2010 Broadcom
2712 + *
2713 + * This program is free software; you can redistribute it and/or modify
2714 + * it under the terms of the GNU General Public License version 2 as
2715 + * published by the Free Software Foundation.
2716 + */
2717 +
2718 +
2719 +#ifndef _MACH_BCM2708_DMA_H
2720 +#define _MACH_BCM2708_DMA_H
2721 +
2722 +#define BCM_DMAMAN_DRIVER_NAME "bcm2708_dma"
2723 +
2724 +/* DMA CS Control and Status bits */
2725 +#define BCM2708_DMA_ACTIVE (1 << 0)
2726 +#define BCM2708_DMA_INT (1 << 2)
2727 +#define BCM2708_DMA_ISPAUSED (1 << 4) /* Pause requested or not active */
2728 +#define BCM2708_DMA_ISHELD (1 << 5) /* Is held by DREQ flow control */
2729 +#define BCM2708_DMA_ERR (1 << 8)
2730 +#define BCM2708_DMA_ABORT (1 << 30) /* stop current CB, go to next, WO */
2731 +#define BCM2708_DMA_RESET (1 << 31) /* WO, self clearing */
2732 +
2733 +/* DMA control block "info" field bits */
2734 +#define BCM2708_DMA_INT_EN (1 << 0)
2735 +#define BCM2708_DMA_TDMODE (1 << 1)
2736 +#define BCM2708_DMA_WAIT_RESP (1 << 3)
2737 +#define BCM2708_DMA_D_INC (1 << 4)
2738 +#define BCM2708_DMA_D_WIDTH (1 << 5)
2739 +#define BCM2708_DMA_D_DREQ (1 << 6)
2740 +#define BCM2708_DMA_S_INC (1 << 8)
2741 +#define BCM2708_DMA_S_WIDTH (1 << 9)
2742 +#define BCM2708_DMA_S_DREQ (1 << 10)
2743 +
2744 +#define BCM2708_DMA_BURST(x) (((x)&0xf) << 12)
2745 +#define BCM2708_DMA_PER_MAP(x) ((x) << 16)
2746 +#define BCM2708_DMA_WAITS(x) (((x)&0x1f) << 21)
2747 +
2748 +#define BCM2708_DMA_DREQ_EMMC 11
2749 +#define BCM2708_DMA_DREQ_SDHOST 13
2750 +
2751 +#define BCM2708_DMA_CS 0x00 /* Control and Status */
2752 +#define BCM2708_DMA_ADDR 0x04
2753 +/* the current control block appears in the following registers - read only */
2754 +#define BCM2708_DMA_INFO 0x08
2755 +#define BCM2708_DMA_SOURCE_AD 0x0c
2756 +#define BCM2708_DMA_DEST_AD 0x10
2757 +#define BCM2708_DMA_NEXTCB 0x1C
2758 +#define BCM2708_DMA_DEBUG 0x20
2759 +
2760 +#define BCM2708_DMA4_CS (BCM2708_DMA_CHAN(4)+BCM2708_DMA_CS)
2761 +#define BCM2708_DMA4_ADDR (BCM2708_DMA_CHAN(4)+BCM2708_DMA_ADDR)
2762 +
2763 +#define BCM2708_DMA_TDMODE_LEN(w, h) ((h) << 16 | (w))
2764 +
2765 +struct bcm2708_dma_cb {
2766 + unsigned long info;
2767 + unsigned long src;
2768 + unsigned long dst;
2769 + unsigned long length;
2770 + unsigned long stride;
2771 + unsigned long next;
2772 + unsigned long pad[2];
2773 +};
2774 +
2775 +extern int bcm_sg_suitable_for_dma(struct scatterlist *sg_ptr, int sg_len);
2776 +extern void bcm_dma_start(void __iomem *dma_chan_base,
2777 + dma_addr_t control_block);
2778 +extern void bcm_dma_wait_idle(void __iomem *dma_chan_base);
2779 +extern int /*rc*/ bcm_dma_abort(void __iomem *dma_chan_base);
2780 +
2781 +/* When listing features we can ask for when allocating DMA channels give
2782 + those with higher priority smaller ordinal numbers */
2783 +#define BCM_DMA_FEATURE_FAST_ORD 0
2784 +#define BCM_DMA_FEATURE_BULK_ORD 1
2785 +#define BCM_DMA_FEATURE_FAST (1<<BCM_DMA_FEATURE_FAST_ORD)
2786 +#define BCM_DMA_FEATURE_BULK (1<<BCM_DMA_FEATURE_BULK_ORD)
2787 +#define BCM_DMA_FEATURE_COUNT 2
2788 +
2789 +/* return channel no or -ve error */
2790 +extern int bcm_dma_chan_alloc(unsigned preferred_feature_set,
2791 + void __iomem **out_dma_base, int *out_dma_irq);
2792 +extern int bcm_dma_chan_free(int channel);
2793 +
2794 +
2795 +#endif /* _MACH_BCM2708_DMA_H */
2796 diff --git a/arch/arm/mach-bcm2708/include/mach/entry-macro.S b/arch/arm/mach-bcm2708/include/mach/entry-macro.S
2797 new file mode 100644
2798 index 0000000..79b62d9
2799 --- /dev/null
2800 +++ b/arch/arm/mach-bcm2708/include/mach/entry-macro.S
2801 @@ -0,0 +1,69 @@
2802 +/*
2803 + * arch/arm/mach-bcm2708/include/mach/entry-macro.S
2804 + *
2805 + * Low-level IRQ helper macros for BCM2708 platforms
2806 + *
2807 + * Copyright (C) 2010 Broadcom
2808 + *
2809 + * This program is free software; you can redistribute it and/or modify
2810 + * it under the terms of the GNU General Public License as published by
2811 + * the Free Software Foundation; either version 2 of the License, or
2812 + * (at your option) any later version.
2813 + *
2814 + * This program is distributed in the hope that it will be useful,
2815 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2816 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2817 + * GNU General Public License for more details.
2818 + *
2819 + * You should have received a copy of the GNU General Public License
2820 + * along with this program; if not, write to the Free Software
2821 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
2822 + */
2823 +#include <mach/hardware.h>
2824 +
2825 + .macro disable_fiq
2826 + .endm
2827 +
2828 + .macro get_irqnr_preamble, base, tmp
2829 + ldr \base, =IO_ADDRESS(ARMCTRL_IC_BASE)
2830 + .endm
2831 +
2832 + .macro arch_ret_to_user, tmp1, tmp2
2833 + .endm
2834 +
2835 + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
2836 + /* get masked status */
2837 + ldr \irqstat, [\base, #(ARM_IRQ_PEND0 - ARMCTRL_IC_BASE)]
2838 + mov \irqnr, #(ARM_IRQ0_BASE + 31)
2839 + and \tmp, \irqstat, #0x300 @ save bits 8 and 9
2840 + /* clear bits 8 and 9, and test */
2841 + bics \irqstat, \irqstat, #0x300
2842 + bne 1010f
2843 +
2844 + tst \tmp, #0x100
2845 + ldrne \irqstat, [\base, #(ARM_IRQ_PEND1 - ARMCTRL_IC_BASE)]
2846 + movne \irqnr, #(ARM_IRQ1_BASE + 31)
2847 + @ Mask out the interrupts also present in PEND0 - see SW-5809
2848 + bicne \irqstat, #((1<<7) | (1<<9) | (1<<10))
2849 + bicne \irqstat, #((1<<18) | (1<<19))
2850 + bne 1010f
2851 +
2852 + tst \tmp, #0x200
2853 + ldrne \irqstat, [\base, #(ARM_IRQ_PEND2 - ARMCTRL_IC_BASE)]
2854 + movne \irqnr, #(ARM_IRQ2_BASE + 31)
2855 + @ Mask out the interrupts also present in PEND0 - see SW-5809
2856 + bicne \irqstat, #((1<<21) | (1<<22) | (1<<23) | (1<<24) | (1<<25))
2857 + bicne \irqstat, #((1<<30))
2858 + beq 1020f
2859 +
2860 +1010:
2861 + @ For non-zero x, LSB(x) = 31 - CLZ(x^(x-1))
2862 + @ N.B. CLZ is an ARM5 instruction.
2863 + sub \tmp, \irqstat, #1
2864 + eor \irqstat, \irqstat, \tmp
2865 + clz \tmp, \irqstat
2866 + sub \irqnr, \tmp
2867 +
2868 +1020: @ EQ will be set if no irqs pending
2869 +
2870 + .endm
2871 diff --git a/arch/arm/mach-bcm2708/include/mach/frc.h b/arch/arm/mach-bcm2708/include/mach/frc.h
2872 new file mode 100644
2873 index 0000000..dd51e07
2874 --- /dev/null
2875 +++ b/arch/arm/mach-bcm2708/include/mach/frc.h
2876 @@ -0,0 +1,38 @@
2877 +/*
2878 + * arch/arm/mach-bcm2708/include/mach/timex.h
2879 + *
2880 + * BCM2708 free running counter (timer)
2881 + *
2882 + * Copyright (C) 2010 Broadcom
2883 + *
2884 + * This program is free software; you can redistribute it and/or modify
2885 + * it under the terms of the GNU General Public License as published by
2886 + * the Free Software Foundation; either version 2 of the License, or
2887 + * (at your option) any later version.
2888 + *
2889 + * This program is distributed in the hope that it will be useful,
2890 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2891 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2892 + * GNU General Public License for more details.
2893 + *
2894 + * You should have received a copy of the GNU General Public License
2895 + * along with this program; if not, write to the Free Software
2896 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
2897 + */
2898 +
2899 +#ifndef _MACH_FRC_H
2900 +#define _MACH_FRC_H
2901 +
2902 +#define FRC_TICK_RATE (1000000)
2903 +
2904 +/*! Free running counter incrementing at the CLOCK_TICK_RATE
2905 + (slightly faster than frc_clock_ticks63()
2906 + */
2907 +extern unsigned long frc_clock_ticks32(void);
2908 +
2909 +/*! Free running counter incrementing at the CLOCK_TICK_RATE
2910 + * Note - top bit should be ignored (see cnt32_to_63)
2911 + */
2912 +extern unsigned long long frc_clock_ticks63(void);
2913 +
2914 +#endif
2915 diff --git a/arch/arm/mach-bcm2708/include/mach/hardware.h b/arch/arm/mach-bcm2708/include/mach/hardware.h
2916 new file mode 100644
2917 index 0000000..c2954e8
2918 --- /dev/null
2919 +++ b/arch/arm/mach-bcm2708/include/mach/hardware.h
2920 @@ -0,0 +1,28 @@
2921 +/*
2922 + * arch/arm/mach-bcm2708/include/mach/hardware.h
2923 + *
2924 + * This file contains the hardware definitions of the BCM2708 devices.
2925 + *
2926 + * Copyright (C) 2010 Broadcom
2927 + *
2928 + * This program is free software; you can redistribute it and/or modify
2929 + * it under the terms of the GNU General Public License as published by
2930 + * the Free Software Foundation; either version 2 of the License, or
2931 + * (at your option) any later version.
2932 + *
2933 + * This program is distributed in the hope that it will be useful,
2934 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2935 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2936 + * GNU General Public License for more details.
2937 + *
2938 + * You should have received a copy of the GNU General Public License
2939 + * along with this program; if not, write to the Free Software
2940 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
2941 + */
2942 +#ifndef __ASM_ARCH_HARDWARE_H
2943 +#define __ASM_ARCH_HARDWARE_H
2944 +
2945 +#include <asm/sizes.h>
2946 +#include <mach/platform.h>
2947 +
2948 +#endif
2949 diff --git a/arch/arm/mach-bcm2708/include/mach/io.h b/arch/arm/mach-bcm2708/include/mach/io.h
2950 new file mode 100644
2951 index 0000000..e6eb84d
2952 --- /dev/null
2953 +++ b/arch/arm/mach-bcm2708/include/mach/io.h
2954 @@ -0,0 +1,27 @@
2955 +/*
2956 + * arch/arm/mach-bcm2708/include/mach/io.h
2957 + *
2958 + * Copyright (C) 2003 ARM Limited
2959 + *
2960 + * This program is free software; you can redistribute it and/or modify
2961 + * it under the terms of the GNU General Public License as published by
2962 + * the Free Software Foundation; either version 2 of the License, or
2963 + * (at your option) any later version.
2964 + *
2965 + * This program is distributed in the hope that it will be useful,
2966 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2967 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2968 + * GNU General Public License for more details.
2969 + *
2970 + * You should have received a copy of the GNU General Public License
2971 + * along with this program; if not, write to the Free Software
2972 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
2973 + */
2974 +#ifndef __ASM_ARM_ARCH_IO_H
2975 +#define __ASM_ARM_ARCH_IO_H
2976 +
2977 +#define IO_SPACE_LIMIT 0xffffffff
2978 +
2979 +#define __io(a) __typesafe_io(a)
2980 +
2981 +#endif
2982 diff --git a/arch/arm/mach-bcm2708/include/mach/irqs.h b/arch/arm/mach-bcm2708/include/mach/irqs.h
2983 new file mode 100644
2984 index 0000000..3a88a1a
2985 --- /dev/null
2986 +++ b/arch/arm/mach-bcm2708/include/mach/irqs.h
2987 @@ -0,0 +1,196 @@
2988 +/*
2989 + * arch/arm/mach-bcm2708/include/mach/irqs.h
2990 + *
2991 + * Copyright (C) 2010 Broadcom
2992 + * Copyright (C) 2003 ARM Limited
2993 + * Copyright (C) 2000 Deep Blue Solutions Ltd.
2994 + *
2995 + * This program is free software; you can redistribute it and/or modify
2996 + * it under the terms of the GNU General Public License as published by
2997 + * the Free Software Foundation; either version 2 of the License, or
2998 + * (at your option) any later version.
2999 + *
3000 + * This program is distributed in the hope that it will be useful,
3001 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
3002 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3003 + * GNU General Public License for more details.
3004 + *
3005 + * You should have received a copy of the GNU General Public License
3006 + * along with this program; if not, write to the Free Software
3007 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
3008 + */
3009 +
3010 +#ifndef _BCM2708_IRQS_H_
3011 +#define _BCM2708_IRQS_H_
3012 +
3013 +#include <mach/platform.h>
3014 +
3015 +/*
3016 + * IRQ interrupts definitions are the same as the INT definitions
3017 + * held within platform.h
3018 + */
3019 +#define IRQ_ARMCTRL_START 0
3020 +#define IRQ_TIMER0 (IRQ_ARMCTRL_START + INTERRUPT_TIMER0)
3021 +#define IRQ_TIMER1 (IRQ_ARMCTRL_START + INTERRUPT_TIMER1)
3022 +#define IRQ_TIMER2 (IRQ_ARMCTRL_START + INTERRUPT_TIMER2)
3023 +#define IRQ_TIMER3 (IRQ_ARMCTRL_START + INTERRUPT_TIMER3)
3024 +#define IRQ_CODEC0 (IRQ_ARMCTRL_START + INTERRUPT_CODEC0)
3025 +#define IRQ_CODEC1 (IRQ_ARMCTRL_START + INTERRUPT_CODEC1)
3026 +#define IRQ_CODEC2 (IRQ_ARMCTRL_START + INTERRUPT_CODEC2)
3027 +#define IRQ_JPEG (IRQ_ARMCTRL_START + INTERRUPT_JPEG)
3028 +#define IRQ_ISP (IRQ_ARMCTRL_START + INTERRUPT_ISP)
3029 +#define IRQ_USB (IRQ_ARMCTRL_START + INTERRUPT_USB)
3030 +#define IRQ_3D (IRQ_ARMCTRL_START + INTERRUPT_3D)
3031 +#define IRQ_TRANSPOSER (IRQ_ARMCTRL_START + INTERRUPT_TRANSPOSER)
3032 +#define IRQ_MULTICORESYNC0 (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC0)
3033 +#define IRQ_MULTICORESYNC1 (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC1)
3034 +#define IRQ_MULTICORESYNC2 (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC2)
3035 +#define IRQ_MULTICORESYNC3 (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC3)
3036 +#define IRQ_DMA0 (IRQ_ARMCTRL_START + INTERRUPT_DMA0)
3037 +#define IRQ_DMA1 (IRQ_ARMCTRL_START + INTERRUPT_DMA1)
3038 +#define IRQ_DMA2 (IRQ_ARMCTRL_START + INTERRUPT_DMA2)
3039 +#define IRQ_DMA3 (IRQ_ARMCTRL_START + INTERRUPT_DMA3)
3040 +#define IRQ_DMA4 (IRQ_ARMCTRL_START + INTERRUPT_DMA4)
3041 +#define IRQ_DMA5 (IRQ_ARMCTRL_START + INTERRUPT_DMA5)
3042 +#define IRQ_DMA6 (IRQ_ARMCTRL_START + INTERRUPT_DMA6)
3043 +#define IRQ_DMA7 (IRQ_ARMCTRL_START + INTERRUPT_DMA7)
3044 +#define IRQ_DMA8 (IRQ_ARMCTRL_START + INTERRUPT_DMA8)
3045 +#define IRQ_DMA9 (IRQ_ARMCTRL_START + INTERRUPT_DMA9)
3046 +#define IRQ_DMA10 (IRQ_ARMCTRL_START + INTERRUPT_DMA10)
3047 +#define IRQ_DMA11 (IRQ_ARMCTRL_START + INTERRUPT_DMA11)
3048 +#define IRQ_DMA12 (IRQ_ARMCTRL_START + INTERRUPT_DMA12)
3049 +#define IRQ_AUX (IRQ_ARMCTRL_START + INTERRUPT_AUX)
3050 +#define IRQ_ARM (IRQ_ARMCTRL_START + INTERRUPT_ARM)
3051 +#define IRQ_VPUDMA (IRQ_ARMCTRL_START + INTERRUPT_VPUDMA)
3052 +#define IRQ_HOSTPORT (IRQ_ARMCTRL_START + INTERRUPT_HOSTPORT)
3053 +#define IRQ_VIDEOSCALER (IRQ_ARMCTRL_START + INTERRUPT_VIDEOSCALER)
3054 +#define IRQ_CCP2TX (IRQ_ARMCTRL_START + INTERRUPT_CCP2TX)
3055 +#define IRQ_SDC (IRQ_ARMCTRL_START + INTERRUPT_SDC)
3056 +#define IRQ_DSI0 (IRQ_ARMCTRL_START + INTERRUPT_DSI0)
3057 +#define IRQ_AVE (IRQ_ARMCTRL_START + INTERRUPT_AVE)
3058 +#define IRQ_CAM0 (IRQ_ARMCTRL_START + INTERRUPT_CAM0)
3059 +#define IRQ_CAM1 (IRQ_ARMCTRL_START + INTERRUPT_CAM1)
3060 +#define IRQ_HDMI0 (IRQ_ARMCTRL_START + INTERRUPT_HDMI0)
3061 +#define IRQ_HDMI1 (IRQ_ARMCTRL_START + INTERRUPT_HDMI1)
3062 +#define IRQ_PIXELVALVE1 (IRQ_ARMCTRL_START + INTERRUPT_PIXELVALVE1)
3063 +#define IRQ_I2CSPISLV (IRQ_ARMCTRL_START + INTERRUPT_I2CSPISLV)
3064 +#define IRQ_DSI1 (IRQ_ARMCTRL_START + INTERRUPT_DSI1)
3065 +#define IRQ_PWA0 (IRQ_ARMCTRL_START + INTERRUPT_PWA0)
3066 +#define IRQ_PWA1 (IRQ_ARMCTRL_START + INTERRUPT_PWA1)
3067 +#define IRQ_CPR (IRQ_ARMCTRL_START + INTERRUPT_CPR)
3068 +#define IRQ_SMI (IRQ_ARMCTRL_START + INTERRUPT_SMI)
3069 +#define IRQ_GPIO0 (IRQ_ARMCTRL_START + INTERRUPT_GPIO0)
3070 +#define IRQ_GPIO1 (IRQ_ARMCTRL_START + INTERRUPT_GPIO1)
3071 +#define IRQ_GPIO2 (IRQ_ARMCTRL_START + INTERRUPT_GPIO2)
3072 +#define IRQ_GPIO3 (IRQ_ARMCTRL_START + INTERRUPT_GPIO3)
3073 +#define IRQ_I2C (IRQ_ARMCTRL_START + INTERRUPT_I2C)
3074 +#define IRQ_SPI (IRQ_ARMCTRL_START + INTERRUPT_SPI)
3075 +#define IRQ_I2SPCM (IRQ_ARMCTRL_START + INTERRUPT_I2SPCM)
3076 +#define IRQ_SDIO (IRQ_ARMCTRL_START + INTERRUPT_SDIO)
3077 +#define IRQ_UART (IRQ_ARMCTRL_START + INTERRUPT_UART)
3078 +#define IRQ_SLIMBUS (IRQ_ARMCTRL_START + INTERRUPT_SLIMBUS)
3079 +#define IRQ_VEC (IRQ_ARMCTRL_START + INTERRUPT_VEC)
3080 +#define IRQ_CPG (IRQ_ARMCTRL_START + INTERRUPT_CPG)
3081 +#define IRQ_RNG (IRQ_ARMCTRL_START + INTERRUPT_RNG)
3082 +#define IRQ_ARASANSDIO (IRQ_ARMCTRL_START + INTERRUPT_ARASANSDIO)
3083 +#define IRQ_AVSPMON (IRQ_ARMCTRL_START + INTERRUPT_AVSPMON)
3084 +
3085 +#define IRQ_ARM_TIMER (IRQ_ARMCTRL_START + INTERRUPT_ARM_TIMER)
3086 +#define IRQ_ARM_MAILBOX (IRQ_ARMCTRL_START + INTERRUPT_ARM_MAILBOX)
3087 +#define IRQ_ARM_DOORBELL_0 (IRQ_ARMCTRL_START + INTERRUPT_ARM_DOORBELL_0)
3088 +#define IRQ_ARM_DOORBELL_1 (IRQ_ARMCTRL_START + INTERRUPT_ARM_DOORBELL_1)
3089 +#define IRQ_VPU0_HALTED (IRQ_ARMCTRL_START + INTERRUPT_VPU0_HALTED)
3090 +#define IRQ_VPU1_HALTED (IRQ_ARMCTRL_START + INTERRUPT_VPU1_HALTED)
3091 +#define IRQ_ILLEGAL_TYPE0 (IRQ_ARMCTRL_START + INTERRUPT_ILLEGAL_TYPE0)
3092 +#define IRQ_ILLEGAL_TYPE1 (IRQ_ARMCTRL_START + INTERRUPT_ILLEGAL_TYPE1)
3093 +#define IRQ_PENDING1 (IRQ_ARMCTRL_START + INTERRUPT_PENDING1)
3094 +#define IRQ_PENDING2 (IRQ_ARMCTRL_START + INTERRUPT_PENDING2)
3095 +
3096 +/*
3097 + * FIQ interrupts definitions are the same as the INT definitions.
3098 + */
3099 +#define FIQ_TIMER0 INT_TIMER0
3100 +#define FIQ_TIMER1 INT_TIMER1
3101 +#define FIQ_TIMER2 INT_TIMER2
3102 +#define FIQ_TIMER3 INT_TIMER3
3103 +#define FIQ_CODEC0 INT_CODEC0
3104 +#define FIQ_CODEC1 INT_CODEC1
3105 +#define FIQ_CODEC2 INT_CODEC2
3106 +#define FIQ_JPEG INT_JPEG
3107 +#define FIQ_ISP INT_ISP
3108 +#define FIQ_USB INT_USB
3109 +#define FIQ_3D INT_3D
3110 +#define FIQ_TRANSPOSER INT_TRANSPOSER
3111 +#define FIQ_MULTICORESYNC0 INT_MULTICORESYNC0
3112 +#define FIQ_MULTICORESYNC1 INT_MULTICORESYNC1
3113 +#define FIQ_MULTICORESYNC2 INT_MULTICORESYNC2
3114 +#define FIQ_MULTICORESYNC3 INT_MULTICORESYNC3
3115 +#define FIQ_DMA0 INT_DMA0
3116 +#define FIQ_DMA1 INT_DMA1
3117 +#define FIQ_DMA2 INT_DMA2
3118 +#define FIQ_DMA3 INT_DMA3
3119 +#define FIQ_DMA4 INT_DMA4
3120 +#define FIQ_DMA5 INT_DMA5
3121 +#define FIQ_DMA6 INT_DMA6
3122 +#define FIQ_DMA7 INT_DMA7
3123 +#define FIQ_DMA8 INT_DMA8
3124 +#define FIQ_DMA9 INT_DMA9
3125 +#define FIQ_DMA10 INT_DMA10
3126 +#define FIQ_DMA11 INT_DMA11
3127 +#define FIQ_DMA12 INT_DMA12
3128 +#define FIQ_AUX INT_AUX
3129 +#define FIQ_ARM INT_ARM
3130 +#define FIQ_VPUDMA INT_VPUDMA
3131 +#define FIQ_HOSTPORT INT_HOSTPORT
3132 +#define FIQ_VIDEOSCALER INT_VIDEOSCALER
3133 +#define FIQ_CCP2TX INT_CCP2TX
3134 +#define FIQ_SDC INT_SDC
3135 +#define FIQ_DSI0 INT_DSI0
3136 +#define FIQ_AVE INT_AVE
3137 +#define FIQ_CAM0 INT_CAM0
3138 +#define FIQ_CAM1 INT_CAM1
3139 +#define FIQ_HDMI0 INT_HDMI0
3140 +#define FIQ_HDMI1 INT_HDMI1
3141 +#define FIQ_PIXELVALVE1 INT_PIXELVALVE1
3142 +#define FIQ_I2CSPISLV INT_I2CSPISLV
3143 +#define FIQ_DSI1 INT_DSI1
3144 +#define FIQ_PWA0 INT_PWA0
3145 +#define FIQ_PWA1 INT_PWA1
3146 +#define FIQ_CPR INT_CPR
3147 +#define FIQ_SMI INT_SMI
3148 +#define FIQ_GPIO0 INT_GPIO0
3149 +#define FIQ_GPIO1 INT_GPIO1
3150 +#define FIQ_GPIO2 INT_GPIO2
3151 +#define FIQ_GPIO3 INT_GPIO3
3152 +#define FIQ_I2C INT_I2C
3153 +#define FIQ_SPI INT_SPI
3154 +#define FIQ_I2SPCM INT_I2SPCM
3155 +#define FIQ_SDIO INT_SDIO
3156 +#define FIQ_UART INT_UART
3157 +#define FIQ_SLIMBUS INT_SLIMBUS
3158 +#define FIQ_VEC INT_VEC
3159 +#define FIQ_CPG INT_CPG
3160 +#define FIQ_RNG INT_RNG
3161 +#define FIQ_ARASANSDIO INT_ARASANSDIO
3162 +#define FIQ_AVSPMON INT_AVSPMON
3163 +
3164 +#define FIQ_ARM_TIMER INT_ARM_TIMER
3165 +#define FIQ_ARM_MAILBOX INT_ARM_MAILBOX
3166 +#define FIQ_ARM_DOORBELL_0 INT_ARM_DOORBELL_0
3167 +#define FIQ_ARM_DOORBELL_1 INT_ARM_DOORBELL_1
3168 +#define FIQ_VPU0_HALTED INT_VPU0_HALTED
3169 +#define FIQ_VPU1_HALTED INT_VPU1_HALTED
3170 +#define FIQ_ILLEGAL_TYPE0 INT_ILLEGAL_TYPE0
3171 +#define FIQ_ILLEGAL_TYPE1 INT_ILLEGAL_TYPE1
3172 +#define FIQ_PENDING1 INT_PENDING1
3173 +#define FIQ_PENDING2 INT_PENDING2
3174 +
3175 +#define HARD_IRQS (64 + 21)
3176 +#define GPIO_IRQ_START (HARD_IRQS)
3177 +#define GPIO_IRQS (32*5)
3178 +#define SPARE_ALLOC_IRQS 64
3179 +#define BCM2708_ALLOC_IRQS (HARD_IRQS+FIQ_IRQS+GPIO_IRQS+SPARE_ALLOC_IRQS)
3180 +#define FREE_IRQS 128
3181 +#define NR_IRQS (BCM2708_ALLOC_IRQS+FREE_IRQS)
3182 +
3183 +#endif /* _BCM2708_IRQS_H_ */
3184 diff --git a/arch/arm/mach-bcm2708/include/mach/memory.h b/arch/arm/mach-bcm2708/include/mach/memory.h
3185 new file mode 100644
3186 index 0000000..7548a52
3187 --- /dev/null
3188 +++ b/arch/arm/mach-bcm2708/include/mach/memory.h
3189 @@ -0,0 +1,57 @@
3190 +/*
3191 + * arch/arm/mach-bcm2708/include/mach/memory.h
3192 + *
3193 + * Copyright (C) 2010 Broadcom
3194 + *
3195 + * This program is free software; you can redistribute it and/or modify
3196 + * it under the terms of the GNU General Public License as published by
3197 + * the Free Software Foundation; either version 2 of the License, or
3198 + * (at your option) any later version.
3199 + *
3200 + * This program is distributed in the hope that it will be useful,
3201 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
3202 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3203 + * GNU General Public License for more details.
3204 + *
3205 + * You should have received a copy of the GNU General Public License
3206 + * along with this program; if not, write to the Free Software
3207 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
3208 + */
3209 +#ifndef __ASM_ARCH_MEMORY_H
3210 +#define __ASM_ARCH_MEMORY_H
3211 +
3212 +/* Memory overview:
3213 +
3214 + [ARMcore] <--virtual addr-->
3215 + [ARMmmu] <--physical addr-->
3216 + [GERTmap] <--bus add-->
3217 + [VCperiph]
3218 +
3219 +*/
3220 +
3221 +/*
3222 + * Physical DRAM offset.
3223 + */
3224 +#define BCM_PLAT_PHYS_OFFSET UL(0x00000000)
3225 +#define VC_ARMMEM_OFFSET UL(0x00000000) /* offset in VC of ARM memory */
3226 +
3227 +#ifdef CONFIG_BCM2708_NOL2CACHE
3228 + #define _REAL_BUS_OFFSET UL(0xC0000000) /* don't use L1 or L2 caches */
3229 +#else
3230 + #define _REAL_BUS_OFFSET UL(0x40000000) /* use L2 cache */
3231 +#endif
3232 +
3233 +/* We're using the memory at 64M in the VideoCore for Linux - this adjustment
3234 + * will provide the offset into this area as well as setting the bits that
3235 + * stop the L1 and L2 cache from being used
3236 + *
3237 + * WARNING: this only works because the ARM is given memory at a fixed location
3238 + * (ARMMEM_OFFSET)
3239 + */
3240 +#define BUS_OFFSET (VC_ARMMEM_OFFSET + _REAL_BUS_OFFSET)
3241 +#define __virt_to_bus(x) ((x) + (BUS_OFFSET - PAGE_OFFSET))
3242 +#define __bus_to_virt(x) ((x) - (BUS_OFFSET - PAGE_OFFSET))
3243 +#define __pfn_to_bus(x) (__pfn_to_phys(x) + (BUS_OFFSET - BCM_PLAT_PHYS_OFFSET))
3244 +#define __bus_to_pfn(x) __phys_to_pfn((x) - (BUS_OFFSET - BCM_PLAT_PHYS_OFFSET))
3245 +
3246 +#endif
3247 diff --git a/arch/arm/mach-bcm2708/include/mach/platform.h b/arch/arm/mach-bcm2708/include/mach/platform.h
3248 new file mode 100644
3249 index 0000000..2e7e1bb
3250 --- /dev/null
3251 +++ b/arch/arm/mach-bcm2708/include/mach/platform.h
3252 @@ -0,0 +1,228 @@
3253 +/*
3254 + * arch/arm/mach-bcm2708/include/mach/platform.h
3255 + *
3256 + * Copyright (C) 2010 Broadcom
3257 + *
3258 + * This program is free software; you can redistribute it and/or modify
3259 + * it under the terms of the GNU General Public License as published by
3260 + * the Free Software Foundation; either version 2 of the License, or
3261 + * (at your option) any later version.
3262 + *
3263 + * This program is distributed in the hope that it will be useful,
3264 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
3265 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3266 + * GNU General Public License for more details.
3267 + *
3268 + * You should have received a copy of the GNU General Public License
3269 + * along with this program; if not, write to the Free Software
3270 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
3271 + */
3272 +
3273 +#ifndef _BCM2708_PLATFORM_H
3274 +#define _BCM2708_PLATFORM_H
3275 +
3276 +
3277 +/* macros to get at IO space when running virtually */
3278 +#define IO_ADDRESS(x) (((x) & 0x0fffffff) + (((x) >> 4) & 0x0f000000) + 0xf0000000)
3279 +
3280 +#define __io_address(n) IOMEM(IO_ADDRESS(n))
3281 +
3282 +
3283 +/*
3284 + * SDRAM
3285 + */
3286 +#define BCM2708_SDRAM_BASE 0x00000000
3287 +
3288 +/*
3289 + * Logic expansion modules
3290 + *
3291 + */
3292 +
3293 +
3294 +/* ------------------------------------------------------------------------
3295 + * BCM2708 ARMCTRL Registers
3296 + * ------------------------------------------------------------------------
3297 + */
3298 +
3299 +#define HW_REGISTER_RW(addr) (addr)
3300 +#define HW_REGISTER_RO(addr) (addr)
3301 +
3302 +#include "arm_control.h"
3303 +#undef ARM_BASE
3304 +
3305 +/*
3306 + * Definitions and addresses for the ARM CONTROL logic
3307 + * This file is manually generated.
3308 + */
3309 +
3310 +#define BCM2708_PERI_BASE 0x20000000
3311 +#define IC0_BASE (BCM2708_PERI_BASE + 0x2000)
3312 +#define ST_BASE (BCM2708_PERI_BASE + 0x3000) /* System Timer */
3313 +#define MPHI_BASE (BCM2708_PERI_BASE + 0x6000) /* Message -based Parallel Host Interface */
3314 +#define DMA_BASE (BCM2708_PERI_BASE + 0x7000) /* DMA controller */
3315 +#define ARM_BASE (BCM2708_PERI_BASE + 0xB000) /* BCM2708 ARM control block */
3316 +#define PM_BASE (BCM2708_PERI_BASE + 0x100000) /* Power Management, Reset controller and Watchdog registers */
3317 +#define PCM_CLOCK_BASE (BCM2708_PERI_BASE + 0x101098) /* PCM Clock */
3318 +#define RNG_BASE (BCM2708_PERI_BASE + 0x104000) /* Hardware RNG */
3319 +#define GPIO_BASE (BCM2708_PERI_BASE + 0x200000) /* GPIO */
3320 +#define UART0_BASE (BCM2708_PERI_BASE + 0x201000) /* Uart 0 */
3321 +#define MMCI0_BASE (BCM2708_PERI_BASE + 0x202000) /* MMC interface */
3322 +#define I2S_BASE (BCM2708_PERI_BASE + 0x203000) /* I2S */
3323 +#define SPI0_BASE (BCM2708_PERI_BASE + 0x204000) /* SPI0 */
3324 +#define BSC0_BASE (BCM2708_PERI_BASE + 0x205000) /* BSC0 I2C/TWI */
3325 +#define UART1_BASE (BCM2708_PERI_BASE + 0x215000) /* Uart 1 */
3326 +#define EMMC_BASE (BCM2708_PERI_BASE + 0x300000) /* eMMC interface */
3327 +#define SMI_BASE (BCM2708_PERI_BASE + 0x600000) /* SMI */
3328 +#define BSC1_BASE (BCM2708_PERI_BASE + 0x804000) /* BSC1 I2C/TWI */
3329 +#define USB_BASE (BCM2708_PERI_BASE + 0x980000) /* DTC_OTG USB controller */
3330 +#define MCORE_BASE (BCM2708_PERI_BASE + 0x0000) /* Fake frame buffer device (actually the multicore sync block*/
3331 +
3332 +#define ARMCTRL_BASE (ARM_BASE + 0x000)
3333 +#define ARMCTRL_IC_BASE (ARM_BASE + 0x200) /* ARM interrupt controller */
3334 +#define ARMCTRL_TIMER0_1_BASE (ARM_BASE + 0x400) /* Timer 0 and 1 */
3335 +#define ARMCTRL_0_SBM_BASE (ARM_BASE + 0x800) /* User 0 (ARM)'s Semaphores Doorbells and Mailboxes */
3336 +
3337 +
3338 +/*
3339 + * Interrupt assignments
3340 + */
3341 +
3342 +#define ARM_IRQ1_BASE 0
3343 +#define INTERRUPT_TIMER0 (ARM_IRQ1_BASE + 0)
3344 +#define INTERRUPT_TIMER1 (ARM_IRQ1_BASE + 1)
3345 +#define INTERRUPT_TIMER2 (ARM_IRQ1_BASE + 2)
3346 +#define INTERRUPT_TIMER3 (ARM_IRQ1_BASE + 3)
3347 +#define INTERRUPT_CODEC0 (ARM_IRQ1_BASE + 4)