add fix from #1516
[openwrt/svn-archive/archive.git] / target / linux / brcm47xx-2.6 / files / drivers / ssb / driver_pci / pcicore.c
1 /*
2 * Sonics Silicon Backplane
3 * Broadcom PCI-core driver
4 *
5 * Copyright 2005, Broadcom Corporation
6 * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
7 *
8 * Licensed under the GNU/GPL. See COPYING for details.
9 */
10
11 #include <linux/ssb/ssb.h>
12 #include <linux/pci.h>
13 #include <linux/delay.h>
14
15 #include "../ssb_private.h"
16
17 static inline
18 u32 pcicore_read32(struct ssb_pcicore *pc, u16 offset)
19 {
20 return ssb_read32(pc->dev, offset);
21 }
22
23 static inline
24 void pcicore_write32(struct ssb_pcicore *pc, u16 offset, u32 value)
25 {
26 ssb_write32(pc->dev, offset, value);
27 }
28
29 /**************************************************
30 * Code for hostmode operation.
31 **************************************************/
32
33 #ifdef CONFIG_SSB_PCICORE_HOSTMODE
34
35 #include <asm/paccess.h>
36 /* Read the bus and catch bus exceptions. This is MIPS specific. */
37 #define mips_busprobe(val, addr) get_dbe((val), (addr))
38
39 /* Assume one-hot slot wiring */
40 #define SSB_PCI_SLOT_MAX 16
41
42 /* Global lock is OK, as we won't have more than one extpci anyway. */
43 static DEFINE_SPINLOCK(cfgspace_lock);
44 /* Core to access the external PCI config space. Can only have one. */
45 static struct ssb_pcicore *extpci_core;
46
47 u32 pci_iobase = 0x100;
48 u32 pci_membase = SSB_PCI_DMA;
49
50 int pcibios_plat_dev_init(struct pci_dev *d)
51 {
52 struct resource *res;
53 int pos, size;
54 u32 *base;
55
56 printk("PCI: Fixing up device %s\n", pci_name(d));
57
58 /* Fix up resource bases */
59 for (pos = 0; pos < 6; pos++) {
60 res = &d->resource[pos];
61 base = ((res->flags & IORESOURCE_IO) ? &pci_iobase : &pci_membase);
62 if (res->end) {
63 size = res->end - res->start + 1;
64 if (*base & (size - 1))
65 *base = (*base + size) & ~(size - 1);
66 res->start = *base;
67 res->end = res->start + size - 1;
68 *base += size;
69 pci_write_config_dword(d, PCI_BASE_ADDRESS_0 + (pos << 2), res->start);
70 }
71 /* Fix up PCI bridge BAR0 only */
72 if (d->bus->number == 0 && PCI_SLOT(d->devfn) == 0)
73 break;
74 }
75 /* Fix up interrupt lines */
76 d->irq = ssb_mips_irq(extpci_core->dev) + 2;
77 pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
78
79 return 0;
80 }
81
82 static void __init ssb_fixup_pcibridge(struct pci_dev *dev)
83 {
84 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) != 0)
85 return;
86
87 printk("PCI: fixing up bridge\n");
88
89 /* Enable PCI bridge bus mastering and memory space */
90 pci_set_master(dev);
91 pcibios_enable_device(dev, ~0);
92
93 /* Enable PCI bridge BAR1 prefetch and burst */
94 pci_write_config_dword(dev, SSB_BAR1_CONTROL, 3);
95 }
96 DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, ssb_fixup_pcibridge);
97
98 int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
99 {
100 return ssb_mips_irq(extpci_core->dev) + 2;
101 }
102
103 static u32 get_cfgspace_addr(struct ssb_pcicore *pc,
104 unsigned int bus, unsigned int dev,
105 unsigned int func, unsigned int off)
106 {
107 u32 addr = 0;
108 u32 tmp;
109
110 if (unlikely(pc->cardbusmode && dev > 1))
111 goto out;
112 if (bus == 0) {//FIXME busnumber ok?
113 /* Type 0 transaction */
114 if (unlikely(dev >= SSB_PCI_SLOT_MAX))
115 goto out;
116 /* Slide the window */
117 tmp = SSB_PCICORE_SBTOPCI_CFG0;
118 tmp |= ((1 << (dev + 16)) & SSB_PCICORE_SBTOPCI1_MASK);
119 pcicore_write32(pc, SSB_PCICORE_SBTOPCI1, tmp);
120 /* Calculate the address */
121 addr = SSB_PCI_CFG;
122 addr |= ((1 << (dev + 16)) & ~SSB_PCICORE_SBTOPCI1_MASK);
123 addr |= (func << 8);
124 addr |= (off & ~3);
125 } else {
126 /* Type 1 transaction */
127 pcicore_write32(pc, SSB_PCICORE_SBTOPCI1,
128 SSB_PCICORE_SBTOPCI_CFG1);
129 /* Calculate the address */
130 addr = SSB_PCI_CFG;
131 addr |= (bus << 16);
132 addr |= (dev << 11);
133 addr |= (func << 8);
134 addr |= (off & ~3);
135 }
136 out:
137 return addr;
138 }
139
140 static int ssb_extpci_read_config(struct ssb_pcicore *pc,
141 unsigned int bus, unsigned int dev,
142 unsigned int func, unsigned int off,
143 void *buf, int len)
144 {
145 int err = -EINVAL;
146 u32 addr, val;
147 void __iomem *mmio;
148
149 assert(pc->hostmode);
150 if (unlikely(len != 1 && len != 2 && len != 4))
151 goto out;
152 addr = get_cfgspace_addr(pc, bus, dev, func, off);
153 if (unlikely(!addr))
154 goto out;
155 err = -ENOMEM;
156 mmio = ioremap_nocache(addr, len);
157 if (!mmio)
158 goto out;
159
160 if (mips_busprobe(val, (u32 *) mmio)) {
161 val = 0xffffffff;
162 goto unmap;
163 }
164
165 val >>= (8 * (off & 3));
166
167 switch (len) {
168 case 1:
169 *((u8 *)buf) = (u8)val;
170 break;
171 case 2:
172 *((u16 *)buf) = (u16)val;
173 break;
174 case 4:
175 *((u32 *)buf) = (u32)val;
176 break;
177 }
178 err = 0;
179 unmap:
180 iounmap(mmio);
181 out:
182 return err;
183 }
184
185 static int ssb_extpci_write_config(struct ssb_pcicore *pc,
186 unsigned int bus, unsigned int dev,
187 unsigned int func, unsigned int off,
188 const void *buf, int len)
189 {
190 int err = -EINVAL;
191 u32 addr, val = 0;
192 void __iomem *mmio;
193
194 assert(pc->hostmode);
195 if (unlikely(len != 1 && len != 2 && len != 4))
196 goto out;
197 addr = get_cfgspace_addr(pc, bus, dev, func, off);
198 if (unlikely(!addr))
199 goto out;
200 err = -ENOMEM;
201 mmio = ioremap_nocache(addr, len);
202 if (!mmio)
203 goto out;
204
205 if (mips_busprobe(val, (u32 *) mmio)) {
206 val = 0xffffffff;
207 goto unmap;
208 }
209
210 switch (len) {
211 case 1:
212 val &= ~(0xFF << (8 * (off & 3)));
213 val |= *((const u8 *)buf) << (8 * (off & 3));
214 break;
215 case 2:
216 val &= ~(0xFFFF << (8 * (off & 3)));
217 val |= *((const u16 *)buf) << (8 * (off & 3));
218 break;
219 case 4:
220 val = *((const u32 *)buf);
221 break;
222 }
223 writel(val, mmio);
224
225 err = 0;
226 unmap:
227 iounmap(mmio);
228 out:
229 return err;
230 }
231
232 static int ssb_pcicore_read_config(struct pci_bus *bus, unsigned int devfn,
233 int reg, int size, u32 *val)
234 {
235 unsigned long flags;
236 int err;
237
238 spin_lock_irqsave(&cfgspace_lock, flags);
239 err = ssb_extpci_read_config(extpci_core, bus->number, PCI_SLOT(devfn),
240 PCI_FUNC(devfn), reg, val, size);
241 spin_unlock_irqrestore(&cfgspace_lock, flags);
242
243 return err ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
244 }
245
246 static int ssb_pcicore_write_config(struct pci_bus *bus, unsigned int devfn,
247 int reg, int size, u32 val)
248 {
249 unsigned long flags;
250 int err;
251
252 spin_lock_irqsave(&cfgspace_lock, flags);
253 err = ssb_extpci_write_config(extpci_core, bus->number, PCI_SLOT(devfn),
254 PCI_FUNC(devfn), reg, &val, size);
255 spin_unlock_irqrestore(&cfgspace_lock, flags);
256
257 return err ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
258 }
259
260 static struct pci_ops ssb_pcicore_pciops = {
261 .read = ssb_pcicore_read_config,
262 .write = ssb_pcicore_write_config,
263 };
264
265 static struct resource ssb_pcicore_mem_resource = {
266 .name = "SSB PCIcore external memory",
267 .start = SSB_PCI_DMA,
268 .end = (u32)SSB_PCI_DMA + (u32)SSB_PCI_DMA_SZ - 1,
269 .flags = IORESOURCE_MEM,
270 };
271
272 static struct resource ssb_pcicore_io_resource = {
273 .name = "SSB PCIcore external I/O",
274 .start = 0x100,
275 .end = 0x7FF,
276 .flags = IORESOURCE_IO,
277 };
278
279 static struct pci_controller ssb_pcicore_controller = {
280 .pci_ops = &ssb_pcicore_pciops,
281 .io_resource = &ssb_pcicore_io_resource,
282 .mem_resource = &ssb_pcicore_mem_resource,
283 .mem_offset = 0x24000000,
284 };
285
286 static void ssb_pcicore_init_hostmode(struct ssb_pcicore *pc)
287 {
288 u32 val;
289
290 assert(!extpci_core);
291 extpci_core = pc;
292
293 ssb_dprintk(KERN_INFO PFX "PCIcore in host mode found\n");
294 /* Reset devices on the external PCI bus */
295 val = SSB_PCICORE_CTL_RST_OE;
296 val |= SSB_PCICORE_CTL_CLK_OE;
297 pcicore_write32(pc, SSB_PCICORE_CTL, val);
298 val |= SSB_PCICORE_CTL_CLK; /* Clock on */
299 pcicore_write32(pc, SSB_PCICORE_CTL, val);
300 udelay(150);
301 val |= SSB_PCICORE_CTL_RST; /* Deassert RST# */
302 pcicore_write32(pc, SSB_PCICORE_CTL, val);
303 val = SSB_PCICORE_ARBCTL_INTERN;
304 pcicore_write32(pc, SSB_PCICORE_ARBCTL, val);
305 udelay(1);
306
307 //TODO cardbus mode
308
309 /* 64MB I/O window */
310 pcicore_write32(pc, SSB_PCICORE_SBTOPCI0,
311 SSB_PCICORE_SBTOPCI_IO);
312 /* 64MB config space */
313 pcicore_write32(pc, SSB_PCICORE_SBTOPCI1,
314 SSB_PCICORE_SBTOPCI_CFG0);
315 /* 1GB memory window */
316 pcicore_write32(pc, SSB_PCICORE_SBTOPCI2,
317 SSB_PCICORE_SBTOPCI_MEM | SSB_PCI_DMA);
318
319 /* Enable PCI bridge BAR0 prefetch and burst */
320 val = PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
321 ssb_extpci_write_config(pc, 0, 0, 0, PCI_COMMAND, &val, 4);
322
323 /* Enable PCI interrupts */
324 pcicore_write32(pc, SSB_PCICORE_IMASK,
325 SSB_PCICORE_IMASK_INTA);
326
327 /* Ok, ready to run, register it to the system.
328 * The following needs change, if we want to port hostmode
329 * to non-MIPS platform. */
330 set_io_port_base((unsigned long)ioremap_nocache(SSB_PCI_MEM, 0x04000000));
331 mdelay(300);
332 register_pci_controller(&ssb_pcicore_controller);
333 }
334
335 static int pcicore_is_in_hostmode(struct ssb_pcicore *pc)
336 {
337 struct ssb_bus *bus = pc->dev->bus;
338 u16 chipid_top;
339 u32 tmp;
340
341 chipid_top = (bus->chip_id & 0xFF00);
342 if (chipid_top != 0x4700 &&
343 chipid_top != 0x5300)
344 return 0;
345
346 if (bus->sprom.r1.boardflags_lo & SSB_PCICORE_BFL_NOPCI)
347 return 0;
348
349 /* The 200-pin BCM4712 package does not bond out PCI. Even when
350 * PCI is bonded out, some boards may leave the pins floating. */
351 if (bus->chip_id == 0x4712) {
352 if (bus->chip_package == SSB_CHIPPACK_BCM4712S)
353 return 0;
354 if (bus->chip_package == SSB_CHIPPACK_BCM4712M)
355 return 0;
356 }
357 if (bus->chip_id == 0x5350)
358 return 0;
359
360 return !mips_busprobe(tmp, (u32 *) (bus->mmio + (pc->dev->core_index * SSB_CORE_SIZE)));
361 }
362 #endif /* CONFIG_SSB_PCICORE_HOSTMODE */
363
364
365 /**************************************************
366 * Generic and Clientmode operation code.
367 **************************************************/
368
369 static void ssb_pcicore_init_clientmode(struct ssb_pcicore *pc)
370 {
371 /* Disable PCI interrupts. */
372 ssb_write32(pc->dev, SSB_INTVEC, 0);
373 }
374
375 void ssb_pcicore_init(struct ssb_pcicore *pc)
376 {
377 struct ssb_device *dev = pc->dev;
378 struct ssb_bus *bus;
379
380 if (!dev)
381 return;
382 bus = dev->bus;
383 if (!ssb_device_is_enabled(dev))
384 ssb_device_enable(dev, 0);
385
386 #ifdef CONFIG_SSB_PCICORE_HOSTMODE
387 pc->hostmode = pcicore_is_in_hostmode(pc);
388 if (pc->hostmode)
389 ssb_pcicore_init_hostmode(pc);
390 #endif /* CONFIG_SSB_PCICORE_HOSTMODE */
391 if (!pc->hostmode)
392 ssb_pcicore_init_clientmode(pc);
393 }
394
395 static u32 ssb_pcie_read(struct ssb_pcicore *pc, u32 address)
396 {
397 pcicore_write32(pc, 0x130, address);
398 return pcicore_read32(pc, 0x134);
399 }
400
401 static void ssb_pcie_write(struct ssb_pcicore *pc, u32 address, u32 data)
402 {
403 pcicore_write32(pc, 0x130, address);
404 pcicore_write32(pc, 0x134, data);
405 }
406
407 static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device,
408 u8 address, u16 data)
409 {
410 const u16 mdio_control = 0x128;
411 const u16 mdio_data = 0x12C;
412 u32 v;
413 int i;
414
415 v = 0x80; /* Enable Preamble Sequence */
416 v |= 0x2; /* MDIO Clock Divisor */
417 pcicore_write32(pc, mdio_control, v);
418
419 v = (1 << 30); /* Start of Transaction */
420 v |= (1 << 28); /* Write Transaction */
421 v |= (1 << 17); /* Turnaround */
422 v |= (u32)device << 22;
423 v |= (u32)address << 18;
424 v |= data;
425 pcicore_write32(pc, mdio_data, v);
426 udelay(10);
427 for (i = 0; i < 10; i++) {
428 v = pcicore_read32(pc, mdio_control);
429 if (v & 0x100 /* Trans complete */)
430 break;
431 msleep(1);
432 }
433 pcicore_write32(pc, mdio_control, 0);
434 }
435
436 static void ssb_broadcast_value(struct ssb_device *dev,
437 u32 address, u32 data)
438 {
439 /* This is used for both, PCI and ChipCommon core, so be careful. */
440 BUILD_BUG_ON(SSB_PCICORE_BCAST_ADDR != SSB_CHIPCO_BCAST_ADDR);
441 BUILD_BUG_ON(SSB_PCICORE_BCAST_DATA != SSB_CHIPCO_BCAST_DATA);
442
443 ssb_write32(dev, SSB_PCICORE_BCAST_ADDR, address);
444 ssb_read32(dev, SSB_PCICORE_BCAST_ADDR); /* flush */
445 ssb_write32(dev, SSB_PCICORE_BCAST_DATA, data);
446 ssb_read32(dev, SSB_PCICORE_BCAST_DATA); /* flush */
447 }
448
449 static void ssb_commit_settings(struct ssb_bus *bus)
450 {
451 struct ssb_device *dev;
452
453 dev = bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev;
454 assert(dev);
455 /* This forces an update of the cached registers. */
456 ssb_broadcast_value(dev, 0xFD8, 0);
457 }
458
459 int ssb_pcicore_dev_irqvecs_enable(struct ssb_pcicore *pc,
460 struct ssb_device *dev)
461 {
462 struct ssb_device *pdev = pc->dev;
463 struct ssb_bus *bus;
464 int err = 0;
465 u32 tmp;
466
467 might_sleep();
468
469 if (!pdev)
470 goto out;
471 bus = pdev->bus;
472
473 /* Enable interrupts for this device. */
474 if (bus->host_pci &&
475 ((pdev->id.revision >= 6) || (pdev->id.coreid == SSB_DEV_PCIE))) {
476 u32 coremask;
477
478 /* Calculate the "coremask" for the device. */
479 coremask = (1 << dev->core_index);
480
481 err = pci_read_config_dword(bus->host_pci, SSB_PCI_IRQMASK, &tmp);
482 if (err)
483 goto out;
484 tmp |= coremask << 8;
485 err = pci_write_config_dword(bus->host_pci, SSB_PCI_IRQMASK, tmp);
486 if (err)
487 goto out;
488 } else {
489 u32 intvec;
490
491 intvec = ssb_read32(pdev, SSB_INTVEC);
492 tmp = ssb_read32(dev, SSB_TPSFLAG);
493 tmp &= SSB_TPSFLAG_BPFLAG;
494 intvec |= tmp;
495 ssb_write32(pdev, SSB_INTVEC, intvec);
496 }
497
498 /* Setup PCIcore operation. */
499 if (pc->setup_done)
500 goto out;
501 if (pdev->id.coreid == SSB_DEV_PCI) {
502 tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
503 tmp |= SSB_PCICORE_SBTOPCI_PREF;
504 tmp |= SSB_PCICORE_SBTOPCI_BURST;
505 pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
506
507 if (pdev->id.revision < 5) {
508 tmp = ssb_read32(pdev, SSB_IMCFGLO);
509 tmp &= ~SSB_IMCFGLO_SERTO;
510 tmp |= 2;
511 tmp &= ~SSB_IMCFGLO_REQTO;
512 tmp |= 3 << SSB_IMCFGLO_REQTO_SHIFT;
513 ssb_write32(pdev, SSB_IMCFGLO, tmp);
514 ssb_commit_settings(bus);
515 } else if (pdev->id.revision >= 11) {
516 tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
517 tmp |= SSB_PCICORE_SBTOPCI_MRM;
518 pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
519 }
520 } else {
521 assert(pdev->id.coreid == SSB_DEV_PCIE);
522 //TODO: Better make defines for all these magic PCIE values.
523 if ((pdev->id.revision == 0) || (pdev->id.revision == 1)) {
524 /* TLP Workaround register. */
525 tmp = ssb_pcie_read(pc, 0x4);
526 tmp |= 0x8;
527 ssb_pcie_write(pc, 0x4, tmp);
528 }
529 if (pdev->id.revision == 0) {
530 const u8 serdes_rx_device = 0x1F;
531
532 ssb_pcie_mdio_write(pc, serdes_rx_device,
533 2 /* Timer */, 0x8128);
534 ssb_pcie_mdio_write(pc, serdes_rx_device,
535 6 /* CDR */, 0x0100);
536 ssb_pcie_mdio_write(pc, serdes_rx_device,
537 7 /* CDR BW */, 0x1466);
538 } else if (pdev->id.revision == 1) {
539 /* DLLP Link Control register. */
540 tmp = ssb_pcie_read(pc, 0x100);
541 tmp |= 0x40;
542 ssb_pcie_write(pc, 0x100, tmp);
543 }
544 }
545 pc->setup_done = 1;
546 out:
547 return err;
548 }
549 EXPORT_SYMBOL(ssb_pcicore_dev_irqvecs_enable);