target/linux/brcm47xx-2.6/files/drivers/ssb/driver_pci/pcicore.c

   1 /*
   2  * Sonics Silicon Backplane
   3  * Broadcom PCI-core driver
   4  *
   5  * Copyright 2005, Broadcom Corporation
   6  * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
   7  *
   8  * Licensed under the GNU/GPL. See COPYING for details.
   9  */
  10
  11 #include <linux/ssb/ssb.h>
  12 #include <linux/pci.h>
  13 #include <linux/delay.h>
  14
  15 #include "../ssb_private.h"
  16
  17 static inline
  18 u32 pcicore_read32(struct ssb_pcicore *pc, u16 offset)
  19 {
  20         return ssb_read32(pc->dev, offset);
  21 }
  22
  23 static inline
  24 void pcicore_write32(struct ssb_pcicore *pc, u16 offset, u32 value)
  25 {
  26         ssb_write32(pc->dev, offset, value);
  27 }
  28
  29 /**************************************************
  30  * Code for hostmode operation.
  31  **************************************************/
  32
  33 #ifdef CONFIG_SSB_PCICORE_HOSTMODE
  34
  35 #include <asm/paccess.h>
  36 /* Read the bus and catch bus exceptions. This is MIPS specific. */
  37 #define mips_busprobe(val, addr)        get_dbe((val), (addr))
  38
  39 /* Assume one-hot slot wiring */
  40 #define SSB_PCI_SLOT_MAX        16
  41
  42 /* Global lock is OK, as we won't have more than one extpci anyway. */
  43 static DEFINE_SPINLOCK(cfgspace_lock);
  44 /* Core to access the external PCI config space. Can only have one. */
  45 static struct ssb_pcicore *extpci_core;
  46
  47 u32 pci_iobase = 0x100;
  48 u32 pci_membase = SSB_PCI_DMA;
  49
  50 int pcibios_plat_dev_init(struct pci_dev *d)
  51 {
  52         struct resource *res;
  53         int pos, size;
  54         u32 *base;
  55
  56         printk("PCI: Fixing up device %s\n", pci_name(d));
  57
  58         /* Fix up resource bases */
  59         for (pos = 0; pos < 6; pos++) {
  60                 res = &d->resource[pos];
  61                 base = ((res->flags & IORESOURCE_IO) ? &pci_iobase : &pci_membase);
  62                 if (res->end) {
  63                         size = res->end - res->start + 1;
  64                         if (*base & (size - 1))
  65                                 *base = (*base + size) & ~(size - 1);
  66                         res->start = *base;
  67                         res->end = res->start + size - 1;
  68                         *base += size;
  69                         pci_write_config_dword(d, PCI_BASE_ADDRESS_0 + (pos << 2), res->start);
  70                 }
  71                 /* Fix up PCI bridge BAR0 only */
  72                 if (d->bus->number == 0 && PCI_SLOT(d->devfn) == 0)
  73                         break;
  74         }
  75         /* Fix up interrupt lines */
  76         d->irq = ssb_mips_irq(extpci_core->dev) + 2;
  77         pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
  78
  79         return 0;
  80 }
  81
  82 static void __init ssb_fixup_pcibridge(struct pci_dev *dev)
  83 {
  84         if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) != 0)
  85                 return;
  86
  87         printk("PCI: fixing up bridge\n");
  88
  89         /* Enable PCI bridge bus mastering and memory space */
  90         pci_set_master(dev);
  91         pcibios_enable_device(dev, ~0);
  92
  93         /* Enable PCI bridge BAR1 prefetch and burst */
  94         pci_write_config_dword(dev, SSB_BAR1_CONTROL, 3);
  95 }
  96 DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, ssb_fixup_pcibridge);
  97
  98 int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
  99 {
 100         return ssb_mips_irq(extpci_core->dev) + 2;
 101 }
 102
 103 static u32 get_cfgspace_addr(struct ssb_pcicore *pc,
 104                              unsigned int bus, unsigned int dev,
 105                              unsigned int func, unsigned int off)
 106 {
 107         u32 addr = 0;
 108         u32 tmp;
 109
 110         if (unlikely(pc->cardbusmode && dev > 1))
 111                 goto out;
 112         if (bus == 0) {//FIXME busnumber ok?
 113                 /* Type 0 transaction */
 114                 if (unlikely(dev >= SSB_PCI_SLOT_MAX))
 115                         goto out;
 116                 /* Slide the window */
 117                 tmp = SSB_PCICORE_SBTOPCI_CFG0;
 118                 tmp |= ((1 << (dev + 16)) & SSB_PCICORE_SBTOPCI1_MASK);
 119                 pcicore_write32(pc, SSB_PCICORE_SBTOPCI1, tmp);
 120                 /* Calculate the address */
 121                 addr = SSB_PCI_CFG;
 122                 addr |= ((1 << (dev + 16)) & ~SSB_PCICORE_SBTOPCI1_MASK);
 123                 addr |= (func << 8);
 124                 addr |= (off & ~3);
 125         } else {
 126                 /* Type 1 transaction */
 127                 pcicore_write32(pc, SSB_PCICORE_SBTOPCI1,
 128                                 SSB_PCICORE_SBTOPCI_CFG1);
 129                 /* Calculate the address */
 130                 addr = SSB_PCI_CFG;
 131                 addr |= (bus << 16);
 132                 addr |= (dev << 11);
 133                 addr |= (func << 8);
 134                 addr |= (off & ~3);
 135         }
 136 out:
 137         return addr;
 138 }
 139
 140 static int ssb_extpci_read_config(struct ssb_pcicore *pc,
 141                                   unsigned int bus, unsigned int dev,
 142                                   unsigned int func, unsigned int off,
 143                                   void *buf, int len)
 144 {
 145         int err = -EINVAL;
 146         u32 addr, val;
 147         void __iomem *mmio;
 148
 149         assert(pc->hostmode);
 150         if (unlikely(len != 1 && len != 2 && len != 4))
 151                 goto out;
 152         addr = get_cfgspace_addr(pc, bus, dev, func, off);
 153         if (unlikely(!addr))
 154                 goto out;
 155         err = -ENOMEM;
 156         mmio = ioremap_nocache(addr, len);
 157         if (!mmio)
 158                 goto out;
 159
 160         if (mips_busprobe(val, (u32 *) mmio)) {
 161                 val = 0xffffffff;
 162                 goto unmap;
 163         }
 164
 165         val = readl(mmio);
 166         val >>= (8 * (off & 3));
 167
 168         switch (len) {
 169         case 1:
 170                 *((u8 *)buf) = (u8)val;
 171                 break;
 172         case 2:
 173                 *((u16 *)buf) = (u16)val;
 174                 break;
 175         case 4:
 176                 *((u32 *)buf) = (u32)val;
 177                 break;
 178         }
 179         err = 0;
 180 unmap:
 181         iounmap(mmio);
 182 out:
 183         return err;
 184 }
 185
 186 static int ssb_extpci_write_config(struct ssb_pcicore *pc,
 187                                    unsigned int bus, unsigned int dev,
 188                                    unsigned int func, unsigned int off,
 189                                    const void *buf, int len)
 190 {
 191         int err = -EINVAL;
 192         u32 addr, val = 0;
 193         void __iomem *mmio;
 194
 195         assert(pc->hostmode);
 196         if (unlikely(len != 1 && len != 2 && len != 4))
 197                 goto out;
 198         addr = get_cfgspace_addr(pc, bus, dev, func, off);
 199         if (unlikely(!addr))
 200                 goto out;
 201         err = -ENOMEM;
 202         mmio = ioremap_nocache(addr, len);
 203         if (!mmio)
 204                 goto out;
 205
 206         if (mips_busprobe(val, (u32 *) mmio)) {
 207                 val = 0xffffffff;
 208                 goto unmap;
 209         }
 210
 211         switch (len) {
 212         case 1:
 213                 val = readl(mmio);
 214                 val &= ~(0xFF << (8 * (off & 3)));
 215                 val |= *((const u8 *)buf) << (8 * (off & 3));
 216                 break;
 217         case 2:
 218                 val = readl(mmio);
 219                 val &= ~(0xFFFF << (8 * (off & 3)));
 220                 val |= *((const u16 *)buf) << (8 * (off & 3));
 221                 break;
 222         case 4:
 223                 val = *((const u32 *)buf);
 224                 break;
 225         }
 226         writel(*((const u32 *)buf), mmio);
 227
 228         err = 0;
 229 unmap:
 230         iounmap(mmio);
 231 out:
 232         return err;
 233 }
 234
 235 static int ssb_pcicore_read_config(struct pci_bus *bus, unsigned int devfn,
 236                                    int reg, int size, u32 *val)
 237 {
 238         unsigned long flags;
 239         int err;
 240
 241         spin_lock_irqsave(&cfgspace_lock, flags);
 242         err = ssb_extpci_read_config(extpci_core, bus->number, PCI_SLOT(devfn),
 243                                      PCI_FUNC(devfn), reg, val, size);
 244         spin_unlock_irqrestore(&cfgspace_lock, flags);
 245
 246         return err ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
 247 }
 248
 249 static int ssb_pcicore_write_config(struct pci_bus *bus, unsigned int devfn,
 250                                     int reg, int size, u32 val)
 251 {
 252         unsigned long flags;
 253         int err;
 254
 255         spin_lock_irqsave(&cfgspace_lock, flags);
 256         err = ssb_extpci_write_config(extpci_core, bus->number, PCI_SLOT(devfn),
 257                                       PCI_FUNC(devfn), reg, &val, size);
 258         spin_unlock_irqrestore(&cfgspace_lock, flags);
 259
 260         return err ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
 261 }
 262
 263 static struct pci_ops ssb_pcicore_pciops = {
 264         .read   = ssb_pcicore_read_config,
 265         .write  = ssb_pcicore_write_config,
 266 };
 267
 268 static struct resource ssb_pcicore_mem_resource = {
 269         .name   = "SSB PCIcore external memory",
 270         .start  = SSB_PCI_DMA,
 271         .end    = (u32)SSB_PCI_DMA + (u32)SSB_PCI_DMA_SZ - 1,
 272         .flags  = IORESOURCE_MEM,
 273 };
 274
 275 static struct resource ssb_pcicore_io_resource = {
 276         .name   = "SSB PCIcore external I/O",
 277         .start  = 0x100,
 278         .end    = 0x7FF,
 279         .flags  = IORESOURCE_IO,
 280 };
 281
 282 static struct pci_controller ssb_pcicore_controller = {
 283         .pci_ops        = &ssb_pcicore_pciops,
 284         .io_resource    = &ssb_pcicore_io_resource,
 285         .mem_resource   = &ssb_pcicore_mem_resource,
 286         .mem_offset     = 0x24000000,
 287 };
 288
 289 static void ssb_pcicore_init_hostmode(struct ssb_pcicore *pc)
 290 {
 291         u32 val;
 292
 293         assert(!extpci_core);
 294         extpci_core = pc;
 295
 296         ssb_dprintk(KERN_INFO PFX "PCIcore in host mode found\n");
 297         /* Reset devices on the external PCI bus */
 298         val = SSB_PCICORE_CTL_RST_OE;
 299         val |= SSB_PCICORE_CTL_CLK_OE;
 300         pcicore_write32(pc, SSB_PCICORE_CTL, val);
 301         val |= SSB_PCICORE_CTL_CLK; /* Clock on */
 302         pcicore_write32(pc, SSB_PCICORE_CTL, val);
 303         udelay(150);
 304         val |= SSB_PCICORE_CTL_RST; /* Deassert RST# */
 305         pcicore_write32(pc, SSB_PCICORE_CTL, val);
 306         val = SSB_PCICORE_ARBCTL_INTERN;
 307         pcicore_write32(pc, SSB_PCICORE_ARBCTL, val);
 308         udelay(1);
 309
 310         //TODO cardbus mode
 311
 312         /* 64MB I/O window */
 313         pcicore_write32(pc, SSB_PCICORE_SBTOPCI0,
 314                         SSB_PCICORE_SBTOPCI_IO);
 315         /* 64MB config space */
 316         pcicore_write32(pc, SSB_PCICORE_SBTOPCI1,
 317                         SSB_PCICORE_SBTOPCI_CFG0);
 318         /* 1GB memory window */
 319         pcicore_write32(pc, SSB_PCICORE_SBTOPCI2,
 320                         SSB_PCICORE_SBTOPCI_MEM | SSB_PCI_DMA);
 321
 322         /* Enable PCI bridge BAR0 prefetch and burst */
 323         val = PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
 324         ssb_extpci_write_config(pc, 0, 0, 0, PCI_COMMAND, &val, 4);
 325
 326         /* Enable PCI interrupts */
 327         pcicore_write32(pc, SSB_PCICORE_IMASK,
 328                         SSB_PCICORE_IMASK_INTA);
 329
 330         /* Ok, ready to run, register it to the system.
 331          * The following needs change, if we want to port hostmode
 332          * to non-MIPS platform. */
 333         set_io_port_base((unsigned long)ioremap_nocache(SSB_PCI_MEM, 0x04000000));
 334         mdelay(300);
 335         register_pci_controller(&ssb_pcicore_controller);
 336 }
 337
 338 static int pcicore_is_in_hostmode(struct ssb_pcicore *pc)
 339 {
 340         struct ssb_bus *bus = pc->dev->bus;
 341         u16 chipid_top;
 342         u32 tmp;
 343
 344         chipid_top = (bus->chip_id & 0xFF00);
 345         if (chipid_top != 0x4700 &&
 346             chipid_top != 0x5300)
 347                 return 0;
 348
 349         if (bus->sprom.r1.boardflags_lo & SSB_PCICORE_BFL_NOPCI)
 350                 return 0;
 351
 352         /* The 200-pin BCM4712 package does not bond out PCI. Even when
 353          * PCI is bonded out, some boards may leave the pins floating. */
 354         if (bus->chip_id == 0x4712) {
 355                 if (bus->chip_package == SSB_CHIPPACK_BCM4712S)
 356                         return 0;
 357                 if (bus->chip_package == SSB_CHIPPACK_BCM4712M)
 358                         return 0;
 359         }
 360         if (bus->chip_id == 0x5350)
 361                 return 0;
 362
 363         return !mips_busprobe(tmp, (u32 *) (bus->mmio + (pc->dev->core_index * SSB_CORE_SIZE)));
 364 }
 365 #endif /* CONFIG_SSB_PCICORE_HOSTMODE */
 366
 367
 368 /**************************************************
 369  * Generic and Clientmode operation code.
 370  **************************************************/
 371
 372 static void ssb_pcicore_init_clientmode(struct ssb_pcicore *pc)
 373 {
 374         /* Disable PCI interrupts. */
 375         ssb_write32(pc->dev, SSB_INTVEC, 0);
 376 }
 377
 378 void ssb_pcicore_init(struct ssb_pcicore *pc)
 379 {
 380         struct ssb_device *dev = pc->dev;
 381         struct ssb_bus *bus;
 382
 383         if (!dev)
 384                 return;
 385         bus = dev->bus;
 386         if (!ssb_device_is_enabled(dev))
 387                 ssb_device_enable(dev, 0);
 388
 389 #ifdef CONFIG_SSB_PCICORE_HOSTMODE
 390         pc->hostmode = pcicore_is_in_hostmode(pc);
 391         if (pc->hostmode)
 392                 ssb_pcicore_init_hostmode(pc);
 393 #endif /* CONFIG_SSB_PCICORE_HOSTMODE */
 394         if (!pc->hostmode)
 395                 ssb_pcicore_init_clientmode(pc);
 396 }
 397
 398 static u32 ssb_pcie_read(struct ssb_pcicore *pc, u32 address)
 399 {
 400         pcicore_write32(pc, 0x130, address);
 401         return pcicore_read32(pc, 0x134);
 402 }
 403
 404 static void ssb_pcie_write(struct ssb_pcicore *pc, u32 address, u32 data)
 405 {
 406         pcicore_write32(pc, 0x130, address);
 407         pcicore_write32(pc, 0x134, data);
 408 }
 409
 410 static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device,
 411                                 u8 address, u16 data)
 412 {
 413         const u16 mdio_control = 0x128;
 414         const u16 mdio_data = 0x12C;
 415         u32 v;
 416         int i;
 417
 418         v = 0x80; /* Enable Preamble Sequence */
 419         v |= 0x2; /* MDIO Clock Divisor */
 420         pcicore_write32(pc, mdio_control, v);
 421
 422         v = (1 << 30); /* Start of Transaction */
 423         v |= (1 << 28); /* Write Transaction */
 424         v |= (1 << 17); /* Turnaround */
 425         v |= (u32)device << 22;
 426         v |= (u32)address << 18;
 427         v |= data;
 428         pcicore_write32(pc, mdio_data, v);
 429         udelay(10);
 430         for (i = 0; i < 10; i++) {
 431                 v = pcicore_read32(pc, mdio_control);
 432                 if (v & 0x100 /* Trans complete */)
 433                         break;
 434                 msleep(1);
 435         }
 436         pcicore_write32(pc, mdio_control, 0);
 437 }
 438
 439 static void ssb_broadcast_value(struct ssb_device *dev,
 440                                 u32 address, u32 data)
 441 {
 442         /* This is used for both, PCI and ChipCommon core, so be careful. */
 443         BUILD_BUG_ON(SSB_PCICORE_BCAST_ADDR != SSB_CHIPCO_BCAST_ADDR);
 444         BUILD_BUG_ON(SSB_PCICORE_BCAST_DATA != SSB_CHIPCO_BCAST_DATA);
 445
 446         ssb_write32(dev, SSB_PCICORE_BCAST_ADDR, address);
 447         ssb_read32(dev, SSB_PCICORE_BCAST_ADDR); /* flush */
 448         ssb_write32(dev, SSB_PCICORE_BCAST_DATA, data);
 449         ssb_read32(dev, SSB_PCICORE_BCAST_DATA); /* flush */
 450 }
 451
 452 static void ssb_commit_settings(struct ssb_bus *bus)
 453 {
 454         struct ssb_device *dev;
 455
 456         dev = bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev;
 457         assert(dev);
 458         /* This forces an update of the cached registers. */
 459         ssb_broadcast_value(dev, 0xFD8, 0);
 460 }
 461
 462 int ssb_pcicore_dev_irqvecs_enable(struct ssb_pcicore *pc,
 463                                    struct ssb_device *dev)
 464 {
 465         struct ssb_device *pdev = pc->dev;
 466         struct ssb_bus *bus;
 467         int err = 0;
 468         u32 tmp;
 469
 470         might_sleep();
 471
 472         if (!pdev)
 473                 goto out;
 474         bus = pdev->bus;
 475
 476         /* Enable interrupts for this device. */
 477         if (bus->host_pci &&
 478             ((pdev->id.revision >= 6) || (pdev->id.coreid == SSB_DEV_PCIE))) {
 479                 u32 coremask;
 480
 481                 /* Calculate the "coremask" for the device. */
 482                 coremask = (1 << dev->core_index);
 483
 484                 err = pci_read_config_dword(bus->host_pci, SSB_PCI_IRQMASK, &tmp);
 485                 if (err)
 486                         goto out;
 487                 tmp |= coremask << 8;
 488                 err = pci_write_config_dword(bus->host_pci, SSB_PCI_IRQMASK, tmp);
 489                 if (err)
 490                         goto out;
 491         } else {
 492                 u32 intvec;
 493
 494                 intvec = ssb_read32(pdev, SSB_INTVEC);
 495                 tmp = ssb_read32(dev, SSB_TPSFLAG);
 496                 tmp &= SSB_TPSFLAG_BPFLAG;
 497                 intvec |= tmp;
 498                 ssb_write32(pdev, SSB_INTVEC, intvec);
 499         }
 500
 501         /* Setup PCIcore operation. */
 502         if (pc->setup_done)
 503                 goto out;
 504         if (pdev->id.coreid == SSB_DEV_PCI) {
 505                 tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
 506                 tmp |= SSB_PCICORE_SBTOPCI_PREF;
 507                 tmp |= SSB_PCICORE_SBTOPCI_BURST;
 508                 pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
 509
 510                 if (pdev->id.revision < 5) {
 511                         tmp = ssb_read32(pdev, SSB_IMCFGLO);
 512                         tmp &= ~SSB_IMCFGLO_SERTO;
 513                         tmp |= 2;
 514                         tmp &= ~SSB_IMCFGLO_REQTO;
 515                         tmp |= 3 << SSB_IMCFGLO_REQTO_SHIFT;
 516                         ssb_write32(pdev, SSB_IMCFGLO, tmp);
 517                         ssb_commit_settings(bus);
 518                 } else if (pdev->id.revision >= 11) {
 519                         tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
 520                         tmp |= SSB_PCICORE_SBTOPCI_MRM;
 521                         pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
 522                 }
 523         } else {
 524                 assert(pdev->id.coreid == SSB_DEV_PCIE);
 525                 //TODO: Better make defines for all these magic PCIE values.
 526                 if ((pdev->id.revision == 0) || (pdev->id.revision == 1)) {
 527                         /* TLP Workaround register. */
 528                         tmp = ssb_pcie_read(pc, 0x4);
 529                         tmp |= 0x8;
 530                         ssb_pcie_write(pc, 0x4, tmp);
 531                 }
 532                 if (pdev->id.revision == 0) {
 533                         const u8 serdes_rx_device = 0x1F;
 534
 535                         ssb_pcie_mdio_write(pc, serdes_rx_device,
 536                                             2 /* Timer */, 0x8128);
 537                         ssb_pcie_mdio_write(pc, serdes_rx_device,
 538                                             6 /* CDR */, 0x0100);
 539                         ssb_pcie_mdio_write(pc, serdes_rx_device,
 540                                             7 /* CDR BW */, 0x1466);
 541                 } else if (pdev->id.revision == 1) {
 542                         /* DLLP Link Control register. */
 543                         tmp = ssb_pcie_read(pc, 0x100);
 544                         tmp |= 0x40;
 545                         ssb_pcie_write(pc, 0x100, tmp);
 546                 }
 547         }
 548         pc->setup_done = 1;
 549 out:
 550         return err;
 551 }
 552 EXPORT_SYMBOL(ssb_pcicore_dev_irqvecs_enable);