[brcm47xx] Fix TG3 build. Thanks Hauke Mehrtens
[openwrt/svn-archive/archive.git] / target / linux / brcm47xx / patches-2.6.25 / 700-ssb-gigabit-ethernet-driver.patch
1 Index: linux-2.6.25.4/drivers/ssb/Kconfig
2 ===================================================================
3 --- linux-2.6.25.4.orig/drivers/ssb/Kconfig
4 +++ linux-2.6.25.4/drivers/ssb/Kconfig
5 @@ -125,4 +125,13 @@ config SSB_DRIVER_EXTIF
6
7 If unsure, say N
8
9 +config SSB_DRIVER_GIGE
10 + bool "SSB Broadcom Gigabit Ethernet driver"
11 + depends on SSB_PCIHOST_POSSIBLE && SSB_EMBEDDED && MIPS
12 + help
13 + Driver for the Sonics Silicon Backplane attached
14 + Broadcom Gigabit Ethernet.
15 +
16 + If unsure, say N
17 +
18 endmenu
19 Index: linux-2.6.25.4/drivers/ssb/Makefile
20 ===================================================================
21 --- linux-2.6.25.4.orig/drivers/ssb/Makefile
22 +++ linux-2.6.25.4/drivers/ssb/Makefile
23 @@ -11,6 +11,7 @@ ssb-y += driver_chipcommon.o
24 ssb-$(CONFIG_SSB_DRIVER_MIPS) += driver_mipscore.o
25 ssb-$(CONFIG_SSB_DRIVER_EXTIF) += driver_extif.o
26 ssb-$(CONFIG_SSB_DRIVER_PCICORE) += driver_pcicore.o
27 +ssb-$(CONFIG_SSB_DRIVER_GIGE) += driver_gige.o
28
29 # b43 pci-ssb-bridge driver
30 # Not strictly a part of SSB, but kept here for convenience
31 Index: linux-2.6.25.4/drivers/ssb/driver_gige.c
32 ===================================================================
33 --- /dev/null
34 +++ linux-2.6.25.4/drivers/ssb/driver_gige.c
35 @@ -0,0 +1,294 @@
36 +/*
37 + * Sonics Silicon Backplane
38 + * Broadcom Gigabit Ethernet core driver
39 + *
40 + * Copyright 2008, Broadcom Corporation
41 + * Copyright 2008, Michael Buesch <mb@bu3sch.de>
42 + *
43 + * Licensed under the GNU/GPL. See COPYING for details.
44 + */
45 +
46 +#include <linux/ssb/ssb.h>
47 +#include <linux/ssb/ssb_driver_gige.h>
48 +#include <linux/pci.h>
49 +#include <linux/pci_regs.h>
50 +
51 +
52 +/*
53 +MODULE_DESCRIPTION("SSB Broadcom Gigabit Ethernet driver");
54 +MODULE_AUTHOR("Michael Buesch");
55 +MODULE_LICENSE("GPL");
56 +*/
57 +
58 +static const struct ssb_device_id ssb_gige_tbl[] = {
59 + SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_ETHERNET_GBIT, SSB_ANY_REV),
60 + SSB_DEVTABLE_END
61 +};
62 +/* MODULE_DEVICE_TABLE(ssb, ssb_gige_tbl); */
63 +
64 +
65 +static inline u8 gige_read8(struct ssb_gige *dev, u16 offset)
66 +{
67 + return ssb_read8(dev->dev, offset);
68 +}
69 +
70 +static inline u16 gige_read16(struct ssb_gige *dev, u16 offset)
71 +{
72 + return ssb_read16(dev->dev, offset);
73 +}
74 +
75 +static inline u32 gige_read32(struct ssb_gige *dev, u16 offset)
76 +{
77 + return ssb_read32(dev->dev, offset);
78 +}
79 +
80 +static inline void gige_write8(struct ssb_gige *dev,
81 + u16 offset, u8 value)
82 +{
83 + ssb_write8(dev->dev, offset, value);
84 +}
85 +
86 +static inline void gige_write16(struct ssb_gige *dev,
87 + u16 offset, u16 value)
88 +{
89 + ssb_write16(dev->dev, offset, value);
90 +}
91 +
92 +static inline void gige_write32(struct ssb_gige *dev,
93 + u16 offset, u32 value)
94 +{
95 + ssb_write32(dev->dev, offset, value);
96 +}
97 +
98 +static inline
99 +u8 gige_pcicfg_read8(struct ssb_gige *dev, unsigned int offset)
100 +{
101 + BUG_ON(offset >= 256);
102 + return gige_read8(dev, SSB_GIGE_PCICFG + offset);
103 +}
104 +
105 +static inline
106 +u16 gige_pcicfg_read16(struct ssb_gige *dev, unsigned int offset)
107 +{
108 + BUG_ON(offset >= 256);
109 + return gige_read16(dev, SSB_GIGE_PCICFG + offset);
110 +}
111 +
112 +static inline
113 +u32 gige_pcicfg_read32(struct ssb_gige *dev, unsigned int offset)
114 +{
115 + BUG_ON(offset >= 256);
116 + return gige_read32(dev, SSB_GIGE_PCICFG + offset);
117 +}
118 +
119 +static inline
120 +void gige_pcicfg_write8(struct ssb_gige *dev,
121 + unsigned int offset, u8 value)
122 +{
123 + BUG_ON(offset >= 256);
124 + gige_write8(dev, SSB_GIGE_PCICFG + offset, value);
125 +}
126 +
127 +static inline
128 +void gige_pcicfg_write16(struct ssb_gige *dev,
129 + unsigned int offset, u16 value)
130 +{
131 + BUG_ON(offset >= 256);
132 + gige_write16(dev, SSB_GIGE_PCICFG + offset, value);
133 +}
134 +
135 +static inline
136 +void gige_pcicfg_write32(struct ssb_gige *dev,
137 + unsigned int offset, u32 value)
138 +{
139 + BUG_ON(offset >= 256);
140 + gige_write32(dev, SSB_GIGE_PCICFG + offset, value);
141 +}
142 +
143 +static int ssb_gige_pci_read_config(struct pci_bus *bus, unsigned int devfn,
144 + int reg, int size, u32 *val)
145 +{
146 + struct ssb_gige *dev = container_of(bus->ops, struct ssb_gige, pci_ops);
147 + unsigned long flags;
148 +
149 + if ((PCI_SLOT(devfn) > 0) || (PCI_FUNC(devfn) > 0))
150 + return PCIBIOS_DEVICE_NOT_FOUND;
151 + if (reg >= 256)
152 + return PCIBIOS_DEVICE_NOT_FOUND;
153 +
154 + spin_lock_irqsave(&dev->lock, flags);
155 + switch (size) {
156 + case 1:
157 + *val = gige_pcicfg_read8(dev, reg);
158 + break;
159 + case 2:
160 + *val = gige_pcicfg_read16(dev, reg);
161 + break;
162 + case 4:
163 + *val = gige_pcicfg_read32(dev, reg);
164 + break;
165 + default:
166 + WARN_ON(1);
167 + }
168 + spin_unlock_irqrestore(&dev->lock, flags);
169 +
170 + return PCIBIOS_SUCCESSFUL;
171 +}
172 +
173 +static int ssb_gige_pci_write_config(struct pci_bus *bus, unsigned int devfn,
174 + int reg, int size, u32 val)
175 +{
176 + struct ssb_gige *dev = container_of(bus->ops, struct ssb_gige, pci_ops);
177 + unsigned long flags;
178 +
179 + if ((PCI_SLOT(devfn) > 0) || (PCI_FUNC(devfn) > 0))
180 + return PCIBIOS_DEVICE_NOT_FOUND;
181 + if (reg >= 256)
182 + return PCIBIOS_DEVICE_NOT_FOUND;
183 +
184 + spin_lock_irqsave(&dev->lock, flags);
185 + switch (size) {
186 + case 1:
187 + gige_pcicfg_write8(dev, reg, val);
188 + break;
189 + case 2:
190 + gige_pcicfg_write16(dev, reg, val);
191 + break;
192 + case 4:
193 + gige_pcicfg_write32(dev, reg, val);
194 + break;
195 + default:
196 + WARN_ON(1);
197 + }
198 + spin_unlock_irqrestore(&dev->lock, flags);
199 +
200 + return PCIBIOS_SUCCESSFUL;
201 +}
202 +
203 +static int ssb_gige_probe(struct ssb_device *sdev, const struct ssb_device_id *id)
204 +{
205 + struct ssb_gige *dev;
206 + u32 base, tmslow, tmshigh;
207 +
208 + dev = kzalloc(sizeof(*dev), GFP_KERNEL);
209 + if (!dev)
210 + return -ENOMEM;
211 + dev->dev = sdev;
212 +
213 + spin_lock_init(&dev->lock);
214 + dev->pci_controller.pci_ops = &dev->pci_ops;
215 + dev->pci_controller.io_resource = &dev->io_resource;
216 + dev->pci_controller.mem_resource = &dev->mem_resource;
217 + dev->pci_controller.io_map_base = 0x800;
218 + dev->pci_ops.read = ssb_gige_pci_read_config;
219 + dev->pci_ops.write = ssb_gige_pci_write_config;
220 +
221 + dev->io_resource.name = SSB_GIGE_IO_RES_NAME;
222 + dev->io_resource.start = 0x800;
223 + dev->io_resource.end = 0x8FF;
224 + dev->io_resource.flags = IORESOURCE_IO | IORESOURCE_PCI_FIXED;
225 +
226 + if (!ssb_device_is_enabled(sdev))
227 + ssb_device_enable(sdev, 0);
228 +
229 + /* Setup BAR0. This is a 64k MMIO region. */
230 + base = ssb_admatch_base(ssb_read32(sdev, SSB_ADMATCH1));
231 + gige_pcicfg_write32(dev, PCI_BASE_ADDRESS_0, base);
232 + gige_pcicfg_write32(dev, PCI_BASE_ADDRESS_1, 0);
233 +
234 + dev->mem_resource.name = SSB_GIGE_MEM_RES_NAME;
235 + dev->mem_resource.start = base;
236 + dev->mem_resource.end = base + 0x10000 - 1;
237 + dev->mem_resource.flags = IORESOURCE_MEM | IORESOURCE_PCI_FIXED;
238 +
239 + /* Enable the memory region. */
240 + gige_pcicfg_write16(dev, PCI_COMMAND,
241 + gige_pcicfg_read16(dev, PCI_COMMAND)
242 + | PCI_COMMAND_MEMORY);
243 +
244 + /* Write flushing is controlled by the Flush Status Control register.
245 + * We want to flush every register write with a timeout and we want
246 + * to disable the IRQ mask while flushing to avoid concurrency.
247 + * Note that automatic write flushing does _not_ work from
248 + * an IRQ handler. The driver must flush manually by reading a register.
249 + */
250 + gige_write32(dev, SSB_GIGE_SHIM_FLUSHSTAT, 0x00000068);
251 +
252 + /* Check if we have an RGMII or GMII PHY-bus.
253 + * On RGMII do not bypass the DLLs */
254 + tmslow = ssb_read32(sdev, SSB_TMSLOW);
255 + tmshigh = ssb_read32(sdev, SSB_TMSHIGH);
256 + if (tmshigh & SSB_GIGE_TMSHIGH_RGMII) {
257 + tmslow &= ~SSB_GIGE_TMSLOW_TXBYPASS;
258 + tmslow &= ~SSB_GIGE_TMSLOW_RXBYPASS;
259 + dev->has_rgmii = 1;
260 + } else {
261 + tmslow |= SSB_GIGE_TMSLOW_TXBYPASS;
262 + tmslow |= SSB_GIGE_TMSLOW_RXBYPASS;
263 + dev->has_rgmii = 0;
264 + }
265 + tmslow |= SSB_GIGE_TMSLOW_DLLEN;
266 + ssb_write32(sdev, SSB_TMSLOW, tmslow);
267 +
268 + ssb_set_drvdata(sdev, dev);
269 + register_pci_controller(&dev->pci_controller);
270 +
271 + return 0;
272 +}
273 +
274 +bool pdev_is_ssb_gige_core(struct pci_dev *pdev)
275 +{
276 + if (!pdev->resource[0].name)
277 + return 0;
278 + return (strcmp(pdev->resource[0].name, SSB_GIGE_MEM_RES_NAME) == 0);
279 +}
280 +EXPORT_SYMBOL(pdev_is_ssb_gige_core);
281 +
282 +int ssb_gige_pcibios_plat_dev_init(struct ssb_device *sdev,
283 + struct pci_dev *pdev)
284 +{
285 + struct ssb_gige *dev = ssb_get_drvdata(sdev);
286 + struct resource *res;
287 +
288 + if (pdev->bus->ops != &dev->pci_ops) {
289 + /* The PCI device is not on this SSB GigE bridge device. */
290 + return -ENODEV;
291 + }
292 +
293 + /* Fixup the PCI resources. */
294 + res = &(pdev->resource[0]);
295 + res->flags = IORESOURCE_MEM | IORESOURCE_PCI_FIXED;
296 + res->name = dev->mem_resource.name;
297 + res->start = dev->mem_resource.start;
298 + res->end = dev->mem_resource.end;
299 +
300 + /* Fixup interrupt lines. */
301 + pdev->irq = ssb_mips_irq(sdev) + 2;
302 + pci_write_config_byte(pdev, PCI_INTERRUPT_LINE, pdev->irq);
303 +
304 + return 0;
305 +}
306 +
307 +int ssb_gige_map_irq(struct ssb_device *sdev,
308 + const struct pci_dev *pdev)
309 +{
310 + struct ssb_gige *dev = ssb_get_drvdata(sdev);
311 +
312 + if (pdev->bus->ops != &dev->pci_ops) {
313 + /* The PCI device is not on this SSB GigE bridge device. */
314 + return -ENODEV;
315 + }
316 +
317 + return ssb_mips_irq(sdev) + 2;
318 +}
319 +
320 +static struct ssb_driver ssb_gige_driver = {
321 + .name = "BCM-GigE",
322 + .id_table = ssb_gige_tbl,
323 + .probe = ssb_gige_probe,
324 +};
325 +
326 +int ssb_gige_init(void)
327 +{
328 + return ssb_driver_register(&ssb_gige_driver);
329 +}
330 Index: linux-2.6.25.4/include/linux/ssb/ssb_driver_gige.h
331 ===================================================================
332 --- /dev/null
333 +++ linux-2.6.25.4/include/linux/ssb/ssb_driver_gige.h
334 @@ -0,0 +1,174 @@
335 +#ifndef LINUX_SSB_DRIVER_GIGE_H_
336 +#define LINUX_SSB_DRIVER_GIGE_H_
337 +
338 +#include <linux/ssb/ssb.h>
339 +#include <linux/pci.h>
340 +#include <linux/spinlock.h>
341 +
342 +
343 +#ifdef CONFIG_SSB_DRIVER_GIGE
344 +
345 +
346 +#define SSB_GIGE_PCIIO 0x0000 /* PCI I/O Registers (1024 bytes) */
347 +#define SSB_GIGE_RESERVED 0x0400 /* Reserved (1024 bytes) */
348 +#define SSB_GIGE_PCICFG 0x0800 /* PCI config space (256 bytes) */
349 +#define SSB_GIGE_SHIM_FLUSHSTAT 0x0C00 /* PCI to OCP: Flush status control (32bit) */
350 +#define SSB_GIGE_SHIM_FLUSHRDA 0x0C04 /* PCI to OCP: Flush read address (32bit) */
351 +#define SSB_GIGE_SHIM_FLUSHTO 0x0C08 /* PCI to OCP: Flush timeout counter (32bit) */
352 +#define SSB_GIGE_SHIM_BARRIER 0x0C0C /* PCI to OCP: Barrier register (32bit) */
353 +#define SSB_GIGE_SHIM_MAOCPSI 0x0C10 /* PCI to OCP: MaocpSI Control (32bit) */
354 +#define SSB_GIGE_SHIM_SIOCPMA 0x0C14 /* PCI to OCP: SiocpMa Control (32bit) */
355 +
356 +/* TM Status High flags */
357 +#define SSB_GIGE_TMSHIGH_RGMII 0x00010000 /* Have an RGMII PHY-bus */
358 +/* TM Status Low flags */
359 +#define SSB_GIGE_TMSLOW_TXBYPASS 0x00080000 /* TX bypass (no delay) */
360 +#define SSB_GIGE_TMSLOW_RXBYPASS 0x00100000 /* RX bypass (no delay) */
361 +#define SSB_GIGE_TMSLOW_DLLEN 0x01000000 /* Enable DLL controls */
362 +
363 +/* Boardflags (low) */
364 +#define SSB_GIGE_BFL_ROBOSWITCH 0x0010
365 +
366 +
367 +#define SSB_GIGE_MEM_RES_NAME "SSB Broadcom 47xx GigE memory"
368 +#define SSB_GIGE_IO_RES_NAME "SSB Broadcom 47xx GigE I/O"
369 +
370 +struct ssb_gige {
371 + struct ssb_device *dev;
372 +
373 + spinlock_t lock;
374 +
375 + /* True, if the device has an RGMII bus.
376 + * False, if the device has a GMII bus. */
377 + bool has_rgmii;
378 +
379 + /* The PCI controller device. */
380 + struct pci_controller pci_controller;
381 + struct pci_ops pci_ops;
382 + struct resource mem_resource;
383 + struct resource io_resource;
384 +};
385 +
386 +/* Check whether a PCI device is a SSB Gigabit Ethernet core. */
387 +extern bool pdev_is_ssb_gige_core(struct pci_dev *pdev);
388 +
389 +/* Convert a pci_dev pointer to a ssb_gige pointer. */
390 +static inline struct ssb_gige * pdev_to_ssb_gige(struct pci_dev *pdev)
391 +{
392 + if (!pdev_is_ssb_gige_core(pdev))
393 + return NULL;
394 + return container_of(pdev->bus->ops, struct ssb_gige, pci_ops);
395 +}
396 +
397 +/* Returns whether the PHY is connected by an RGMII bus. */
398 +static inline bool ssb_gige_is_rgmii(struct pci_dev *pdev)
399 +{
400 + struct ssb_gige *dev = pdev_to_ssb_gige(pdev);
401 + return (dev ? dev->has_rgmii : 0);
402 +}
403 +
404 +/* Returns whether we have a Roboswitch. */
405 +static inline bool ssb_gige_have_roboswitch(struct pci_dev *pdev)
406 +{
407 + struct ssb_gige *dev = pdev_to_ssb_gige(pdev);
408 + if (dev)
409 + return !!(dev->dev->bus->sprom.boardflags_lo &
410 + SSB_GIGE_BFL_ROBOSWITCH);
411 + return 0;
412 +}
413 +
414 +/* Returns whether we can only do one DMA at once. */
415 +static inline bool ssb_gige_one_dma_at_once(struct pci_dev *pdev)
416 +{
417 + struct ssb_gige *dev = pdev_to_ssb_gige(pdev);
418 + if (dev)
419 + return ((dev->dev->bus->chip_id == 0x4785) &&
420 + (dev->dev->bus->chip_rev < 2));
421 + return 0;
422 +}
423 +
424 +/* Returns whether we must flush posted writes. */
425 +static inline bool ssb_gige_must_flush_posted_writes(struct pci_dev *pdev)
426 +{
427 + struct ssb_gige *dev = pdev_to_ssb_gige(pdev);
428 + if (dev)
429 + return (dev->dev->bus->chip_id == 0x4785);
430 + return 0;
431 +}
432 +
433 +extern char * nvram_get(const char *name);
434 +/* Get the device MAC address */
435 +static inline void ssb_gige_get_macaddr(struct pci_dev *pdev, u8 *macaddr)
436 +{
437 +#ifdef CONFIG_BCM947XX
438 + char *res = nvram_get("et0macaddr");
439 + if (res)
440 + memcpy(macaddr, res, 6);
441 +#endif
442 +}
443 +
444 +extern int ssb_gige_pcibios_plat_dev_init(struct ssb_device *sdev,
445 + struct pci_dev *pdev);
446 +extern int ssb_gige_map_irq(struct ssb_device *sdev,
447 + const struct pci_dev *pdev);
448 +
449 +/* The GigE driver is not a standalone module, because we don't have support
450 + * for unregistering the driver. So we could not unload the module anyway. */
451 +extern int ssb_gige_init(void);
452 +static inline void ssb_gige_exit(void)
453 +{
454 + /* Currently we can not unregister the GigE driver,
455 + * because we can not unregister the PCI bridge. */
456 + BUG();
457 +}
458 +
459 +
460 +#else /* CONFIG_SSB_DRIVER_GIGE */
461 +/* Gigabit Ethernet driver disabled */
462 +
463 +
464 +static inline int ssb_gige_pcibios_plat_dev_init(struct ssb_device *sdev,
465 + struct pci_dev *pdev)
466 +{
467 + return -ENOSYS;
468 +}
469 +static inline int ssb_gige_map_irq(struct ssb_device *sdev,
470 + const struct pci_dev *pdev)
471 +{
472 + return -ENOSYS;
473 +}
474 +static inline int ssb_gige_init(void)
475 +{
476 + return 0;
477 +}
478 +static inline void ssb_gige_exit(void)
479 +{
480 +}
481 +
482 +static inline bool pdev_is_ssb_gige_core(struct pci_dev *pdev)
483 +{
484 + return 0;
485 +}
486 +static inline struct ssb_gige * pdev_to_ssb_gige(struct pci_dev *pdev)
487 +{
488 + return NULL;
489 +}
490 +static inline bool ssb_gige_is_rgmii(struct pci_dev *pdev)
491 +{
492 + return 0;
493 +}
494 +static inline bool ssb_gige_have_roboswitch(struct pci_dev *pdev)
495 +{
496 + return 0;
497 +}
498 +static inline bool ssb_gige_one_dma_at_once(struct pci_dev *pdev)
499 +{
500 + return 0;
501 +}
502 +static inline bool ssb_gige_must_flush_posted_writes(struct pci_dev *pdev)
503 +{
504 + return 0;
505 +}
506 +
507 +#endif /* CONFIG_SSB_DRIVER_GIGE */
508 +#endif /* LINUX_SSB_DRIVER_GIGE_H_ */
509 Index: linux-2.6.25.4/drivers/ssb/driver_pcicore.c
510 ===================================================================
511 --- linux-2.6.25.4.orig/drivers/ssb/driver_pcicore.c
512 +++ linux-2.6.25.4/drivers/ssb/driver_pcicore.c
513 @@ -60,78 +60,6 @@ static DEFINE_SPINLOCK(cfgspace_lock);
514 /* Core to access the external PCI config space. Can only have one. */
515 static struct ssb_pcicore *extpci_core;
516
517 -static u32 ssb_pcicore_pcibus_iobase = 0x100;
518 -static u32 ssb_pcicore_pcibus_membase = SSB_PCI_DMA;
519 -
520 -int pcibios_plat_dev_init(struct pci_dev *d)
521 -{
522 - struct resource *res;
523 - int pos, size;
524 - u32 *base;
525 -
526 - ssb_printk(KERN_INFO "PCI: Fixing up device %s\n",
527 - pci_name(d));
528 -
529 - /* Fix up resource bases */
530 - for (pos = 0; pos < 6; pos++) {
531 - res = &d->resource[pos];
532 - if (res->flags & IORESOURCE_IO)
533 - base = &ssb_pcicore_pcibus_iobase;
534 - else
535 - base = &ssb_pcicore_pcibus_membase;
536 - res->flags |= IORESOURCE_PCI_FIXED;
537 - if (res->end) {
538 - size = res->end - res->start + 1;
539 - if (*base & (size - 1))
540 - *base = (*base + size) & ~(size - 1);
541 - res->start = *base;
542 - res->end = res->start + size - 1;
543 - *base += size;
544 - pci_write_config_dword(d, PCI_BASE_ADDRESS_0 + (pos << 2), res->start);
545 - }
546 - /* Fix up PCI bridge BAR0 only */
547 - if (d->bus->number == 0 && PCI_SLOT(d->devfn) == 0)
548 - break;
549 - }
550 - /* Fix up interrupt lines */
551 - d->irq = ssb_mips_irq(extpci_core->dev) + 2;
552 - pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
553 -
554 - return 0;
555 -}
556 -
557 -static void __init ssb_fixup_pcibridge(struct pci_dev *dev)
558 -{
559 - u8 lat;
560 -
561 - if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) != 0)
562 - return;
563 -
564 - ssb_printk(KERN_INFO "PCI: Fixing up bridge %s\n", pci_name(dev));
565 -
566 - /* Enable PCI bridge bus mastering and memory space */
567 - pci_set_master(dev);
568 - if (pcibios_enable_device(dev, ~0) < 0) {
569 - ssb_printk(KERN_ERR "PCI: SSB bridge enable failed\n");
570 - return;
571 - }
572 -
573 - /* Enable PCI bridge BAR1 prefetch and burst */
574 - pci_write_config_dword(dev, SSB_BAR1_CONTROL, 3);
575 -
576 - /* Make sure our latency is high enough to handle the devices behind us */
577 - lat = 168;
578 - ssb_printk(KERN_INFO "PCI: Fixing latency timer of device %s to %u\n",
579 - pci_name(dev), lat);
580 - pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
581 -}
582 -DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, ssb_fixup_pcibridge);
583 -
584 -int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
585 -{
586 - return ssb_mips_irq(extpci_core->dev) + 2;
587 -}
588 -
589 static u32 get_cfgspace_addr(struct ssb_pcicore *pc,
590 unsigned int bus, unsigned int dev,
591 unsigned int func, unsigned int off)
592 @@ -320,6 +248,95 @@ static struct pci_controller ssb_pcicore
593 .mem_offset = 0x24000000,
594 };
595
596 +static u32 ssb_pcicore_pcibus_iobase = 0x100;
597 +static u32 ssb_pcicore_pcibus_membase = SSB_PCI_DMA;
598 +
599 +/* This function is called when doing a pci_enable_device().
600 + * We must first check if the device is a device on the PCI-core bridge. */
601 +int ssb_pcicore_plat_dev_init(struct pci_dev *d)
602 +{
603 + struct resource *res;
604 + int pos, size;
605 + u32 *base;
606 +
607 + if (d->bus->ops != &ssb_pcicore_pciops) {
608 + /* This is not a device on the PCI-core bridge. */
609 + return -ENODEV;
610 + }
611 +
612 + ssb_printk(KERN_INFO "PCI: Fixing up device %s\n",
613 + pci_name(d));
614 +
615 + /* Fix up resource bases */
616 + for (pos = 0; pos < 6; pos++) {
617 + res = &d->resource[pos];
618 + if (res->flags & IORESOURCE_IO)
619 + base = &ssb_pcicore_pcibus_iobase;
620 + else
621 + base = &ssb_pcicore_pcibus_membase;
622 + res->flags |= IORESOURCE_PCI_FIXED;
623 + if (res->end) {
624 + size = res->end - res->start + 1;
625 + if (*base & (size - 1))
626 + *base = (*base + size) & ~(size - 1);
627 + res->start = *base;
628 + res->end = res->start + size - 1;
629 + *base += size;
630 + pci_write_config_dword(d, PCI_BASE_ADDRESS_0 + (pos << 2), res->start);
631 + }
632 + /* Fix up PCI bridge BAR0 only */
633 + if (d->bus->number == 0 && PCI_SLOT(d->devfn) == 0)
634 + break;
635 + }
636 + /* Fix up interrupt lines */
637 + d->irq = ssb_mips_irq(extpci_core->dev) + 2;
638 + pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
639 +
640 + return 0;
641 +}
642 +
643 +/* Early PCI fixup for a device on the PCI-core bridge. */
644 +static void ssb_pcicore_fixup_pcibridge(struct pci_dev *dev)
645 +{
646 + u8 lat;
647 +
648 + if (dev->bus->ops != &ssb_pcicore_pciops) {
649 + /* This is not a device on the PCI-core bridge. */
650 + return;
651 + }
652 + if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) != 0)
653 + return;
654 +
655 + ssb_printk(KERN_INFO "PCI: Fixing up bridge %s\n", pci_name(dev));
656 +
657 + /* Enable PCI bridge bus mastering and memory space */
658 + pci_set_master(dev);
659 + if (pcibios_enable_device(dev, ~0) < 0) {
660 + ssb_printk(KERN_ERR "PCI: SSB bridge enable failed\n");
661 + return;
662 + }
663 +
664 + /* Enable PCI bridge BAR1 prefetch and burst */
665 + pci_write_config_dword(dev, SSB_BAR1_CONTROL, 3);
666 +
667 + /* Make sure our latency is high enough to handle the devices behind us */
668 + lat = 168;
669 + ssb_printk(KERN_INFO "PCI: Fixing latency timer of device %s to %u\n",
670 + pci_name(dev), lat);
671 + pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
672 +}
673 +DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, ssb_pcicore_fixup_pcibridge);
674 +
675 +/* PCI device IRQ mapping. */
676 +int ssb_pcicore_pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
677 +{
678 + if (dev->bus->ops != &ssb_pcicore_pciops) {
679 + /* This is not a device on the PCI-core bridge. */
680 + return -ENODEV;
681 + }
682 + return ssb_mips_irq(extpci_core->dev) + 2;
683 +}
684 +
685 static void ssb_pcicore_init_hostmode(struct ssb_pcicore *pc)
686 {
687 u32 val;
688 Index: linux-2.6.25.4/drivers/ssb/embedded.c
689 ===================================================================
690 --- linux-2.6.25.4.orig/drivers/ssb/embedded.c
691 +++ linux-2.6.25.4/drivers/ssb/embedded.c
692 @@ -10,6 +10,9 @@
693
694 #include <linux/ssb/ssb.h>
695 #include <linux/ssb/ssb_embedded.h>
696 +#include <linux/ssb/ssb_driver_pci.h>
697 +#include <linux/ssb/ssb_driver_gige.h>
698 +#include <linux/pci.h>
699
700 #include "ssb_private.h"
701
702 @@ -130,3 +133,90 @@ u32 ssb_gpio_polarity(struct ssb_bus *bu
703 return res;
704 }
705 EXPORT_SYMBOL(ssb_gpio_polarity);
706 +
707 +#ifdef CONFIG_SSB_DRIVER_GIGE
708 +static int gige_pci_init_callback(struct ssb_bus *bus, unsigned long data)
709 +{
710 + struct pci_dev *pdev = (struct pci_dev *)data;
711 + struct ssb_device *dev;
712 + unsigned int i;
713 + int res;
714 +
715 + for (i = 0; i < bus->nr_devices; i++) {
716 + dev = &(bus->devices[i]);
717 + if (dev->id.coreid != SSB_DEV_ETHERNET_GBIT)
718 + continue;
719 + if (!dev->dev ||
720 + !dev->dev->driver ||
721 + !device_is_registered(dev->dev))
722 + continue;
723 + res = ssb_gige_pcibios_plat_dev_init(dev, pdev);
724 + if (res >= 0)
725 + return res;
726 + }
727 +
728 + return -ENODEV;
729 +}
730 +#endif /* CONFIG_SSB_DRIVER_GIGE */
731 +
732 +int ssb_pcibios_plat_dev_init(struct pci_dev *dev)
733 +{
734 + int err;
735 +
736 + err = ssb_pcicore_plat_dev_init(dev);
737 + if (!err)
738 + return 0;
739 +#ifdef CONFIG_SSB_DRIVER_GIGE
740 + err = ssb_for_each_bus_call((unsigned long)dev, gige_pci_init_callback);
741 + if (err >= 0)
742 + return err;
743 +#endif
744 + /* This is not a PCI device on any SSB device. */
745 +
746 + return -ENODEV;
747 +}
748 +
749 +#ifdef CONFIG_SSB_DRIVER_GIGE
750 +static int gige_map_irq_callback(struct ssb_bus *bus, unsigned long data)
751 +{
752 + const struct pci_dev *pdev = (const struct pci_dev *)data;
753 + struct ssb_device *dev;
754 + unsigned int i;
755 + int res;
756 +
757 + for (i = 0; i < bus->nr_devices; i++) {
758 + dev = &(bus->devices[i]);
759 + if (dev->id.coreid != SSB_DEV_ETHERNET_GBIT)
760 + continue;
761 + if (!dev->dev ||
762 + !dev->dev->driver ||
763 + !device_is_registered(dev->dev))
764 + continue;
765 + res = ssb_gige_map_irq(dev, pdev);
766 + if (res >= 0)
767 + return res;
768 + }
769 +
770 + return -ENODEV;
771 +}
772 +#endif /* CONFIG_SSB_DRIVER_GIGE */
773 +
774 +int ssb_pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
775 +{
776 + int res;
777 +
778 + /* Check if this PCI device is a device on a SSB bus or device
779 + * and return the IRQ number for it. */
780 +
781 + res = ssb_pcicore_pcibios_map_irq(dev, slot, pin);
782 + if (res >= 0)
783 + return res;
784 +#ifdef CONFIG_SSB_DRIVER_GIGE
785 + res = ssb_for_each_bus_call((unsigned long)dev, gige_map_irq_callback);
786 + if (res >= 0)
787 + return res;
788 +#endif
789 + /* This is not a PCI device on any SSB device. */
790 +
791 + return -ENODEV;
792 +}
793 Index: linux-2.6.25.4/include/linux/ssb/ssb.h
794 ===================================================================
795 --- linux-2.6.25.4.orig/include/linux/ssb/ssb.h
796 +++ linux-2.6.25.4/include/linux/ssb/ssb.h
797 @@ -426,5 +426,12 @@ extern int ssb_bus_powerup(struct ssb_bu
798 extern u32 ssb_admatch_base(u32 adm);
799 extern u32 ssb_admatch_size(u32 adm);
800
801 +/* PCI device mapping and fixup routines.
802 + * Called from the architecture pcibios init code.
803 + * These are only available on SSB_EMBEDDED configurations. */
804 +#ifdef CONFIG_SSB_EMBEDDED
805 +int ssb_pcibios_plat_dev_init(struct pci_dev *dev);
806 +int ssb_pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
807 +#endif /* CONFIG_SSB_EMBEDDED */
808
809 #endif /* LINUX_SSB_H_ */
810 Index: linux-2.6.25.4/include/linux/ssb/ssb_driver_pci.h
811 ===================================================================
812 --- linux-2.6.25.4.orig/include/linux/ssb/ssb_driver_pci.h
813 +++ linux-2.6.25.4/include/linux/ssb/ssb_driver_pci.h
814 @@ -1,6 +1,11 @@
815 #ifndef LINUX_SSB_PCICORE_H_
816 #define LINUX_SSB_PCICORE_H_
817
818 +#include <linux/types.h>
819 +
820 +struct pci_dev;
821 +
822 +
823 #ifdef CONFIG_SSB_DRIVER_PCICORE
824
825 /* PCI core registers. */
826 @@ -88,6 +93,9 @@ extern void ssb_pcicore_init(struct ssb_
827 extern int ssb_pcicore_dev_irqvecs_enable(struct ssb_pcicore *pc,
828 struct ssb_device *dev);
829
830 +int ssb_pcicore_plat_dev_init(struct pci_dev *d);
831 +int ssb_pcicore_pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
832 +
833
834 #else /* CONFIG_SSB_DRIVER_PCICORE */
835
836 @@ -107,5 +115,16 @@ int ssb_pcicore_dev_irqvecs_enable(struc
837 return 0;
838 }
839
840 +static inline
841 +int ssb_pcicore_plat_dev_init(struct pci_dev *d)
842 +{
843 + return -ENODEV;
844 +}
845 +static inline
846 +int ssb_pcicore_pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
847 +{
848 + return -ENODEV;
849 +}
850 +
851 #endif /* CONFIG_SSB_DRIVER_PCICORE */
852 #endif /* LINUX_SSB_PCICORE_H_ */
853 Index: linux-2.6.25.4/drivers/ssb/main.c
854 ===================================================================
855 --- linux-2.6.25.4.orig/drivers/ssb/main.c
856 +++ linux-2.6.25.4/drivers/ssb/main.c
857 @@ -14,6 +14,7 @@
858 #include <linux/io.h>
859 #include <linux/ssb/ssb.h>
860 #include <linux/ssb/ssb_regs.h>
861 +#include <linux/ssb/ssb_driver_gige.h>
862 #include <linux/dma-mapping.h>
863 #include <linux/pci.h>
864
865 @@ -68,6 +69,25 @@ found:
866 }
867 #endif /* CONFIG_SSB_PCIHOST */
868
869 +int ssb_for_each_bus_call(unsigned long data,
870 + int (*func)(struct ssb_bus *bus, unsigned long data))
871 +{
872 + struct ssb_bus *bus;
873 + int res;
874 +
875 + ssb_buses_lock();
876 + list_for_each_entry(bus, &buses, list) {
877 + res = func(bus, data);
878 + if (res >= 0) {
879 + ssb_buses_unlock();
880 + return res;
881 + }
882 + }
883 + ssb_buses_unlock();
884 +
885 + return -ENODEV;
886 +}
887 +
888 static struct ssb_device *ssb_device_get(struct ssb_device *dev)
889 {
890 if (dev)
891 @@ -1181,7 +1201,14 @@ static int __init ssb_modinit(void)
892 err = b43_pci_ssb_bridge_init();
893 if (err) {
894 ssb_printk(KERN_ERR "Broadcom 43xx PCI-SSB-bridge "
895 - "initialization failed");
896 + "initialization failed\n");
897 + /* don't fail SSB init because of this */
898 + err = 0;
899 + }
900 + err = ssb_gige_init();
901 + if (err) {
902 + ssb_printk(KERN_ERR "SSB Broadcom Gigabit Ethernet "
903 + "driver initialization failed\n");
904 /* don't fail SSB init because of this */
905 err = 0;
906 }
907 @@ -1195,6 +1222,7 @@ fs_initcall(ssb_modinit);
908
909 static void __exit ssb_modexit(void)
910 {
911 + ssb_gige_exit();
912 b43_pci_ssb_bridge_exit();
913 bus_unregister(&ssb_bustype);
914 }
915 Index: linux-2.6.25.4/drivers/ssb/ssb_private.h
916 ===================================================================
917 --- linux-2.6.25.4.orig/drivers/ssb/ssb_private.h
918 +++ linux-2.6.25.4/drivers/ssb/ssb_private.h
919 @@ -118,6 +118,8 @@ extern u32 ssb_calc_clock_rate(u32 pllty
920 extern int ssb_devices_freeze(struct ssb_bus *bus);
921 extern int ssb_devices_thaw(struct ssb_bus *bus);
922 extern struct ssb_bus *ssb_pci_dev_to_bus(struct pci_dev *pdev);
923 +int ssb_for_each_bus_call(unsigned long data,
924 + int (*func)(struct ssb_bus *bus, unsigned long data));
925
926 /* b43_pci_bridge.c */
927 #ifdef CONFIG_SSB_B43_PCI_BRIDGE
928 Index: linux-2.6.25.4/drivers/net/tg3.c
929 ===================================================================
930 --- linux-2.6.25.4.orig/drivers/net/tg3.c
931 +++ linux-2.6.25.4/drivers/net/tg3.c
932 @@ -38,6 +38,7 @@
933 #include <linux/workqueue.h>
934 #include <linux/prefetch.h>
935 #include <linux/dma-mapping.h>
936 +#include <linux/ssb/ssb_driver_gige.h>
937
938 #include <net/checksum.h>
939 #include <net/ip.h>
940 @@ -425,8 +426,9 @@ static void _tw32_flush(struct tg3 *tp,
941 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
942 {
943 tp->write32_mbox(tp, off, val);
944 - if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
945 - !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
946 + if ((tp->tg3_flags3 & TG3_FLG3_FLUSH_POSTED_WRITES) ||
947 + (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
948 + !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND)))
949 tp->read32_mbox(tp, off);
950 }
951
952 @@ -706,7 +708,7 @@ static void tg3_switch_clocks(struct tg3
953
954 #define PHY_BUSY_LOOPS 5000
955
956 -static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
957 +static int __tg3_readphy(struct tg3 *tp, unsigned int phy_addr, int reg, u32 *val)
958 {
959 u32 frame_val;
960 unsigned int loops;
961 @@ -720,7 +722,7 @@ static int tg3_readphy(struct tg3 *tp, i
962
963 *val = 0x0;
964
965 - frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
966 + frame_val = ((phy_addr << MI_COM_PHY_ADDR_SHIFT) &
967 MI_COM_PHY_ADDR_MASK);
968 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
969 MI_COM_REG_ADDR_MASK);
970 @@ -755,7 +757,12 @@ static int tg3_readphy(struct tg3 *tp, i
971 return ret;
972 }
973
974 -static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
975 +static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
976 +{
977 + return __tg3_readphy(tp, PHY_ADDR, reg, val);
978 +}
979 +
980 +static int __tg3_writephy(struct tg3 *tp, unsigned int phy_addr, int reg, u32 val)
981 {
982 u32 frame_val;
983 unsigned int loops;
984 @@ -771,7 +778,7 @@ static int tg3_writephy(struct tg3 *tp,
985 udelay(80);
986 }
987
988 - frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
989 + frame_val = ((phy_addr << MI_COM_PHY_ADDR_SHIFT) &
990 MI_COM_PHY_ADDR_MASK);
991 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
992 MI_COM_REG_ADDR_MASK);
993 @@ -804,6 +811,11 @@ static int tg3_writephy(struct tg3 *tp,
994 return ret;
995 }
996
997 +static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
998 +{
999 + return __tg3_writephy(tp, PHY_ADDR, reg, val);
1000 +}
1001 +
1002 static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1003 {
1004 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1005 @@ -2250,6 +2262,14 @@ static int tg3_setup_copper_phy(struct t
1006 }
1007 }
1008
1009 + if (tp->tg3_flags & TG3_FLG3_ROBOSWITCH) {
1010 + current_link_up = 1;
1011 + current_speed = SPEED_1000; //FIXME
1012 + current_duplex = DUPLEX_FULL;
1013 + tp->link_config.active_speed = current_speed;
1014 + tp->link_config.active_duplex = current_duplex;
1015 + }
1016 +
1017 if (current_link_up == 1 &&
1018 tp->link_config.active_duplex == DUPLEX_FULL)
1019 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1020 @@ -5197,6 +5217,11 @@ static int tg3_poll_fw(struct tg3 *tp)
1021 int i;
1022 u32 val;
1023
1024 + if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE) {
1025 + /* We don't use firmware. */
1026 + return 0;
1027 + }
1028 +
1029 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1030 /* Wait up to 20ms for init done. */
1031 for (i = 0; i < 200; i++) {
1032 @@ -5435,6 +5460,14 @@ static int tg3_chip_reset(struct tg3 *tp
1033 tw32(0x5000, 0x400);
1034 }
1035
1036 + if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE) {
1037 + /* BCM4785: In order to avoid repercussions from using potentially
1038 + * defective internal ROM, stop the Rx RISC CPU, which is not
1039 + * required. */
1040 + tg3_stop_fw(tp);
1041 + tg3_halt_cpu(tp, RX_CPU_BASE);
1042 + }
1043 +
1044 tw32(GRC_MODE, tp->grc_mode);
1045
1046 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
1047 @@ -5704,9 +5737,12 @@ static int tg3_halt_cpu(struct tg3 *tp,
1048 return -ENODEV;
1049 }
1050
1051 - /* Clear firmware's nvram arbitration. */
1052 - if (tp->tg3_flags & TG3_FLAG_NVRAM)
1053 - tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
1054 + if (!(tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE)) {
1055 + /* Clear firmware's nvram arbitration. */
1056 + if (tp->tg3_flags & TG3_FLAG_NVRAM)
1057 + tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
1058 + }
1059 +
1060 return 0;
1061 }
1062
1063 @@ -5787,6 +5823,11 @@ static int tg3_load_5701_a0_firmware_fix
1064 struct fw_info info;
1065 int err, i;
1066
1067 + if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE) {
1068 + /* We don't use firmware. */
1069 + return 0;
1070 + }
1071 +
1072 info.text_base = TG3_FW_TEXT_ADDR;
1073 info.text_len = TG3_FW_TEXT_LEN;
1074 info.text_data = &tg3FwText[0];
1075 @@ -6345,6 +6386,11 @@ static int tg3_load_tso_firmware(struct
1076 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
1077 int err, i;
1078
1079 + if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE) {
1080 + /* We don't use firmware. */
1081 + return 0;
1082 + }
1083 +
1084 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
1085 return 0;
1086
1087 @@ -7306,6 +7352,11 @@ static void tg3_timer(unsigned long __op
1088
1089 spin_lock(&tp->lock);
1090
1091 + if (tp->tg3_flags3 & TG3_FLG3_FLUSH_POSTED_WRITES) {
1092 + /* BCM4785: Flush posted writes from GbE to host memory. */
1093 + tr32(HOSTCC_MODE);
1094 + }
1095 +
1096 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
1097 /* All of this garbage is because when using non-tagged
1098 * IRQ status the mailbox/status_block protocol the chip
1099 @@ -8906,6 +8957,11 @@ static int tg3_test_nvram(struct tg3 *tp
1100 __le32 *buf;
1101 int i, j, k, err = 0, size;
1102
1103 + if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE) {
1104 + /* We don't have NVRAM. */
1105 + return 0;
1106 + }
1107 +
1108 if (tg3_nvram_read_swab(tp, 0, &magic) != 0)
1109 return -EIO;
1110
1111 @@ -9689,7 +9745,7 @@ static int tg3_ioctl(struct net_device *
1112 return -EAGAIN;
1113
1114 spin_lock_bh(&tp->lock);
1115 - err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
1116 + err = __tg3_readphy(tp, data->phy_id & 0x1f, data->reg_num & 0x1f, &mii_regval);
1117 spin_unlock_bh(&tp->lock);
1118
1119 data->val_out = mii_regval;
1120 @@ -9708,7 +9764,7 @@ static int tg3_ioctl(struct net_device *
1121 return -EAGAIN;
1122
1123 spin_lock_bh(&tp->lock);
1124 - err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
1125 + err = __tg3_writephy(tp, data->phy_id & 0x1f, data->reg_num & 0x1f, data->val_in);
1126 spin_unlock_bh(&tp->lock);
1127
1128 return err;
1129 @@ -10177,6 +10233,12 @@ static void __devinit tg3_get_5906_nvram
1130 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
1131 static void __devinit tg3_nvram_init(struct tg3 *tp)
1132 {
1133 + if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE) {
1134 + /* No NVRAM and EEPROM on the SSB Broadcom GigE core. */
1135 + tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
1136 + return;
1137 + }
1138 +
1139 tw32_f(GRC_EEPROM_ADDR,
1140 (EEPROM_ADDR_FSM_RESET |
1141 (EEPROM_DEFAULT_CLOCK_PERIOD <<
1142 @@ -10317,6 +10379,9 @@ static int tg3_nvram_read(struct tg3 *tp
1143 {
1144 int ret;
1145
1146 + if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE)
1147 + return -ENODEV;
1148 +
1149 if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
1150 return tg3_nvram_read_using_eeprom(tp, offset, val);
1151
1152 @@ -10563,6 +10628,9 @@ static int tg3_nvram_write_block(struct
1153 {
1154 int ret;
1155
1156 + if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE)
1157 + return -ENODEV;
1158 +
1159 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
1160 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
1161 ~GRC_LCLCTRL_GPIO_OUTPUT1);
1162 @@ -11610,7 +11678,6 @@ static int __devinit tg3_get_invariants(
1163 tp->write32 = tg3_write_flush_reg32;
1164 }
1165
1166 -
1167 if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
1168 (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
1169 tp->write32_tx_mbox = tg3_write32_tx_mbox;
1170 @@ -11646,6 +11713,11 @@ static int __devinit tg3_get_invariants(
1171 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
1172 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
1173
1174 + if (tp->tg3_flags3 & TG3_FLG3_FLUSH_POSTED_WRITES) {
1175 + tp->write32_tx_mbox = tg3_write_flush_reg32;
1176 + tp->write32_rx_mbox = tg3_write_flush_reg32;
1177 + }
1178 +
1179 /* Get eeprom hw config before calling tg3_set_power_state().
1180 * In particular, the TG3_FLG2_IS_NIC flag must be
1181 * determined before calling tg3_set_power_state() so that
1182 @@ -12017,6 +12089,10 @@ static int __devinit tg3_get_device_addr
1183 }
1184
1185 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
1186 + if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE)
1187 + ssb_gige_get_macaddr(tp->pdev, &dev->dev_addr[0]);
1188 + }
1189 + if (!is_valid_ether_addr(&dev->dev_addr[0])) {
1190 #ifdef CONFIG_SPARC
1191 if (!tg3_get_default_macaddr_sparc(tp))
1192 return 0;
1193 @@ -12508,6 +12584,7 @@ static char * __devinit tg3_phy_string(s
1194 case PHY_ID_BCM5704: return "5704";
1195 case PHY_ID_BCM5705: return "5705";
1196 case PHY_ID_BCM5750: return "5750";
1197 + case PHY_ID_BCM5750_2: return "5750-2";
1198 case PHY_ID_BCM5752: return "5752";
1199 case PHY_ID_BCM5714: return "5714";
1200 case PHY_ID_BCM5780: return "5780";
1201 @@ -12695,6 +12772,13 @@ static int __devinit tg3_init_one(struct
1202 tp->msg_enable = tg3_debug;
1203 else
1204 tp->msg_enable = TG3_DEF_MSG_ENABLE;
1205 + if (pdev_is_ssb_gige_core(pdev)) {
1206 + tp->tg3_flags3 |= TG3_FLG3_IS_SSB_CORE;
1207 + if (ssb_gige_must_flush_posted_writes(pdev))
1208 + tp->tg3_flags3 |= TG3_FLG3_FLUSH_POSTED_WRITES;
1209 + if (ssb_gige_have_roboswitch(pdev))
1210 + tp->tg3_flags3 |= TG3_FLG3_ROBOSWITCH;
1211 + }
1212
1213 /* The word/byte swap controls here control register access byte
1214 * swapping. DMA data byte swapping is controlled in the GRC_MODE
1215 Index: linux-2.6.25.4/drivers/net/tg3.h
1216 ===================================================================
1217 --- linux-2.6.25.4.orig/drivers/net/tg3.h
1218 +++ linux-2.6.25.4/drivers/net/tg3.h
1219 @@ -2477,6 +2477,9 @@ struct tg3 {
1220 #define TG3_FLG3_ENABLE_APE 0x00000002
1221 #define TG3_FLG3_5761_5784_AX_FIXES 0x00000004
1222 #define TG3_FLG3_5701_DMA_BUG 0x00000008
1223 +#define TG3_FLG3_IS_SSB_CORE 0x00000010
1224 +#define TG3_FLG3_FLUSH_POSTED_WRITES 0x00000020
1225 +#define TG3_FLG3_ROBOSWITCH 0x00000040
1226
1227 struct timer_list timer;
1228 u16 timer_counter;
1229 @@ -2532,6 +2535,7 @@ struct tg3 {
1230 #define PHY_ID_BCM5714 0x60008340
1231 #define PHY_ID_BCM5780 0x60008350
1232 #define PHY_ID_BCM5755 0xbc050cc0
1233 +#define PHY_ID_BCM5750_2 0xbc050cd0
1234 #define PHY_ID_BCM5787 0xbc050ce0
1235 #define PHY_ID_BCM5756 0xbc050ed0
1236 #define PHY_ID_BCM5784 0xbc050fa0
1237 @@ -2568,7 +2572,7 @@ struct tg3 {
1238 (X) == PHY_ID_BCM5780 || (X) == PHY_ID_BCM5787 || \
1239 (X) == PHY_ID_BCM5755 || (X) == PHY_ID_BCM5756 || \
1240 (X) == PHY_ID_BCM5906 || (X) == PHY_ID_BCM5761 || \
1241 - (X) == PHY_ID_BCM8002)
1242 + (X) == PHY_ID_BCM8002 || (X) == PHY_ID_BCM5750_2)
1243
1244 struct tg3_hw_stats *hw_stats;
1245 dma_addr_t stats_mapping;
1246 Index: linux-2.6.25.4/drivers/ssb/driver_mipscore.c
1247 ===================================================================
1248 --- linux-2.6.25.4.orig/drivers/ssb/driver_mipscore.c
1249 +++ linux-2.6.25.4/drivers/ssb/driver_mipscore.c
1250 @@ -212,6 +212,7 @@ void ssb_mipscore_init(struct ssb_mipsco
1251 /* fallthrough */
1252 case SSB_DEV_PCI:
1253 case SSB_DEV_ETHERNET:
1254 + case SSB_DEV_ETHERNET_GBIT:
1255 case SSB_DEV_80211:
1256 case SSB_DEV_USB20_HOST:
1257 /* These devices get their own IRQ line if available, the rest goes on IRQ0 */