bcm47xx: Add support for the 5354 PMU.
[openwrt/svn-archive/archive.git] / target / linux / brcm47xx / patches-2.6.28 / 810-ssb-add-pmu-support.patch
1 Index: linux-2.6.28.2/drivers/ssb/Makefile
2 ===================================================================
3 --- linux-2.6.28.2.orig/drivers/ssb/Makefile 2009-02-01 13:09:04.000000000 +0100
4 +++ linux-2.6.28.2/drivers/ssb/Makefile 2009-02-01 13:09:31.000000000 +0100
5 @@ -9,6 +9,7 @@ ssb-$(CONFIG_SSB_PCMCIAHOST) += pcmcia.
6
7 # built-in drivers
8 ssb-y += driver_chipcommon.o
9 +ssb-y += driver_chipcommon_pmu.o
10 ssb-$(CONFIG_SSB_DRIVER_MIPS) += driver_mipscore.o
11 ssb-$(CONFIG_SSB_DRIVER_EXTIF) += driver_extif.o
12 ssb-$(CONFIG_SSB_DRIVER_PCICORE) += driver_pcicore.o
13 Index: linux-2.6.28.2/drivers/ssb/driver_chipcommon_pmu.c
14 ===================================================================
15 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
16 +++ linux-2.6.28.2/drivers/ssb/driver_chipcommon_pmu.c 2009-02-01 19:51:46.000000000 +0100
17 @@ -0,0 +1,259 @@
18 +/*
19 + * Sonics Silicon Backplane
20 + * Broadcom ChipCommon Power Management Unit driver
21 + *
22 + * Copyright 2009, Michael Buesch <mb@bu3sch.de>
23 + * Copyright 2007, Broadcom Corporation
24 + *
25 + * Licensed under the GNU/GPL. See COPYING for details.
26 + */
27 +
28 +#include <linux/ssb/ssb.h>
29 +#include <linux/ssb/ssb_regs.h>
30 +#include <linux/ssb/ssb_driver_chipcommon.h>
31 +#include <linux/delay.h>
32 +
33 +#include "ssb_private.h"
34 +
35 +static u32 ssb_chipco_pll_read(struct ssb_chipcommon *cc, u32 offset)
36 +{
37 + chipco_write32(cc, SSB_CHIPCO_PLLCTL_ADDR, offset);
38 + return chipco_read32(cc, SSB_CHIPCO_PLLCTL_DATA);
39 +}
40 +
41 +static void ssb_chipco_pll_write(struct ssb_chipcommon *cc,
42 + u32 offset, u32 value)
43 +{
44 + chipco_write32(cc, SSB_CHIPCO_PLLCTL_ADDR, offset);
45 + chipco_write32(cc, SSB_CHIPCO_PLLCTL_DATA, value);
46 +}
47 +
48 +struct pmu0_plltab_entry {
49 + u16 freq; /* Crystal frequency in kHz.*/
50 + u8 xf; /* Crystal frequency value for PMU control */
51 + u8 wb_int;
52 + u32 wb_frac;
53 +};
54 +
55 +static const struct pmu0_plltab_entry pmu0_plltab[] = {
56 + { .freq = 12000, .xf = 1, .wb_int = 73, .wb_frac = 349525, },
57 + { .freq = 13000, .xf = 2, .wb_int = 67, .wb_frac = 725937, },
58 + { .freq = 14400, .xf = 3, .wb_int = 61, .wb_frac = 116508, },
59 + { .freq = 15360, .xf = 4, .wb_int = 57, .wb_frac = 305834, },
60 + { .freq = 16200, .xf = 5, .wb_int = 54, .wb_frac = 336579, },
61 + { .freq = 16800, .xf = 6, .wb_int = 52, .wb_frac = 399457, },
62 + { .freq = 19200, .xf = 7, .wb_int = 45, .wb_frac = 873813, },
63 + { .freq = 19800, .xf = 8, .wb_int = 44, .wb_frac = 466033, },
64 + { .freq = 20000, .xf = 9, .wb_int = 44, .wb_frac = 0, },
65 + { .freq = 25000, .xf = 10, .wb_int = 70, .wb_frac = 419430, },
66 + { .freq = 26000, .xf = 11, .wb_int = 67, .wb_frac = 725937, },
67 + { .freq = 30000, .xf = 12, .wb_int = 58, .wb_frac = 699050, },
68 + { .freq = 38400, .xf = 13, .wb_int = 45, .wb_frac = 873813, },
69 + { .freq = 40000, .xf = 14, .wb_int = 45, .wb_frac = 0, },
70 +};
71 +#define SSB_PMU0_DEFAULT_XTALFREQ 20000
72 +
73 +static const struct pmu0_plltab_entry * pmu0_plltab_find_entry(u32 crystalfreq)
74 +{
75 + const struct pmu0_plltab_entry *e;
76 + unsigned int i;
77 +
78 + for (i = 0; i < ARRAY_SIZE(pmu0_plltab); i++) {
79 + e = &pmu0_plltab[i];
80 + if (e->freq == crystalfreq)
81 + return e;
82 + }
83 +
84 + return NULL;
85 +}
86 +
87 +/* Tune the PLL to the crystal speed. crystalfreq is in kHz. */
88 +static void ssb_pmu0_pllinit_r0(struct ssb_chipcommon *cc,
89 + u32 crystalfreq)
90 +{
91 + struct ssb_bus *bus = cc->dev->bus;
92 + const struct pmu0_plltab_entry *e;
93 + u32 pmuctl, tmp, pllctl;
94 + unsigned int i;
95 +
96 + if ((bus->chip_id == 0x5354) && !crystalfreq) {
97 + /* The 5354 crystal freq is 25MHz */
98 + crystalfreq = 25000;
99 + }
100 + e = pmu0_plltab_find_entry(crystalfreq);
101 + if (!e)
102 + e = pmu0_plltab_find_entry(SSB_PMU0_DEFAULT_XTALFREQ);
103 + BUG_ON(!e);
104 + crystalfreq = e->freq;
105 + cc->pmu.crystalfreq = e->freq;
106 +
107 + /* Check if the PLL already is programmed to this frequency. */
108 + pmuctl = chipco_read32(cc, SSB_CHIPCO_PMU_CTL);
109 + if (((pmuctl & SSB_CHIPCO_PMU_CTL_XTALFREQ) >> SSB_CHIPCO_PMU_CTL_XTALFREQ_SHIFT) == e->xf) {
110 + /* We're already there... */
111 + return;
112 + }
113 +
114 + ssb_printk(KERN_INFO PFX "Programming PLL to %u.%u MHz\n",
115 + (crystalfreq / 1000), (crystalfreq % 1000));
116 +
117 + /* First turn the PLL off. */
118 + switch (bus->chip_id) {
119 + case 0x4328:
120 + chipco_mask32(cc, SSB_CHIPCO_PMU_MINRES_MSK,
121 + ~(1 << SSB_PLLRES_4328_BB_PLL_PU));
122 + chipco_mask32(cc, SSB_CHIPCO_PMU_MAXRES_MSK,
123 + ~(1 << SSB_PLLRES_4328_BB_PLL_PU));
124 + break;
125 + case 0x5354:
126 + chipco_mask32(cc, SSB_CHIPCO_PMU_MINRES_MSK,
127 + ~(1 << SSB_PLLRES_5354_BB_PLL_PU));
128 + chipco_mask32(cc, SSB_CHIPCO_PMU_MAXRES_MSK,
129 + ~(1 << SSB_PLLRES_5354_BB_PLL_PU));
130 + break;
131 + default:
132 + SSB_WARN_ON(1);
133 + }
134 + for (i = 1500; i; i--) {
135 + tmp = chipco_read32(cc, SSB_CHIPCO_CLKCTLST);
136 + if (!(tmp & SSB_CHIPCO_CLKCTLST_HAVEHT))
137 + break;
138 + udelay(10);
139 + }
140 + tmp = chipco_read32(cc, SSB_CHIPCO_CLKCTLST);
141 + if (tmp & SSB_CHIPCO_CLKCTLST_HAVEHT)
142 + ssb_printk(KERN_EMERG PFX "Failed to turn the PLL off!\n");
143 +
144 + /* Set PDIV in PLL control 0. */
145 + pllctl = ssb_chipco_pll_read(cc, SSB_PMU0_PLLCTL0);
146 + if (crystalfreq >= SSB_PMU0_PLLCTL0_PDIV_FREQ)
147 + pllctl |= SSB_PMU0_PLLCTL0_PDIV_MSK;
148 + else
149 + pllctl &= ~SSB_PMU0_PLLCTL0_PDIV_MSK;
150 + ssb_chipco_pll_write(cc, SSB_PMU0_PLLCTL0, pllctl);
151 +
152 + /* Set WILD in PLL control 1. */
153 + pllctl = ssb_chipco_pll_read(cc, SSB_PMU0_PLLCTL1);
154 + pllctl &= ~SSB_PMU0_PLLCTL1_STOPMOD;
155 + pllctl &= ~(SSB_PMU0_PLLCTL1_WILD_IMSK | SSB_PMU0_PLLCTL1_WILD_FMSK);
156 + pllctl |= ((u32)e->wb_int << SSB_PMU0_PLLCTL1_WILD_IMSK_SHIFT) & SSB_PMU0_PLLCTL1_WILD_IMSK;
157 + pllctl |= ((u32)e->wb_frac << SSB_PMU0_PLLCTL1_WILD_FMSK_SHIFT) & SSB_PMU0_PLLCTL1_WILD_FMSK;
158 + if (e->wb_frac == 0)
159 + pllctl |= SSB_PMU0_PLLCTL1_STOPMOD;
160 + ssb_chipco_pll_write(cc, SSB_PMU0_PLLCTL1, pllctl);
161 +
162 + /* Set WILD in PLL control 2. */
163 + pllctl = ssb_chipco_pll_read(cc, SSB_PMU0_PLLCTL2);
164 + pllctl &= ~SSB_PMU0_PLLCTL2_WILD_IMSKHI;
165 + pllctl |= (((u32)e->wb_int >> 4) << SSB_PMU0_PLLCTL2_WILD_IMSKHI_SHIFT) & SSB_PMU0_PLLCTL2_WILD_IMSKHI;
166 + ssb_chipco_pll_write(cc, SSB_PMU0_PLLCTL2, pllctl);
167 +
168 + /* Set the crystalfrequency and the divisor. */
169 + pmuctl = chipco_read32(cc, SSB_CHIPCO_PMU_CTL);
170 + pmuctl &= ~SSB_CHIPCO_PMU_CTL_ILP_DIV;
171 + pmuctl |= (((crystalfreq + 127) / 128 - 1) << SSB_CHIPCO_PMU_CTL_ILP_DIV_SHIFT)
172 + & SSB_CHIPCO_PMU_CTL_ILP_DIV;
173 + pmuctl &= ~SSB_CHIPCO_PMU_CTL_XTALFREQ;
174 + pmuctl |= ((u32)e->xf << SSB_CHIPCO_PMU_CTL_XTALFREQ_SHIFT) & SSB_CHIPCO_PMU_CTL_XTALFREQ;
175 + chipco_write32(cc, SSB_CHIPCO_PMU_CTL, pmuctl);
176 +}
177 +
178 +/* Tune the PLL to the crystal speed. crystalfreq is in kHz. */
179 +static void ssb_pmu1_pllinit_r0(struct ssb_chipcommon *cc,
180 + u32 crystalfreq)
181 +{
182 + WARN_ON(1);
183 + //TODO
184 +}
185 +
186 +static void ssb_pmu_pll_init(struct ssb_chipcommon *cc)
187 +{
188 + struct ssb_bus *bus = cc->dev->bus;
189 + u32 crystalfreq = 0; /* in kHz. 0 = keep default freq. */
190 +
191 + if (bus->bustype == SSB_BUSTYPE_SSB) {
192 + /* TODO: The user may override the crystal frequency. */
193 + }
194 +
195 + switch (bus->chip_id) {
196 + case 0x4312:
197 + case 0x4325:
198 + ssb_pmu1_pllinit_r0(cc, crystalfreq);
199 + break;
200 + case 0x4328:
201 + case 0x5354:
202 + ssb_pmu0_pllinit_r0(cc, crystalfreq);
203 + break;
204 + default:
205 + ssb_printk(KERN_ERR PFX
206 + "ERROR: PLL init unknown for device %04X\n",
207 + bus->chip_id);
208 + }
209 +}
210 +
211 +static void ssb_pmu_resources_init(struct ssb_chipcommon *cc)
212 +{
213 + struct ssb_bus *bus = cc->dev->bus;
214 + u32 min_msk = 0, max_msk = 0;
215 +
216 + switch (bus->chip_id) {
217 + case 0x4312:
218 + /* We keep the default settings:
219 + * min_msk = 0xCBB
220 + * max_msk = 0x7FFFF
221 + * updown table size = 0
222 + * depend table size = 0
223 + */
224 + break;
225 + case 0x4325:
226 + //TODO
227 + break;
228 + case 0x4328:
229 + //TODO
230 + break;
231 + case 0x5354:
232 + /* The PLL may turn on, if it decides so. */
233 + max_msk = 0xFFFFF;
234 + break;
235 + default:
236 + ssb_printk(KERN_ERR PFX
237 + "ERROR: PMU resource config unknown for device %04X\n",
238 + bus->chip_id);
239 + }
240 + //TODO table upload
241 +
242 + /* Set the resource masks. */
243 + if (min_msk)
244 + chipco_write32(cc, SSB_CHIPCO_PMU_MINRES_MSK, min_msk);
245 + if (max_msk)
246 + chipco_write32(cc, SSB_CHIPCO_PMU_MAXRES_MSK, max_msk);
247 +}
248 +
249 +void ssb_pmu_init(struct ssb_chipcommon *cc)
250 +{
251 + struct ssb_bus *bus = cc->dev->bus;
252 + u32 pmucap;
253 +
254 +if (bus->chip_id != 0x5354) return; //FIXME currently only 5354 code implemented.
255 +
256 + if (!(cc->capabilities & SSB_CHIPCO_CAP_PMU))
257 + return;
258 +
259 + pmucap = chipco_read32(cc, SSB_CHIPCO_PMU_CAP);
260 + cc->pmu.rev = (pmucap & SSB_CHIPCO_PMU_CAP_REVISION);
261 +
262 + ssb_dprintk(KERN_DEBUG PFX "Found rev %u PMU (capabilities 0x%08X)\n",
263 + cc->pmu.rev, pmucap);
264 +
265 + if (cc->pmu.rev >= 1) {
266 + if ((bus->chip_id == 0x4325) && (bus->chip_rev < 2)) {
267 + chipco_mask32(cc, SSB_CHIPCO_PMU_CTL,
268 + ~SSB_CHIPCO_PMU_CTL_NOILPONW);
269 + } else {
270 + chipco_set32(cc, SSB_CHIPCO_PMU_CTL,
271 + SSB_CHIPCO_PMU_CTL_NOILPONW);
272 + }
273 + }
274 + ssb_pmu_pll_init(cc);
275 + ssb_pmu_resources_init(cc);
276 +}
277 Index: linux-2.6.28.2/drivers/ssb/driver_chipcommon.c
278 ===================================================================
279 --- linux-2.6.28.2.orig/drivers/ssb/driver_chipcommon.c 2009-02-01 13:07:03.000000000 +0100
280 +++ linux-2.6.28.2/drivers/ssb/driver_chipcommon.c 2009-02-01 13:47:17.000000000 +0100
281 @@ -26,19 +26,6 @@ enum ssb_clksrc {
282 };
283
284
285 -static inline u32 chipco_read32(struct ssb_chipcommon *cc,
286 - u16 offset)
287 -{
288 - return ssb_read32(cc->dev, offset);
289 -}
290 -
291 -static inline void chipco_write32(struct ssb_chipcommon *cc,
292 - u16 offset,
293 - u32 value)
294 -{
295 - ssb_write32(cc->dev, offset, value);
296 -}
297 -
298 static inline u32 chipco_write32_masked(struct ssb_chipcommon *cc, u16 offset,
299 u32 mask, u32 value)
300 {
301 @@ -246,6 +233,7 @@ void ssb_chipcommon_init(struct ssb_chip
302 {
303 if (!cc->dev)
304 return; /* We don't have a ChipCommon */
305 + ssb_pmu_init(cc);
306 chipco_powercontrol_init(cc);
307 ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST);
308 calc_fast_powerup_delay(cc);
309 Index: linux-2.6.28.2/include/linux/ssb/ssb_driver_chipcommon.h
310 ===================================================================
311 --- linux-2.6.28.2.orig/include/linux/ssb/ssb_driver_chipcommon.h 2009-02-01 13:22:59.000000000 +0100
312 +++ linux-2.6.28.2/include/linux/ssb/ssb_driver_chipcommon.h 2009-02-01 19:17:25.000000000 +0100
313 @@ -181,6 +181,16 @@
314 #define SSB_CHIPCO_PROG_WAITCNT 0x0124
315 #define SSB_CHIPCO_FLASH_CFG 0x0128
316 #define SSB_CHIPCO_FLASH_WAITCNT 0x012C
317 +#define SSB_CHIPCO_CLKCTLST 0x01E0 /* Clock control and status (rev >= 20) */
318 +#define SSB_CHIPCO_CLKCTLST_FORCEALP 0x00000001 /* Force ALP request */
319 +#define SSB_CHIPCO_CLKCTLST_FORCEHT 0x00000002 /* Force HT request */
320 +#define SSB_CHIPCO_CLKCTLST_FORCEILP 0x00000004 /* Force ILP request */
321 +#define SSB_CHIPCO_CLKCTLST_HAVEALPREQ 0x00000008 /* ALP available request */
322 +#define SSB_CHIPCO_CLKCTLST_HAVEHTREQ 0x00000010 /* HT available request */
323 +#define SSB_CHIPCO_CLKCTLST_HWCROFF 0x00000020 /* Force HW clock request off */
324 +#define SSB_CHIPCO_CLKCTLST_HAVEHT 0x00010000 /* HT available */
325 +#define SSB_CHIPCO_CLKCTLST_HAVEALP 0x00020000 /* APL available */
326 +#define SSB_CHIPCO_HW_WORKAROUND 0x01E4 /* Hardware workaround (rev >= 20) */
327 #define SSB_CHIPCO_UART0_DATA 0x0300
328 #define SSB_CHIPCO_UART0_IMR 0x0304
329 #define SSB_CHIPCO_UART0_FCR 0x0308
330 @@ -197,6 +207,156 @@
331 #define SSB_CHIPCO_UART1_LSR 0x0414
332 #define SSB_CHIPCO_UART1_MSR 0x0418
333 #define SSB_CHIPCO_UART1_SCRATCH 0x041C
334 +/* PMU registers (rev >= 20) */
335 +#define SSB_CHIPCO_PMU_CTL 0x0600 /* PMU control */
336 +#define SSB_CHIPCO_PMU_CTL_ILP_DIV 0xFFFF0000 /* ILP div mask */
337 +#define SSB_CHIPCO_PMU_CTL_ILP_DIV_SHIFT 16
338 +#define SSB_CHIPCO_PMU_CTL_NOILPONW 0x00000200 /* No ILP on wait */
339 +#define SSB_CHIPCO_PMU_CTL_HTREQEN 0x00000100 /* HT req enable */
340 +#define SSB_CHIPCO_PMU_CTL_ALPREQEN 0x00000080 /* ALP req enable */
341 +#define SSB_CHIPCO_PMU_CTL_XTALFREQ 0x0000007C /* Crystal freq */
342 +#define SSB_CHIPCO_PMU_CTL_XTALFREQ_SHIFT 2
343 +#define SSB_CHIPCO_PMU_CTL_ILPDIVEN 0x00000002 /* ILP div enable */
344 +#define SSB_CHIPCO_PMU_CTL_LPOSEL 0x00000001 /* LPO sel */
345 +#define SSB_CHIPCO_PMU_CAP 0x0604 /* PMU capabilities */
346 +#define SSB_CHIPCO_PMU_CAP_REVISION 0x000000FF /* Revision mask */
347 +#define SSB_CHIPCO_PMU_STAT 0x0608 /* PMU status */
348 +#define SSB_CHIPCO_PMU_STAT_INTPEND 0x00000040 /* Interrupt pending */
349 +#define SSB_CHIPCO_PMU_STAT_SBCLKST 0x00000030 /* Backplane clock status? */
350 +#define SSB_CHIPCO_PMU_STAT_HAVEALP 0x00000008 /* ALP available */
351 +#define SSB_CHIPCO_PMU_STAT_HAVEHT 0x00000004 /* HT available */
352 +#define SSB_CHIPCO_PMU_STAT_RESINIT 0x00000003 /* Res init */
353 +#define SSB_CHIPCO_PMU_RES_STAT 0x060C /* PMU res status */
354 +#define SSB_CHIPCO_PMU_RES_PEND 0x0610 /* PMU res pending */
355 +#define SSB_CHIPCO_PMU_TIMER 0x0614 /* PMU timer */
356 +#define SSB_CHIPCO_PMU_MINRES_MSK 0x0618 /* PMU min res mask */
357 +#define SSB_CHIPCO_PMU_MAXRES_MSK 0x061C /* PMU max res mask */
358 +#define SSB_CHIPCO_PMU_RES_TABSEL 0x0620 /* PMU res table sel */
359 +#define SSB_CHIPCO_PMU_RES_DEPMSK 0x0624 /* PMU res dep mask */
360 +#define SSB_CHIPCO_PMU_RES_UPDNTM 0x0628 /* PMU res updown timer */
361 +#define SSB_CHIPCO_PMU_RES_TIMER 0x062C /* PMU res timer */
362 +#define SSB_CHIPCO_PMU_CLKSTRETCH 0x0630 /* PMU clockstretch */
363 +#define SSB_CHIPCO_PMU_WATCHDOG 0x0634 /* PMU watchdog */
364 +#define SSB_CHIPCO_PMU_RES_REQTS 0x0640 /* PMU res req timer sel */
365 +#define SSB_CHIPCO_PMU_RES_REQT 0x0644 /* PMU res req timer */
366 +#define SSB_CHIPCO_PMU_RES_REQM 0x0648 /* PMU res req mask */
367 +#define SSB_CHIPCO_CHIPCTL_ADDR 0x0650
368 +#define SSB_CHIPCO_CHIPCTL_DATA 0x0654
369 +#define SSB_CHIPCO_REGCTL_ADDR 0x0658
370 +#define SSB_CHIPCO_REGCTL_DATA 0x065C
371 +#define SSB_CHIPCO_PLLCTL_ADDR 0x0660
372 +#define SSB_CHIPCO_PLLCTL_DATA 0x0664
373 +
374 +
375 +
376 +/** PMU PLL registers */
377 +
378 +/* PMU rev 0 PLL registers */
379 +#define SSB_PMU0_PLLCTL0 0
380 +#define SSB_PMU0_PLLCTL0_PDIV_MSK 0x00000001
381 +#define SSB_PMU0_PLLCTL0_PDIV_FREQ 25000 /* kHz */
382 +#define SSB_PMU0_PLLCTL1 1
383 +#define SSB_PMU0_PLLCTL1_WILD_IMSK 0xF0000000 /* Wild int mask (low nibble) */
384 +#define SSB_PMU0_PLLCTL1_WILD_IMSK_SHIFT 28
385 +#define SSB_PMU0_PLLCTL1_WILD_FMSK 0x0FFFFF00 /* Wild frac mask */
386 +#define SSB_PMU0_PLLCTL1_WILD_FMSK_SHIFT 8
387 +#define SSB_PMU0_PLLCTL1_STOPMOD 0x00000040 /* Stop mod */
388 +#define SSB_PMU0_PLLCTL2 2
389 +#define SSB_PMU0_PLLCTL2_WILD_IMSKHI 0x0000000F /* Wild int mask (high nibble) */
390 +#define SSB_PMU0_PLLCTL2_WILD_IMSKHI_SHIFT 0
391 +
392 +/* PMU rev 1 PLL registers */
393 +#define SSB_PMU1_PLLCTL0 0
394 +#define SSB_PMU1_PLLCTL1 1
395 +#define SSB_PMU1_PLLCTL2 2
396 +#define SSB_PMU1_PLLCTL3 3
397 +#define SSB_PMU1_PLLCTL4 4
398 +#define SSB_PMU1_PLLCTL5 5
399 +
400 +/* BCM4312 PLL resource numbers. */
401 +#define SSB_PLLRES_4312_SWITCHER_BURST 0
402 +#define SSB_PLLRES_4312_SWITCHER_PWM 1
403 +#define SSB_PLLRES_4312_PA_REF_LDO 2
404 +#define SSB_PLLRES_4312_CORE_LDO_BURST 3
405 +#define SSB_PLLRES_4312_CORE_LDO_PWM 4
406 +#define SSB_PLLRES_4312_RADIO_LDO 5
407 +#define SSB_PLLRES_4312_ILP_REQUEST 6
408 +#define SSB_PLLRES_4312_BG_FILTBYP 7
409 +#define SSB_PLLRES_4312_TX_FILTBYP 8
410 +#define SSB_PLLRES_4312_RX_FILTBYP 9
411 +#define SSB_PLLRES_4312_XTAL_PU 10
412 +#define SSB_PLLRES_4312_ALP_AVAIL 11
413 +#define SSB_PLLRES_4312_BB_PLL_FILTBYP 12
414 +#define SSB_PLLRES_4312_RF_PLL_FILTBYP 13
415 +#define SSB_PLLRES_4312_HT_AVAIL 14
416 +
417 +/* BCM4325 PLL resource numbers. */
418 +#define SSB_PLLRES_4325_BUCK_BOOST_BURST 0
419 +#define SSB_PLLRES_4325_CBUCK_BURST 1
420 +#define SSB_PLLRES_4325_CBUCK_PWM 2
421 +#define SSB_PLLRES_4325_CLDO_CBUCK_BURST 3
422 +#define SSB_PLLRES_4325_CLDO_CBUCK_PWM 4
423 +#define SSB_PLLRES_4325_BUCK_BOOST_PWM 5
424 +#define SSB_PLLRES_4325_ILP_REQUEST 6
425 +#define SSB_PLLRES_4325_ABUCK_BURST 7
426 +#define SSB_PLLRES_4325_ABUCK_PWM 8
427 +#define SSB_PLLRES_4325_LNLDO1_PU 9
428 +#define SSB_PLLRES_4325_LNLDO2_PU 10
429 +#define SSB_PLLRES_4325_LNLDO3_PU 11
430 +#define SSB_PLLRES_4325_LNLDO4_PU 12
431 +#define SSB_PLLRES_4325_XTAL_PU 13
432 +#define SSB_PLLRES_4325_ALP_AVAIL 14
433 +#define SSB_PLLRES_4325_RX_PWRSW_PU 15
434 +#define SSB_PLLRES_4325_TX_PWRSW_PU 16
435 +#define SSB_PLLRES_4325_RFPLL_PWRSW_PU 17
436 +#define SSB_PLLRES_4325_LOGEN_PWRSW_PU 18
437 +#define SSB_PLLRES_4325_AFE_PWRSW_PU 19
438 +#define SSB_PLLRES_4325_BBPLL_PWRSW_PU 20
439 +#define SSB_PLLRES_4325_HT_AVAIL 21
440 +
441 +/* BCM4328 PLL resource numbers. */
442 +#define SSB_PLLRES_4328_EXT_SWITCHER_PWM 0
443 +#define SSB_PLLRES_4328_BB_SWITCHER_PWM 1
444 +#define SSB_PLLRES_4328_BB_SWITCHER_BURST 2
445 +#define SSB_PLLRES_4328_BB_EXT_SWITCHER_BURST 3
446 +#define SSB_PLLRES_4328_ILP_REQUEST 4
447 +#define SSB_PLLRES_4328_RADIO_SWITCHER_PWM 5
448 +#define SSB_PLLRES_4328_RADIO_SWITCHER_BURST 6
449 +#define SSB_PLLRES_4328_ROM_SWITCH 7
450 +#define SSB_PLLRES_4328_PA_REF_LDO 8
451 +#define SSB_PLLRES_4328_RADIO_LDO 9
452 +#define SSB_PLLRES_4328_AFE_LDO 10
453 +#define SSB_PLLRES_4328_PLL_LDO 11
454 +#define SSB_PLLRES_4328_BG_FILTBYP 12
455 +#define SSB_PLLRES_4328_TX_FILTBYP 13
456 +#define SSB_PLLRES_4328_RX_FILTBYP 14
457 +#define SSB_PLLRES_4328_XTAL_PU 15
458 +#define SSB_PLLRES_4328_XTAL_EN 16
459 +#define SSB_PLLRES_4328_BB_PLL_FILTBYP 17
460 +#define SSB_PLLRES_4328_RF_PLL_FILTBYP 18
461 +#define SSB_PLLRES_4328_BB_PLL_PU 19
462 +
463 +/* BCM5354 PLL resource numbers. */
464 +#define SSB_PLLRES_5354_EXT_SWITCHER_PWM 0
465 +#define SSB_PLLRES_5354_BB_SWITCHER_PWM 1
466 +#define SSB_PLLRES_5354_BB_SWITCHER_BURST 2
467 +#define SSB_PLLRES_5354_BB_EXT_SWITCHER_BURST 3
468 +#define SSB_PLLRES_5354_ILP_REQUEST 4
469 +#define SSB_PLLRES_5354_RADIO_SWITCHER_PWM 5
470 +#define SSB_PLLRES_5354_RADIO_SWITCHER_BURST 6
471 +#define SSB_PLLRES_5354_ROM_SWITCH 7
472 +#define SSB_PLLRES_5354_PA_REF_LDO 8
473 +#define SSB_PLLRES_5354_RADIO_LDO 9
474 +#define SSB_PLLRES_5354_AFE_LDO 10
475 +#define SSB_PLLRES_5354_PLL_LDO 11
476 +#define SSB_PLLRES_5354_BG_FILTBYP 12
477 +#define SSB_PLLRES_5354_TX_FILTBYP 13
478 +#define SSB_PLLRES_5354_RX_FILTBYP 14
479 +#define SSB_PLLRES_5354_XTAL_PU 15
480 +#define SSB_PLLRES_5354_XTAL_EN 16
481 +#define SSB_PLLRES_5354_BB_PLL_FILTBYP 17
482 +#define SSB_PLLRES_5354_RF_PLL_FILTBYP 18
483 +#define SSB_PLLRES_5354_BB_PLL_PU 19
484
485
486
487 @@ -353,11 +513,20 @@
488 struct ssb_device;
489 struct ssb_serial_port;
490
491 +/* Data for the PMU, if available.
492 + * Check availability with ((struct ssb_chipcommon)->capabilities & SSB_CHIPCO_CAP_PMU)
493 + */
494 +struct ssb_chipcommon_pmu {
495 + u8 rev; /* PMU revision */
496 + u32 crystalfreq; /* The active crystal frequency (in kHz) */
497 +};
498 +
499 struct ssb_chipcommon {
500 struct ssb_device *dev;
501 u32 capabilities;
502 /* Fast Powerup Delay constant */
503 u16 fast_pwrup_delay;
504 + struct ssb_chipcommon_pmu pmu;
505 };
506
507 static inline bool ssb_chipco_available(struct ssb_chipcommon *cc)
508 @@ -365,6 +534,17 @@ static inline bool ssb_chipco_available(
509 return (cc->dev != NULL);
510 }
511
512 +/* Register access */
513 +#define chipco_read32(cc, offset) ssb_read32((cc)->dev, offset)
514 +#define chipco_write32(cc, offset, val) ssb_write32((cc)->dev, offset, val)
515 +
516 +#define chipco_mask32(cc, offset, mask) \
517 + chipco_write32(cc, offset, chipco_read32(cc, offset) & (mask))
518 +#define chipco_set32(cc, offset, set) \
519 + chipco_write32(cc, offset, chipco_read32(cc, offset) | (set))
520 +#define chipco_maskset32(cc, offset, mask, set) \
521 + chipco_write32(cc, offset, (chipco_read32(cc, offset) & (mask)) | (set))
522 +
523 extern void ssb_chipcommon_init(struct ssb_chipcommon *cc);
524
525 extern void ssb_chipco_suspend(struct ssb_chipcommon *cc);
526 @@ -406,4 +586,8 @@ extern int ssb_chipco_serial_init(struct
527 struct ssb_serial_port *ports);
528 #endif /* CONFIG_SSB_SERIAL */
529
530 +/* PMU support */
531 +extern void ssb_pmu_init(struct ssb_chipcommon *cc);
532 +
533 +
534 #endif /* LINUX_SSB_CHIPCO_H_ */