brcm47xx: prepare brcm47xx patches for sending to mainline.
[openwrt/svn-archive/archive.git] / target / linux / brcm47xx / patches-2.6.35 / 700-ssb-gigabit-ethernet-driver.patch
1 --- a/drivers/net/tg3.c
2 +++ b/drivers/net/tg3.c
3 @@ -41,6 +41,7 @@
4 #include <linux/prefetch.h>
5 #include <linux/dma-mapping.h>
6 #include <linux/firmware.h>
7 +#include <linux/ssb/ssb_driver_gige.h>
8
9 #include <net/checksum.h>
10 #include <net/ip.h>
11 @@ -494,8 +495,9 @@ static void _tw32_flush(struct tg3 *tp,
12 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
13 {
14 tp->write32_mbox(tp, off, val);
15 - if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
16 - !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
17 + if ((tp->tg3_flags3 & TG3_FLG3_FLUSH_POSTED_WRITES) ||
18 + (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
19 + !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND)))
20 tp->read32_mbox(tp, off);
21 }
22
23 @@ -505,7 +507,7 @@ static void tg3_write32_tx_mbox(struct t
24 writel(val, mbox);
25 if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
26 writel(val, mbox);
27 - if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
28 + if ((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) || (tp->tg3_flags3 & TG3_FLG3_FLUSH_POSTED_WRITES))
29 readl(mbox);
30 }
31
32 @@ -807,7 +809,7 @@ static void tg3_switch_clocks(struct tg3
33
34 #define PHY_BUSY_LOOPS 5000
35
36 -static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
37 +static int __tg3_readphy(struct tg3 *tp, unsigned int phy_addr, int reg, u32 *val)
38 {
39 u32 frame_val;
40 unsigned int loops;
41 @@ -821,7 +823,7 @@ static int tg3_readphy(struct tg3 *tp, i
42
43 *val = 0x0;
44
45 - frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
46 + frame_val = ((phy_addr << MI_COM_PHY_ADDR_SHIFT) &
47 MI_COM_PHY_ADDR_MASK);
48 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
49 MI_COM_REG_ADDR_MASK);
50 @@ -856,7 +858,12 @@ static int tg3_readphy(struct tg3 *tp, i
51 return ret;
52 }
53
54 -static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
55 +static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
56 +{
57 + return __tg3_readphy(tp, tp->phy_addr, reg, val);
58 +}
59 +
60 +static int __tg3_writephy(struct tg3 *tp, unsigned int phy_addr, int reg, u32 val)
61 {
62 u32 frame_val;
63 unsigned int loops;
64 @@ -872,7 +879,7 @@ static int tg3_writephy(struct tg3 *tp,
65 udelay(80);
66 }
67
68 - frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
69 + frame_val = ((phy_addr << MI_COM_PHY_ADDR_SHIFT) &
70 MI_COM_PHY_ADDR_MASK);
71 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
72 MI_COM_REG_ADDR_MASK);
73 @@ -905,6 +912,11 @@ static int tg3_writephy(struct tg3 *tp,
74 return ret;
75 }
76
77 +static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
78 +{
79 + return __tg3_writephy(tp, tp->phy_addr, reg, val);
80 +}
81 +
82 static int tg3_bmcr_reset(struct tg3 *tp)
83 {
84 u32 phy_control;
85 @@ -2411,6 +2423,9 @@ static int tg3_nvram_read(struct tg3 *tp
86 {
87 int ret;
88
89 + if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE)
90 + return -ENODEV;
91 +
92 if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
93 return tg3_nvram_read_using_eeprom(tp, offset, val);
94
95 @@ -2742,8 +2757,10 @@ static int tg3_set_power_state(struct tg
96 tg3_frob_aux_power(tp);
97
98 /* Workaround for unstable PLL clock */
99 - if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
100 - (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
101 + if ((tp->phy_id & TG3_PHY_ID_MASK) != TG3_PHY_ID_BCM5750_2 &&
102 + /* !!! FIXME !!! */
103 + ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
104 + (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX))) {
105 u32 val = tr32(0x7d00);
106
107 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
108 @@ -3236,6 +3253,14 @@ relink:
109
110 tg3_phy_copper_begin(tp);
111
112 + if (tp->tg3_flags3 & TG3_FLG3_ROBOSWITCH) {
113 + current_link_up = 1;
114 + current_speed = SPEED_1000; //FIXME
115 + current_duplex = DUPLEX_FULL;
116 + tp->link_config.active_speed = current_speed;
117 + tp->link_config.active_duplex = current_duplex;
118 + }
119 +
120 tg3_readphy(tp, MII_BMSR, &tmp);
121 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
122 (tmp & BMSR_LSTATUS))
123 @@ -6719,6 +6744,11 @@ static int tg3_poll_fw(struct tg3 *tp)
124 int i;
125 u32 val;
126
127 + if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE) {
128 + /* We don't use firmware. */
129 + return 0;
130 + }
131 +
132 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
133 /* Wait up to 20ms for init done. */
134 for (i = 0; i < 200; i++) {
135 @@ -7002,6 +7032,14 @@ static int tg3_chip_reset(struct tg3 *tp
136 tw32(0x5000, 0x400);
137 }
138
139 + if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE) {
140 + /* BCM4785: In order to avoid repercussions from using potentially
141 + * defective internal ROM, stop the Rx RISC CPU, which is not
142 + * required. */
143 + tg3_stop_fw(tp);
144 + tg3_halt_cpu(tp, RX_CPU_BASE);
145 + }
146 +
147 tw32(GRC_MODE, tp->grc_mode);
148
149 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
150 @@ -7179,9 +7217,12 @@ static int tg3_halt_cpu(struct tg3 *tp,
151 return -ENODEV;
152 }
153
154 - /* Clear firmware's nvram arbitration. */
155 - if (tp->tg3_flags & TG3_FLAG_NVRAM)
156 - tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
157 + if (!(tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE)) {
158 + /* Clear firmware's nvram arbitration. */
159 + if (tp->tg3_flags & TG3_FLAG_NVRAM)
160 + tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
161 + }
162 +
163 return 0;
164 }
165
166 @@ -7244,6 +7285,11 @@ static int tg3_load_5701_a0_firmware_fix
167 const __be32 *fw_data;
168 int err, i;
169
170 + if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE) {
171 + /* We don't use firmware. */
172 + return 0;
173 + }
174 +
175 fw_data = (void *)tp->fw->data;
176
177 /* Firmware blob starts with version numbers, followed by
178 @@ -7302,6 +7348,11 @@ static int tg3_load_tso_firmware(struct
179 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
180 int err, i;
181
182 + if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE) {
183 + /* We don't use firmware. */
184 + return 0;
185 + }
186 +
187 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
188 return 0;
189
190 @@ -8446,6 +8497,11 @@ static void tg3_timer(unsigned long __op
191
192 spin_lock(&tp->lock);
193
194 + if (tp->tg3_flags3 & TG3_FLG3_FLUSH_POSTED_WRITES) {
195 + /* BCM4785: Flush posted writes from GbE to host memory. */
196 + tr32(HOSTCC_MODE);
197 + }
198 +
199 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
200 /* All of this garbage is because when using non-tagged
201 * IRQ status the mailbox/status_block protocol the chip
202 @@ -10113,6 +10169,11 @@ static int tg3_test_nvram(struct tg3 *tp
203 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
204 return 0;
205
206 + if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE) {
207 + /* We don't have NVRAM. */
208 + return 0;
209 + }
210 +
211 if (tg3_nvram_read(tp, 0, &magic) != 0)
212 return -EIO;
213
214 @@ -10932,7 +10993,7 @@ static int tg3_ioctl(struct net_device *
215 return -EAGAIN;
216
217 spin_lock_bh(&tp->lock);
218 - err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
219 + err = __tg3_readphy(tp, data->phy_id & 0x1f, data->reg_num & 0x1f, &mii_regval);
220 spin_unlock_bh(&tp->lock);
221
222 data->val_out = mii_regval;
223 @@ -10948,7 +11009,7 @@ static int tg3_ioctl(struct net_device *
224 return -EAGAIN;
225
226 spin_lock_bh(&tp->lock);
227 - err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
228 + err = __tg3_writephy(tp, data->phy_id & 0x1f, data->reg_num & 0x1f, data->val_in);
229 spin_unlock_bh(&tp->lock);
230
231 return err;
232 @@ -11593,6 +11654,12 @@ static void __devinit tg3_get_5717_nvram
233 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
234 static void __devinit tg3_nvram_init(struct tg3 *tp)
235 {
236 + if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE) {
237 + /* No NVRAM and EEPROM on the SSB Broadcom GigE core. */
238 + tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
239 + return;
240 + }
241 +
242 tw32_f(GRC_EEPROM_ADDR,
243 (EEPROM_ADDR_FSM_RESET |
244 (EEPROM_DEFAULT_CLOCK_PERIOD <<
245 @@ -11855,6 +11922,9 @@ static int tg3_nvram_write_block(struct
246 {
247 int ret;
248
249 + if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE)
250 + return -ENODEV;
251 +
252 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
253 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
254 ~GRC_LCLCTRL_GPIO_OUTPUT1);
255 @@ -13227,6 +13297,11 @@ static int __devinit tg3_get_invariants(
256 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
257 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
258
259 + if (tp->tg3_flags3 & TG3_FLG3_FLUSH_POSTED_WRITES) {
260 + tp->write32_tx_mbox = tg3_write_flush_reg32;
261 + tp->write32_rx_mbox = tg3_write_flush_reg32;
262 + }
263 +
264 /* Get eeprom hw config before calling tg3_set_power_state().
265 * In particular, the TG3_FLG2_IS_NIC flag must be
266 * determined before calling tg3_set_power_state() so that
267 @@ -13624,6 +13699,10 @@ static int __devinit tg3_get_device_addr
268 }
269
270 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
271 + if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE)
272 + ssb_gige_get_macaddr(tp->pdev, &dev->dev_addr[0]);
273 + }
274 + if (!is_valid_ether_addr(&dev->dev_addr[0])) {
275 #ifdef CONFIG_SPARC
276 if (!tg3_get_default_macaddr_sparc(tp))
277 return 0;
278 @@ -14144,6 +14223,7 @@ static char * __devinit tg3_phy_string(s
279 case TG3_PHY_ID_BCM5704: return "5704";
280 case TG3_PHY_ID_BCM5705: return "5705";
281 case TG3_PHY_ID_BCM5750: return "5750";
282 + case TG3_PHY_ID_BCM5750_2: return "5750-2";
283 case TG3_PHY_ID_BCM5752: return "5752";
284 case TG3_PHY_ID_BCM5714: return "5714";
285 case TG3_PHY_ID_BCM5780: return "5780";
286 @@ -14354,6 +14434,13 @@ static int __devinit tg3_init_one(struct
287 tp->msg_enable = tg3_debug;
288 else
289 tp->msg_enable = TG3_DEF_MSG_ENABLE;
290 + if (pdev_is_ssb_gige_core(pdev)) {
291 + tp->tg3_flags3 |= TG3_FLG3_IS_SSB_CORE;
292 + if (ssb_gige_must_flush_posted_writes(pdev))
293 + tp->tg3_flags3 |= TG3_FLG3_FLUSH_POSTED_WRITES;
294 + if (ssb_gige_have_roboswitch(pdev))
295 + tp->tg3_flags3 |= TG3_FLG3_ROBOSWITCH;
296 + }
297
298 /* The word/byte swap controls here control register access byte
299 * swapping. DMA data byte swapping is controlled in the GRC_MODE
300 --- a/drivers/net/tg3.h
301 +++ b/drivers/net/tg3.h
302 @@ -2014,6 +2014,9 @@
303 #define NIC_SRAM_RGMII_INBAND_DISABLE 0x00000004
304 #define NIC_SRAM_RGMII_EXT_IBND_RX_EN 0x00000008
305 #define NIC_SRAM_RGMII_EXT_IBND_TX_EN 0x00000010
306 +#define TG3_FLG3_IS_SSB_CORE 0x00000800
307 +#define TG3_FLG3_FLUSH_POSTED_WRITES 0x00001000
308 +#define TG3_FLG3_ROBOSWITCH 0x00002000
309
310 #define NIC_SRAM_RX_MINI_BUFFER_DESC 0x00001000
311
312 @@ -2931,6 +2934,7 @@ struct tg3 {
313 #define TG3_PHY_ID_BCM5704 0x60008190
314 #define TG3_PHY_ID_BCM5705 0x600081a0
315 #define TG3_PHY_ID_BCM5750 0x60008180
316 +#define TG3_PHY_ID_BCM5750_2 0xbc050cd0
317 #define TG3_PHY_ID_BCM5752 0x60008100
318 #define TG3_PHY_ID_BCM5714 0x60008340
319 #define TG3_PHY_ID_BCM5780 0x60008350
320 @@ -2965,7 +2969,8 @@ struct tg3 {
321 (X) == TG3_PHY_ID_BCM5755 || (X) == TG3_PHY_ID_BCM5756 || \
322 (X) == TG3_PHY_ID_BCM5906 || (X) == TG3_PHY_ID_BCM5761 || \
323 (X) == TG3_PHY_ID_BCM5718C || (X) == TG3_PHY_ID_BCM5718S || \
324 - (X) == TG3_PHY_ID_BCM57765 || (X) == TG3_PHY_ID_BCM8002)
325 + (X) == TG3_PHY_ID_BCM57765 || (X) == TG3_PHY_ID_BCM8002 || \
326 + (X) == TG3_PHY_ID_BCM5750_2)
327
328 u32 led_ctrl;
329 u32 phy_otp;