brcm47xx: add initial support for devices with bcma bus.
[openwrt/svn-archive/archive.git] / target / linux / brcm47xx / patches-3.0 / 0007-bcma-get-CPU-clock.patch
1 From 257d5fe12600f08df764cac0abc17bef7b6fae9b Mon Sep 17 00:00:00 2001
2 From: Hauke Mehrtens <hauke@hauke-m.de>
3 Date: Sun, 19 Jun 2011 17:51:30 +0200
4 Subject: [PATCH 07/14] bcma: get CPU clock
5
6 Add method to return the clock of the CPU. This is needed by the arch
7 code to calculate the mips_hpt_frequency.
8
9 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
10 ---
11 drivers/bcma/bcma_private.h | 3 +
12 drivers/bcma/driver_chipcommon_pmu.c | 87 +++++++++++++++++++++++++++
13 drivers/bcma/driver_mips.c | 12 ++++
14 include/linux/bcma/bcma_driver_chipcommon.h | 35 +++++++++++
15 include/linux/bcma/bcma_driver_mips.h | 1 +
16 5 files changed, 138 insertions(+), 0 deletions(-)
17
18 --- a/drivers/bcma/bcma_private.h
19 +++ b/drivers/bcma/bcma_private.h
20 @@ -29,6 +29,9 @@ void bcma_init_bus(struct bcma_bus *bus)
21 /* sprom.c */
22 int bcma_sprom_get(struct bcma_bus *bus);
23
24 +/* driver_chipcommon_pmu.c */
25 +extern u32 bcma_pmu_get_clockcpu(struct bcma_drv_cc *cc);
26 +
27 /* driver_chipcommon.c */
28 #ifdef CONFIG_BCMA_DRIVER_MIPS
29 extern int bcma_chipco_serial_init(struct bcma_drv_cc *cc,
30 --- a/drivers/bcma/driver_chipcommon_pmu.c
31 +++ b/drivers/bcma/driver_chipcommon_pmu.c
32 @@ -11,6 +11,13 @@
33 #include "bcma_private.h"
34 #include <linux/bcma/bcma.h>
35
36 +static u32 bcma_chipco_pll_read(struct bcma_drv_cc *cc, u32 offset)
37 +{
38 + bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset);
39 + bcma_cc_read32(cc, BCMA_CC_PLLCTL_ADDR);
40 + return bcma_cc_read32(cc, BCMA_CC_PLLCTL_DATA);
41 +}
42 +
43 static void bcma_chipco_chipctl_maskset(struct bcma_drv_cc *cc,
44 u32 offset, u32 mask, u32 set)
45 {
46 @@ -136,3 +143,83 @@ void bcma_pmu_init(struct bcma_drv_cc *c
47 bcma_pmu_swreg_init(cc);
48 bcma_pmu_workarounds(cc);
49 }
50 +
51 +static u32 bcma_pmu_alp_clock(struct bcma_drv_cc *cc)
52 +{
53 + struct bcma_bus *bus = cc->core->bus;
54 +
55 + switch (bus->chipinfo.id) {
56 + case 0x4716:
57 + case 0x4748:
58 + case 47162:
59 + /* always 20Mhz */
60 + return 20000 * 1000;
61 + default:
62 + pr_warn("No ALP clock specified for %04X device, "
63 + "pmu rev. %d, using default %d Hz\n",
64 + bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_ALP_CLOCK);
65 + }
66 + return BCMA_CC_PMU_ALP_CLOCK;
67 +}
68 +
69 +/* Find the output of the "m" pll divider given pll controls that start with
70 + * pllreg "pll0" i.e. 12 for main 6 for phy, 0 for misc.
71 + */
72 +static u32 bcma_pmu_clock(struct bcma_drv_cc *cc, u32 pll0, u32 m)
73 +{
74 + u32 tmp, div, ndiv, p1, p2, fc;
75 +
76 + BUG_ON(!m || m > 4);
77 +
78 + BUG_ON((pll0 & 3) || (pll0 > BCMA_CC_PMU4716_MAINPLL_PLL0));
79 +
80 + tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PPL_P1P2_OFF);
81 + p1 = (tmp & BCMA_CC_PPL_P1_MASK) >> BCMA_CC_PPL_P1_SHIFT;
82 + p2 = (tmp & BCMA_CC_PPL_P2_MASK) >> BCMA_CC_PPL_P2_SHIFT;
83 +
84 + tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PPL_M14_OFF);
85 + div = (tmp >> ((m - 1) * BCMA_CC_PPL_MDIV_WIDTH)) &
86 + BCMA_CC_PPL_MDIV_MASK;
87 +
88 + tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PPL_NM5_OFF);
89 + ndiv = (tmp & BCMA_CC_PPL_NDIV_MASK) >> BCMA_CC_PPL_NDIV_SHIFT;
90 +
91 + /* Do calculation in Mhz */
92 + fc = bcma_pmu_alp_clock(cc) / 1000000;
93 + fc = (p1 * ndiv * fc) / p2;
94 +
95 + /* Return clock in Hertz */
96 + return (fc / div) * 1000000;
97 +}
98 +
99 +/* query bus clock frequency for PMU-enabled chipcommon */
100 +u32 bcma_pmu_get_clockcontrol(struct bcma_drv_cc *cc)
101 +{
102 + struct bcma_bus *bus = cc->core->bus;
103 +
104 + switch (bus->chipinfo.id) {
105 + case 0x4716:
106 + case 0x4748:
107 + case 47162:
108 + return bcma_pmu_clock(cc, BCMA_CC_PMU4716_MAINPLL_PLL0,
109 + BCMA_CC_PMU5_MAINPLL_SSB);
110 + default:
111 + pr_warn("No backplane clock specified for %04X device, "
112 + "pmu rev. %d, using default %d Hz\n",
113 + bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_HT_CLOCK);
114 + }
115 + return BCMA_CC_PMU_HT_CLOCK;
116 +}
117 +
118 +/* query cpu clock frequency for PMU-enabled chipcommon */
119 +u32 bcma_pmu_get_clockcpu(struct bcma_drv_cc *cc)
120 +{
121 + struct bcma_bus *bus = cc->core->bus;
122 +
123 + if ((cc->pmu.rev == 5 || cc->pmu.rev == 6 || cc->pmu.rev == 7) &&
124 + (bus->chipinfo.id != 0x4319))
125 + return bcma_pmu_clock(cc, BCMA_CC_PMU4716_MAINPLL_PLL0,
126 + BCMA_CC_PMU5_MAINPLL_CPU);
127 +
128 + return bcma_pmu_get_clockcontrol(cc);
129 +}
130 --- a/drivers/bcma/driver_mips.c
131 +++ b/drivers/bcma/driver_mips.c
132 @@ -157,6 +157,18 @@ static void bcma_core_mips_dump_irq(stru
133 }
134 }
135
136 +u32 bcma_cpu_clock(struct bcma_drv_mips *mcore)
137 +{
138 + struct bcma_bus *bus = mcore->core->bus;
139 +
140 + if (bus->drv_cc.capabilities & BCMA_CC_CAP_PMU)
141 + return bcma_pmu_get_clockcpu(&bus->drv_cc);
142 +
143 + pr_err("No PMU available, need this to get the cpu clock\n");
144 + return 0;
145 +}
146 +EXPORT_SYMBOL(bcma_cpu_clock);
147 +
148 static void bcma_core_mips_serial_init(struct bcma_drv_mips *mcore)
149 {
150 struct bcma_bus *bus = mcore->core->bus;
151 --- a/include/linux/bcma/bcma_driver_chipcommon.h
152 +++ b/include/linux/bcma/bcma_driver_chipcommon.h
153 @@ -246,6 +246,41 @@
154 #define BCMA_CC_PLLCTL_DATA 0x0664
155 #define BCMA_CC_SPROM 0x0830 /* SPROM beginning */
156
157 +/* Divider allocation in 4716/47162/5356 */
158 +#define BCMA_CC_PMU5_MAINPLL_CPU 1
159 +#define BCMA_CC_PMU5_MAINPLL_MEM 2
160 +#define BCMA_CC_PMU5_MAINPLL_SSB 3
161 +
162 +/* PLL usage in 4716/47162 */
163 +#define BCMA_CC_PMU4716_MAINPLL_PLL0 12
164 +
165 +/* ALP clock on pre-PMU chips */
166 +#define BCMA_CC_PMU_ALP_CLOCK 20000000
167 +/* HT clock for systems with PMU-enabled chipcommon */
168 +#define BCMA_CC_PMU_HT_CLOCK 80000000
169 +
170 +/* PMU rev 5 (& 6) */
171 +#define BCMA_CC_PPL_P1P2_OFF 0
172 +#define BCMA_CC_PPL_P1_MASK 0x0f000000
173 +#define BCMA_CC_PPL_P1_SHIFT 24
174 +#define BCMA_CC_PPL_P2_MASK 0x00f00000
175 +#define BCMA_CC_PPL_P2_SHIFT 20
176 +#define BCMA_CC_PPL_M14_OFF 1
177 +#define BCMA_CC_PPL_MDIV_MASK 0x000000ff
178 +#define BCMA_CC_PPL_MDIV_WIDTH 8
179 +#define BCMA_CC_PPL_NM5_OFF 2
180 +#define BCMA_CC_PPL_NDIV_MASK 0xfff00000
181 +#define BCMA_CC_PPL_NDIV_SHIFT 20
182 +#define BCMA_CC_PPL_FMAB_OFF 3
183 +#define BCMA_CC_PPL_MRAT_MASK 0xf0000000
184 +#define BCMA_CC_PPL_MRAT_SHIFT 28
185 +#define BCMA_CC_PPL_ABRAT_MASK 0x08000000
186 +#define BCMA_CC_PPL_ABRAT_SHIFT 27
187 +#define BCMA_CC_PPL_FDIV_MASK 0x07ffffff
188 +#define BCMA_CC_PPL_PLLCTL_OFF 4
189 +#define BCMA_CC_PPL_PCHI_OFF 5
190 +#define BCMA_CC_PPL_PCHI_MASK 0x0000003f
191 +
192 /* Data for the PMU, if available.
193 * Check availability with ((struct bcma_chipcommon)->capabilities & BCMA_CC_CAP_PMU)
194 */
195 --- a/include/linux/bcma/bcma_driver_mips.h
196 +++ b/include/linux/bcma/bcma_driver_mips.h
197 @@ -54,6 +54,7 @@ struct bcma_drv_mips {
198 };
199
200 extern void bcma_core_mips_init(struct bcma_drv_mips *mcore);
201 +extern u32 bcma_cpu_clock(struct bcma_drv_mips *mcore);
202
203 extern unsigned int bcma_core_mips_irq(struct bcma_device *dev);
204