f3229eb115cc19dd6a0b80cfa7cb49a8be89d716
[openwrt/svn-archive/archive.git] / target / linux / brcm47xx / patches-3.0 / 0011-bcm47xx-fix-irq-assignment-for-new-SoCs.patch
1 From a277b0b02837a167a5766c048dedef8dfc2fb707 Mon Sep 17 00:00:00 2001
2 From: Hauke Mehrtens <hauke@hauke-m.de>
3 Date: Mon, 6 Jun 2011 00:07:38 +0200
4 Subject: [PATCH 11/22] bcm47xx: fix irq assignment for new SoCs.
5
6 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
7 ---
8 arch/mips/bcm47xx/irq.c | 12 ++++++++++++
9 1 files changed, 12 insertions(+), 0 deletions(-)
10
11 --- a/arch/mips/bcm47xx/irq.c
12 +++ b/arch/mips/bcm47xx/irq.c
13 @@ -26,6 +26,7 @@
14 #include <linux/interrupt.h>
15 #include <linux/irq.h>
16 #include <asm/irq_cpu.h>
17 +#include <bcm47xx.h>
18
19 void plat_irq_dispatch(void)
20 {
21 @@ -51,5 +52,16 @@ void plat_irq_dispatch(void)
22
23 void __init arch_init_irq(void)
24 {
25 +#ifdef CONFIG_BCM47XX_BCMA
26 + if (bcm47xx_active_bus_type == BCM47XX_BUS_TYPE_BCMA) {
27 + bcma_write32(bcm47xx_bus.bcma.bus.drv_mips.core,
28 + BCMA_MIPS_MIPS74K_INTMASK(5), 1 << 31);
29 + /*
30 + * the kernel reads the timer irq from some register and thinks
31 + * it's #5, but we offset it by 2 and route to #7
32 + */
33 + cp0_compare_irq = 7;
34 + }
35 +#endif
36 mips_cpu_irq_init();
37 }