target/linux/brcm47xx/patches-3.10/111-MIPS-BCM47XX-add-cpu-overwrite.patch

   1 From b27da7f1ee034d32e410faf5ab32fc96424a0c62 Mon Sep 17 00:00:00 2001
   2 From: Hauke Mehrtens <hauke@hauke-m.de>
   3 Date: Wed, 20 Nov 2013 22:16:43 +0100
   4 Subject: [PATCH 17/18] add overwrite
   5
   6 ---
   7  .../asm/mach-bcm47xx/cpu-feature-overrides.h       |   82 ++++++++++++++++++++
   8  1 file changed, 82 insertions(+)
   9  create mode 100644 arch/mips/include/asm/mach-bcm47xx/cpu-feature-overrides.h
  10
  11 --- /dev/null
  12 +++ b/arch/mips/include/asm/mach-bcm47xx/cpu-feature-overrides.h
  13 @@ -0,0 +1,82 @@
  14 +#ifndef __ASM_MACH_BCM47XX_CPU_FEATURE_OVERRIDES_H
  15 +#define __ASM_MACH_BCM47XX_CPU_FEATURE_OVERRIDES_H
  16 +
  17 +#define cpu_has_tlb                    1
  18 +#define cpu_has_4kex                   1
  19 +#define cpu_has_3k_cache               0
  20 +#define cpu_has_4k_cache               1
  21 +#define cpu_has_tx39_cache             0
  22 +#define cpu_has_fpu                    0
  23 +#define cpu_has_32fpr                  0
  24 +#define cpu_has_counter                        1
  25 +#if defined(CONFIG_BCM47XX_BCMA) && !defined(CONFIG_BCM47XX_SSB)
  26 +#define cpu_has_watch                  1
  27 +#elif defined(CONFIG_BCM47XX_SSB) && !defined(CONFIG_BCM47XX_BCMA)
  28 +#define cpu_has_watch                  0
  29 +#endif
  30 +#define cpu_has_divec                  1
  31 +#define cpu_has_vce                    0
  32 +#define cpu_has_cache_cdex_p           0
  33 +#define cpu_has_cache_cdex_s           0
  34 +#define cpu_has_prefetch               1
  35 +#define cpu_has_mcheck                 1
  36 +#define cpu_has_ejtag                  1
  37 +#define cpu_has_llsc                   1
  38 +
  39 +/* cpu_has_mips16 */
  40 +#define cpu_has_mdmx                   0
  41 +#define cpu_has_mips3d                 0
  42 +#define cpu_has_rixi                   0
  43 +#define cpu_has_mmips                  0
  44 +#define cpu_has_smartmips              0
  45 +#define cpu_has_vtag_icache            0
  46 +/* cpu_has_dc_aliases */
  47 +#define cpu_has_ic_fills_f_dc          0
  48 +#define cpu_has_pindexed_dcache                0
  49 +#define cpu_icache_snoops_remote_store 0
  50 +
  51 +#define cpu_has_mips_2                 1
  52 +#define cpu_has_mips_3                 0
  53 +#define cpu_has_mips32r1               1
  54 +#if defined(CONFIG_BCM47XX_BCMA) && !defined(CONFIG_BCM47XX_SSB)
  55 +#define cpu_has_mips32r2               1
  56 +#elif defined(CONFIG_BCM47XX_SSB) && !defined(CONFIG_BCM47XX_BCMA)
  57 +#define cpu_has_mips32r2               0
  58 +#endif
  59 +#define cpu_has_mips64r1               0
  60 +#define cpu_has_mips64r2               0
  61 +
  62 +#if defined(CONFIG_BCM47XX_BCMA) && !defined(CONFIG_BCM47XX_SSB)
  63 +#define cpu_has_dsp                    1
  64 +#define cpu_has_dsp2                   1
  65 +#elif defined(CONFIG_BCM47XX_SSB) && !defined(CONFIG_BCM47XX_BCMA)
  66 +#define cpu_has_dsp                    0
  67 +#define cpu_has_dsp2                   0
  68 +#endif
  69 +#define cpu_has_mipsmt                 0
  70 +/* cpu_has_userlocal */
  71 +
  72 +#define cpu_has_nofpuex                        0
  73 +#define cpu_has_64bits                 0
  74 +#define cpu_has_64bit_zero_reg         0
  75 +#if defined(CONFIG_BCM47XX_BCMA) && !defined(CONFIG_BCM47XX_SSB)
  76 +#define cpu_has_vint                   1
  77 +#elif defined(CONFIG_BCM47XX_SSB) && !defined(CONFIG_BCM47XX_BCMA)
  78 +#define cpu_has_vint                   0
  79 +#endif
  80 +#define cpu_has_veic                   0
  81 +#define cpu_has_inclusive_pcaches      0
  82 +
  83 +#if defined(CONFIG_BCM47XX_BCMA) && !defined(CONFIG_BCM47XX_SSB)
  84 +#define cpu_dcache_line_size()         32
  85 +#define cpu_icache_line_size()         32
  86 +#define cpu_has_perf_cntr_intr_bit     1
  87 +#elif defined(CONFIG_BCM47XX_SSB) && !defined(CONFIG_BCM47XX_BCMA)
  88 +#define cpu_dcache_line_size()         16
  89 +#define cpu_icache_line_size()         16
  90 +#define cpu_has_perf_cntr_intr_bit     0
  91 +#endif
  92 +#define cpu_scache_line_size()         0
  93 +#define cpu_has_vz                     0
  94 +
  95 +#endif /* __ASM_MACH_BCM47XX_CPU_FEATURE_OVERRIDES_H */