brcm47xx: 3.14: backport MIPS patches for early HIGHMEM support
[openwrt/svn-archive/archive.git] / target / linux / brcm47xx / patches-3.14 / 152-Revert-MIPS-Delete-unused-function-add_temporary_ent.patch
1 From d377732c8c9aac14ccb900b65678558b0fb8f0f3 Mon Sep 17 00:00:00 2001
2 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <zajec5@gmail.com>
3 Date: Thu, 17 Jul 2014 23:26:32 +0200
4 Subject: [PATCH 152/153] Revert "MIPS: Delete unused function
5 add_temporary_entry."
6 MIME-Version: 1.0
7 Content-Type: text/plain; charset=UTF-8
8 Content-Transfer-Encoding: 8bit
9
10 This reverts commit d7a887a73dec6c387b02a966a71aac767bbd9ce6.
11
12 Function add_temporary_entry is needed by bcm47xx to support highmem. We
13 need to add a temporary entry to check for amount of RAM.
14 The only change made in this revert was replacing (ENTER|EXIT)_CRITICAL.
15
16 Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
17 Cc: linux-mips@linux-mips.org
18 Cc: Hauke Mehrtens <hauke@hauke-m.de>
19 Patchwork: https://patchwork.linux-mips.org/patch/7395/
20 Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
21 ---
22 arch/mips/include/asm/pgtable-32.h | 10 ++++++++
23 arch/mips/mm/tlb-r4k.c | 47 ++++++++++++++++++++++++++++++++++++++
24 2 files changed, 57 insertions(+)
25
26 --- a/arch/mips/include/asm/pgtable-32.h
27 +++ b/arch/mips/include/asm/pgtable-32.h
28 @@ -19,6 +19,16 @@
29 #include <asm-generic/pgtable-nopmd.h>
30
31 /*
32 + * - add_temporary_entry() add a temporary TLB entry. We use TLB entries
33 + * starting at the top and working down. This is for populating the
34 + * TLB before trap_init() puts the TLB miss handler in place. It
35 + * should be used only for entries matching the actual page tables,
36 + * to prevent inconsistencies.
37 + */
38 +extern int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1,
39 + unsigned long entryhi, unsigned long pagemask);
40 +
41 +/*
42 * Basically we have the same two-level (which is the logical three level
43 * Linux page table layout folded) page tables as the i386. Some day
44 * when we have proper page coloring support we can have a 1% quicker
45 --- a/arch/mips/mm/tlb-r4k.c
46 +++ b/arch/mips/mm/tlb-r4k.c
47 @@ -411,6 +411,51 @@ int __init has_transparent_hugepage(void
48
49 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
50
51 +/*
52 + * Used for loading TLB entries before trap_init() has started, when we
53 + * don't actually want to add a wired entry which remains throughout the
54 + * lifetime of the system
55 + */
56 +
57 +static int temp_tlb_entry __cpuinitdata;
58 +
59 +__init int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1,
60 + unsigned long entryhi, unsigned long pagemask)
61 +{
62 + int ret = 0;
63 + unsigned long flags;
64 + unsigned long wired;
65 + unsigned long old_pagemask;
66 + unsigned long old_ctx;
67 +
68 + local_irq_save(flags);
69 + /* Save old context and create impossible VPN2 value */
70 + old_ctx = read_c0_entryhi();
71 + old_pagemask = read_c0_pagemask();
72 + wired = read_c0_wired();
73 + if (--temp_tlb_entry < wired) {
74 + printk(KERN_WARNING
75 + "No TLB space left for add_temporary_entry\n");
76 + ret = -ENOSPC;
77 + goto out;
78 + }
79 +
80 + write_c0_index(temp_tlb_entry);
81 + write_c0_pagemask(pagemask);
82 + write_c0_entryhi(entryhi);
83 + write_c0_entrylo0(entrylo0);
84 + write_c0_entrylo1(entrylo1);
85 + mtc0_tlbw_hazard();
86 + tlb_write_indexed();
87 + tlbw_use_hazard();
88 +
89 + write_c0_entryhi(old_ctx);
90 + write_c0_pagemask(old_pagemask);
91 +out:
92 + local_irq_restore(flags);
93 + return ret;
94 +}
95 +
96 static int ntlb;
97 static int __init set_ntlb(char *str)
98 {
99 @@ -448,6 +493,8 @@ void tlb_init(void)
100 write_c0_pagegrain(pg);
101 }
102
103 + temp_tlb_entry = current_cpu_data.tlbsize - 1;
104 +
105 /* From this point on the ARC firmware is dead. */
106 local_flush_tlb_all();
107