brcm47xx: add support for kernel 3.6
[openwrt/svn-archive/archive.git] / target / linux / brcm47xx / patches-3.6 / 700-ssb-gigabit-ethernet-driver.patch
1 --- a/drivers/net/ethernet/broadcom/tg3.c
2 +++ b/drivers/net/ethernet/broadcom/tg3.c
3 @@ -44,6 +44,7 @@
4 #include <linux/prefetch.h>
5 #include <linux/dma-mapping.h>
6 #include <linux/firmware.h>
7 +#include <linux/ssb/ssb_driver_gige.h>
8 #if IS_ENABLED(CONFIG_HWMON)
9 #include <linux/hwmon.h>
10 #include <linux/hwmon-sysfs.h>
11 @@ -253,6 +254,7 @@ static DEFINE_PCI_DEVICE_TABLE(tg3_pci_t
12 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
13 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
14 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
15 + {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
16 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
17 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
18 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
19 @@ -535,7 +537,9 @@ static void _tw32_flush(struct tg3 *tp,
20 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
21 {
22 tp->write32_mbox(tp, off, val);
23 - if (!tg3_flag(tp, MBOX_WRITE_REORDER) && !tg3_flag(tp, ICH_WORKAROUND))
24 + if (tg3_flag(tp, FLUSH_POSTED_WRITES) ||
25 + (!tg3_flag(tp, MBOX_WRITE_REORDER) &&
26 + !tg3_flag(tp, ICH_WORKAROUND)))
27 tp->read32_mbox(tp, off);
28 }
29
30 @@ -545,7 +549,8 @@ static void tg3_write32_tx_mbox(struct t
31 writel(val, mbox);
32 if (tg3_flag(tp, TXD_MBOX_HWBUG))
33 writel(val, mbox);
34 - if (tg3_flag(tp, MBOX_WRITE_REORDER))
35 + if (tg3_flag(tp, MBOX_WRITE_REORDER) ||
36 + tg3_flag(tp, FLUSH_POSTED_WRITES))
37 readl(mbox);
38 }
39
40 @@ -1052,7 +1057,8 @@ static void tg3_switch_clocks(struct tg3
41
42 #define PHY_BUSY_LOOPS 5000
43
44 -static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
45 +static int __tg3_readphy(struct tg3 *tp, unsigned int phy_addr, int reg,
46 + u32 *val)
47 {
48 u32 frame_val;
49 unsigned int loops;
50 @@ -1068,7 +1074,7 @@ static int tg3_readphy(struct tg3 *tp, i
51
52 *val = 0x0;
53
54 - frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
55 + frame_val = ((phy_addr << MI_COM_PHY_ADDR_SHIFT) &
56 MI_COM_PHY_ADDR_MASK);
57 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
58 MI_COM_REG_ADDR_MASK);
59 @@ -1105,7 +1111,13 @@ static int tg3_readphy(struct tg3 *tp, i
60 return ret;
61 }
62
63 -static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
64 +static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
65 +{
66 + return __tg3_readphy(tp, tp->phy_addr, reg, val);
67 +}
68 +
69 +static int __tg3_writephy(struct tg3 *tp, unsigned int phy_addr, int reg,
70 + u32 val)
71 {
72 u32 frame_val;
73 unsigned int loops;
74 @@ -1123,7 +1135,7 @@ static int tg3_writephy(struct tg3 *tp,
75
76 tg3_ape_lock(tp, tp->phy_ape_lock);
77
78 - frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
79 + frame_val = ((phy_addr << MI_COM_PHY_ADDR_SHIFT) &
80 MI_COM_PHY_ADDR_MASK);
81 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
82 MI_COM_REG_ADDR_MASK);
83 @@ -1158,6 +1170,11 @@ static int tg3_writephy(struct tg3 *tp,
84 return ret;
85 }
86
87 +static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
88 +{
89 + return __tg3_writephy(tp, tp->phy_addr, reg, val);
90 +}
91 +
92 static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val)
93 {
94 int err;
95 @@ -1730,6 +1747,11 @@ static int tg3_poll_fw(struct tg3 *tp)
96 int i;
97 u32 val;
98
99 + if (tg3_flag(tp, IS_SSB_CORE)) {
100 + /* We don't use firmware. */
101 + return 0;
102 + }
103 +
104 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
105 /* Wait up to 20ms for init done. */
106 for (i = 0; i < 200; i++) {
107 @@ -3312,6 +3334,8 @@ static int tg3_nvram_write_block(struct
108 {
109 int ret;
110
111 + if (tg3_flag(tp, IS_SSB_CORE))
112 + return -ENODEV;
113 if (tg3_flag(tp, EEPROM_WRITE_PROT)) {
114 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
115 ~GRC_LCLCTRL_GPIO_OUTPUT1);
116 @@ -3387,6 +3411,11 @@ static int tg3_halt_cpu(struct tg3 *tp,
117 tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
118 udelay(10);
119 } else {
120 + /* There is only an Rx CPU for the 5750 derivative in the
121 + * BCM4785. */
122 + if (tg3_flag(tp, IS_SSB_CORE))
123 + return 0;
124 +
125 for (i = 0; i < 10000; i++) {
126 tw32(offset + CPU_STATE, 0xffffffff);
127 tw32(offset + CPU_MODE, CPU_MODE_HALT);
128 @@ -3401,9 +3430,12 @@ static int tg3_halt_cpu(struct tg3 *tp,
129 return -ENODEV;
130 }
131
132 - /* Clear firmware's nvram arbitration. */
133 - if (tg3_flag(tp, NVRAM))
134 - tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
135 + if (!tg3_flag(tp, IS_SSB_CORE)) {
136 + /* Clear firmware's nvram arbitration. */
137 + if (tg3_flag(tp, NVRAM))
138 + tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
139 + }
140 +
141 return 0;
142 }
143
144 @@ -3466,6 +3498,11 @@ static int tg3_load_5701_a0_firmware_fix
145 const __be32 *fw_data;
146 int err, i;
147
148 + if (tg3_flag(tp, IS_SSB_CORE)) {
149 + /* We don't use firmware. */
150 + return 0;
151 + }
152 +
153 fw_data = (void *)tp->fw->data;
154
155 /* Firmware blob starts with version numbers, followed by
156 @@ -3522,6 +3559,11 @@ static int tg3_load_tso_firmware(struct
157 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
158 int err, i;
159
160 + if (tg3_flag(tp, IS_SSB_CORE)) {
161 + /* We don't use firmware. */
162 + return 0;
163 + }
164 +
165 if (tg3_flag(tp, HW_TSO_1) ||
166 tg3_flag(tp, HW_TSO_2) ||
167 tg3_flag(tp, HW_TSO_3))
168 @@ -3862,8 +3904,9 @@ static int tg3_power_down_prepare(struct
169 tg3_frob_aux_power(tp, true);
170
171 /* Workaround for unstable PLL clock */
172 - if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
173 - (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
174 + if ((!tg3_flag(tp, IS_SSB_CORE)) &&
175 + ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
176 + (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX))) {
177 u32 val = tr32(0x7d00);
178
179 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
180 @@ -4365,6 +4408,14 @@ relink:
181 if (current_link_up == 0 || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
182 tg3_phy_copper_begin(tp);
183
184 + if (tg3_flag(tp, ROBOSWITCH)) {
185 + current_link_up = 1;
186 + current_speed = SPEED_1000; /* FIXME */
187 + current_duplex = DUPLEX_FULL;
188 + tp->link_config.active_speed = current_speed;
189 + tp->link_config.active_duplex = current_duplex;
190 + }
191 +
192 tg3_readphy(tp, MII_BMSR, &bmsr);
193 if ((!tg3_readphy(tp, MII_BMSR, &bmsr) && (bmsr & BMSR_LSTATUS)) ||
194 (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK))
195 @@ -4383,6 +4434,26 @@ relink:
196 else
197 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
198
199 + /* In order for the 5750 core in BCM4785 chip to work properly
200 + * in RGMII mode, the Led Control Register must be set up.
201 + */
202 + if (tg3_flag(tp, RGMII_MODE)) {
203 + u32 led_ctrl = tr32(MAC_LED_CTRL);
204 + led_ctrl &= ~(LED_CTRL_1000MBPS_ON | LED_CTRL_100MBPS_ON);
205 +
206 + if (tp->link_config.active_speed == SPEED_10)
207 + led_ctrl |= LED_CTRL_LNKLED_OVERRIDE;
208 + else if (tp->link_config.active_speed == SPEED_100)
209 + led_ctrl |= (LED_CTRL_LNKLED_OVERRIDE |
210 + LED_CTRL_100MBPS_ON);
211 + else if (tp->link_config.active_speed == SPEED_1000)
212 + led_ctrl |= (LED_CTRL_LNKLED_OVERRIDE |
213 + LED_CTRL_1000MBPS_ON);
214 +
215 + tw32(MAC_LED_CTRL, led_ctrl);
216 + udelay(40);
217 + }
218 +
219 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
220 if (tp->link_config.active_duplex == DUPLEX_HALF)
221 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
222 @@ -8110,6 +8181,14 @@ static int tg3_chip_reset(struct tg3 *tp
223 tw32(0x5000, 0x400);
224 }
225
226 + if (tg3_flag(tp, IS_SSB_CORE)) {
227 + /* BCM4785: In order to avoid repercussions from using
228 + * potentially defective internal ROM, stop the Rx RISC CPU,
229 + * which is not required. */
230 + tg3_stop_fw(tp);
231 + tg3_halt_cpu(tp, RX_CPU_BASE);
232 + }
233 +
234 tw32(GRC_MODE, tp->grc_mode);
235
236 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
237 @@ -9729,6 +9808,11 @@ static void tg3_timer(unsigned long __op
238 tg3_flag(tp, 57765_CLASS))
239 tg3_chk_missed_msi(tp);
240
241 + if (tg3_flag(tp, FLUSH_POSTED_WRITES)) {
242 + /* BCM4785: Flush posted writes from GbE to host memory. */
243 + tr32(HOSTCC_MODE);
244 + }
245 +
246 if (!tg3_flag(tp, TAGGED_STATUS)) {
247 /* All of this garbage is because when using non-tagged
248 * IRQ status the mailbox/status_block protocol the chip
249 @@ -11424,6 +11508,11 @@ static int tg3_test_nvram(struct tg3 *tp
250 if (tg3_flag(tp, NO_NVRAM))
251 return 0;
252
253 + if (tg3_flag(tp, IS_SSB_CORE)) {
254 + /* We don't have NVRAM. */
255 + return 0;
256 + }
257 +
258 if (tg3_nvram_read(tp, 0, &magic) != 0)
259 return -EIO;
260
261 @@ -12392,11 +12481,12 @@ static int tg3_ioctl(struct net_device *
262 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
263 break; /* We have no PHY */
264
265 - if (!netif_running(dev))
266 + if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
267 return -EAGAIN;
268
269 spin_lock_bh(&tp->lock);
270 - err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
271 + err = __tg3_readphy(tp, data->phy_id & 0x1f,
272 + data->reg_num & 0x1f, &mii_regval);
273 spin_unlock_bh(&tp->lock);
274
275 data->val_out = mii_regval;
276 @@ -12408,11 +12498,12 @@ static int tg3_ioctl(struct net_device *
277 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
278 break; /* We have no PHY */
279
280 - if (!netif_running(dev))
281 + if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
282 return -EAGAIN;
283
284 spin_lock_bh(&tp->lock);
285 - err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
286 + err = __tg3_writephy(tp, data->phy_id & 0x1f,
287 + data->reg_num & 0x1f, data->val_in);
288 spin_unlock_bh(&tp->lock);
289
290 return err;
291 @@ -13260,6 +13351,13 @@ static void __devinit tg3_get_5720_nvram
292 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
293 static void __devinit tg3_nvram_init(struct tg3 *tp)
294 {
295 + if (tg3_flag(tp, IS_SSB_CORE)) {
296 + /* No NVRAM and EEPROM on the SSB Broadcom GigE core. */
297 + tg3_flag_clear(tp, NVRAM);
298 + tg3_flag_clear(tp, NVRAM_BUFFERED);
299 + return;
300 + }
301 +
302 tw32_f(GRC_EEPROM_ADDR,
303 (EEPROM_ADDR_FSM_RESET |
304 (EEPROM_DEFAULT_CLOCK_PERIOD <<
305 @@ -13752,10 +13850,19 @@ static int __devinit tg3_phy_probe(struc
306 * subsys device table.
307 */
308 p = tg3_lookup_by_subsys(tp);
309 - if (!p)
310 + if (p) {
311 + tp->phy_id = p->phy_id;
312 + } else if (!tg3_flag(tp, IS_SSB_CORE)) {
313 + /* For now we saw the IDs 0xbc050cd0,
314 + * 0xbc050f80 and 0xbc050c30 on devices
315 + * connected to an BCM4785 and there are
316 + * probably more. Just assume that the phy is
317 + * supported when it is connected to a SSB core
318 + * for now.
319 + */
320 return -ENODEV;
321 + }
322
323 - tp->phy_id = p->phy_id;
324 if (!tp->phy_id ||
325 tp->phy_id == TG3_PHY_ID_BCM8002)
326 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
327 @@ -14765,6 +14872,11 @@ static int __devinit tg3_get_invariants(
328 }
329 }
330
331 + if (tg3_flag(tp, FLUSH_POSTED_WRITES)) {
332 + tp->write32_tx_mbox = tg3_write_flush_reg32;
333 + tp->write32_rx_mbox = tg3_write_flush_reg32;
334 + }
335 +
336 /* Get eeprom hw config before calling tg3_set_power_state().
337 * In particular, the TG3_FLAG_IS_NIC flag must be
338 * determined before calling tg3_set_power_state() so that
339 @@ -15174,6 +15286,10 @@ static int __devinit tg3_get_device_addr
340 }
341
342 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
343 + if (tg3_flag(tp, IS_SSB_CORE))
344 + ssb_gige_get_macaddr(tp->pdev, &dev->dev_addr[0]);
345 + }
346 + if (!is_valid_ether_addr(&dev->dev_addr[0])) {
347 #ifdef CONFIG_SPARC
348 if (!tg3_get_default_macaddr_sparc(tp))
349 return 0;
350 @@ -15458,7 +15574,8 @@ static int __devinit tg3_test_dma(struct
351 if (tg3_flag(tp, 40BIT_DMA_BUG) &&
352 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
353 tp->dma_rwctrl |= 0x8000;
354 - else if (ccval == 0x6 || ccval == 0x7)
355 + else if ((ccval == 0x6 || ccval == 0x7) ||
356 + tg3_flag(tp, ONE_DMA_AT_ONCE))
357 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
358
359 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
360 @@ -15820,6 +15937,17 @@ static int __devinit tg3_init_one(struct
361 tp->msg_enable = tg3_debug;
362 else
363 tp->msg_enable = TG3_DEF_MSG_ENABLE;
364 + if (pdev_is_ssb_gige_core(pdev)) {
365 + tg3_flag_set(tp, IS_SSB_CORE);
366 + if (ssb_gige_must_flush_posted_writes(pdev))
367 + tg3_flag_set(tp, FLUSH_POSTED_WRITES);
368 + if (ssb_gige_one_dma_at_once(pdev))
369 + tg3_flag_set(tp, ONE_DMA_AT_ONCE);
370 + if (ssb_gige_have_roboswitch(pdev))
371 + tg3_flag_set(tp, ROBOSWITCH);
372 + if (ssb_gige_is_rgmii(pdev))
373 + tg3_flag_set(tp, RGMII_MODE);
374 + }
375
376 /* The word/byte swap controls here control register access byte
377 * swapping. DMA data byte swapping is controlled in the GRC_MODE
378 --- a/drivers/net/ethernet/broadcom/tg3.h
379 +++ b/drivers/net/ethernet/broadcom/tg3.h
380 @@ -2973,6 +2973,11 @@ enum TG3_FLAGS {
381 TG3_FLAG_57765_PLUS,
382 TG3_FLAG_57765_CLASS,
383 TG3_FLAG_5717_PLUS,
384 + TG3_FLAG_IS_SSB_CORE,
385 + TG3_FLAG_FLUSH_POSTED_WRITES,
386 + TG3_FLAG_ROBOSWITCH,
387 + TG3_FLAG_ONE_DMA_AT_ONCE,
388 + TG3_FLAG_RGMII_MODE,
389
390 /* Add new flags before this comment and TG3_FLAG_NUMBER_OF_FLAGS */
391 TG3_FLAG_NUMBER_OF_FLAGS, /* Last entry in enum TG3_FLAGS */
392 --- a/include/linux/pci_ids.h
393 +++ b/include/linux/pci_ids.h
394 @@ -2121,6 +2121,7 @@
395 #define PCI_DEVICE_ID_TIGON3_5754M 0x1672
396 #define PCI_DEVICE_ID_TIGON3_5755M 0x1673
397 #define PCI_DEVICE_ID_TIGON3_5756 0x1674
398 +#define PCI_DEVICE_ID_TIGON3_5750 0x1676
399 #define PCI_DEVICE_ID_TIGON3_5751 0x1677
400 #define PCI_DEVICE_ID_TIGON3_5715 0x1678
401 #define PCI_DEVICE_ID_TIGON3_5715S 0x1679
402 --- a/include/linux/ssb/ssb_driver_gige.h
403 +++ b/include/linux/ssb/ssb_driver_gige.h
404 @@ -97,21 +97,12 @@ static inline bool ssb_gige_must_flush_p
405 return 0;
406 }
407
408 -#ifdef CONFIG_BCM47XX
409 -#include <asm/mach-bcm47xx/nvram.h>
410 -/* Get the device MAC address */
411 -static inline void ssb_gige_get_macaddr(struct pci_dev *pdev, u8 *macaddr)
412 -{
413 - char buf[20];
414 - if (nvram_getenv("et0macaddr", buf, sizeof(buf)) < 0)
415 - return;
416 - nvram_parse_macaddr(buf, macaddr);
417 -}
418 -#else
419 static inline void ssb_gige_get_macaddr(struct pci_dev *pdev, u8 *macaddr)
420 {
421 + struct ssb_gige *dev = pdev_to_ssb_gige(pdev);
422 +
423 + memcpy(macaddr, dev->dev->bus->sprom.et0mac, 6);
424 }
425 -#endif
426
427 extern int ssb_gige_pcibios_plat_dev_init(struct ssb_device *sdev,
428 struct pci_dev *pdev);
429 @@ -175,6 +166,9 @@ static inline bool ssb_gige_must_flush_p
430 {
431 return 0;
432 }
433 +static inline void ssb_gige_get_macaddr(struct pci_dev *pdev, u8 *macaddr)
434 +{
435 +}
436
437 #endif /* CONFIG_SSB_DRIVER_GIGE */
438 #endif /* LINUX_SSB_DRIVER_GIGE_H_ */