[8.09] kernel: refresh patches
[openwrt/svn-archive/archive.git] / target / linux / brcm47xx / patches / 130-remove_scache.patch
1 --- a/arch/mips/Kconfig
2 +++ b/arch/mips/Kconfig
3 @@ -228,7 +228,6 @@ config MIPS_MALTA
4 select I8259
5 select MIPS_BOARDS_GEN
6 select MIPS_BONITO64
7 - select MIPS_CPU_SCACHE
8 select PCI_GT64XXX_PCI0
9 select MIPS_MSC
10 select SWAP_IO_SPACE
11 @@ -1421,13 +1420,6 @@ config IP22_CPU_SCACHE
12 bool
13 select BOARD_SCACHE
14
15 -#
16 -# Support for a MIPS32 / MIPS64 style S-caches
17 -#
18 -config MIPS_CPU_SCACHE
19 - bool
20 - select BOARD_SCACHE
21 -
22 config R5000_CPU_SCACHE
23 bool
24 select BOARD_SCACHE
25 --- a/arch/mips/kernel/cpu-probe.c
26 +++ b/arch/mips/kernel/cpu-probe.c
27 @@ -704,6 +704,8 @@ static inline void cpu_probe_mips(struct
28 break;
29 case PRID_IMP_25KF:
30 c->cputype = CPU_25KF;
31 + /* Probe for L2 cache */
32 + c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
33 break;
34 case PRID_IMP_34K:
35 c->cputype = CPU_34K;
36 --- a/arch/mips/mm/c-r4k.c
37 +++ b/arch/mips/mm/c-r4k.c
38 @@ -1103,7 +1103,6 @@ static void __init loongson2_sc_init(voi
39
40 extern int r5k_sc_init(void);
41 extern int rm7k_sc_init(void);
42 -extern int mips_sc_init(void);
43
44 static void __cpuinit setup_scache(void)
45 {
46 @@ -1157,29 +1156,17 @@ static void __cpuinit setup_scache(void)
47 #endif
48
49 default:
50 - if (c->isa_level == MIPS_CPU_ISA_M32R1 ||
51 - c->isa_level == MIPS_CPU_ISA_M32R2 ||
52 - c->isa_level == MIPS_CPU_ISA_M64R1 ||
53 - c->isa_level == MIPS_CPU_ISA_M64R2) {
54 -#ifdef CONFIG_MIPS_CPU_SCACHE
55 - if (mips_sc_init ()) {
56 - scache_size = c->scache.ways * c->scache.sets * c->scache.linesz;
57 - printk("MIPS secondary cache %ldkB, %s, linesize %d bytes.\n",
58 - scache_size >> 10,
59 - way_string[c->scache.ways], c->scache.linesz);
60 - }
61 -#else
62 - if (!(c->scache.flags & MIPS_CACHE_NOT_PRESENT))
63 - panic("Dunno how to handle MIPS32 / MIPS64 second level cache");
64 -#endif
65 - return;
66 - }
67 sc_present = 0;
68 }
69
70 if (!sc_present)
71 return;
72
73 + if ((c->isa_level == MIPS_CPU_ISA_M32R1 ||
74 + c->isa_level == MIPS_CPU_ISA_M64R1) &&
75 + !(c->scache.flags & MIPS_CACHE_NOT_PRESENT))
76 + panic("Dunno how to handle MIPS32 / MIPS64 second level cache");
77 +
78 /* compute a couple of other cache variables */
79 c->scache.waysize = scache_size / c->scache.ways;
80
81 --- a/arch/mips/mm/Makefile
82 +++ b/arch/mips/mm/Makefile
83 @@ -32,6 +32,5 @@ obj-$(CONFIG_CPU_VR41XX) += c-r4k.o cex-
84 obj-$(CONFIG_IP22_CPU_SCACHE) += sc-ip22.o
85 obj-$(CONFIG_R5000_CPU_SCACHE) += sc-r5k.o
86 obj-$(CONFIG_RM7000_CPU_SCACHE) += sc-rm7k.o
87 -obj-$(CONFIG_MIPS_CPU_SCACHE) += sc-mips.o
88
89 EXTRA_CFLAGS += -Werror