target/linux/brcm63xx/files/arch/mips/bcm63xx/cpu.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
   7  */
   8
   9 #include <linux/kernel.h>
  10 #include <linux/module.h>
  11 #include <linux/cpu.h>
  12 #include <bcm63xx_cpu.h>
  13 #include <bcm63xx_regs.h>
  14 #include <bcm63xx_io.h>
  15 #include <bcm63xx_irq.h>
  16
  17 const unsigned long *bcm63xx_regs_base;
  18 EXPORT_SYMBOL(bcm63xx_regs_base);
  19
  20 const int *bcm63xx_irqs;
  21 EXPORT_SYMBOL(bcm63xx_irqs);
  22
  23 static u16 bcm63xx_cpu_id;
  24 static u16 bcm63xx_cpu_rev;
  25 static unsigned int bcm63xx_cpu_freq;
  26 static unsigned int bcm63xx_memory_size;
  27
  28 /*
  29  * 6338 register sets and irqs
  30  */
  31
  32 static const unsigned long bcm96338_regs_base[] = {
  33         [RSET_PERF]             = BCM_6338_PERF_BASE,
  34         [RSET_TIMER]            = BCM_6338_TIMER_BASE,
  35         [RSET_WDT]              = BCM_6338_WDT_BASE,
  36         [RSET_UART0]            = BCM_6338_UART0_BASE,
  37         [RSET_GPIO]             = BCM_6338_GPIO_BASE,
  38         [RSET_SPI]              = BCM_6338_SPI_BASE,
  39         [RSET_MEMC]             = BCM_6338_MEMC_BASE,
  40 };
  41
  42 static const int bcm96338_irqs[] = {
  43         [IRQ_TIMER]             = BCM_6338_TIMER_IRQ,
  44         [IRQ_UART0]             = BCM_6338_UART0_IRQ,
  45         [IRQ_DSL]               = BCM_6338_DSL_IRQ,
  46         [IRQ_ENET0]             = BCM_6338_ENET0_IRQ,
  47         [IRQ_ENET_PHY]          = BCM_6338_ENET_PHY_IRQ,
  48         [IRQ_ENET0_RXDMA]       = BCM_6338_ENET0_RXDMA_IRQ,
  49         [IRQ_ENET0_TXDMA]       = BCM_6338_ENET0_TXDMA_IRQ,
  50 };
  51
  52 /*
  53  * 6348 register sets and irqs
  54  */
  55 static const unsigned long bcm96348_regs_base[] = {
  56         [RSET_DSL_LMEM]         = BCM_6348_DSL_LMEM_BASE,
  57         [RSET_PERF]             = BCM_6348_PERF_BASE,
  58         [RSET_TIMER]            = BCM_6348_TIMER_BASE,
  59         [RSET_WDT]              = BCM_6348_WDT_BASE,
  60         [RSET_UART0]            = BCM_6348_UART0_BASE,
  61         [RSET_GPIO]             = BCM_6348_GPIO_BASE,
  62         [RSET_SPI]              = BCM_6348_SPI_BASE,
  63         [RSET_OHCI0]            = BCM_6348_OHCI0_BASE,
  64         [RSET_OHCI_PRIV]        = BCM_6348_OHCI_PRIV_BASE,
  65         [RSET_USBH_PRIV]        = BCM_6348_USBH_PRIV_BASE,
  66         [RSET_MPI]              = BCM_6348_MPI_BASE,
  67         [RSET_PCMCIA]           = BCM_6348_PCMCIA_BASE,
  68         [RSET_SDRAM]            = BCM_6348_SDRAM_BASE,
  69         [RSET_DSL]              = BCM_6348_DSL_BASE,
  70         [RSET_ENET0]            = BCM_6348_ENET0_BASE,
  71         [RSET_ENET1]            = BCM_6348_ENET1_BASE,
  72         [RSET_ENETDMA]          = BCM_6348_ENETDMA_BASE,
  73         [RSET_MEMC]             = BCM_6348_MEMC_BASE,
  74         [RSET_DDR]              = BCM_6348_DDR_BASE,
  75 };
  76
  77 static const int bcm96348_irqs[] = {
  78         [IRQ_TIMER]             = BCM_6348_TIMER_IRQ,
  79         [IRQ_UART0]             = BCM_6348_UART0_IRQ,
  80         [IRQ_DSL]               = BCM_6348_DSL_IRQ,
  81         [IRQ_ENET0]             = BCM_6348_ENET0_IRQ,
  82         [IRQ_ENET1]             = BCM_6348_ENET1_IRQ,
  83         [IRQ_ENET_PHY]          = BCM_6348_ENET_PHY_IRQ,
  84         [IRQ_OHCI0]             = BCM_6348_OHCI0_IRQ,
  85         [IRQ_PCMCIA]            = BCM_6348_PCMCIA_IRQ,
  86         [IRQ_ENET0_RXDMA]       = BCM_6348_ENET0_RXDMA_IRQ,
  87         [IRQ_ENET0_TXDMA]       = BCM_6348_ENET0_TXDMA_IRQ,
  88         [IRQ_ENET1_RXDMA]       = BCM_6348_ENET1_RXDMA_IRQ,
  89         [IRQ_ENET1_TXDMA]       = BCM_6348_ENET1_TXDMA_IRQ,
  90         [IRQ_PCI]               = BCM_6348_PCI_IRQ,
  91 };
  92
  93 /*
  94  * 6358 register sets and irqs
  95  */
  96 static const unsigned long bcm96358_regs_base[] = {
  97         [RSET_DSL_LMEM]         = BCM_6358_DSL_LMEM_BASE,
  98         [RSET_PERF]             = BCM_6358_PERF_BASE,
  99         [RSET_TIMER]            = BCM_6358_TIMER_BASE,
 100         [RSET_WDT]              = BCM_6358_WDT_BASE,
 101         [RSET_UART0]            = BCM_6358_UART0_BASE,
 102         [RSET_GPIO]             = BCM_6358_GPIO_BASE,
 103         [RSET_SPI]              = BCM_6358_SPI_BASE,
 104         [RSET_OHCI0]            = BCM_6358_OHCI0_BASE,
 105         [RSET_EHCI0]            = BCM_6358_EHCI0_BASE,
 106         [RSET_OHCI_PRIV]        = BCM_6358_OHCI_PRIV_BASE,
 107         [RSET_USBH_PRIV]        = BCM_6358_USBH_PRIV_BASE,
 108         [RSET_MPI]              = BCM_6358_MPI_BASE,
 109         [RSET_PCMCIA]           = BCM_6358_PCMCIA_BASE,
 110         [RSET_SDRAM]            = BCM_6358_SDRAM_BASE,
 111         [RSET_DSL]              = BCM_6358_DSL_BASE,
 112         [RSET_ENET0]            = BCM_6358_ENET0_BASE,
 113         [RSET_ENET1]            = BCM_6358_ENET1_BASE,
 114         [RSET_ENETDMA]          = BCM_6358_ENETDMA_BASE,
 115         [RSET_MEMC]             = BCM_6358_MEMC_BASE,
 116         [RSET_DDR]              = BCM_6358_DDR_BASE,
 117 };
 118
 119 static const int bcm96358_irqs[] = {
 120         [IRQ_TIMER]             = BCM_6358_TIMER_IRQ,
 121         [IRQ_UART0]             = BCM_6358_UART0_IRQ,
 122         [IRQ_DSL]               = BCM_6358_DSL_IRQ,
 123         [IRQ_ENET0]             = BCM_6358_ENET0_IRQ,
 124         [IRQ_ENET1]             = BCM_6358_ENET1_IRQ,
 125         [IRQ_ENET_PHY]          = BCM_6358_ENET_PHY_IRQ,
 126         [IRQ_OHCI0]             = BCM_6358_OHCI0_IRQ,
 127         [IRQ_EHCI0]             = BCM_6358_EHCI0_IRQ,
 128         [IRQ_PCMCIA]            = BCM_6358_PCMCIA_IRQ,
 129         [IRQ_ENET0_RXDMA]       = BCM_6358_ENET0_RXDMA_IRQ,
 130         [IRQ_ENET0_TXDMA]       = BCM_6358_ENET0_TXDMA_IRQ,
 131         [IRQ_ENET1_RXDMA]       = BCM_6358_ENET1_RXDMA_IRQ,
 132         [IRQ_ENET1_TXDMA]       = BCM_6358_ENET1_TXDMA_IRQ,
 133         [IRQ_PCI]               = BCM_6358_PCI_IRQ,
 134 };
 135
 136 u16 __bcm63xx_get_cpu_id(void)
 137 {
 138         return bcm63xx_cpu_id;
 139 }
 140
 141 EXPORT_SYMBOL(__bcm63xx_get_cpu_id);
 142
 143 u16 bcm63xx_get_cpu_rev(void)
 144 {
 145         return bcm63xx_cpu_rev;
 146 }
 147
 148 EXPORT_SYMBOL(bcm63xx_get_cpu_rev);
 149
 150 unsigned int bcm63xx_get_cpu_freq(void)
 151 {
 152         return bcm63xx_cpu_freq;
 153 }
 154
 155 unsigned int bcm63xx_get_memory_size(void)
 156 {
 157         return bcm63xx_memory_size;
 158 }
 159
 160 static unsigned int detect_cpu_clock(void)
 161 {
 162         unsigned int tmp, n1 = 0, n2 = 0, m1 = 0;
 163
 164         if (BCMCPU_IS_6338()) {
 165                 return 240000000;
 166         }
 167
 168         /*
 169          * frequency depends on PLL configuration:
 170          */
 171         if (BCMCPU_IS_6348()) {
 172                 /* 16MHz * (N1 + 1) * (N2 + 2) / (M1_CPU + 1) */
 173                 tmp = bcm_perf_readl(PERF_MIPSPLLCTL_REG);
 174                 n1 = (tmp & MIPSPLLCTL_N1_MASK) >> MIPSPLLCTL_N1_SHIFT;
 175                 n2 = (tmp & MIPSPLLCTL_N2_MASK) >> MIPSPLLCTL_N2_SHIFT;
 176                 m1 = (tmp & MIPSPLLCTL_M1CPU_MASK) >> MIPSPLLCTL_M1CPU_SHIFT;
 177                 n1 += 1;
 178                 n2 += 2;
 179                 m1 += 1;
 180         }
 181
 182         if (BCMCPU_IS_6358()) {
 183                 /* 16MHz * N1 * N2 / M1_CPU */
 184                 tmp = bcm_ddr_readl(DDR_DMIPSPLLCFG_REG);
 185                 n1 = (tmp & DMIPSPLLCFG_N1_MASK) >> DMIPSPLLCFG_N1_SHIFT;
 186                 n2 = (tmp & DMIPSPLLCFG_N2_MASK) >> DMIPSPLLCFG_N2_SHIFT;
 187                 m1 = (tmp & DMIPSPLLCFG_M1_MASK) >> DMIPSPLLCFG_M1_SHIFT;
 188         }
 189
 190         return (16 * 1000000 * n1 * n2) / m1;
 191 }
 192
 193 /*
 194  * attempt to detect the amount of memory installed
 195  */
 196 static unsigned int detect_memory_size(void)
 197 {
 198         unsigned int cols = 0, rows = 0, is_32bits = 0, banks = 0;
 199         u32 val;
 200
 201         if (BCMCPU_IS_6338() || BCMCPU_IS_6348()) {
 202                 val = bcm_sdram_readl(SDRAM_CFG_REG);
 203                 rows = (val & SDRAM_CFG_ROW_MASK) >> SDRAM_CFG_ROW_SHIFT;
 204                 cols = (val & SDRAM_CFG_COL_MASK) >> SDRAM_CFG_COL_SHIFT;
 205                 is_32bits = (val & SDRAM_CFG_32B_MASK) ? 1 : 0;
 206                 banks = (val & SDRAM_CFG_BANK_MASK) ? 2 : 1;
 207         }
 208
 209         if (BCMCPU_IS_6358()) {
 210                 val = bcm_memc_readl(MEMC_CFG_REG);
 211                 rows = (val & MEMC_CFG_ROW_MASK) >> MEMC_CFG_ROW_SHIFT;
 212                 cols = (val & MEMC_CFG_COL_MASK) >> MEMC_CFG_COL_SHIFT;
 213                 is_32bits = (val & MEMC_CFG_32B_MASK) ? 0 : 1;
 214                 banks = 2;
 215         }
 216
 217         /* 0 => 11 address bits ... 2 => 13 address bits */
 218         rows += 11;
 219
 220         /* 0 => 8 address bits ... 2 => 10 address bits */
 221         cols += 8;
 222
 223         return 1 << (cols + rows + (is_32bits + 1) + banks);
 224 }
 225
 226 void __init bcm63xx_cpu_init(void)
 227 {
 228         unsigned int tmp, expected_cpu_id;
 229         struct cpuinfo_mips *c = &current_cpu_data;
 230
 231         /* soc registers location depends on cpu type */
 232         expected_cpu_id = 0;
 233
 234         switch (c->cputype) {
 235         case CPU_BCM6338:
 236                 expected_cpu_id = BCM6338_CPU_ID;
 237                 bcm63xx_regs_base = bcm96338_regs_base;
 238                 bcm63xx_irqs = bcm96338_irqs;
 239                 break;
 240         case CPU_BCM6348:
 241                 expected_cpu_id = BCM6348_CPU_ID;
 242                 bcm63xx_regs_base = bcm96348_regs_base;
 243                 bcm63xx_irqs = bcm96348_irqs;
 244                 break;
 245         case CPU_BCM6358:
 246                 expected_cpu_id = BCM6358_CPU_ID;
 247                 bcm63xx_regs_base = bcm96358_regs_base;
 248                 bcm63xx_irqs = bcm96358_irqs;
 249                 break;
 250         }
 251
 252         /* really early to panic, but delaying panic would not help
 253          * since we will never get any working console */
 254         if (!expected_cpu_id)
 255                 panic("unsupported Broadcom CPU");
 256
 257         /*
 258          * bcm63xx_regs_base is set, we can access soc registers
 259          */
 260
 261         /* double check CPU type */
 262         tmp = bcm_perf_readl(PERF_REV_REG);
 263         bcm63xx_cpu_id = (tmp & REV_CHIPID_MASK) >> REV_CHIPID_SHIFT;
 264         bcm63xx_cpu_rev = (tmp & REV_REVID_MASK) >> REV_REVID_SHIFT;
 265
 266         if (bcm63xx_cpu_id != expected_cpu_id)
 267                 panic("bcm63xx CPU id mismatch");
 268
 269         bcm63xx_cpu_freq = detect_cpu_clock();
 270         bcm63xx_memory_size = detect_memory_size();
 271
 272         printk(KERN_INFO "Detected Broadcom 0x%04x CPU revision %02x\n",
 273                bcm63xx_cpu_id, bcm63xx_cpu_rev);
 274         printk(KERN_INFO "CPU frequency is %u Hz\n",
 275                bcm63xx_cpu_freq);
 276         printk(KERN_INFO "%uMB of RAM installed\n",
 277                bcm63xx_memory_size >> 20);
 278 }