[brcm63xx] define bcm6338 SDRAM base register and make sure that the right CPU id...
[openwrt/svn-archive/archive.git] / target / linux / brcm63xx / files / arch / mips / bcm63xx / cpu.c
1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
7 * 2009 Florian Fainelli <florian@openwrt.org>
8 */
9
10 #include <linux/kernel.h>
11 #include <linux/module.h>
12 #include <linux/cpu.h>
13 #include <bcm63xx_cpu.h>
14 #include <bcm63xx_regs.h>
15 #include <bcm63xx_io.h>
16 #include <bcm63xx_irq.h>
17
18 const unsigned long *bcm63xx_regs_base;
19 EXPORT_SYMBOL(bcm63xx_regs_base);
20
21 const int *bcm63xx_irqs;
22 EXPORT_SYMBOL(bcm63xx_irqs);
23
24 const unsigned long *bcm63xx_regs_spi;
25 EXPORT_SYMBOL(bcm63xx_regs_spi);
26
27 static u16 bcm63xx_cpu_id;
28 static u16 bcm63xx_cpu_rev;
29 static unsigned int bcm63xx_cpu_freq;
30 static unsigned int bcm63xx_memory_size;
31
32 /*
33 * 6338 register sets and irqs
34 */
35
36 static const unsigned long bcm96338_regs_base[] = {
37 [RSET_PERF] = BCM_6338_PERF_BASE,
38 [RSET_TIMER] = BCM_6338_TIMER_BASE,
39 [RSET_WDT] = BCM_6338_WDT_BASE,
40 [RSET_UDC0] = BCM_6338_UDC0_BASE,
41 [RSET_UART0] = BCM_6338_UART0_BASE,
42 [RSET_GPIO] = BCM_6338_GPIO_BASE,
43 [RSET_SDRAM] = BCM_6338_SDRAM_BASE,
44 [RSET_SPI] = BCM_6338_SPI_BASE,
45 [RSET_MEMC] = BCM_6338_MEMC_BASE,
46 };
47
48 static const int bcm96338_irqs[] = {
49 [IRQ_TIMER] = BCM_6338_TIMER_IRQ,
50 [IRQ_SPI] = BCM_6338_SPI_IRQ,
51 [IRQ_UART0] = BCM_6338_UART0_IRQ,
52 [IRQ_DSL] = BCM_6338_DSL_IRQ,
53 [IRQ_UDC0] = BCM_6338_UDC0_IRQ,
54 [IRQ_ENET0] = BCM_6338_ENET0_IRQ,
55 [IRQ_ENET_PHY] = BCM_6338_ENET_PHY_IRQ,
56 [IRQ_ENET0_RXDMA] = BCM_6338_ENET0_RXDMA_IRQ,
57 [IRQ_ENET0_TXDMA] = BCM_6338_ENET0_TXDMA_IRQ,
58 };
59
60 static const unsigned long bcm96338_regs_spi[] = {
61 [SPI_CMD] = SPI_BCM_6338_SPI_CMD,
62 [SPI_INT_STATUS] = SPI_BCM_6338_SPI_INT_STATUS,
63 [SPI_INT_MASK_ST] = SPI_BCM_6338_SPI_MASK_INT_ST,
64 [SPI_INT_MASK] = SPI_BCM_6338_SPI_INT_MASK,
65 [SPI_ST] = SPI_BCM_6338_SPI_ST,
66 [SPI_CLK_CFG] = SPI_BCM_6338_SPI_CLK_CFG,
67 [SPI_FILL_BYTE] = SPI_BCM_6338_SPI_FILL_BYTE,
68 [SPI_MSG_TAIL] = SPI_BCM_6338_SPI_MSG_TAIL,
69 [SPI_RX_TAIL] = SPI_BCM_6338_SPI_RX_TAIL,
70 [SPI_MSG_CTL] = SPI_BCM_6338_SPI_MSG_CTL,
71 [SPI_MSG_DATA] = SPI_BCM_6338_SPI_MSG_DATA,
72 [SPI_RX_DATA] = SPI_BCM_6338_SPI_RX_DATA,
73 };
74
75 /*
76 * 6345 register sets and irqs
77 */
78
79 static const unsigned long bcm96345_regs_base[] = {
80 [RSET_PERF] = BCM_6345_PERF_BASE,
81 [RSET_TIMER] = BCM_6345_TIMER_BASE,
82 [RSET_WDT] = BCM_6345_WDT_BASE,
83 [RSET_UART0] = BCM_6345_UART0_BASE,
84 [RSET_GPIO] = BCM_6345_GPIO_BASE,
85 };
86
87 static const int bcm96345_irqs[] = {
88 [IRQ_TIMER] = BCM_6345_TIMER_IRQ,
89 [IRQ_UART0] = BCM_6345_UART0_IRQ,
90 [IRQ_DSL] = BCM_6345_DSL_IRQ,
91 [IRQ_ENET0] = BCM_6345_ENET0_IRQ,
92 [IRQ_ENET_PHY] = BCM_6345_ENET_PHY_IRQ,
93 };
94
95 /*
96 * 6348 register sets and irqs
97 */
98 static const unsigned long bcm96348_regs_base[] = {
99 [RSET_DSL_LMEM] = BCM_6348_DSL_LMEM_BASE,
100 [RSET_PERF] = BCM_6348_PERF_BASE,
101 [RSET_TIMER] = BCM_6348_TIMER_BASE,
102 [RSET_WDT] = BCM_6348_WDT_BASE,
103 [RSET_UART0] = BCM_6348_UART0_BASE,
104 [RSET_GPIO] = BCM_6348_GPIO_BASE,
105 [RSET_SPI] = BCM_6348_SPI_BASE,
106 [RSET_OHCI0] = BCM_6348_OHCI0_BASE,
107 [RSET_OHCI_PRIV] = BCM_6348_OHCI_PRIV_BASE,
108 [RSET_USBH_PRIV] = BCM_6348_USBH_PRIV_BASE,
109 [RSET_UDC0] = BCM_6348_UDC0_BASE,
110 [RSET_MPI] = BCM_6348_MPI_BASE,
111 [RSET_PCMCIA] = BCM_6348_PCMCIA_BASE,
112 [RSET_SDRAM] = BCM_6348_SDRAM_BASE,
113 [RSET_DSL] = BCM_6348_DSL_BASE,
114 [RSET_ENET0] = BCM_6348_ENET0_BASE,
115 [RSET_ENET1] = BCM_6348_ENET1_BASE,
116 [RSET_ENETDMA] = BCM_6348_ENETDMA_BASE,
117 [RSET_MEMC] = BCM_6348_MEMC_BASE,
118 [RSET_DDR] = BCM_6348_DDR_BASE,
119 };
120
121 static const int bcm96348_irqs[] = {
122 [IRQ_TIMER] = BCM_6348_TIMER_IRQ,
123 [IRQ_SPI] = BCM_6348_SPI_IRQ,
124 [IRQ_UART0] = BCM_6348_UART0_IRQ,
125 [IRQ_DSL] = BCM_6348_DSL_IRQ,
126 [IRQ_UDC0] = BCM_6348_UDC0_IRQ,
127 [IRQ_ENET0] = BCM_6348_ENET0_IRQ,
128 [IRQ_ENET1] = BCM_6348_ENET1_IRQ,
129 [IRQ_ENET_PHY] = BCM_6348_ENET_PHY_IRQ,
130 [IRQ_OHCI0] = BCM_6348_OHCI0_IRQ,
131 [IRQ_PCMCIA] = BCM_6348_PCMCIA_IRQ,
132 [IRQ_ENET0_RXDMA] = BCM_6348_ENET0_RXDMA_IRQ,
133 [IRQ_ENET0_TXDMA] = BCM_6348_ENET0_TXDMA_IRQ,
134 [IRQ_ENET1_RXDMA] = BCM_6348_ENET1_RXDMA_IRQ,
135 [IRQ_ENET1_TXDMA] = BCM_6348_ENET1_TXDMA_IRQ,
136 [IRQ_PCI] = BCM_6348_PCI_IRQ,
137 };
138
139 static const unsigned long bcm96348_regs_spi[] = {
140 [SPI_CMD] = SPI_BCM_6348_SPI_CMD,
141 [SPI_INT_STATUS] = SPI_BCM_6348_SPI_INT_STATUS,
142 [SPI_INT_MASK_ST] = SPI_BCM_6348_SPI_MASK_INT_ST,
143 [SPI_INT_MASK] = SPI_BCM_6348_SPI_INT_MASK,
144 [SPI_ST] = SPI_BCM_6348_SPI_ST,
145 [SPI_CLK_CFG] = SPI_BCM_6348_SPI_CLK_CFG,
146 [SPI_FILL_BYTE] = SPI_BCM_6348_SPI_FILL_BYTE,
147 [SPI_MSG_TAIL] = SPI_BCM_6348_SPI_MSG_TAIL,
148 [SPI_RX_TAIL] = SPI_BCM_6348_SPI_RX_TAIL,
149 [SPI_MSG_CTL] = SPI_BCM_6348_SPI_MSG_CTL,
150 [SPI_MSG_DATA] = SPI_BCM_6348_SPI_MSG_DATA,
151 [SPI_RX_DATA] = SPI_BCM_6348_SPI_RX_DATA,
152 };
153
154 /*
155 * 6358 register sets and irqs
156 */
157 static const unsigned long bcm96358_regs_base[] = {
158 [RSET_DSL_LMEM] = BCM_6358_DSL_LMEM_BASE,
159 [RSET_PERF] = BCM_6358_PERF_BASE,
160 [RSET_TIMER] = BCM_6358_TIMER_BASE,
161 [RSET_WDT] = BCM_6358_WDT_BASE,
162 [RSET_UART0] = BCM_6358_UART0_BASE,
163 [RSET_GPIO] = BCM_6358_GPIO_BASE,
164 [RSET_SPI] = BCM_6358_SPI_BASE,
165 [RSET_OHCI0] = BCM_6358_OHCI0_BASE,
166 [RSET_EHCI0] = BCM_6358_EHCI0_BASE,
167 [RSET_OHCI_PRIV] = BCM_6358_OHCI_PRIV_BASE,
168 [RSET_USBH_PRIV] = BCM_6358_USBH_PRIV_BASE,
169 [RSET_MPI] = BCM_6358_MPI_BASE,
170 [RSET_PCMCIA] = BCM_6358_PCMCIA_BASE,
171 [RSET_SDRAM] = BCM_6358_SDRAM_BASE,
172 [RSET_DSL] = BCM_6358_DSL_BASE,
173 [RSET_ENET0] = BCM_6358_ENET0_BASE,
174 [RSET_ENET1] = BCM_6358_ENET1_BASE,
175 [RSET_ENETDMA] = BCM_6358_ENETDMA_BASE,
176 [RSET_MEMC] = BCM_6358_MEMC_BASE,
177 [RSET_DDR] = BCM_6358_DDR_BASE,
178 };
179
180 static const int bcm96358_irqs[] = {
181 [IRQ_TIMER] = BCM_6358_TIMER_IRQ,
182 [IRQ_SPI] = BCM_6358_SPI_IRQ,
183 [IRQ_UART0] = BCM_6358_UART0_IRQ,
184 [IRQ_DSL] = BCM_6358_DSL_IRQ,
185 [IRQ_ENET0] = BCM_6358_ENET0_IRQ,
186 [IRQ_ENET1] = BCM_6358_ENET1_IRQ,
187 [IRQ_ENET_PHY] = BCM_6358_ENET_PHY_IRQ,
188 [IRQ_OHCI0] = BCM_6358_OHCI0_IRQ,
189 [IRQ_EHCI0] = BCM_6358_EHCI0_IRQ,
190 [IRQ_PCMCIA] = BCM_6358_PCMCIA_IRQ,
191 [IRQ_ENET0_RXDMA] = BCM_6358_ENET0_RXDMA_IRQ,
192 [IRQ_ENET0_TXDMA] = BCM_6358_ENET0_TXDMA_IRQ,
193 [IRQ_ENET1_RXDMA] = BCM_6358_ENET1_RXDMA_IRQ,
194 [IRQ_ENET1_TXDMA] = BCM_6358_ENET1_TXDMA_IRQ,
195 [IRQ_PCI] = BCM_6358_PCI_IRQ,
196 };
197
198 static const unsigned long bcm96358_regs_spi[] = {
199 [SPI_CMD] = SPI_BCM_6358_SPI_CMD,
200 [SPI_INT_STATUS] = SPI_BCM_6358_SPI_INT_STATUS,
201 [SPI_INT_MASK_ST] = SPI_BCM_6358_SPI_MASK_INT_ST,
202 [SPI_INT_MASK] = SPI_BCM_6358_SPI_INT_MASK,
203 [SPI_ST] = SPI_BCM_6358_SPI_STATUS,
204 [SPI_CLK_CFG] = SPI_BCM_6358_SPI_CLK_CFG,
205 [SPI_FILL_BYTE] = SPI_BCM_6358_SPI_FILL_BYTE,
206 [SPI_MSG_TAIL] = SPI_BCM_6358_SPI_MSG_TAIL,
207 [SPI_RX_TAIL] = SPI_BCM_6358_SPI_RX_TAIL,
208 [SPI_MSG_CTL] = SPI_BCM_6358_MSG_CTL,
209 [SPI_MSG_DATA] = SPI_BCM_6358_SPI_MSG_DATA,
210 [SPI_RX_DATA] = SPI_BCM_6358_SPI_RX_DATA,
211 };
212
213 u16 __bcm63xx_get_cpu_id(void)
214 {
215 return bcm63xx_cpu_id;
216 }
217
218 EXPORT_SYMBOL(__bcm63xx_get_cpu_id);
219
220 u16 bcm63xx_get_cpu_rev(void)
221 {
222 return bcm63xx_cpu_rev;
223 }
224
225 EXPORT_SYMBOL(bcm63xx_get_cpu_rev);
226
227 unsigned int bcm63xx_get_cpu_freq(void)
228 {
229 return bcm63xx_cpu_freq;
230 }
231
232 unsigned int bcm63xx_get_memory_size(void)
233 {
234 return bcm63xx_memory_size;
235 }
236
237 static unsigned int detect_cpu_clock(void)
238 {
239 unsigned int tmp, n1 = 0, n2 = 0, m1 = 0;
240
241 if (BCMCPU_IS_6338())
242 return 240000000;
243
244 if (BCMCPU_IS_6345())
245 return 140000000;
246
247 /*
248 * frequency depends on PLL configuration:
249 */
250 if (BCMCPU_IS_6348()) {
251 /* 16MHz * (N1 + 1) * (N2 + 2) / (M1_CPU + 1) */
252 tmp = bcm_perf_readl(PERF_MIPSPLLCTL_REG);
253 n1 = (tmp & MIPSPLLCTL_N1_MASK) >> MIPSPLLCTL_N1_SHIFT;
254 n2 = (tmp & MIPSPLLCTL_N2_MASK) >> MIPSPLLCTL_N2_SHIFT;
255 m1 = (tmp & MIPSPLLCTL_M1CPU_MASK) >> MIPSPLLCTL_M1CPU_SHIFT;
256 n1 += 1;
257 n2 += 2;
258 m1 += 1;
259 }
260
261 if (BCMCPU_IS_6358()) {
262 /* 16MHz * N1 * N2 / M1_CPU */
263 tmp = bcm_ddr_readl(DDR_DMIPSPLLCFG_REG);
264 n1 = (tmp & DMIPSPLLCFG_N1_MASK) >> DMIPSPLLCFG_N1_SHIFT;
265 n2 = (tmp & DMIPSPLLCFG_N2_MASK) >> DMIPSPLLCFG_N2_SHIFT;
266 m1 = (tmp & DMIPSPLLCFG_M1_MASK) >> DMIPSPLLCFG_M1_SHIFT;
267 }
268
269 return (16 * 1000000 * n1 * n2) / m1;
270 }
271
272 /*
273 * attempt to detect the amount of memory installed
274 */
275 static unsigned int detect_memory_size(void)
276 {
277 unsigned int cols = 0, rows = 0, is_32bits = 0, banks = 0;
278 u32 val;
279
280 if (BCMCPU_IS_6338() || BCMCPU_IS_6348()) {
281 val = bcm_sdram_readl(SDRAM_CFG_REG);
282 rows = (val & SDRAM_CFG_ROW_MASK) >> SDRAM_CFG_ROW_SHIFT;
283 cols = (val & SDRAM_CFG_COL_MASK) >> SDRAM_CFG_COL_SHIFT;
284 is_32bits = (val & SDRAM_CFG_32B_MASK) ? 1 : 0;
285 banks = (val & SDRAM_CFG_BANK_MASK) ? 2 : 1;
286 }
287
288 if (BCMCPU_IS_6358()) {
289 val = bcm_memc_readl(MEMC_CFG_REG);
290 rows = (val & MEMC_CFG_ROW_MASK) >> MEMC_CFG_ROW_SHIFT;
291 cols = (val & MEMC_CFG_COL_MASK) >> MEMC_CFG_COL_SHIFT;
292 is_32bits = (val & MEMC_CFG_32B_MASK) ? 0 : 1;
293 banks = 2;
294 }
295
296 /* 0 => 11 address bits ... 2 => 13 address bits */
297 rows += 11;
298
299 /* 0 => 8 address bits ... 2 => 10 address bits */
300 cols += 8;
301
302 return 1 << (cols + rows + (is_32bits + 1) + banks);
303 }
304
305 void __init bcm63xx_cpu_init(void)
306 {
307 unsigned int tmp, expected_cpu_id;
308 struct cpuinfo_mips *c = &current_cpu_data;
309
310 /* soc registers location depends on cpu type */
311 expected_cpu_id = 0;
312
313 switch (c->cputype) {
314 case CPU_BCM3302:
315 expected_cpu_id = BCM6338_CPU_ID;
316 bcm63xx_regs_base = bcm96338_regs_base;
317 bcm63xx_irqs = bcm96338_irqs;
318 bcm63xx_regs_spi = bcm96338_regs_spi;
319 break;
320 case CPU_BCM6345:
321 expected_cpu_id = BCM6345_CPU_ID;
322 bcm63xx_regs_base = bcm96345_regs_base;
323 bcm63xx_irqs = bcm96345_irqs;
324 break;
325 case CPU_BCM6348:
326 expected_cpu_id = BCM6348_CPU_ID;
327 bcm63xx_regs_base = bcm96348_regs_base;
328 bcm63xx_irqs = bcm96348_irqs;
329 bcm63xx_regs_spi = bcm96348_regs_spi;
330 break;
331 case CPU_BCM6358:
332 expected_cpu_id = BCM6358_CPU_ID;
333 bcm63xx_regs_base = bcm96358_regs_base;
334 bcm63xx_irqs = bcm96358_irqs;
335 bcm63xx_regs_spi = bcm96358_regs_spi;
336 break;
337 }
338
339 /* really early to panic, but delaying panic would not help
340 * since we will never get any working console */
341 if (!expected_cpu_id)
342 panic("unsupported Broadcom CPU");
343
344 /*
345 * bcm63xx_regs_base is set, we can access soc registers
346 */
347
348 /* double check CPU type */
349 tmp = bcm_perf_readl(PERF_REV_REG);
350 bcm63xx_cpu_id = (tmp & REV_CHIPID_MASK) >> REV_CHIPID_SHIFT;
351 bcm63xx_cpu_rev = (tmp & REV_REVID_MASK) >> REV_REVID_SHIFT;
352
353 if (bcm63xx_cpu_id != expected_cpu_id)
354 panic("bcm63xx CPU id mismatch");
355
356 bcm63xx_cpu_freq = detect_cpu_clock();
357 bcm63xx_memory_size = detect_memory_size();
358
359 printk(KERN_INFO "Detected Broadcom 0x%04x CPU revision %02x\n",
360 bcm63xx_cpu_id, bcm63xx_cpu_rev);
361 printk(KERN_INFO "CPU frequency is %u Hz\n",
362 bcm63xx_cpu_freq);
363 printk(KERN_INFO "%uMB of RAM installed\n",
364 bcm63xx_memory_size >> 20);
365 }